85187 lines
6.2 MiB
85187 lines
6.2 MiB
; --------------------------------------------------------------------------------
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; @Title: AM387x, DM3814x, DRA6x, C6A814x On-Chip Peripherals
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; @Props: Released
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; @Author: ART, LEM, MAR, PAC, SLA, SOL, STR
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; @Changelog:
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; 2011-02-28 MAR
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; 2011-12-22 MAR
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; 2012-06-25 MAR
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; @Manufacturer: TI - Texas Instruments
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; @Doc: SPRS694splat_DRA6xx_DM_AUTODM_f5_02_08_11.pdf
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; DM814x_PRCM_Registers_12Oct10.pdf
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; DM814x_HDVPSS_Advanced_Information_Document.pdf; MCBSP_DM8XX.pdf
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; ETHERNET_Spruf57b.pdf; DM8x_USB_SPRUGX8_11_03_10_draft.pdf
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; device_config_j5_ug_v0p1.pdf; GPIO_DM8xx.pdf; McASP_DM8x.pdf; UART_DM8xx.pdf
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; PATA_SPRUGI0.pdf; dcan_j5_SPRUGI2.pdf; WDTimer_DM8xx.pdf; Timers_DM8xx.pdf
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; DM814x_PCIe_User's_Guide.pdf; I2C_DM8xx.pdf; mailbox_j5_ug_082910.pdf
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; mlb_j5_ug_082910.pdf; dmm_j5_ug_081710.pdf; RTC_DM8x.pdf; SPI_DM8x.pdf
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; mmcsd_j5_ug_082310.pdf; SATA_SPRUGX9.pdf; intc_j5_ug_082310.pdf
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; edma_j5_ug_082310.pdf; Centaurus_DM81xx_TRM_2_15_11.pdf
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; sprs695.pdf (Rev. 2011-09); sprugz7.pdf (Rev.14 2011-10)
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; SPRS778A_DRx62x.pdf; SPRUHF4A_DRA62x.pdf
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; @Core: Cortex-A8
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peram387x.per 12537 2020-11-13 13:58:59Z amerkle $
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;Known problems:
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; Ethernet: Missing base address for CPSW_3GSS, SGMII, MDIO. Not implemented.
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; DDR_PHY: Missing base address. Not implemented
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; PRUSS Crossbar muxing not described.Not implemented.
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; PRCM registers PRM_HDVICP and PRM_ISP not described. Not implemented.
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config 16. 8.
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width 0x0b
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base ad:0x00000000
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tree "Core Registers (Cortex-A8)"
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup c15:0x0--0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x100--0x100
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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textline " "
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup c15:0x200--0x200
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line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "ARMv6,ARMv6,ARMv6,ARMv6,ARMv7,ARMv6,ARMv6,ARMv6"
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bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x300--0x300
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line.long 0x0 "TLBTR,TLB Type Register"
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hexmask.long.byte 0x0 16.--23. 0x1 " ITLBLOCK ,Specifies the number of instruction TLB lockable entries"
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hexmask.long.byte 0x0 8.--15. 0x1 " DTLBLOCK ,Specifies the number of unified or data TLB lockable entries"
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bitfld.long 0x0 0. " S ,Unified or Separate TLBs" "Unified,Separate"
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rgroup c15:0x400--0x400
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line.long 0x0 "MPUTR,MPU type register"
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rgroup c15:0x500--0x500
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitniy Level 2"
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hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitniy Level 1"
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hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitniy Level 0"
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textline " "
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rgroup c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
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rgroup c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
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rgroup c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
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rgroup c15:0x0020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup c15:0x0520++0x00
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line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
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rgroup c15:0x0620++0x00
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line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
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rgroup c15:0x0720++0x00
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line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
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rgroup c15:0x0010++0x00
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line.long 0x00 "PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup c15:0x0110++0x00
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line.long 0x00 "PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
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textline " "
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rgroup c15:0x0210++0x00
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line.long 0x00 "DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
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rgroup c15:0x0310++0x00
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line.long 0x00 "AFR0,Auxiliary Feature Register 0"
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hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group c15:0x1--0x1
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line.long 0x0 "SCTLR,Control Register"
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bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
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bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
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bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
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bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
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bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
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bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
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textline " "
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group c15:0x101--0x101
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line.long 0x0 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 31. " L2RD ,L2 hardware reset disable" "Enable,Disable"
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bitfld.long 0x00 30. " L1RD ,L1 hardware reset disable" "Enable,Disable"
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textline " "
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bitfld.long 0x00 18. " CPISEL ,CP14/CP15 instruction serialization" "No,Yes"
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bitfld.long 0x00 17. " CPWAI ,CP14/CP15 wait on idle" "No,Yes"
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bitfld.long 0x00 16. " CPFL ,CP14/CP15 pipeline flush" "No,Yes"
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textline " "
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bitfld.long 0x00 15. " FETMCLK ,Force ETM clock" "No,Yes"
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bitfld.long 0x00 14. " FNCLK ,Force NEON clock" "No,Yes"
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bitfld.long 0x00 13. " FMCLK ,Force main clock" "No,Yes"
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textline " "
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bitfld.long 0x00 12. " FNSI ,Force NEON single issue" "No,Yes"
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bitfld.long 0x00 11. " FLSSI ,Force load/store single issue" "No,Yes"
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bitfld.long 0x00 10. " FSI ,Force single issue" "No,Yes"
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textline " "
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bitfld.long 0x00 9. " PLDNOP ,PLD executes as NOP" "Execute,NOP"
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bitfld.long 0x00 8. " WFINOP ,WFI executes as NOP" "Execute,NOP"
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textline " "
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bitfld.long 0x00 7. " DBSM ,Disable branch size mispredicts" "Enable,Disable"
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bitfld.long 0x00 6. " IBE ,Invalidate BTB Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 5. " L1NEON ,NEON Data Caching Within the L1 Data Cache Enable" "Disable,Enable"
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bitfld.long 0x00 4. " ASA ,Speculative Accesses on AXI Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 3. " L1PE ,L1 Cache Parity Detection Enable" "Disable,Enable"
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bitfld.long 0x00 1. " L2EN ,L2 Cache Enable" "Disable,Enable"
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bitfld.long 0x00 0. " L1ALIAS ,L1 Data Cache Hardware Alias Checks Enable" "Enable,Disable"
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group c15:0x201--0x201
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line.long 0x0 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
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textline " "
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bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
group c15:0x11--0x11
|
|
line.long 0x0 "SCR,Secure Configuration Register"
|
|
bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
|
|
bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
|
|
bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
|
|
group c15:0x111--0x111
|
|
line.long 0x0 "SDER,Secure Debug Enable Register"
|
|
bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
group c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " PLE ,PLE Registers Access in Nonsecure World" "Denied,Permitted"
|
|
bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CL ,Lockdown Entries Allocation Within the L2 Cache in Nonsecure World" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CP13 ,Coprocessor 13 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 12. " CP12 ,Coprocessor 12 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CP9 ,Coprocessor 9 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 8. " CP8 ,Coprocessor 8 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CP7 ,Coprocessor 7 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 6. " CP6 ,Coprocessor 6 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CP5 ,Coprocessor 5 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 4. " CP4 ,Coprocessor 4 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CP3 ,Coprocessor 3 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 2. " CP2 ,Coprocessor 2 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CP1 ,Coprocessor 1 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " CP0 ,Coprocessor 0 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
group c15:0x000c++0x00
|
|
line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address"
|
|
group c15:0x10c--0x10c
|
|
line.long 0x0 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address"
|
|
textline " "
|
|
rgroup c15:0x1C--0x1C
|
|
line.long 0x0 "ISR,Interrupt status Register"
|
|
bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending"
|
|
bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending"
|
|
bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending"
|
|
tree.end
|
|
width 0x0d
|
|
tree "Memory Management Unit"
|
|
width 8.
|
|
group c15:0x1--0x1
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
|
|
textline " "
|
|
group c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
|
|
group c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
|
|
group c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable"
|
|
bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable"
|
|
bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000"
|
|
textline " "
|
|
group c15:0x3--0x3
|
|
line.long 0x0 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
group c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/decode,Reserved,Imprecise/parity/ECC,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/slave,?..."
|
|
group c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
group c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/parity,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,?..."
|
|
group c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
group c15:0x0015++0x00
|
|
line.long 0x00 "DAFSR,Data Auxiliary Fault Status Register"
|
|
group c15:0x0115++0x00
|
|
line.long 0x00 "IAFSR,Instruction Auxiliary Fault Status Register"
|
|
textline " "
|
|
group c15:0x002A--0x002A
|
|
line.long 0x00 "PMRRR,Primary Memory Region Remap Register"
|
|
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
group c15:0x012A--0x012A
|
|
line.long 0x00 "NMRR,Normal Memory Remap Register"
|
|
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
group c15:0x000d++0x00
|
|
line.long 0x00 "FCSEPID,FCSE PID Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " FCSEPID ,Process for Fast Context Switch Identification and Specification"
|
|
group c15:0x10d--0x10d
|
|
line.long 0x0 "CONTEXT,Context ID Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID"
|
|
hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID"
|
|
group c15:0x020d++0x00
|
|
line.long 0x00 "URWTPID,User Read/Write Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " URWTPID ,User Read/Write Thread and Process ID"
|
|
group c15:0x030d++0x00
|
|
line.long 0x00 "UROTPID,User Read-Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " UROTPID ,User Read-Only Thread and Process ID"
|
|
group c15:0x040d++0x00
|
|
line.long 0x00 "POTPID,Privileged Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " POTPID ,Privileged Only Thread and Process ID"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup c15:0x1100--0x1100
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CTYPE8 ,Cache type for levels 8" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
rgroup c15:0x1000--0x1000
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. 1. " SETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words"
|
|
group c15:0x2000--0x2000
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/unified,Instruction"
|
|
tree.end
|
|
width 0x8
|
|
tree "L2 Cache Control and Configuration"
|
|
group c15:0x1009++0x00
|
|
line.long 0x00 "L2CLR,L2 Cache Lockdown Register"
|
|
bitfld.long 0x00 7. " LOCK_way_7 ,Way 7 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LOCK_way_6 ,Way 6 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LOCK_way_5 ,Way 5 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOCK_way_4 ,Way 4 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LOCK_way_3 ,Way 3 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LOCK_way_2 ,Way 2 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOCK_way_1 ,Way 1 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LOCK_way_0 ,Way 0 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
group c15:0x1209++0x00
|
|
line.long 0x00 "L2CACR,L2 Cache Auxiliary Control Register"
|
|
bitfld.long 0x00 28. " ECCP ,ECC/Parity Selection" "Parity,ECC"
|
|
bitfld.long 0x00 27. " PLDFD ,PLD Forwarding to LS Request Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " PLDD ,PLD Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCD ,Write Combining Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " WADD ,External Linefill When Storing an Entire Line With Write Allocate Permission Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 23. " WACD ,Combining of Data in the L2 Write Combining Buffers Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAD ,Allocate on Write Miss in L2 Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 21. " PECCE ,Parity/ECC Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " L2I ,L2 Inner" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " TRAML ,Program Tag RAM Latency" "2 cycles,2 cycles,3 cycles,4 cycles,4 cycles,4 cycles,4 cycles,4 cycles"
|
|
bitfld.long 0x00 0.--3. " DRAML ,Program Data RAM Latency" "3 cycles,3 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,13 cycles,13 cycles,13 cycles"
|
|
textline " "
|
|
rgroup c15:0x000b++0x00
|
|
line.long 0x00 "PLEISR0,PLE Identification and Status Register 0"
|
|
bitfld.long 0x00 1. " CH1P ,Channel 1 Present" "Not present,Present"
|
|
bitfld.long 0x00 0. " CH0P ,Channel 0 Present" "Not present,Present"
|
|
rgroup c15:0x010b++0x00
|
|
line.long 0x00 "PLEISR1,PLE Identification and Status Register 1"
|
|
bitfld.long 0x00 1. " CH1Q ,Channel 1 Queue" "Not queued,Queued"
|
|
bitfld.long 0x00 0. " CH0Q ,Channel 0 Queue" "Not queued,Queued"
|
|
rgroup c15:0x020b++0x00
|
|
line.long 0x00 "PLEISR2,PLE Identification and Status Register 2"
|
|
bitfld.long 0x00 1. " CH1R ,Channel 1 Run" "Not running,Running"
|
|
bitfld.long 0x00 0. " CH0R ,Channel 0 Run" "Not running,Running"
|
|
rgroup c15:0x030b++0x00
|
|
line.long 0x00 "PLEISR3,PLE Identification and Status Register 3"
|
|
bitfld.long 0x00 1. " CH1I ,Channel 1 Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " CH0I ,Channel 0 Interrupt" "No interrupt,Interrupt"
|
|
group c15:0x001b++0x00
|
|
line.long 0x00 "PLEUAR,PLE User Accessibility Register"
|
|
bitfld.long 0x00 1. " U1 ,User Mode Process Access Registers for Channel 1 Permission" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " U0 ,User Mode Process Access Registers for Channel 0 Permission" "Not permitted,Permitted"
|
|
group c15:0x002b++0x00
|
|
line.long 0x00 "PLECNR,PLE Channel Number Register"
|
|
bitfld.long 0x00 0. " CN ,PLE Channel Selection" "Channel 0,Channel 1"
|
|
wgroup c15:0x003b++0x00
|
|
line.long 0x00 "PLEER0,PLE Enable Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PLEE_STOP ,PLE Enable Stop"
|
|
wgroup c15:0x013b++0x00
|
|
line.long 0x00 "PLEER1,PLE Enable Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PLEE_START ,PLE Enable Start"
|
|
wgroup c15:0x023b++0x00
|
|
line.long 0x00 "PLEER2,PLE Enable Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PLEES_CLEAR ,PLE Enable Clear"
|
|
group c15:0x004b++0x00
|
|
line.long 0x00 "PLECR,PLE Control Register"
|
|
bitfld.long 0x00 30. " DT ,Transfer Direction" "Memory->cache,Cache->memory"
|
|
bitfld.long 0x00 29. " IC ,Interrupt on Completion of the PLE Transfer" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IE ,Interrupt on an Error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " UM ,Permission Checks Type" "Privileged,User"
|
|
bitfld.long 0x00 0.--2. " Wy ,L2 Cache Way for Filling Data" "Way 0,Way 1,Way 2,Way 3,Way 4,Way 5,Way 6,Way 7"
|
|
textline " "
|
|
group c15:0x005b++0x00
|
|
line.long 0x00 "PLEISAR,PLE Internal Start Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " PLEISA ,PLE Internal Start Address"
|
|
group c15:0x007b++0x00
|
|
line.long 0x00 "PLEIEAR,PLE Internal End Address Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " Lines ,Number of Cache Lines Transferred"
|
|
rgroup c15:0x008b++0x00
|
|
line.long 0x00 "PLECSR,PLE Channel Status Register"
|
|
hexmask.long.byte 0x00 2.--8. 1. " EC ,External Address Error Status"
|
|
bitfld.long 0x00 0.--1. " Status ,PLE Channel Status" "Idle,Queued,Running,Complete/error"
|
|
group c15:0x00fb++0x00
|
|
line.long 0x00 "PLECIDR,PLE Context ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,ASID Extension to Form the Process ID and Current Process Identification"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ASID ,ASID of the Current Process and the Current ASID Identification"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group c15:0xC9--0xC9
|
|
line.long 0x0 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
|
|
group c15:0x1C9--0x1C9
|
|
line.long 0x0 "CNTENS,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x2C9--0x2C9
|
|
line.long 0x0 "CNTENC,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x3C9--0x3C9
|
|
line.long 0x0 "FLAG,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group c15:0x4C9--0x4C9
|
|
line.long 0x0 "SWINCR,Software Increment Register"
|
|
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group c15:0x5C9--0x5C9
|
|
line.long 0x0 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,..."
|
|
group c15:0xD9--0xD9
|
|
line.long 0x0 "PMCCNTR,Cycle Count Register"
|
|
group c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
line.long 0x00 "PMCNT,Performance Monitor Count Register"
|
|
group c15:0xE9--0xE9
|
|
line.long 0x0 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
|
|
group c15:0x1E9--0x1E9
|
|
line.long 0x0 "INTENS,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
group c15:0x2E9--0x2E9
|
|
line.long 0x0 "INTENC,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
tree.end
|
|
width 8.
|
|
tree "Debug Registers"
|
|
width 10.
|
|
rgroup c14:0x000--0x000
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CONTEXT ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..."
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 10.
|
|
group c14:0x22--0x22
|
|
line.long 0x0 "DBGDSCR,Debug Status and Control Register"
|
|
bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full"
|
|
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full"
|
|
bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired"
|
|
bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
|
|
bitfld.long 0x0 17. " nSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced"
|
|
bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception"
|
|
textline " "
|
|
bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..."
|
|
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
|
|
textline " "
|
|
width 10.
|
|
if (((data.long(c14:0x00))&0x01000)==0x00000)
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
else
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
endif
|
|
width 10.
|
|
hgroup c14:0x020--0x020
|
|
hide.long 0x0 "DBGDTRRX,Debug Receive Register (External View)"
|
|
in
|
|
group c14:0x023--0x023
|
|
line.long 0x0 "DBGDTRTX,Debug Transmit Register (External View)"
|
|
group c14:0x09++0x00
|
|
line.long 0x00 "DBGECR,Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group c14:0x0a++0x00
|
|
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal"
|
|
bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal"
|
|
wgroup c14:0x21++0x00
|
|
line.long 0x00 "DBGITR,Instruction Transfer Register"
|
|
wgroup c14:0x24++0x00
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
|
|
wgroup c14:0xc0++0x00
|
|
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
|
|
rgroup c14:0xc1++0x00
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required"
|
|
bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented"
|
|
group c14:0xc2++0x00
|
|
line.long 0x00 "DBGOSSRR,Operating System Save and Restore Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore"
|
|
group c14:0xc4++0x00
|
|
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held"
|
|
bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high"
|
|
hgroup c14:0xc5++0x00
|
|
hide.long 0x00 "DBGPRSR,Device Power-Down and Reset Status Register"
|
|
in
|
|
width 11.
|
|
tree "Processor Identifier Registers"
|
|
rgroup c14:0x340--0x340
|
|
line.long 0x00 "CPUID,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup c14:0x341--0x341
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup c14:0x343--0x343
|
|
line.long 0x00 "TLBTYPE,TLB Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
|
|
hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
|
|
textline " "
|
|
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
|
|
rgroup c14:0x348--0x348
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x349--0x349
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x34a--0x34a
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup c14:0x34b--0x34b
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
|
|
rgroup c14:0x34c--0x34c
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x34d--0x34d
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup c14:0x34e--0x34e
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup c14:0x34f--0x34f
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x350--0x350
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x351--0x351
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x352--0x352
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x353--0x353
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x354--0x354
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x355--0x355
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
|
width 0xC
|
|
tree "Coresight Management Registers"
|
|
width 17.
|
|
group c14:0x03bd++0x00
|
|
line.long 0x00 "DBGITCTRL_IOC,Integration Internal Output Control Register"
|
|
bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1"
|
|
bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I_nPMUIRQ ,Internal nPMUIRQ" "0,1"
|
|
bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1"
|
|
group c14:0x03be++0x00
|
|
line.long 0x00 "DBGITCTRL_EOC,Integration External Output Control Register"
|
|
bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1"
|
|
bitfld.long 0x00 6. " nDMASIRQ ,External nDMASIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1"
|
|
bitfld.long 0x00 4. " nPMUIRQ ,External nPMUIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1"
|
|
bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1"
|
|
rgroup c14:0x03bf++0x00
|
|
line.long 0x00 "DBGITCTRL_IS,Integration Input Status Register"
|
|
bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1"
|
|
bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1"
|
|
bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " nFIQ ,nFIQ Input" "0,1"
|
|
bitfld.long 0x00 1. " nIRQ ,nIRQ Input" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1"
|
|
group c14:0x3c0--0x3c0
|
|
line.long 0x0 "DBGITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group c14:0x3e8--0x3e8
|
|
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
|
|
group c14:0x3e9--0x3e9
|
|
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
|
|
wgroup c14:0x3ec--0x3ec
|
|
line.long 0x0 "DBGLAR,Lock Access Register"
|
|
rgroup c14:0x3ed--0x3ed
|
|
line.long 0x0 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit"
|
|
bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented"
|
|
width 17.
|
|
rgroup c14:0x3ee--0x3ee
|
|
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled"
|
|
width 17.
|
|
hgroup c14:0x3f2--0x3f2
|
|
hide.long 0x0 "DBGDEVID,Device Identifier (RESERVED)"
|
|
rgroup c14:0x3f3--0x3f3
|
|
line.long 0x0 "DBGDEVTYPE,Device Type"
|
|
bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup c14:0x3f8--0x3f8
|
|
line.long 0x00 "DBGPID0,Debug Peripheral ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]"
|
|
rgroup c14:0x3f9--0x3f9
|
|
line.long 0x00 "DBGPID1,Debug Peripheral ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]"
|
|
rgroup c14:0x3fa--0x3fa
|
|
line.long 0x00 "DBGPID2,Debug Peripheral ID 2"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]"
|
|
rgroup c14:0x3fb--0x3fb
|
|
line.long 0x00 "DBGPID3,Debug Peripheral ID 3"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified"
|
|
rgroup c14:0x3f4--0x3f4
|
|
line.long 0x00 "DBGPID4,Debug Peripheral ID 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code"
|
|
rgroup c14:0x3fc--0x3fc
|
|
line.long 0x00 "DBGCID0,Debug Component ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0"
|
|
rgroup c14:0x3fd--0x3fd
|
|
line.long 0x00 "DBGCID1,Debug Component ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1"
|
|
rgroup c14:0x3fe--0x3fe
|
|
line.long 0x00 "DBGCID2,Debug Component ID 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2"
|
|
rgroup c14:0x3ff--0x3ff
|
|
line.long 0x00 "DBGCID3,Debug Component ID 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3"
|
|
tree.end
|
|
tree.end
|
|
width 7.
|
|
tree "Breakpoint Registers"
|
|
group c14:0x40++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
group c14:0x50++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x41++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
group c14:0x51++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x42++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
group c14:0x52++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x43++0x00
|
|
line.long 0x00 "BVR3,Breakpoint Value Register 3"
|
|
group c14:0x53++0x00
|
|
line.long 0x00 "BCR3,Breakpoint Control Register 3"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x44++0x00
|
|
line.long 0x00 "BVR4,Breakpoint Value Register 4"
|
|
group c14:0x54++0x00
|
|
line.long 0x00 "BCR4,Breakpoint Control Register 4"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x45++0x00
|
|
line.long 0x00 "BVR5,Breakpoint Value Register 5"
|
|
group c14:0x55++0x00
|
|
line.long 0x00 "BCR5,Breakpoint Control Register 5"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 6.
|
|
tree "Watchpoint Control Registers"
|
|
group c14:0x60++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group c14:0x70--0x70
|
|
line.long 0x0 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x61++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
|
|
group c14:0x71--0x71
|
|
line.long 0x0 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x006--0x006
|
|
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
|
|
hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("DRA62*"))
|
|
tree "Media Control Subsystem"
|
|
base ad:0x55080000
|
|
width 22.
|
|
tree "CACHE Control Registers"
|
|
group.long 0x4++0x1f
|
|
line.long 0x00 "CACHE_CFG,Configuration Register"
|
|
bitfld.long 0x00 1. " BYPASS ,Bypass cache" "Non-cacheable,Cacheable"
|
|
line.long 0x04 "CACHE_INT,Interrupt Register"
|
|
bitfld.long 0x04 5.--8. " PORT ,Slave interface number that has recorded an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 4. " READ ,Interface read response error" "No error,Error"
|
|
eventfld.long 0x04 3. " WRITE ,Interface write response error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 2. " MAINT ,Maintenance is completed" "Not completed,Completed"
|
|
eventfld.long 0x04 1. " PAGEFAULT ,AMMU page fault" "No fault,Fault"
|
|
eventfld.long 0x04 0. " CONFIG ,Configuration error" "No error,Error"
|
|
line.long 0x08 "CACHE_OCP,Interface Configuration Register"
|
|
bitfld.long 0x08 5. " CLEANBUF ,Clean write and prefetch buffers in cache" "Not cleaned,Cleaned"
|
|
bitfld.long 0x08 4. " PREFETCH ,Always prefetch data" "Follow MMU policies,Always prefetch"
|
|
bitfld.long 0x08 3. " CACHED ,Follow cacheable sideband signals" "Not followed,Followed"
|
|
textline " "
|
|
bitfld.long 0x08 2. " WRALLOCATE ,Follow write allocate sideband signals" "Not followed,Followed"
|
|
bitfld.long 0x08 1. " WRBUFFER ,Write throughs and write back no allocate are buffered" "Not buffered,Buffered"
|
|
bitfld.long 0x08 0. " WRAP ,OCP wrap mode (critical word first)" "Disabled,Enabled"
|
|
line.long 0x0c "CACHE_MAINT,Maintenance Configuration Register"
|
|
bitfld.long 0x0c 5. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "Not generated,Generated"
|
|
bitfld.long 0x0c 4. " INVALIDATE ,Invalidate lines in region defined by maintenance start/end addresses" "No effect,Invalidated"
|
|
bitfld.long 0x0c 3. " CLEAN ,Evict dirty lines in region defined by maintenance start/end addresses" "No effece,Cleaned"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " UNLOCK ,Unlock region defined by maintenance start/end addresses" "No effect,Unlocked"
|
|
bitfld.long 0x0c 1. " LOCK ,Lock region defined by maintenance start/end addresses" "No effect,Locked"
|
|
bitfld.long 0x0c 0. " PRELOAD ,Preload region defined by maintenance start/end addresses" "No effect,Preload"
|
|
line.long 0x10 "CACHE_MTSTART,Maintenance Start Configuration Register"
|
|
line.long 0x14 "CACHE_MTEND,Maintenance End Configuration Register"
|
|
line.long 0x18 "CACHE_CTADDR,Cache Test Address Register"
|
|
line.long 0x1c "CACHE_CTDATA,Cache Test Data Register"
|
|
tree.end
|
|
tree "SCTM Registers"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "CACHE_SCTM_CTCNTL,Counter Timer Control Register"
|
|
bitfld.long 0x00 26.--31. " NUMSTM ,Number of timers that can export via STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x00 18.--25. 1. " NUMINPT ,Number of event input signals"
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bitfld.long 0x00 13.--17. " NUMTIMR ,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 7.--12. " NUMCNTR ,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 3.--6. " REVISION ,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1.--2. " IDLEMODE ,Idle mode control" "Forced,ACK only,Smart idle,Smart idle"
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textline " "
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bitfld.long 0x00 0. " ENBL ,SCTM global enable" "Disabled,Enabled"
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group.long 0x420++0x13
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line.long 0x00 "CACHE_SCTM_CTSTMCNTL,Counter Timer STM Control Register"
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bitfld.long 0x00 10. " XPORTACT ,Indicates if a frame is currently being written to the STM" "Not written,Written"
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bitfld.long 0x00 5.--9. " NUMXPORT ,The total number of counters designated for export" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 4. " CCMXPORT ,SW control of CCM message export" "Low,High"
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bitfld.long 0x00 3. " CCMVAIL ,SCTM supports CCM export" "Not supported,Supported"
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textline " "
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bitfld.long 0x00 2. " CSMXPORT ,SW control of CSM message export" "Low,High"
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bitfld.long 0x00 1. " SENDOVR ,Send overflow data in CSM frame" "No,Yes"
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textline " "
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bitfld.long 0x00 0. " ENBL ,STM global enable" "Disabled,Enabled"
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line.long 0x04 "CACHE_SCTM_CTSTMMSTID,Counter Timer STM Master ID Register"
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hexmask.long.byte 0x04 0.--6. 1. " MASTID ,HW Master ID for this module"
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line.long 0x08 "CACHE_SCTM_CTSTMINTVL,Counter Timer STM Interval Register"
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hexmask.long.word 0x08 0.--15. 1. " INTERVAL ,Periodic export interval"
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line.long 0x0c "CACHE_SCTM_CTSTMSEL0,Counter Timer STM Count Select Register 0"
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line.long 0x10 "CACHE_SCTM_CTSTMSEL1,Counter Timer STM Count Select Register 1"
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group.long 0x440++0x03
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line.long 0x00 "CACHE_SCTM_TINTVL_R_I,Counter Timer Interval Number Debug Event Register"
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group.long 0x47c++0x03
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line.long 0x00 "CACHE_SCTM_CTDBGNUM,Counter Timer Number Debug Event Register"
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bitfld.long 0x00 0.--2. " NUMEVT ,Number of input selectors for debug events" "0,1,2,3,4,5,6,7"
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group.long 0x4F0++0x0f
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line.long 0x0 "CACHE_SCTM_CTGNBL0,Counter Timer Global Enable Register 0"
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hexmask.long.byte 0x0 0.--7. 1. " ENABLE ,The counter enable bit-field"
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line.long 0x4 "CACHE_SCTM_CTGNBL1,Counter Timer Global Enable Register 1"
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hexmask.long.byte 0x4 0.--7. 1. " ENABLE ,The counter enable bit-field"
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line.long 0x8 "CACHE_SCTM_CTGRST0,Counter Timer Global Reset Register 0"
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hexmask.long.byte 0x8 0.--7. 1. " RESET ,The counter enable bit-field"
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line.long 0xC "CACHE_SCTM_CTGRST1,Counter Timer Global Reset Register 1"
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hexmask.long.byte 0xC 0.--7. 1. " RESET ,The counter enable bit-field"
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tree "Counter Timer Control Registers 0-31"
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group.long 0x500++0x7f
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line.long 0x0 "CACHE_SCTM_CTCRWT_0,Counter Timer Control Register 0"
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bitfld.long 0x0 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
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bitfld.long 0x0 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
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textline " "
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bitfld.long 0x0 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
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bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
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bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
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textline " "
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bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
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bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
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bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
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textline " "
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bitfld.long 0x0 1. " RESET ,Counter reset control" "No effect,Reset"
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bitfld.long 0x0 0. " ENBL ,Counter enable control" "Disabled,Enabled"
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line.long 0x4 "CACHE_SCTM_CTCRWT_1,Counter Timer Control Register 1"
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bitfld.long 0x4 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
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bitfld.long 0x4 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
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textline " "
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bitfld.long 0x4 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
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bitfld.long 0x4 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
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bitfld.long 0x4 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
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|
textline " "
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bitfld.long 0x4 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
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bitfld.long 0x4 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
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bitfld.long 0x4 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
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textline " "
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bitfld.long 0x4 1. " RESET ,Counter reset control" "No effect,Reset"
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bitfld.long 0x4 0. " ENBL ,Counter enable control" "Disabled,Enabled"
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line.long 0x8 "CACHE_SCTM_CTCRWT_2,Counter Timer Control Register 2"
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bitfld.long 0x8 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x8 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
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bitfld.long 0x8 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
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|
textline " "
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|
bitfld.long 0x8 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
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bitfld.long 0x8 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
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bitfld.long 0x8 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
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|
textline " "
|
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bitfld.long 0x8 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
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bitfld.long 0x8 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
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bitfld.long 0x8 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
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textline " "
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bitfld.long 0x8 1. " RESET ,Counter reset control" "No effect,Reset"
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bitfld.long 0x8 0. " ENBL ,Counter enable control" "Disabled,Enabled"
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line.long 0xC "CACHE_SCTM_CTCRWT_3,Counter Timer Control Register 3"
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bitfld.long 0xC 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xC 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
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bitfld.long 0xC 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
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textline " "
|
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bitfld.long 0xC 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
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bitfld.long 0xC 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
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bitfld.long 0xC 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
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textline " "
|
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bitfld.long 0xC 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
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bitfld.long 0xC 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
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bitfld.long 0xC 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
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textline " "
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bitfld.long 0xC 1. " RESET ,Counter reset control" "No effect,Reset"
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bitfld.long 0xC 0. " ENBL ,Counter enable control" "Disabled,Enabled"
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line.long 0x10 "CACHE_SCTM_CTCRWT_4,Counter Timer Control Register 4"
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bitfld.long 0x10 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
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bitfld.long 0x10 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
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textline " "
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bitfld.long 0x10 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
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bitfld.long 0x10 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
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bitfld.long 0x10 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
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bitfld.long 0x10 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
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bitfld.long 0x10 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
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bitfld.long 0x10 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
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textline " "
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bitfld.long 0x10 1. " RESET ,Counter reset control" "No effect,Reset"
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bitfld.long 0x10 0. " ENBL ,Counter enable control" "Disabled,Enabled"
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line.long 0x14 "CACHE_SCTM_CTCRWT_5,Counter Timer Control Register 5"
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bitfld.long 0x14 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
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bitfld.long 0x14 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
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textline " "
|
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bitfld.long 0x14 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
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bitfld.long 0x14 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
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bitfld.long 0x14 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x14 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
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bitfld.long 0x14 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
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bitfld.long 0x14 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
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textline " "
|
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bitfld.long 0x14 1. " RESET ,Counter reset control" "No effect,Reset"
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bitfld.long 0x14 0. " ENBL ,Counter enable control" "Disabled,Enabled"
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line.long 0x18 "CACHE_SCTM_CTCRWT_6,Counter Timer Control Register 6"
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bitfld.long 0x18 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x18 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
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bitfld.long 0x18 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x18 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x18 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
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bitfld.long 0x18 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
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bitfld.long 0x18 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x18 1. " RESET ,Counter reset control" "No effect,Reset"
|
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bitfld.long 0x18 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
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line.long 0x1C "CACHE_SCTM_CTCRWT_7,Counter Timer Control Register 7"
|
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bitfld.long 0x1C 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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bitfld.long 0x1C 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x1C 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x1C 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x1C 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x1C 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x1C 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x1C 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x20 "CACHE_SCTM_CTCRWT_8,Counter Timer Control Register 8"
|
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bitfld.long 0x20 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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bitfld.long 0x20 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x20 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x20 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x20 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x20 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x20 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x20 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x20 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x20 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x24 "CACHE_SCTM_CTCRWT_9,Counter Timer Control Register 9"
|
|
bitfld.long 0x24 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x24 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x24 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x24 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x24 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x24 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x24 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x24 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x24 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x24 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x24 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x28 "CACHE_SCTM_CTCRWT_10,Counter Timer Control Register 10"
|
|
bitfld.long 0x28 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x28 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x28 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x28 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x28 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x28 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x28 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x28 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x28 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x28 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x28 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x2C "CACHE_SCTM_CTCRWT_11,Counter Timer Control Register 11"
|
|
bitfld.long 0x2C 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x2C 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x2C 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x2C 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x2C 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x2C 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x2C 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x2C 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x2C 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x30 "CACHE_SCTM_CTCRWT_12,Counter Timer Control Register 12"
|
|
bitfld.long 0x30 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x30 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x30 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x30 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x30 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x30 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x30 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x30 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x30 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x30 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x30 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x34 "CACHE_SCTM_CTCRWT_13,Counter Timer Control Register 13"
|
|
bitfld.long 0x34 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x34 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x34 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x34 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x34 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x34 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x34 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x34 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x34 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x34 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x34 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x38 "CACHE_SCTM_CTCRWT_14,Counter Timer Control Register 14"
|
|
bitfld.long 0x38 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x38 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x38 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x38 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x38 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x38 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x38 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x38 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x38 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x38 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x38 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x3C "CACHE_SCTM_CTCRWT_15,Counter Timer Control Register 15"
|
|
bitfld.long 0x3C 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x3C 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x3C 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x3C 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x3C 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x3C 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x3C 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x3C 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x3C 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x3C 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x40 "CACHE_SCTM_CTCRWT_16,Counter Timer Control Register 16"
|
|
bitfld.long 0x40 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x40 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x40 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x40 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x40 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x40 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x40 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x40 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x40 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x40 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x40 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x44 "CACHE_SCTM_CTCRWT_17,Counter Timer Control Register 17"
|
|
bitfld.long 0x44 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x44 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x44 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x44 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x44 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x44 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x44 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x44 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x44 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x44 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x44 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x48 "CACHE_SCTM_CTCRWT_18,Counter Timer Control Register 18"
|
|
bitfld.long 0x48 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x48 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x48 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x48 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x48 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x48 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x48 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x48 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x48 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x48 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x48 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x4C "CACHE_SCTM_CTCRWT_19,Counter Timer Control Register 19"
|
|
bitfld.long 0x4C 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x4C 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x4C 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x4C 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x4C 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x4C 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x4C 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x4C 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x4C 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x4C 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x50 "CACHE_SCTM_CTCRWT_20,Counter Timer Control Register 20"
|
|
bitfld.long 0x50 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x50 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x50 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x50 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x50 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x50 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x50 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x50 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x50 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x50 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x50 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x54 "CACHE_SCTM_CTCRWT_21,Counter Timer Control Register 21"
|
|
bitfld.long 0x54 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x54 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x54 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x54 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x54 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x54 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x54 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x54 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x54 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x54 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x54 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x58 "CACHE_SCTM_CTCRWT_22,Counter Timer Control Register 22"
|
|
bitfld.long 0x58 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x58 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x58 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x58 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x58 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x58 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x58 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x58 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x58 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x58 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x58 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x5C "CACHE_SCTM_CTCRWT_23,Counter Timer Control Register 23"
|
|
bitfld.long 0x5C 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x5C 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x5C 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x5C 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x5C 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x5C 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x5C 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x5C 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x5C 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x5C 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x5C 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x60 "CACHE_SCTM_CTCRWT_24,Counter Timer Control Register 24"
|
|
bitfld.long 0x60 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x60 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x60 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x60 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x60 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x60 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x60 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x60 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x60 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x60 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x60 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x64 "CACHE_SCTM_CTCRWT_25,Counter Timer Control Register 25"
|
|
bitfld.long 0x64 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x64 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x64 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x64 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x64 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x64 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x64 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x64 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x64 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x64 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x64 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x68 "CACHE_SCTM_CTCRWT_26,Counter Timer Control Register 26"
|
|
bitfld.long 0x68 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x68 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x68 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x68 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x68 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x68 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x68 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x68 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x68 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x68 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x68 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x6C "CACHE_SCTM_CTCRWT_27,Counter Timer Control Register 27"
|
|
bitfld.long 0x6C 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x6C 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x6C 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x6C 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x6C 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x6C 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x6C 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x6C 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x6C 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x6C 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x6C 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x70 "CACHE_SCTM_CTCRWT_28,Counter Timer Control Register 28"
|
|
bitfld.long 0x70 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x70 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x70 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x70 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x70 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x70 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x70 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x70 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x70 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x70 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x70 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x74 "CACHE_SCTM_CTCRWT_29,Counter Timer Control Register 29"
|
|
bitfld.long 0x74 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x74 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x74 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x74 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x74 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x74 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x74 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x74 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x74 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x74 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x74 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x78 "CACHE_SCTM_CTCRWT_30,Counter Timer Control Register 30"
|
|
bitfld.long 0x78 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x78 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x78 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x78 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x78 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x78 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x78 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x78 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x78 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x78 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x78 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
line.long 0x7C "CACHE_SCTM_CTCRWT_31,Counter Timer Control Register 31"
|
|
bitfld.long 0x7C 16.--20. " INPSEL ,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x7C 10. " RESTART ,Restart the timer after an interval match." "No restart,Restart"
|
|
bitfld.long 0x7C 9. " DBG ,Signal debug logic on interval match" "No signal,Signal"
|
|
textline " "
|
|
bitfld.long 0x7C 8. " INT ,Generate interrupt on interval match" "Not generated,Generated"
|
|
bitfld.long 0x7C 6. " OVRFLW ,Counter has wrapped since it was last read" "Not wrapped,Wrapped"
|
|
bitfld.long 0x7C 5. " IDLE ,Counter ignores processor IDLE state" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x7C 4. " FREE ,Counter ignores processor debug halt state" "Not ignored,Ignored"
|
|
bitfld.long 0x7C 3. " DURMODE ,Counter is in duration or occurrence mode" "Occurrence,Duration"
|
|
bitfld.long 0x7C 2. " CHAIN ,Counter is chained to an adjacent counter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x7C 1. " RESET ,Counter reset control" "No effect,Reset"
|
|
bitfld.long 0x7C 0. " ENBL ,Counter enable control" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Counter Timer Count Registers 0-31"
|
|
group.long 0x580++0x7f
|
|
line.long 0x0 "CACHE_SCTM_CTCNTR_0,Counter Timer Count Register 0"
|
|
line.long 0x4 "CACHE_SCTM_CTCNTR_1,Counter Timer Count Register 1"
|
|
line.long 0x8 "CACHE_SCTM_CTCNTR_2,Counter Timer Count Register 2"
|
|
line.long 0xC "CACHE_SCTM_CTCNTR_3,Counter Timer Count Register 3"
|
|
line.long 0x10 "CACHE_SCTM_CTCNTR_4,Counter Timer Count Register 4"
|
|
line.long 0x14 "CACHE_SCTM_CTCNTR_5,Counter Timer Count Register 5"
|
|
line.long 0x18 "CACHE_SCTM_CTCNTR_6,Counter Timer Count Register 6"
|
|
line.long 0x1C "CACHE_SCTM_CTCNTR_7,Counter Timer Count Register 7"
|
|
line.long 0x20 "CACHE_SCTM_CTCNTR_8,Counter Timer Count Register 8"
|
|
line.long 0x24 "CACHE_SCTM_CTCNTR_9,Counter Timer Count Register 9"
|
|
line.long 0x28 "CACHE_SCTM_CTCNTR_10,Counter Timer Count Register 10"
|
|
line.long 0x2C "CACHE_SCTM_CTCNTR_11,Counter Timer Count Register 11"
|
|
line.long 0x30 "CACHE_SCTM_CTCNTR_12,Counter Timer Count Register 12"
|
|
line.long 0x34 "CACHE_SCTM_CTCNTR_13,Counter Timer Count Register 13"
|
|
line.long 0x38 "CACHE_SCTM_CTCNTR_14,Counter Timer Count Register 14"
|
|
line.long 0x3C "CACHE_SCTM_CTCNTR_15,Counter Timer Count Register 15"
|
|
line.long 0x40 "CACHE_SCTM_CTCNTR_16,Counter Timer Count Register 16"
|
|
line.long 0x44 "CACHE_SCTM_CTCNTR_17,Counter Timer Count Register 17"
|
|
line.long 0x48 "CACHE_SCTM_CTCNTR_18,Counter Timer Count Register 18"
|
|
line.long 0x4C "CACHE_SCTM_CTCNTR_19,Counter Timer Count Register 19"
|
|
line.long 0x50 "CACHE_SCTM_CTCNTR_20,Counter Timer Count Register 20"
|
|
line.long 0x54 "CACHE_SCTM_CTCNTR_21,Counter Timer Count Register 21"
|
|
line.long 0x58 "CACHE_SCTM_CTCNTR_22,Counter Timer Count Register 22"
|
|
line.long 0x5C "CACHE_SCTM_CTCNTR_23,Counter Timer Count Register 23"
|
|
line.long 0x60 "CACHE_SCTM_CTCNTR_24,Counter Timer Count Register 24"
|
|
line.long 0x64 "CACHE_SCTM_CTCNTR_25,Counter Timer Count Register 25"
|
|
line.long 0x68 "CACHE_SCTM_CTCNTR_26,Counter Timer Count Register 26"
|
|
line.long 0x6C "CACHE_SCTM_CTCNTR_27,Counter Timer Count Register 27"
|
|
line.long 0x70 "CACHE_SCTM_CTCNTR_28,Counter Timer Count Register 28"
|
|
line.long 0x74 "CACHE_SCTM_CTCNTR_29,Counter Timer Count Register 29"
|
|
line.long 0x78 "CACHE_SCTM_CTCNTR_30,Counter Timer Count Register 30"
|
|
line.long 0x7C "CACHE_SCTM_CTCNTR_31,Counter Timer Count Register 31"
|
|
tree.end
|
|
tree.end
|
|
tree "Page Address Registers"
|
|
width 25.
|
|
tree "Large Pages 0-3"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "CACHE_MMU_LARGE_ADDR_0,Large Page 0 Address Register"
|
|
bitfld.long 0x00 28.--31. " ADDRESS ,Logical source address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x800+0x20)++0x03
|
|
line.long 0x00 "CACHE_MMU_LARGE_XLTE_0,Large Page 0 Translated Address Register"
|
|
bitfld.long 0x00 28.--31. " ADDRESS ,Logical source address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x800+0x40)++0x03
|
|
line.long 0x00 "CACHE_MMU_LARGE_POLY_0,Large Page 0 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "32MB,512MB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "CACHE_MMU_LARGE_ADDR_1,Large Page 1 Address Register"
|
|
bitfld.long 0x00 28.--31. " ADDRESS ,Logical source address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x804+0x20)++0x03
|
|
line.long 0x00 "CACHE_MMU_LARGE_XLTE_1,Large Page 1 Translated Address Register"
|
|
bitfld.long 0x00 28.--31. " ADDRESS ,Logical source address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x804+0x40)++0x03
|
|
line.long 0x00 "CACHE_MMU_LARGE_POLY_1,Large Page 1 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "32MB,512MB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "CACHE_MMU_LARGE_ADDR_2,Large Page 2 Address Register"
|
|
bitfld.long 0x00 28.--31. " ADDRESS ,Logical source address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x808+0x20)++0x03
|
|
line.long 0x00 "CACHE_MMU_LARGE_XLTE_2,Large Page 2 Translated Address Register"
|
|
bitfld.long 0x00 28.--31. " ADDRESS ,Logical source address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x808+0x40)++0x03
|
|
line.long 0x00 "CACHE_MMU_LARGE_POLY_2,Large Page 2 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "32MB,512MB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "CACHE_MMU_LARGE_ADDR_3,Large Page 3 Address Register"
|
|
bitfld.long 0x00 28.--31. " ADDRESS ,Logical source address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x80C+0x20)++0x03
|
|
line.long 0x00 "CACHE_MMU_LARGE_XLTE_3,Large Page 3 Translated Address Register"
|
|
bitfld.long 0x00 28.--31. " ADDRESS ,Logical source address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x80C+0x40)++0x03
|
|
line.long 0x00 "CACHE_MMU_LARGE_POLY_3,Large Page 3 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "32MB,512MB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Medium Pages 0-1"
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "CACHE_MMU_MED_ADDR_0,Medium Page 0 Address Register"
|
|
hexmask.long.word 0x00 17.--31. 0x02 " ADDRESS ,Logical source address"
|
|
group.long (0x860+0x40)++0x03
|
|
line.long 0x00 "CACHE_MMU_MED_XLTE_0,Medium Page 0 Translated Address Register"
|
|
hexmask.long.word 0x00 17.--31. 0x02 " ADDRESS ,Logical Destination address"
|
|
group.long (0x860+0x80)++0x03
|
|
line.long 0x00 "CACHE_MMU_MED_POLY_0,Medium Page 0 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "128KB,256KB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
group.long 0x864++0x03
|
|
line.long 0x00 "CACHE_MMU_MED_ADDR_1,Medium Page 1 Address Register"
|
|
hexmask.long.word 0x00 17.--31. 0x02 " ADDRESS ,Logical source address"
|
|
group.long (0x864+0x40)++0x03
|
|
line.long 0x00 "CACHE_MMU_MED_XLTE_1,Medium Page 1 Translated Address Register"
|
|
hexmask.long.word 0x00 17.--31. 0x02 " ADDRESS ,Logical Destination address"
|
|
group.long (0x864+0x80)++0x03
|
|
line.long 0x00 "CACHE_MMU_MED_POLY_1,Medium Page 1 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "128KB,256KB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Small Pages 0-9"
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_ADDR_0,Small Page 0 Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical source address"
|
|
group.long (0x920+0x80)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_XLTE_0,Small Page 0 Translated Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical Destination address"
|
|
group.long (0x920+0x100)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_POLY_0,Small Page 0 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "128KB,256KB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
group.long 0x924++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_ADDR_1,Small Page 1 Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical source address"
|
|
group.long (0x924+0x80)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_XLTE_1,Small Page 1 Translated Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical Destination address"
|
|
group.long (0x924+0x100)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_POLY_1,Small Page 1 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "128KB,256KB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_ADDR_2,Small Page 2 Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical source address"
|
|
group.long (0x928+0x80)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_XLTE_2,Small Page 2 Translated Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical Destination address"
|
|
group.long (0x928+0x100)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_POLY_2,Small Page 2 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "128KB,256KB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
group.long 0x92C++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_ADDR_3,Small Page 3 Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical source address"
|
|
group.long (0x92C+0x80)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_XLTE_3,Small Page 3 Translated Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical Destination address"
|
|
group.long (0x92C+0x100)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_POLY_3,Small Page 3 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "128KB,256KB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_ADDR_4,Small Page 4 Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical source address"
|
|
group.long (0x930+0x80)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_XLTE_4,Small Page 4 Translated Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical Destination address"
|
|
group.long (0x930+0x100)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_POLY_4,Small Page 4 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "128KB,256KB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
group.long 0x934++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_ADDR_5,Small Page 5 Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical source address"
|
|
group.long (0x934+0x80)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_XLTE_5,Small Page 5 Translated Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical Destination address"
|
|
group.long (0x934+0x100)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_POLY_5,Small Page 5 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "128KB,256KB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
group.long 0x938++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_ADDR_6,Small Page 6 Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical source address"
|
|
group.long (0x938+0x80)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_XLTE_6,Small Page 6 Translated Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical Destination address"
|
|
group.long (0x938+0x100)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_POLY_6,Small Page 6 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "128KB,256KB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
group.long 0x93C++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_ADDR_7,Small Page 7 Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical source address"
|
|
group.long (0x93C+0x80)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_XLTE_7,Small Page 7 Translated Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical Destination address"
|
|
group.long (0x93C+0x100)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_POLY_7,Small Page 7 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "128KB,256KB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_ADDR_8,Small Page 8 Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical source address"
|
|
group.long (0x940+0x80)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_XLTE_8,Small Page 8 Translated Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical Destination address"
|
|
group.long (0x940+0x100)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_POLY_8,Small Page 8 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "128KB,256KB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
group.long 0x944++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_ADDR_9,Small Page 9 Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical source address"
|
|
group.long (0x944+0x80)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_XLTE_9,Small Page 9 Translated Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Logical Destination address"
|
|
group.long (0x944+0x100)++0x03
|
|
line.long 0x00 "CACHE_MMU_SMALL_POLY_9,Small Page 9 Policy Register"
|
|
bitfld.long 0x00 23. " L2_WR_POLICY ,L2 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 22. " L2_ALLOCATE ,L2 allocate policy" "No allocation,Follow sideband"
|
|
bitfld.long 0x00 21. " L2_POSTED ,L2 posted policy" "Not posted,Posted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L2_CACHEABLE ,L2 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 19. " L1_WR_POLICY ,L1 write policy" "Write through,Write back"
|
|
bitfld.long 0x00 18. " L1_ALLOCATE ,L1 allocate policy" "No allocation,Follow sideband"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L1_POSTED ,L1 posted policy" "Not posted,Posted"
|
|
bitfld.long 0x00 16. " L1_CACHEABLE ,L1 cache policy" "Non cacheable,Cacheable"
|
|
bitfld.long 0x00 7. " EXCLUSION ,Cache exclusion" "No exclusion,Exclusion"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PRELOAD ,Preload region" "No preload,Preload"
|
|
bitfld.long 0x00 5. " READ ,Preload region" "Low,High"
|
|
bitfld.long 0x00 4. " EXECUTE ,Execute only" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VOLATILE ,Volatile qualifier" "Not followed,Followed"
|
|
bitfld.long 0x00 1. " SIZE ,Size of page" "128KB,256KB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable page" "Disabled,Enabled"
|
|
tree.end
|
|
group.long 0xca8++0x13
|
|
line.long 0x00 "CACHE_MMU_MAINT,MMU Start/End Maintenance Config Register"
|
|
bitfld.long 0x00 10. " G_FLUSH ,Global flush bit" "No effect,Flushed"
|
|
bitfld.long 0x00 9. " L2_CACHE ,Do maintenance operation in L2 Cache" "No effect,Operation"
|
|
bitfld.long 0x00 8. " L1_CACHE2 ,Do maintenance operation in L1 Cache 2" "No effect,Operation"
|
|
textline " "
|
|
bitfld.long 0x00 7. " L1_CACHE1 ,Do maintenance operation in L1 Cache1" "No effect,Operation"
|
|
bitfld.long 0x00 6. " CPU_INTERRUPT ,Generate interrupt to cpu when maintenance operation initiated by CPU is complete" "No,Yes"
|
|
bitfld.long 0x00 5. " HOST_INTERRUPT ,Generate interrupt when maintenance operation is complete" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INVALIDATE ,Invalidate lines in region defined by maintenance start/end addresses" "No effect,Invalidate"
|
|
bitfld.long 0x00 3. " CLEAN ,Evict dirty lines in region defined by maintenance start/end addresses" "No effect,Clean"
|
|
bitfld.long 0x00 2. " UNLOCK ,Unlock region defined by maintenance start/end addresses" "No effect,Unlock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOCK ,Lock region defined by maintenance start/end addresses" "No effect,Lock"
|
|
bitfld.long 0x00 0. " PRELOAD ,Preload region defined by maintenance start/end addresses" "No effect,Preload"
|
|
line.long 0x04 "CACHE_MMU_MTSTART, Maintenance Start Address Register"
|
|
line.long 0x08 "CACHE_MTEND,Maintenance End Address Register"
|
|
line.long 0x0c "CACHE_MMU_MAINTST,Maintenance Status Register"
|
|
bitfld.long 0x0c 0. " STATUS ,Status bit" "Maintenance completed,Maintenance ongoing"
|
|
line.long 0x10 "CACHE_MMU_MMUCONFIG,MMU Configuration Register"
|
|
bitfld.long 0x010 1. " PRIVILEDGE ,Privilege bit [CPU access]" "Everything,Mantenance and DMA"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.open "MMU (Memory Management Unit)"
|
|
tree "L2 MMU"
|
|
base ad:0x55082000
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "MMU_REVISION,IP Revision Code"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!cpuis("DM8165"))&&(!cpuis("DM8166"))&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")&&(!cpuis("DM8167"))&&(!cpuis("DM8168"))&&(!cpuis("DM8165DSP"))&&(!cpuis("DM8166DSP"))&&(!cpuis("DM8167DSP"))&&(!cpuis("DM8168DSP"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP Revision"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MMU_SYSCONFIG,Various Parameters Of The Interconnect Interface"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "Switched off,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode" "Force,No idle,Smart,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Always,Never"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interconnect clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MMU_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "MMU_IRQSTATUS,Interrupt Status Register"
|
|
eventfld.long 0x00 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB (MultiHitFault)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " TABLEWALKFAULT ,Error response received during a table walk (TableWalkFault)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 2. " EMUMISS ,Unrecoverable TLB miss during debug (EMUMiss)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (TranslationFault)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TLBMISS ,Unrecoverable TLB miss" "False,Pending"
|
|
line.long 0x04 "MMU_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TABLEWALKFAULT ,Error response received during a table walk" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EMUMISS ,Unrecoverable TLB miss during debug" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TLBMISS ,Unrecoverable TLB miss" "Masked,Enabled"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "MMU_WALKING_ST,Status Information About The Table Walking Logic"
|
|
bitfld.long 0x00 0. " TWLRUNNING ,Table walking logic is running" "Completed,Running"
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "MMU_CNTL,MMU Features"
|
|
bitfld.long 0x00 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TWLENABLE ,Table walking logic enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MMUENABLE ,MMU enable" "Disabled,Enabled"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x00 "MMU_FAULT_AD,Virtual Address That Generated The Interrupt"
|
|
group.long 0x4C++0x7
|
|
line.long 0x00 "MMU_TTB,Resolution Table Base Address"
|
|
hexmask.long 0x00 7.--31. 0x80 " TTBADDRESS ,Translation table base address"
|
|
line.long 0x04 "MMU_LOCK,Lock the TLB entries to be read"
|
|
bitfld.long 0x04 10.--14. " BASEVALUE ,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 4.--8. " CURRENTVICTIM ,Eentry updated by the TWL/by the software/TLB entry read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x54++0x13
|
|
line.long 0x00 "MMU_LD_TLB,Loads A TLB Entry"
|
|
bitfld.long 0x00 0. " LDTLBITEM ,Write (load) data in the TLB" "No effect,Load"
|
|
line.long 0x04 "MMU_CAM,CAM Entry"
|
|
hexmask.long.tbyte 0x04 12.--31. 0x10 " VATAG ,Virtual address tag"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P ,Preserved bit (TLB entry flushed)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 2. " V ,Valid bit (TLB entry)" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " PAGESIZE ,Page size" "1MB,64KB,4KB,16MB"
|
|
line.long 0x08 "MMU_RAM,RAM Entry"
|
|
hexmask.long.tbyte 0x08 12.--31. 0x10 " PHYSICALADDRESS ,Physical address of the page"
|
|
textline " "
|
|
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
|
|
bitfld.long 0x08 9. " ENDIANNESS ,Endianness of the page" "Little endian,?..."
|
|
else
|
|
bitfld.long 0x08 9. " ENDIANNESS ,Endianness of the page" "Little endian,Big endian"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 7.--8. " ELEMENTSIZE ,Element size of the page" "8 bits,16 bits,32 bits,No translation"
|
|
textline " "
|
|
bitfld.long 0x08 6. " MIXED ,Mixed page attribute (use CPU element size)" "TLB,CPU"
|
|
line.long 0x0C "MMU_GFLUSH,Flushes All The Non-protected TLB Entries"
|
|
bitfld.long 0x0C 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries" "No effect,Flush"
|
|
line.long 0x10 "MMU_FLUSH_ENTRY,Flushes The Entry Pointed To By The CAM Virtual Address"
|
|
bitfld.long 0x10 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address" "No effect,Flush"
|
|
rgroup.long 0x68++0xB
|
|
line.long 0x00 "MMU_READ_CAM,Reads CAM Data From A CAM Entry"
|
|
hexmask.long 0x00 12.--31. 0x1000 " VATAG ,Virtual address tag"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P ,Preserved bit (TLB entry flushed)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " V ,Valid bit (TLB entry)" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PAGESIZE ,Page size" "1MB,64KB,4KB,16MB"
|
|
line.long 0x04 "MMU_READ_RAM,Reads RAM Data From A RAM Entry"
|
|
hexmask.long 0x04 12.--31. 0x1000 " PHYSICALADDRESS ,Physical address of the page"
|
|
textline " "
|
|
bitfld.long 0x04 9. " ENDIANNESS ,Endianness of the page" "Little endian,Big endian"
|
|
textline " "
|
|
bitfld.long 0x04 7.--8. " ELEMENTSIZE ,Element size of the page" "8 bits,16 bits,32 bits,No translation"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MIXED ,Mixed page attribute (use CPU element size)" "TLB,CPU"
|
|
line.long 0x08 "MMU_EMU_FAULT_AD,Last Virtual Address Of A Fault Caused By The Debugger"
|
|
sif (cpuis("AM389*")||cpuis("C6A816*")||cpu()=="DM8147DSP"||cpu()=="DM8148DSP"||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP")||cpuis("DRA62*"))
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x00 "MMU_FAULT_PC,MMU Fault Caused By CPU Program Counter Value"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "DSP and EDMA MMU"
|
|
base ad:0x48010000
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "MMU_REVISION,IP Revision Code"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!cpuis("DM8165"))&&(!cpuis("DM8166"))&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")&&(!cpuis("DM8167"))&&(!cpuis("DM8168"))&&(!cpuis("DM8165DSP"))&&(!cpuis("DM8166DSP"))&&(!cpuis("DM8167DSP"))&&(!cpuis("DM8168DSP"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP Revision"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MMU_SYSCONFIG,Various Parameters Of The Interconnect Interface"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "Switched off,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode" "Force,No idle,Smart,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Always,Never"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interconnect clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MMU_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "MMU_IRQSTATUS,Interrupt Status Register"
|
|
eventfld.long 0x00 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB (MultiHitFault)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " TABLEWALKFAULT ,Error response received during a table walk (TableWalkFault)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 2. " EMUMISS ,Unrecoverable TLB miss during debug (EMUMiss)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (TranslationFault)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TLBMISS ,Unrecoverable TLB miss" "False,Pending"
|
|
line.long 0x04 "MMU_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TABLEWALKFAULT ,Error response received during a table walk" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EMUMISS ,Unrecoverable TLB miss during debug" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TLBMISS ,Unrecoverable TLB miss" "Masked,Enabled"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "MMU_WALKING_ST,Status Information About The Table Walking Logic"
|
|
bitfld.long 0x00 0. " TWLRUNNING ,Table walking logic is running" "Completed,Running"
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "MMU_CNTL,MMU Features"
|
|
bitfld.long 0x00 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TWLENABLE ,Table walking logic enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MMUENABLE ,MMU enable" "Disabled,Enabled"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x00 "MMU_FAULT_AD,Virtual Address That Generated The Interrupt"
|
|
group.long 0x4C++0x7
|
|
line.long 0x00 "MMU_TTB,Resolution Table Base Address"
|
|
hexmask.long 0x00 7.--31. 0x80 " TTBADDRESS ,Translation table base address"
|
|
line.long 0x04 "MMU_LOCK,Lock the TLB entries to be read"
|
|
bitfld.long 0x04 10.--14. " BASEVALUE ,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 4.--8. " CURRENTVICTIM ,Eentry updated by the TWL/by the software/TLB entry read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x54++0x13
|
|
line.long 0x00 "MMU_LD_TLB,Loads A TLB Entry"
|
|
bitfld.long 0x00 0. " LDTLBITEM ,Write (load) data in the TLB" "No effect,Load"
|
|
line.long 0x04 "MMU_CAM,CAM Entry"
|
|
hexmask.long.tbyte 0x04 12.--31. 0x10 " VATAG ,Virtual address tag"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P ,Preserved bit (TLB entry flushed)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 2. " V ,Valid bit (TLB entry)" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " PAGESIZE ,Page size" "1MB,64KB,4KB,16MB"
|
|
line.long 0x08 "MMU_RAM,RAM Entry"
|
|
hexmask.long.tbyte 0x08 12.--31. 0x10 " PHYSICALADDRESS ,Physical address of the page"
|
|
textline " "
|
|
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
|
|
bitfld.long 0x08 9. " ENDIANNESS ,Endianness of the page" "Little endian,?..."
|
|
else
|
|
bitfld.long 0x08 9. " ENDIANNESS ,Endianness of the page" "Little endian,Big endian"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 7.--8. " ELEMENTSIZE ,Element size of the page" "8 bits,16 bits,32 bits,No translation"
|
|
textline " "
|
|
bitfld.long 0x08 6. " MIXED ,Mixed page attribute (use CPU element size)" "TLB,CPU"
|
|
line.long 0x0C "MMU_GFLUSH,Flushes All The Non-protected TLB Entries"
|
|
bitfld.long 0x0C 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries" "No effect,Flush"
|
|
line.long 0x10 "MMU_FLUSH_ENTRY,Flushes The Entry Pointed To By The CAM Virtual Address"
|
|
bitfld.long 0x10 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address" "No effect,Flush"
|
|
rgroup.long 0x68++0xB
|
|
line.long 0x00 "MMU_READ_CAM,Reads CAM Data From A CAM Entry"
|
|
hexmask.long 0x00 12.--31. 0x1000 " VATAG ,Virtual address tag"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P ,Preserved bit (TLB entry flushed)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " V ,Valid bit (TLB entry)" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PAGESIZE ,Page size" "1MB,64KB,4KB,16MB"
|
|
line.long 0x04 "MMU_READ_RAM,Reads RAM Data From A RAM Entry"
|
|
hexmask.long 0x04 12.--31. 0x1000 " PHYSICALADDRESS ,Physical address of the page"
|
|
textline " "
|
|
bitfld.long 0x04 9. " ENDIANNESS ,Endianness of the page" "Little endian,Big endian"
|
|
textline " "
|
|
bitfld.long 0x04 7.--8. " ELEMENTSIZE ,Element size of the page" "8 bits,16 bits,32 bits,No translation"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MIXED ,Mixed page attribute (use CPU element size)" "TLB,CPU"
|
|
line.long 0x08 "MMU_EMU_FAULT_AD,Last Virtual Address Of A Fault Caused By The Debugger"
|
|
sif (cpuis("AM389*")||cpuis("C6A816*")||cpu()=="DM8147DSP"||cpu()=="DM8148DSP"||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP")||cpuis("DRA62*"))
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x00 "MMU_FAULT_PC,MMU Fault Caused By CPU Program Counter Value"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.open "System Control"
|
|
tree "CCM (Chip Control Module)"
|
|
base ad:0x48140000
|
|
sif (cpuis("DRA62*"))
|
|
width 19.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "CONTROL_REVISION,Control Module Revision Register"
|
|
bitfld.long 0x00 30.--31. " IP_REV_SCHEME ,Register scheme" "Legacy,New,?..."
|
|
hexmask.long.word 0x00 16.--27. 1. " IP_REV_FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " IP_REV_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " IP_REV_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " IP_REV_CUSTOM ,Special version for a particular device" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " IP_REV_MINOR ,Minor Revision (Y)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CONTROL_HWINFO,Control Module Hardware Info Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "CONTROL_SYSCONFIG,System Configuration Register"
|
|
rbitfld.long 0x00 4.--5. " STANDBY ,Configure local initiator state management" "Force Standby,No Standby,Smart Standby,Smart Standby wakeup capable"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Configure module slave interface state management" "Force Idle,No Idle,Smart Idle,Smart Idle wakeup capable"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FREEEMU ,Sensitivity to Emulation suspend input" "Sensitive,Not sensitive"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "CONTROL_STATUS,Control Status Register"
|
|
bitfld.long 0x00 26. " BOOT[11] ,Reset output (RSTOUT) configuration" "OR of 3 WD Timer,3 WD timer reset + PRCM"
|
|
bitfld.long 0x00 25. " BOOT[10] ,NAND boot mode ECC control" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BOOT_14_13 ,GPMC CS0 Default Address Muxing" "No Addr/Data,Addr/Data,Addr/Addr/Data,?..."
|
|
bitfld.long 0x00 17. " BOOT_15 ,GPMC CS0 Default Wait Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BOOT_12 ,GPMC CS0 Default Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8.--10. " DEVTYPE ,Device Type" "Reserved,Reserved,Reserved,General purpose,Reserved,Reserved,Reserved,Bad"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " BOOT_4_0 ,System Boot Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "BOOTSTAT,Boot Status Register"
|
|
bitfld.long 0x00 16.--19. " BOOTERR ,Boot Error" "No error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error"
|
|
bitfld.long 0x00 0. " BC ,Boot Complete" "Not completed,Completed"
|
|
line.long 0x04 "DSPBOOTADDR,DSP Boot Address Register"
|
|
hexmask.long.tbyte 0x04 10.--31. 0x4 " BOOTADDR ,DSP Boot Address (upper 22 bits)"
|
|
rbitfld.long 0x04 0. " RSTDONE ,DSP Reset Done" "Not done,Done"
|
|
group.long 0x60++0x13
|
|
line.long 0x00 "MMR_LOCK0,Lock/Unlock Register for Region 0x0400 - 0x05FF"
|
|
line.long 0x04 "MMR_LOCK1,Lock/Unlock Register for Region 0x0600 - 0x07FF"
|
|
line.long 0x08 "MMR_LOCK2,Lock/Unlock Register for Region 0x0800 - 0x0fFF"
|
|
line.long 0x0c "MMR_LOCK3,Lock/Unlock Register for Region 0x1000 - 0x12FF"
|
|
line.long 0x10 "MMR_LOCK4,Lock/Unlock Register for Region 0x1300 - 0x17FF"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CONTROL_SEC_CTL,Control Module Second Control Register"
|
|
bitfld.long 0x00 3. " WD0OPDISABLE ,Watch Dog Timer disable" "No,Yes"
|
|
group.long 0x468++0x7
|
|
line.long 0x00 "DEVOSC,Device Oscilator Register"
|
|
bitfld.long 0x00 0. " RESELECT ,Internal feedback resistor select" "Used,Not used"
|
|
line.long 0x04 "AUXOSC,Auxilliary Oscillator Register"
|
|
bitfld.long 0x04 3. " GZ ,Oscillator disable" "No,Yes"
|
|
bitfld.long 0x04 2. " SW2 ,Select 15-35 MHz range" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SW1 ,Select 15-35 MHz range" "Low,High"
|
|
bitfld.long 0x04 0. " RESELECT ,Internal feedback resistor select" "Used,Not used"
|
|
group.long 0x480++0x3
|
|
line.long 0x00 "PCIE_CFG,PCIE Configuration Register"
|
|
bitfld.long 0x00 31. " PCIE_TERM_ENABLE ,PCIE Termination enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " PCIE_TERM_VALUE ,PCIE Termination value" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PCIDEVTYPE ,PCI device type" "EP,Legazy EP,Root Complex,?..."
|
|
rgroup.long 0x600++0x7
|
|
line.long 0x00 "DEVICE_ID,Device Identification Register"
|
|
bitfld.long 0x00 28.--31. " DEVREV ,Device revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 12.--27. 1. " PARTNUM ,Device part number"
|
|
textline " "
|
|
hexmask.long.word 0x00 1.--11. 1. " MFGR ,Manufacturer's JTAG ID"
|
|
line.long 0x04 "DEV_FEATURE,Device Feature Set Register"
|
|
bitfld.long 0x04 31. " DSP ,C674x DSP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " SGX530 ,3D-Graphics Module (SGX530) Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PCIE ,PCIE Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " VCP ,VCP2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " MLB ,MLB Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " ATL ,ATL Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " ICSS ,ICSS Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " BITBLT ,2D BitBlt Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " THREECC ,3CC Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VIP2 ,Enable VIP2 pins" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " GMII1_RMII1 ,Enable GMII1/RMII1 pins" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MACROV ,Macrovision Enable" "Disabled,Enabled"
|
|
group.long 0x608++0xf
|
|
line.long 0x00 "INIT_PRIORITY_0,Initiator Priority 0 Register"
|
|
bitfld.long 0x00 30.--31. " TCWR3 ,EDMA3TC 3 Write Port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " TCRD3 ,EDMA3TC 3 Read Port initiator priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " TCWR2 ,EDMA3TC 2 Write Port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " TCRD2 ,EDMA3TC 2 Read Port initiator priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " TCWR1 ,EDMA3TC 1 Write Port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " TCRD1 ,EDMA3TC 1 Read Port initiator priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TCWR0 ,EDMA3TC 0 Write Port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " TCRD0 ,EDMA3TC 0 Read Port initiator priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " P1500 ,P1500 Port Initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " BITBLT ,BitBlt (MMU) Port Initiator PrioritY" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DSS1 ,Display Subsystem Port 1 initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DSS0 ,Display Subsystem Port 0 initiator priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MMU ,System MMU initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DSP_CFG ,DSP CFG port initiator priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DSP_MDMA ,DSP MDMA port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " HOST_ARM ,Host Cortex A8 initiator priority" "0,1,2,3"
|
|
line.long 0x04 "INIT_PRIORITY_1,Initiator Priority 1 Register"
|
|
bitfld.long 0x04 24.--25. " DEBUG ,Debug Subsystem initiator priority" "0,1,2,3"
|
|
textline " "
|
|
sif (cpu()!="DRA623")
|
|
bitfld.long 0x04 20.--21. " GRFX ,SGX530 initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 18.--19. " PRUSS1 ,PRUSS1 Initiator Priority" "0,1,2,3"
|
|
else
|
|
bitfld.long 0x04 18.--19. " PRUSS1 ,PRUSS1 Initiator Priority" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " PCIE ,PCIe initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " DSS_CTLR ,DSS Controller (Media Controller) initiator priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " SECURITYSS ,Security Subsystem initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 10.--11. " HOST_ARM1 ,Host Cortex A8 initiator priority (128b port)" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " USB_QMGR ,USB Queue Manager initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " USB_DMA ,USB DMA port initiator priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " PRUSS0 ,PRUSS0 initiator Priority" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " EMACSS ,3PGSW initiator priority" "0,1,2,3"
|
|
line.long 0x08 "MMU_CFG,MMU Configuration Register"
|
|
bitfld.long 0x08 15. " MMU_ABORT ,MMU abort operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " BITBLT_MMU_ABORT ,MMU abort operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MMU_EN ,MMU Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " BITBLT_MMU ,BitBlt MMU enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DSP_BYPASS_EN ,DSP Bypass Enable" "Low,High"
|
|
bitfld.long 0x08 1. " TC1MMU ,TPTC1 Uses MMU" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TC0MMU ,TPTC0 Uses MMU" "Low,High"
|
|
line.long 0x0c "TPTC_CFG,TPTC Configuration Register"
|
|
bitfld.long 0x0C 6.--7. " TC3DBS ,TC3 Default Burst Size" "16 byte,32 byte,64 byte,128 byte"
|
|
bitfld.long 0x0C 4.--5. " TC2DBS ,TC2 Default Burst Size" "16 byte,32 byte,64 byte,128 byte"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " TC1DBS ,TC1 Default Burst Size" "16 byte,32 byte,64 byte,128 byte"
|
|
bitfld.long 0x0C 0.--1. " TC0DBS ,TC0 Default Burst Size" "16 byte,32 byte,64 byte,128 byte"
|
|
group.long 0x61c++0x3
|
|
line.long 0x00 "DSP_IDLE_CFG,DSP Standby/Idle Management Register"
|
|
bitfld.long 0x00 15. " DSPSTBY ,Assert DSP Standby" "De-asserted,Asserted"
|
|
bitfld.long 0x00 4.--5. " STBYMODE ,Initiator state management mode" "Force-standby,No-standby,Smart-standby,Smart-standby wakeup-capable"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
|
|
tree "USB Registers"
|
|
group.long 0x620++0x3
|
|
line.long 0x00 "USB_CTRL0,USB Control Register 0"
|
|
bitfld.long 0x00 31. " SPAREIN7 ,PHY SPAREIN7 ports" "Low,High"
|
|
bitfld.long 0x00 30. " SPAREIN6 ,PHY SPAREIN6 ports" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SPAREIN5 ,PHY SPAREIN5 ports" "Low,High"
|
|
bitfld.long 0x00 28. " SPAREIN4 ,PHY SPAREIN4 ports" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SPAREIN3 ,PHY SPAREIN3 ports" "Low,High"
|
|
bitfld.long 0x00 26. " SPAREIN2 ,PHY SPAREIN2 ports" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPAREIN1 ,PHY SPAREIN1 ports" "Low,High"
|
|
bitfld.long 0x00 24. " SPAREIN0 ,PHY SPAREIN0 ports" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DATAPOLARITY_INV ,Data Polarity Invert" "Not inverted (DP/DM),Inverted (DM/DP)"
|
|
bitfld.long 0x00 20. " OTGSESSENDEN ,Session End Detect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OTGVDET_EN ,VBUS Detect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DMGPIO_PD ,Pull-down on DM in GPIO Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DPGPIO_PD ,Pull-down on DP in GPIO Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DMINPUT ,DM Input in GPIO Mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DPINPUT ,DP Input in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 14. " DMOPBUFCTL ,DM Output Buffer Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DPOPBUFCTL ,DP Output Buffer Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " GPIOMODE ,GPIO Mode" "USB,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CDET_EXTCTL ,Bypass the charger detection state machine" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 9. " DPPULLUP ,Pull-up on DP line" "No effect,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMPULLUP ,Pull-up on DM line" "No effect,Pull-up"
|
|
bitfld.long 0x00 7. " CHGVSRC_EN ,Enable VSRC on DP line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CHGISINK_EN ,Enable ISINK on DM line" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SINKONDP ,Sink on DP" "DM,DP"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SRCONDM ,Source on DM" "DP,DM"
|
|
bitfld.long 0x00 3. " CHGDET_RSTRT ,Restart Charger Detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHGDET_DIS ,Charger Detect Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " OTG_PWRDN ,Power down the USB OTG PHY" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM_PWRDN ,Power down the USB CM PHY" "Not powered down,Powered down"
|
|
rgroup.long (0x620+0x4)++0x3
|
|
line.long 0x00 "USB_STS0,USB Status Register 0"
|
|
bitfld.long 0x00 13. " GPIO_DMOUT ,Data on DM in GPIO mode" "No data,Data"
|
|
bitfld.long 0x00 12. " GPIO_DPOUT ,Data on DP in GPIO mode" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " CHGDETSTS ,Charge Detection Status" "Wait State,No Contact,PS/2,Error,Dedicated,HOST,PC,Interrupt"
|
|
bitfld.long 0x00 4. " CDET_DMDET ,DM Comparator Output Detection" "Not deteced,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CDET_DPDET ,DP Comparator Output Detection" "Not deteced,Detected"
|
|
bitfld.long 0x00 2. " CDET_DATADET ,Charger Comparator Output Detection" "Not deteced,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHGDETECT ,Charger Detection Status" "Not deteced,Detected"
|
|
bitfld.long 0x00 0. " CHGDETDONE ,Charger Detection Protocol Done" "Not done,Done"
|
|
group.long 0x628++0x3
|
|
line.long 0x00 "USB_CTRL1,USB Control Register 1"
|
|
bitfld.long 0x00 31. " SPAREIN7 ,PHY SPAREIN7 ports" "Low,High"
|
|
bitfld.long 0x00 30. " SPAREIN6 ,PHY SPAREIN6 ports" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SPAREIN5 ,PHY SPAREIN5 ports" "Low,High"
|
|
bitfld.long 0x00 28. " SPAREIN4 ,PHY SPAREIN4 ports" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SPAREIN3 ,PHY SPAREIN3 ports" "Low,High"
|
|
bitfld.long 0x00 26. " SPAREIN2 ,PHY SPAREIN2 ports" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPAREIN1 ,PHY SPAREIN1 ports" "Low,High"
|
|
bitfld.long 0x00 24. " SPAREIN0 ,PHY SPAREIN0 ports" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DATAPOLARITY_INV ,Data Polarity Invert" "Not inverted (DP/DM),Inverted (DM/DP)"
|
|
bitfld.long 0x00 20. " OTGSESSENDEN ,Session End Detect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OTGVDET_EN ,VBUS Detect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DMGPIO_PD ,Pull-down on DM in GPIO Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DPGPIO_PD ,Pull-down on DP in GPIO Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DMINPUT ,DM Input in GPIO Mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DPINPUT ,DP Input in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 14. " DMOPBUFCTL ,DM Output Buffer Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DPOPBUFCTL ,DP Output Buffer Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " GPIOMODE ,GPIO Mode" "USB,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CDET_EXTCTL ,Bypass the charger detection state machine" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 9. " DPPULLUP ,Pull-up on DP line" "No effect,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMPULLUP ,Pull-up on DM line" "No effect,Pull-up"
|
|
bitfld.long 0x00 7. " CHGVSRC_EN ,Enable VSRC on DP line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CHGISINK_EN ,Enable ISINK on DM line" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SINKONDP ,Sink on DP" "DM,DP"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SRCONDM ,Source on DM" "DP,DM"
|
|
bitfld.long 0x00 3. " CHGDET_RSTRT ,Restart Charger Detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHGDET_DIS ,Charger Detect Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " OTG_PWRDN ,Power down the USB OTG PHY" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM_PWRDN ,Power down the USB CM PHY" "Not powered down,Powered down"
|
|
rgroup.long (0x628+0x4)++0x3
|
|
line.long 0x00 "USB_STS1,USB Status Register 1"
|
|
bitfld.long 0x00 13. " GPIO_DMOUT ,Data on DM in GPIO mode" "No data,Data"
|
|
bitfld.long 0x00 12. " GPIO_DPOUT ,Data on DP in GPIO mode" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " CHGDETSTS ,Charge Detection Status" "Wait State,No Contact,PS/2,Error,Dedicated,HOST,PC,Interrupt"
|
|
bitfld.long 0x00 4. " CDET_DMDET ,DM Comparator Output Detection" "Not deteced,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CDET_DPDET ,DP Comparator Output Detection" "Not deteced,Detected"
|
|
bitfld.long 0x00 2. " CDET_DATADET ,Charger Comparator Output Detection" "Not deteced,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHGDETECT ,Charger Detection Status" "Not deteced,Detected"
|
|
bitfld.long 0x00 0. " CHGDETDONE ,Charger Detection Protocol Done" "Not done,Done"
|
|
tree.end
|
|
tree "MAC Registers"
|
|
rgroup.long 0x630++0x0F
|
|
line.long 0x0 "MAC_ID0_LO,Ethernet MAC ID0 Low Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " MACADDR[7:0] ,MAC0 Address - Byte 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MACADDR[15:8] ,MAC0 Address - Byte 1"
|
|
line.long (0x0+0x4) "MAC_ID0_HI,Ethernet MAC ID0 High Register"
|
|
hexmask.long.byte (0x0+0x4) 24.--31. 1. " MACADDR[23:16] ,MAC0 Address - Byte 2"
|
|
hexmask.long.byte (0x0+0x4) 16.--23. 1. " MACADDR[31:24] ,MAC0 Address - Byte 3"
|
|
textline " "
|
|
hexmask.long.byte (0x0+0x4) 8.--15. 1. " MACADDR[39:32] ,MAC0 Address - Byte 4"
|
|
hexmask.long.byte (0x0+0x4) 0.--7. 1. " MACADDR[47:40] ,MAC0 Address - Byte 5"
|
|
line.long 0x8 "MAC_ID1_LO,Ethernet MAC ID1 Low Register"
|
|
hexmask.long.byte 0x8 8.--15. 1. " MACADDR[7:0] ,MAC1 Address - Byte 0"
|
|
hexmask.long.byte 0x8 0.--7. 1. " MACADDR[15:8] ,MAC1 Address - Byte 1"
|
|
line.long (0x8+0x4) "MAC_ID1_HI,Ethernet MAC ID1 High Register"
|
|
hexmask.long.byte (0x8+0x4) 24.--31. 1. " MACADDR[23:16] ,MAC1 Address - Byte 2"
|
|
hexmask.long.byte (0x8+0x4) 16.--23. 1. " MACADDR[31:24] ,MAC1 Address - Byte 3"
|
|
textline " "
|
|
hexmask.long.byte (0x8+0x4) 8.--15. 1. " MACADDR[39:32] ,MAC1 Address - Byte 4"
|
|
hexmask.long.byte (0x8+0x4) 0.--7. 1. " MACADDR[47:40] ,MAC1 Address - Byte 5"
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "SW_REVISION,SW Revision Register"
|
|
tree.end
|
|
group.long 0x644++0x3
|
|
line.long 0x00 "DCAN_RAMINIT,DCAN RAM Init Register"
|
|
eventfld.long 0x00 9. " DCAN1_RAMINIT_DONE ,DCAN1 RAM Initialization complete" "Not completed,Completed"
|
|
eventfld.long 0x00 8. " DCAN0_RAMINIT_DONE ,DCAN0 RAM Initialization complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DCAN1_RAMINIT_START ,Start DCAN1 RAM initialization sequence" "Not started,Started"
|
|
bitfld.long 0x00 0. " DCAN0_RAMINIT_START ,Start DCAN0 RAM initialization sequence" "Not started,Started"
|
|
group.long 0x64c++0x7
|
|
line.long 0x00 "AUD_CTRL,Audio Interface Control Register"
|
|
bitfld.long 0x00 1. " MCB_LBFSX ,McBSP FSX Loopback enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MCB_LBCLKX ,McBSP CLKX Loopback enable" "Disabled,Enabled"
|
|
line.long 0x04 "GMII_SEL,MII Mode Selection Register"
|
|
bitfld.long 0x04 9. " RGMII1_EN ,Enable RGMII1 PIN selection" "PINCTRL,RGMII"
|
|
bitfld.long 0x04 8. " RGMII0_EN ,Enable RGMII0 PIN selection" "PINCTRL,RGMII"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RGMII1_ID_MODE ,Port 1 CPRGMII Internal Delay Mode" "Internal delay,No internal delay"
|
|
bitfld.long 0x04 4. " RGMII0_ID_MODE ,Port 0 CPRGMII Internal Delay Mode" "Internal delay,No internal delay"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " GMII1_SEL ,Port 1 functionality" "GMII/MII,RMII,RGMII,?..."
|
|
bitfld.long 0x04 0.--1. " GMII0_SEL ,Port 0 functionality" "GMII/MII,RMII,RGMII,?..."
|
|
tree "Memory Powerdown Registers"
|
|
width 28.
|
|
group.long 0x654++0x3
|
|
line.long 0x00 "OCMEM_PWRDN,OCMEM Powerdown Register"
|
|
bitfld.long 0x00 1. " MEM_PWRDN_STATUS ,Power down status from the OCMEM" "Not powered down,Powered down"
|
|
bitfld.long 0x00 0. " MEM_PWRDN ,Power down request to the OCMEM" "Not requested,Requested"
|
|
group.long 0x65C++0x3
|
|
line.long 0x00 "MEDIA_CONTROLLER_MEM_PWRDN,MEDIA_CONTROLLER_MEM Powerdown Register"
|
|
bitfld.long 0x00 1. " MEM_PWRDN_STATUS ,Power down status from the MEDIA_CONTROLLER_MEM" "Not powered down,Powered down"
|
|
bitfld.long 0x00 0. " MEM_PWRDN ,Power down request to the MEDIA_CONTROLLER_MEM" "Not requested,Requested"
|
|
tree.end
|
|
tree "SD DAC Registers"
|
|
width 19.
|
|
group.long 0x670++0x1b
|
|
line.long 0x00 "SD_DAC_CTRL,SD DAC Control Register"
|
|
bitfld.long 0x00 24. " DAC1_CM3 ,Channel configuration" "Single,Dual"
|
|
bitfld.long 0x00 23. " DAC1_CM2 ,Channel configuration (dual/single)" "Luma/Composite video,Chroma video"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DAC1_CM1 ,Lower output swing control (full-scale)" "High,Low"
|
|
bitfld.long 0x00 21. " DAC1_CM0 ,IInternal current reference control" "External,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " DAC0_CM3 ,Channel configuration" "Single,Dual"
|
|
bitfld.long 0x00 18. " DAC0_CM2 ,Channel configuration (dual/single)" "Luma/Composite video,Chroma video"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DAC0_CM1 ,Lower output swing control (full-scale)" "High,Low"
|
|
bitfld.long 0x00 16. " DAC0_CM0 ,IInternal current reference control" "External,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " TVOUTBYPASS ,TVOUT Bypass Signal" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 7. " ACEN ,AC coupling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INPUTINV ,Inversion of din[9:0]" "Inverted,Not inverted"
|
|
bitfld.long 0x00 5. " DEMEN ,Dynamic Element Matching enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PBNDACZ ,DAC Power-Down Control Input" "Powered down,Not powered down"
|
|
bitfld.long 0x00 3. " PBNBGZ ,Bandgap Power-Down Control" "Powered down,Not powered down"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OFFMODE ,Master power-down" "Not powered down,Powered down"
|
|
bitfld.long 0x00 1. " SD_CALSEL ,SD DAC Calibration Select" "Normal,Calibration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESETZ ,Reset signal" "Reset,No reset"
|
|
line.long 0x04 "SD_DAC0_CAL,SD DAC 0 Calibration Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " SDDAC_0_CAL ,SD DAC 0 calibration value"
|
|
line.long 0x08 "SD_DAC1_CAL,SD DAC 1 Calibration Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " SDDAC_1_CAL ,SD DAC 1 calibration value"
|
|
line.long 0x0c "SD_DAC0_REGCTRL,SD DAC 0 Internal Register Control Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " SDDAC_0_CTL ,CTL interface for the AVDAC"
|
|
line.long 0x10 "SD_DAC0_REGSTATUS,SD DAC 0 Internal Register Status Register"
|
|
eventfld.long 0x10 0. " STATUS ,Write status for the AVDAC" "Pending,Acknowledged"
|
|
line.long 0x14 "SD_DAC1_REGCTRL,SD DAC 1 Internal Register Control Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " SDDAC_1_CTL ,CTL interface for the AVDAC"
|
|
line.long 0x18 "SD_DAC1_REGSTATUS,SD DAC 1 Internal Register Status Register"
|
|
eventfld.long 0x18 0. " STATUS ,Write status for the AVDAC" "Pending,Acknowledged"
|
|
tree.end
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "EMIF_CLK_GATE,Clock Gating Register"
|
|
rbitfld.long 0x00 2. " DDR0_CKE_STATUS ,CKE status for DDR0" "No Self Refresh,Self Refresh"
|
|
bitfld.long 0x00 0. " DDRPHY0_CLK_GATE ,Enables/disables the clock to the DDR0 PHY" "Enabled,Disabled"
|
|
group.long 0x6a0++0x07
|
|
line.long 0x00 "SMRT_CTRL,Smart Reflex Control Register"
|
|
bitfld.long 0x00 2. " SR2_SRSLLEP ,Sensor 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SR1_SRSLLEP ,Sensor 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SR0_SRSLLEP ,Sensor 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "ARM_HW_DBG_SEL,ARM Hardware Debug Selection Register"
|
|
bitfld.long 0x04 9. " HW_DBG_GATE_EN ,Debug info not gated off" "Gated off,Not gated off"
|
|
bitfld.long 0x04 8. " HW_DBG_READ_EN ,Read of ARM_HW_DBG_INFO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " HW_DBG_SEL ,Group of signals sent out to the ARM_HW_DBG_INFO" "Group 0,Group 1,Group 2,Group 3,Group 4,Group 5,Group 6,Group 7,?..."
|
|
rgroup.long 0x6a8++0x03
|
|
line.long 0x00 "MPU_HW_DBG_INFO,ARM Hardware Debug Information Register"
|
|
tree "PRCM Debug"
|
|
width 29.
|
|
group.long 0x6b0++0x7
|
|
line.long 0x00 "PRCM_DEBUG_ALWON_DEFAULT,PRCM Debug AlwaysOn Default Register"
|
|
rbitfld.long 0x00 29. " USB_CLK_OFF ,USB Clock OFF" "On,Off"
|
|
rbitfld.long 0x00 27. " PCI_CLK_OFF ,PCI Clock OFF" "On,Off"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " MEDIACTL_CLK_OFF ,MEDIACTL Clock OFF" "On,Off"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " RTC_CLK_OFF ,RTC_ Clock OFF" "On,Off"
|
|
rbitfld.long 0x00 21. " VCP_CLK_OFF ,VCP Clock OFF" "On,Off"
|
|
textline " "
|
|
rbitfld.long 0x00 20. " OCMC_RAM_CLK_OFF ,OCMC_RAM Clock OFF" "On,Off"
|
|
rbitfld.long 0x00 19. " MPU_CLK_OFF ,MPU Clock OFF" "On,Off"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " MMU_CLK_OFF ,MMU Clock OFF" "On,Off"
|
|
rbitfld.long 0x00 16. " ETHERNET_CLK_OFF ,ETHERNET Clock OFF" "On,Off"
|
|
textline " "
|
|
rbitfld.long 0x00 14. " L3_SLOW_CLK_OFF ,L3_SLOW Clock OFF" "On,Off"
|
|
rbitfld.long 0x00 13. " L3_MED_CLK_OFF ,L3_MED Clock OFF" "On,Off"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " L3_FAST_CLK_OFF ,L3_FAST Clock OFF" "On,Off"
|
|
rbitfld.long 0x00 10. " SYSCLK6_CLK_OFF ,SYSCLK6 Clock OFF" "On,Off"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " SYSCLK5_CLK_OFF ,SYSCLK5 Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 8. " SYSCLK4_CLK_OFF ,SYSCLK4 Clock OFF" "On,Off"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DEF_PWR_ON ,Default domain power up" "Powered down,Powered up"
|
|
bitfld.long 0x00 3. " HW_DBG_READ_EN ,PRCM_DEBUG_ALWON_DEFAULT read enable" "Disabled,Enabled"
|
|
line.long 0x04 "PRCM_DEBUG_PD_DOMAIN_STATUS,PRCM Debug Power Domain Status Register"
|
|
rbitfld.long 0x04 31. " SGX_PD_HDVPSS_CLK_STATUS_GLUE ,SGX clk is idled status from glue" "Not idled,Idled"
|
|
rbitfld.long 0x04 30. " SGX_PD_CLK_STATUS_PRCM ,SGX domain clks are idled" "Not idled,Idled"
|
|
textline " "
|
|
rbitfld.long 0x04 29. " SGX_PD_MEM_ON_GLUE ,SGX domain memories are off" "ON,OFF"
|
|
rbitfld.long 0x04 28. " SGX_PD_SWITCH_ON_GLUE ,SGX domain switches are off" "ON,OFF"
|
|
textline " "
|
|
rbitfld.long 0x04 27. " SGX_PD_ON_PRCM ,SGX domain is not powered up" "Powered up,Powered down"
|
|
rbitfld.long 0x04 25. " DSS_PD_DSS_CLK_STATUS_GLUE ,Active domain power switch status" "OM,OFF"
|
|
textline " "
|
|
rbitfld.long 0x04 24. " DSS_PD_CLK_STATUS_PRCM ,HActive domain power switch status" "OM,OFF"
|
|
rbitfld.long 0x04 23. " DSS_PD_MEM_ON_GLUE ,Active domain power switch status" "ON,OFF"
|
|
textline " "
|
|
rbitfld.long 0x04 22. " DSS_PD_SWITCH_ON_GLUE ,Active domain power switch status" "ON,OFF"
|
|
rbitfld.long 0x04 21. " DSS_PD_ON_PRCM ,Active domain power switch status" "Powered up,Powered down"
|
|
textline " "
|
|
rbitfld.long 0x04 8. " ACTIVE_PD_C674X_DSP_CLK_STATUS_GLUE ,C674x_DSP clk status from the glue logic" "Not idled,Idled"
|
|
rbitfld.long 0x04 7. " ACTIVE_PD_C674X_DSP_CLK_STATUS_PRCM ,C674x_DSP clk status" "Not idled,Idled"
|
|
textline " "
|
|
rbitfld.long 0x04 6. " ACTIVE_PD_MEM_ON_GLUE ,Active domain power switch status" "ON,OFF"
|
|
rbitfld.long 0x04 5. " ACTIVE_PD_SWITCH_ON_GLUE ,Active domain power switch status" "ON,OFF"
|
|
textline " "
|
|
rbitfld.long 0x04 4. " ACTIVE_PD_ON_PRCM ,Active domain power status" "Powered up,Powered down"
|
|
bitfld.long 0x04 3. " HW_DBG_READ_EN ,Enables the read of the other bitfileds in this MMR" "Disabled,Enabled"
|
|
tree.end
|
|
tree "PCIE Registers"
|
|
width 18.
|
|
group.long 0x6d8++0x03
|
|
line.long 0x00 "PCIE_PLLCFG0,PCIe PLL Configuration 0 Register"
|
|
bitfld.long 0x00 31. " SEL_IN_FREQ ,Select input frequency" "100 MHz,20 MHz"
|
|
bitfld.long 0x00 30. " DIGCLRZ ,CLRZ for APLL DIG and DLL DIG" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AMUXSEL ,AMUX select" "KVCD,VRTRIM"
|
|
bitfld.long 0x00 26. " TESTCLKMUXSEL ,Selects test clock mux" "REF,Divided"
|
|
textline " "
|
|
bitfld.long 0x00 25. " APLL_MISC_CTRL[5] ,APLL DIG lock speed" "128 clock,256clock"
|
|
bitfld.long 0x00 24. " APLL_MISC_CTRL[4] ,APLL DIG 50Mhz trim disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " APLL_MISC_CTRL[3] ,APLL DIG divider" "Fixed,Programmable"
|
|
bitfld.long 0x00 22. " APLL_MISC_CTRL[2] ,APLL DIG power saving" "Default,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " APLL_MISC_CTRL[0:1] , APLL DIG steps" "No step,57%-100%,75%-87.5%-100% in 60/20/20,75%-87.5%-100% in 40/40/40"
|
|
bitfld.long 0x00 19. " DIS_REFCLK ,Disable CML that control FREF output clock buffer" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EN_3P ,SC circuit in the APLL LF enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PFD_CLR ,Open PLL loop" "Closed,Opened"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CLK_FLIP ,Output clock phase flip enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_RTRIM ,Enable resistor calibration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EN_MEAS ,Enable measurement circuit inside APLL ANA" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " EN_LATCH ,Output latch in differential ring enable" "All on,Remove 33%,Remove 16%,Remove 50%"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CP_CTRL ,Charge pump control (+/- 50%)" "Nom,+13%,+27%,+50%,-20%,Reserved,Reserved,Reserved,-27%,Reserved,-50%,?..."
|
|
bitfld.long 0x00 6.--7. " RESVALUE ,Loop filter resistor value" "1 Kohm PCIE,1.67 Kohm eSata,2.5 Kohm SSC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " C1_2X ,Increase filter capacitance by 2x in low reference (20 MHz) clock" "120 pF for PCIe,240 pF for eSATA/SSC"
|
|
bitfld.long 0x00 4. " ENDIGLDO ,Enable DIG LDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " APLL_CP_CURR ,Post_Cent_PG1.0" "Low,High"
|
|
bitfld.long 0x00 2. " ENBGSC_REF ,Increases the APLL CP current" "No increase,Increase"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENPLLLDO ,Enable PLL LDO" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENPLL ,Enable PLL" "Disabled,Enabled"
|
|
if (((d.l(ad:0x48140000+0x6d8))&0x800000)==0x800000)
|
|
group.long 0x6dc++0x03
|
|
line.long 0x00 "PCIE_PLLCFG1,PCIe PLL Configuration 1 Register"
|
|
bitfld.long 0x00 31. " ENSATAMODE ,Enable SATA Mode" "PCIe (2.5 GHz),SATA (1.5 GHz)"
|
|
bitfld.long 0x00 30. " PLLREFSEL ,PLL reference clock value" "100 MHz,20 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--29. " NP1_DIV_INT ,Integer value of N+1 divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 18.--25. 1. " MDIVINT ,8-bit integer value for M divide"
|
|
textline " "
|
|
hexmask.long.word 0x00 6.--17. 1. " MDIVFRAC ,12-bit fractional value for M divider"
|
|
bitfld.long 0x00 5. " EN_CLKAUX ,Enable/disable auxilary clock" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EN_CLK125M ,Enable for 125MHz clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EN_CLK100M ,Enable for 100MHz clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EN_CLK50M ,Enable for 50MHz clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENSSC ,Enable spread specturm support" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MDIVPULSE ,Update M div when pulse is high" "Low,High"
|
|
else
|
|
group.long 0x6dc++0x03
|
|
line.long 0x00 "PCIE_PLLCFG1,PCIe PLL Configuration 1 Register"
|
|
bitfld.long 0x00 30.--31. " DIV ,Division ratio" "25,125,15,75"
|
|
bitfld.long 0x00 26.--29. " NP1_DIV_INT ,Integer value of N+1 divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " MDIVINT ,8-bit integer value for M divide"
|
|
hexmask.long.word 0x00 6.--17. 1. " MDIVFRAC ,12-bit fractional value for M divider"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EN_CLKAUX ,Enable/disable auxilary clock" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " EN_CLK125M ,Enable for 125MHz clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN_CLK100M ,Enable for 100MHz clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EN_CLK50M ,Enable for 50MHz clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENSSC ,Enable spread specturm support" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MDIVPULSE ,Update M div when pulse is high" "Low,High"
|
|
endif
|
|
group.long 0x6e0++0x17
|
|
line.long 0x00 "PCIE_PLLCFG2,PCIe PLL Configuration 2 Register"
|
|
bitfld.long 0x00 31. " SSCDNSPREAD ,SSC downspread" "Low,High"
|
|
hexmask.long.byte 0x00 24.--30. 1. " SSCMANT ,Mantesa portion of the modified frequency in SSC operation"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " SSCEXPO ,Exponent portion of the modified frequency in SSC operation" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " SSCFRSPREAD ,SSC frequency spread"
|
|
line.long 0x04 "PCIE_PLLCFG3,PCIe PLL Configuration 3 Register"
|
|
bitfld.long 0x04 27. " DIGLDO_BYPASS ,DIG LDO bypass mode" "Low,High"
|
|
bitfld.long 0x04 26. " DIGLDO_PULLDOWNZ ,Disables all the pull down paths for LDO output" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 25. " DIGLDO_DIS_SC_PROT ,Disables short circuit protection" "No,Yes"
|
|
bitfld.long 0x04 24. " DIGLDO_EN_SUB_REGULATION ,Disables sub regulation" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DIGLDO_EN_HP_CAPLESSMODE ,High performance Capless mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " DIGLDO_EN_CAPLESSMODE ,Capless Mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " DIGLDO_EN_LP_CAPLESSMODE ,Low Power Capless Mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--20. " DIGLDO_VSET ,VDDAR (V) voltage setup" "1.21,1.22,1.23,1.24,1.25,1.26,1.27,1.28,1.29,1.30,1.31,1.32,1.33,1.34,1.35,1.36,1.05,1.06,1.07,1.08,1.09,1.10,1.11,1.12,1.13,1.14,1.15,1.16,1.17,1.18,1.19,1.20"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PLLLDO_EN_RETENTION ,Enable retention mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PLLLDO_EN_LDO_STABLE ,LDO Stable Signal" "Unstable,Stable"
|
|
textline " "
|
|
bitfld.long 0x04 10. " PLLLDO_EN_BYPASS ,Enable bypass mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PLLLDO_EN_SC_PROT ,Enable short circuit protection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PLLLDO_EN_EXT_CAP ,Enable external cap mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PLLLDO_EN_BUF_CUR ,Enable Increased Buffer Current" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PLLLDO_EN_LP ,Enable Low Power" "Disabled,Enabled"
|
|
bitfld.long 0x04 1.--5. " PLLLDO_CTRL_TRIM ,Output voltage" "1.000,1.025,1.050,1.075,1.100,1.125,1.150,1.175,1.200,1.225,1.250,1.275,1.300,1.325,1.350,1.375,1.400,1.425,1.450,1.475,1.500,1.525,1.550,1.575,1.600,?..."
|
|
line.long 0x08 "PCIE_PLLCFG4,PCIe PLL Configuration 4 Register"
|
|
bitfld.long 0x08 25. " AUX_CLK_SEL ,AUX Clock Select" "Divided,Ref-clk"
|
|
bitfld.long 0x08 20.--24. " AUX_DIV ,Aux divider control" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " RTRIM_RANGE ,Range for rtrim" "0.9-0.8,1.0-0.9,1.1-1.0,1.1-0.9"
|
|
bitfld.long 0x08 17. " RTRIM_EXT_EN ,Select loop starting point" "Mid-code,External"
|
|
textline " "
|
|
bitfld.long 0x08 16. " RTRIM_SPEED ,Selection on wait for # REFCLKs after previous update" "128,256"
|
|
bitfld.long 0x08 14.--15. " RTRIM_MODE ,Loop mode" "OFF,ON (continouos),ON (freeze),ON (continouos)"
|
|
textline " "
|
|
bitfld.long 0x08 10.--13. " RTRIM_EXT_VAL ,2's compliment vtune control loop value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--9. " VTUNE_RANGE ,Range for Vtune" "0.9-0.8,1.0-0.9,1.1-1.0,1.1-0.9"
|
|
textline " "
|
|
bitfld.long 0x08 7. " VTUNE_EXT_EN ,Select loop starting point" "Mid-code,External"
|
|
bitfld.long 0x08 6. " VTUNE_SPEED ,Selection on wait for # REFCLKs after previous update" "128,256"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " VTUNE_MODE ,Loop mode" "OFF,ON (continouos),ON (freeze),ON (continouos)"
|
|
bitfld.long 0x08 0.--3. " VTUNE_EXT_VAL ,2's compliment vtune control loop value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0c "PCIE_PLLSTATUS,PCIe PLL Status Register"
|
|
bitfld.long 0x0c 8.--11. " RTRIMSTS ,Value of the rtrim loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 4.--7. " VTUNESTS ,Value of the vtune control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " PLLDIG_EN , Digital Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " PLLANA_EN , Analog Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " PLLSSC_EN ,SSC is engaged" "Not engaged,Engaged"
|
|
bitfld.long 0x0c 0. " PLL_LOCK ,APLL locked" "Unlocked,Locked"
|
|
line.long 0x10 "PCIE_RXSTATUS,PCIe RX Status Register"
|
|
bitfld.long 0x10 0. " TESTFAIL ,Test failure" "No error,Error"
|
|
line.long 0x14 "PCIE_TXSTATUS,PCIe TX Status Register"
|
|
bitfld.long 0x14 0. " TESTFAIL ,Test failure" "No error,Error"
|
|
tree.end
|
|
tree "VDD Registers"
|
|
group.long 0x770++0x0f
|
|
line.long 0x0 "VDD_MPU_OPP_050,VDD MPU OPP 50"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domains OPP50"
|
|
line.long 0x4 "VDD_MPU_OPP_100,VDD MPU OPP 100"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domains OPP100"
|
|
line.long 0x8 "VDD_MPU_OPP_120,VDD MPU OPP 119"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domains OPP119"
|
|
line.long 0xC "VDD_MPU_OPP_166,VDD MPU OPP TURBO"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domains OPPTURBO"
|
|
group.long 0x7b8++0x0f
|
|
line.long 0x0 "VDD_CORE_OPP_050,VDD CORE OPP 50"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domains OPP50"
|
|
line.long 0x4 "VDD_CORE_OPP_100,VDD CORE OPP 100"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domains OPP100"
|
|
line.long 0x8 "VDD_CORE_OPP_120,VDD CORE OPP 119"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domains OPP119"
|
|
line.long 0xC "VDD_CORE_OPP_166,VDD CORE OPP TURBO"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domains OPPTURBO"
|
|
tree.end
|
|
rgroup.long 0x7d0++0x03
|
|
line.long 0x00 "BB_SCALE,Back Bias Scaling Register"
|
|
bitfld.long 0x00 8.--11. " SCALE ,Dynamic Core Voltage Scaling for class 0 smart reflex" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. " BBIAS ,BBIAS value from Efuse" "0,1,2,3"
|
|
rgroup.long 0x7f4++0x7
|
|
line.long 0x00 "USB_VID_PID,USB VID/PID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " USB_VID ,USB Vendor ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " USB_PID ,USB Product ID"
|
|
line.long 0x04 "PCIE_VID_PID,PCIE VID/PID Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " PCIE_VID ,PCIE Vendor ID"
|
|
hexmask.long.word 0x04 0.--15. 1. " PCIE_PID ,PCIE Product ID"
|
|
tree "Pin Control Registers"
|
|
group.long 0x800++0x437
|
|
line.long 0x0 "PINCTRL1,Pin 1 Control Register"
|
|
bitfld.long 0x0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x4 "PINCTRL2,Pin 2 Control Register"
|
|
bitfld.long 0x4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x8 "PINCTRL3,Pin 3 Control Register"
|
|
bitfld.long 0x8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xC "PINCTRL4,Pin 4 Control Register"
|
|
bitfld.long 0xC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x10 "PINCTRL5,Pin 5 Control Register"
|
|
bitfld.long 0x10 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x10 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x10 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x14 "PINCTRL6,Pin 6 Control Register"
|
|
bitfld.long 0x14 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x14 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x14 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x18 "PINCTRL7,Pin 7 Control Register"
|
|
bitfld.long 0x18 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x18 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x18 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1C "PINCTRL8,Pin 8 Control Register"
|
|
bitfld.long 0x1C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x20 "PINCTRL9,Pin 9 Control Register"
|
|
bitfld.long 0x20 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x20 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x24 "PINCTRL10,Pin 10 Control Register"
|
|
bitfld.long 0x24 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x24 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x24 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x28 "PINCTRL11,Pin 11 Control Register"
|
|
bitfld.long 0x28 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x28 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x28 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2C "PINCTRL12,Pin 12 Control Register"
|
|
bitfld.long 0x2C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x30 "PINCTRL13,Pin 13 Control Register"
|
|
bitfld.long 0x30 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x30 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x30 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x34 "PINCTRL14,Pin 14 Control Register"
|
|
bitfld.long 0x34 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x34 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x34 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x38 "PINCTRL15,Pin 15 Control Register"
|
|
bitfld.long 0x38 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x38 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x38 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3C "PINCTRL16,Pin 16 Control Register"
|
|
bitfld.long 0x3C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x40 "PINCTRL17,Pin 17 Control Register"
|
|
bitfld.long 0x40 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x40 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x40 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x44 "PINCTRL18,Pin 18 Control Register"
|
|
bitfld.long 0x44 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x44 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x44 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x48 "PINCTRL19,Pin 19 Control Register"
|
|
bitfld.long 0x48 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x48 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x48 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x4C "PINCTRL20,Pin 20 Control Register"
|
|
bitfld.long 0x4C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x4C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x4C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x50 "PINCTRL21,Pin 21 Control Register"
|
|
bitfld.long 0x50 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x50 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x50 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x54 "PINCTRL22,Pin 22 Control Register"
|
|
bitfld.long 0x54 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x54 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x54 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x58 "PINCTRL23,Pin 23 Control Register"
|
|
bitfld.long 0x58 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x58 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x58 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x5C "PINCTRL24,Pin 24 Control Register"
|
|
bitfld.long 0x5C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x5C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x5C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x60 "PINCTRL25,Pin 25 Control Register"
|
|
bitfld.long 0x60 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x60 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x60 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x64 "PINCTRL26,Pin 26 Control Register"
|
|
bitfld.long 0x64 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x64 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x64 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x68 "PINCTRL27,Pin 27 Control Register"
|
|
bitfld.long 0x68 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x68 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x68 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x6C "PINCTRL28,Pin 28 Control Register"
|
|
bitfld.long 0x6C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x6C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x6C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x70 "PINCTRL29,Pin 29 Control Register"
|
|
bitfld.long 0x70 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x70 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x70 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x74 "PINCTRL30,Pin 30 Control Register"
|
|
bitfld.long 0x74 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x74 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x74 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x78 "PINCTRL31,Pin 31 Control Register"
|
|
bitfld.long 0x78 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x78 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x78 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x7C "PINCTRL32,Pin 32 Control Register"
|
|
bitfld.long 0x7C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x7C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x7C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x80 "PINCTRL33,Pin 33 Control Register"
|
|
bitfld.long 0x80 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x80 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x80 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x84 "PINCTRL34,Pin 34 Control Register"
|
|
bitfld.long 0x84 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x84 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x84 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x88 "PINCTRL35,Pin 35 Control Register"
|
|
bitfld.long 0x88 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x88 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x88 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x8C "PINCTRL36,Pin 36 Control Register"
|
|
bitfld.long 0x8C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x8C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x8C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x90 "PINCTRL37,Pin 37 Control Register"
|
|
bitfld.long 0x90 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x90 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x90 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x94 "PINCTRL38,Pin 38 Control Register"
|
|
bitfld.long 0x94 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x94 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x94 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x98 "PINCTRL39,Pin 39 Control Register"
|
|
bitfld.long 0x98 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x98 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x98 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x9C "PINCTRL40,Pin 40 Control Register"
|
|
bitfld.long 0x9C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x9C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x9C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xA0 "PINCTRL41,Pin 41 Control Register"
|
|
bitfld.long 0xA0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xA0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xA0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xA4 "PINCTRL42,Pin 42 Control Register"
|
|
bitfld.long 0xA4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xA4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xA4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xA8 "PINCTRL43,Pin 43 Control Register"
|
|
bitfld.long 0xA8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xA8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xA8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xAC "PINCTRL44,Pin 44 Control Register"
|
|
bitfld.long 0xAC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xAC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xAC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xB0 "PINCTRL45,Pin 45 Control Register"
|
|
bitfld.long 0xB0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xB0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xB0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xB4 "PINCTRL46,Pin 46 Control Register"
|
|
bitfld.long 0xB4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xB4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xB4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xB8 "PINCTRL47,Pin 47 Control Register"
|
|
bitfld.long 0xB8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xB8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xB8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xBC "PINCTRL48,Pin 48 Control Register"
|
|
bitfld.long 0xBC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xBC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xBC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xC0 "PINCTRL49,Pin 49 Control Register"
|
|
bitfld.long 0xC0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xC0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xC0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xC4 "PINCTRL50,Pin 50 Control Register"
|
|
bitfld.long 0xC4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xC4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xC4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xC8 "PINCTRL51,Pin 51 Control Register"
|
|
bitfld.long 0xC8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xC8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xC8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xCC "PINCTRL52,Pin 52 Control Register"
|
|
bitfld.long 0xCC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xCC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xCC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xD0 "PINCTRL53,Pin 53 Control Register"
|
|
bitfld.long 0xD0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xD0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xD0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xD4 "PINCTRL54,Pin 54 Control Register"
|
|
bitfld.long 0xD4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xD4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xD4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xD8 "PINCTRL55,Pin 55 Control Register"
|
|
bitfld.long 0xD8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xD8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xD8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xDC "PINCTRL56,Pin 56 Control Register"
|
|
bitfld.long 0xDC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xDC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xDC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xE0 "PINCTRL57,Pin 57 Control Register"
|
|
bitfld.long 0xE0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xE0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xE0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xE4 "PINCTRL58,Pin 58 Control Register"
|
|
bitfld.long 0xE4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xE4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xE4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xE8 "PINCTRL59,Pin 59 Control Register"
|
|
bitfld.long 0xE8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xE8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xE8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xEC "PINCTRL60,Pin 60 Control Register"
|
|
bitfld.long 0xEC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xEC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xEC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xF0 "PINCTRL61,Pin 61 Control Register"
|
|
bitfld.long 0xF0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xF0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xF0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xF4 "PINCTRL62,Pin 62 Control Register"
|
|
bitfld.long 0xF4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xF4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xF4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xF8 "PINCTRL63,Pin 63 Control Register"
|
|
bitfld.long 0xF8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xF8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xF8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xFC "PINCTRL64,Pin 64 Control Register"
|
|
bitfld.long 0xFC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xFC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0xFC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x100 "PINCTRL65,Pin 65 Control Register"
|
|
bitfld.long 0x100 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x100 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x100 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x104 "PINCTRL66,Pin 66 Control Register"
|
|
bitfld.long 0x104 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x104 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x104 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x108 "PINCTRL67,Pin 67 Control Register"
|
|
bitfld.long 0x108 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x108 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x108 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x10C "PINCTRL68,Pin 68 Control Register"
|
|
bitfld.long 0x10C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x10C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x10C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x110 "PINCTRL69,Pin 69 Control Register"
|
|
bitfld.long 0x110 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x110 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x110 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x114 "PINCTRL70,Pin 70 Control Register"
|
|
bitfld.long 0x114 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x114 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x114 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x118 "PINCTRL71,Pin 71 Control Register"
|
|
bitfld.long 0x118 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x118 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x118 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x11C "PINCTRL72,Pin 72 Control Register"
|
|
bitfld.long 0x11C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x11C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x11C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x120 "PINCTRL73,Pin 73 Control Register"
|
|
bitfld.long 0x120 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x120 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x120 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x124 "PINCTRL74,Pin 74 Control Register"
|
|
bitfld.long 0x124 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x124 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x124 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x128 "PINCTRL75,Pin 75 Control Register"
|
|
bitfld.long 0x128 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x128 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x128 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x12C "PINCTRL76,Pin 76 Control Register"
|
|
bitfld.long 0x12C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x12C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x12C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x130 "PINCTRL77,Pin 77 Control Register"
|
|
bitfld.long 0x130 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x130 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x130 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x134 "PINCTRL78,Pin 78 Control Register"
|
|
bitfld.long 0x134 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x134 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x134 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x138 "PINCTRL79,Pin 79 Control Register"
|
|
bitfld.long 0x138 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x138 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x138 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x13C "PINCTRL80,Pin 80 Control Register"
|
|
bitfld.long 0x13C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x13C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x13C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x140 "PINCTRL81,Pin 81 Control Register"
|
|
bitfld.long 0x140 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x140 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x140 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x144 "PINCTRL82,Pin 82 Control Register"
|
|
bitfld.long 0x144 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x144 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x144 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x148 "PINCTRL83,Pin 83 Control Register"
|
|
bitfld.long 0x148 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x148 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x148 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x14C "PINCTRL84,Pin 84 Control Register"
|
|
bitfld.long 0x14C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x14C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x14C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x150 "PINCTRL85,Pin 85 Control Register"
|
|
bitfld.long 0x150 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x150 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x150 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x154 "PINCTRL86,Pin 86 Control Register"
|
|
bitfld.long 0x154 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x154 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x154 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x158 "PINCTRL87,Pin 87 Control Register"
|
|
bitfld.long 0x158 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x158 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x158 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x15C "PINCTRL88,Pin 88 Control Register"
|
|
bitfld.long 0x15C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x15C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x15C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x160 "PINCTRL89,Pin 89 Control Register"
|
|
bitfld.long 0x160 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x160 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x160 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x164 "PINCTRL90,Pin 90 Control Register"
|
|
bitfld.long 0x164 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x164 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x164 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x168 "PINCTRL91,Pin 91 Control Register"
|
|
bitfld.long 0x168 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x168 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x168 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x16C "PINCTRL92,Pin 92 Control Register"
|
|
bitfld.long 0x16C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x16C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x16C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x170 "PINCTRL93,Pin 93 Control Register"
|
|
bitfld.long 0x170 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x170 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x170 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x174 "PINCTRL94,Pin 94 Control Register"
|
|
bitfld.long 0x174 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x174 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x174 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x178 "PINCTRL95,Pin 95 Control Register"
|
|
bitfld.long 0x178 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x178 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x178 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x17C "PINCTRL96,Pin 96 Control Register"
|
|
bitfld.long 0x17C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x17C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x17C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x180 "PINCTRL97,Pin 97 Control Register"
|
|
bitfld.long 0x180 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x180 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x180 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x184 "PINCTRL98,Pin 98 Control Register"
|
|
bitfld.long 0x184 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x184 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x184 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x188 "PINCTRL99,Pin 99 Control Register"
|
|
bitfld.long 0x188 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x188 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x188 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x18C "PINCTRL100,Pin 100 Control Register"
|
|
bitfld.long 0x18C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x18C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x18C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x190 "PINCTRL101,Pin 101 Control Register"
|
|
bitfld.long 0x190 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x190 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x190 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x194 "PINCTRL102,Pin 102 Control Register"
|
|
bitfld.long 0x194 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x194 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x194 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x198 "PINCTRL103,Pin 103 Control Register"
|
|
bitfld.long 0x198 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x198 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x198 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x19C "PINCTRL104,Pin 104 Control Register"
|
|
bitfld.long 0x19C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x19C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x19C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1A0 "PINCTRL105,Pin 105 Control Register"
|
|
bitfld.long 0x1A0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1A0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1A0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1A4 "PINCTRL106,Pin 106 Control Register"
|
|
bitfld.long 0x1A4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1A4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1A4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1A8 "PINCTRL107,Pin 107 Control Register"
|
|
bitfld.long 0x1A8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1A8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1A8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1AC "PINCTRL108,Pin 108 Control Register"
|
|
bitfld.long 0x1AC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1AC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1AC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1B0 "PINCTRL109,Pin 109 Control Register"
|
|
bitfld.long 0x1B0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1B0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1B0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1B4 "PINCTRL110,Pin 110 Control Register"
|
|
bitfld.long 0x1B4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1B4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1B4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1B8 "PINCTRL111,Pin 111 Control Register"
|
|
bitfld.long 0x1B8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1B8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1B8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1BC "PINCTRL112,Pin 112 Control Register"
|
|
bitfld.long 0x1BC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1BC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1BC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1C0 "PINCTRL113,Pin 113 Control Register"
|
|
bitfld.long 0x1C0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1C0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1C0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1C4 "PINCTRL114,Pin 114 Control Register"
|
|
bitfld.long 0x1C4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1C4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1C4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1C8 "PINCTRL115,Pin 115 Control Register"
|
|
bitfld.long 0x1C8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1C8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1C8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1CC "PINCTRL116,Pin 116 Control Register"
|
|
bitfld.long 0x1CC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1CC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1CC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1D0 "PINCTRL117,Pin 117 Control Register"
|
|
bitfld.long 0x1D0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1D0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1D0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1D4 "PINCTRL118,Pin 118 Control Register"
|
|
bitfld.long 0x1D4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1D4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1D4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1D8 "PINCTRL119,Pin 119 Control Register"
|
|
bitfld.long 0x1D8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1D8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1D8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1DC "PINCTRL120,Pin 120 Control Register"
|
|
bitfld.long 0x1DC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1DC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1DC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1E0 "PINCTRL121,Pin 121 Control Register"
|
|
bitfld.long 0x1E0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1E0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1E0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1E4 "PINCTRL122,Pin 122 Control Register"
|
|
bitfld.long 0x1E4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1E4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1E4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1E8 "PINCTRL123,Pin 123 Control Register"
|
|
bitfld.long 0x1E8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1E8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1E8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1EC "PINCTRL124,Pin 124 Control Register"
|
|
bitfld.long 0x1EC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1EC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1EC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1F0 "PINCTRL125,Pin 125 Control Register"
|
|
bitfld.long 0x1F0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1F0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1F0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1F4 "PINCTRL126,Pin 126 Control Register"
|
|
bitfld.long 0x1F4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1F4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1F4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1F8 "PINCTRL127,Pin 127 Control Register"
|
|
bitfld.long 0x1F8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1F8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1F8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1FC "PINCTRL128,Pin 128 Control Register"
|
|
bitfld.long 0x1FC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1FC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x1FC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x200 "PINCTRL129,Pin 129 Control Register"
|
|
bitfld.long 0x200 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x200 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x200 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x204 "PINCTRL130,Pin 130 Control Register"
|
|
bitfld.long 0x204 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x204 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x204 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x208 "PINCTRL131,Pin 131 Control Register"
|
|
bitfld.long 0x208 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x208 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x208 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x20C "PINCTRL132,Pin 132 Control Register"
|
|
bitfld.long 0x20C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x20C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x20C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x210 "PINCTRL133,Pin 133 Control Register"
|
|
bitfld.long 0x210 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x210 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x210 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x214 "PINCTRL134,Pin 134 Control Register"
|
|
bitfld.long 0x214 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x214 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x214 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x218 "PINCTRL135,Pin 135 Control Register"
|
|
bitfld.long 0x218 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x218 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x218 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x21C "PINCTRL136,Pin 136 Control Register"
|
|
bitfld.long 0x21C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x21C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x21C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x220 "PINCTRL137,Pin 137 Control Register"
|
|
bitfld.long 0x220 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x220 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x220 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x224 "PINCTRL138,Pin 138 Control Register"
|
|
bitfld.long 0x224 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x224 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x224 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x228 "PINCTRL139,Pin 139 Control Register"
|
|
bitfld.long 0x228 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x228 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x228 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x22C "PINCTRL140,Pin 140 Control Register"
|
|
bitfld.long 0x22C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x22C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x22C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x230 "PINCTRL141,Pin 141 Control Register"
|
|
bitfld.long 0x230 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x230 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x230 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x234 "PINCTRL142,Pin 142 Control Register"
|
|
bitfld.long 0x234 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x234 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x234 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x238 "PINCTRL143,Pin 143 Control Register"
|
|
bitfld.long 0x238 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x238 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x238 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x23C "PINCTRL144,Pin 144 Control Register"
|
|
bitfld.long 0x23C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x23C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x23C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x240 "PINCTRL145,Pin 145 Control Register"
|
|
bitfld.long 0x240 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x240 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x240 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x244 "PINCTRL146,Pin 146 Control Register"
|
|
bitfld.long 0x244 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x244 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x244 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x248 "PINCTRL147,Pin 147 Control Register"
|
|
bitfld.long 0x248 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x248 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x248 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x24C "PINCTRL148,Pin 148 Control Register"
|
|
bitfld.long 0x24C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x24C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x24C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x250 "PINCTRL149,Pin 149 Control Register"
|
|
bitfld.long 0x250 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x250 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x250 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x254 "PINCTRL150,Pin 150 Control Register"
|
|
bitfld.long 0x254 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x254 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x254 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x258 "PINCTRL151,Pin 151 Control Register"
|
|
bitfld.long 0x258 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x258 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x258 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x25C "PINCTRL152,Pin 152 Control Register"
|
|
bitfld.long 0x25C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x25C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x25C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x260 "PINCTRL153,Pin 153 Control Register"
|
|
bitfld.long 0x260 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x260 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x260 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x264 "PINCTRL154,Pin 154 Control Register"
|
|
bitfld.long 0x264 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x264 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x264 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x268 "PINCTRL155,Pin 155 Control Register"
|
|
bitfld.long 0x268 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x268 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x268 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x26C "PINCTRL156,Pin 156 Control Register"
|
|
bitfld.long 0x26C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x26C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x26C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x270 "PINCTRL157,Pin 157 Control Register"
|
|
bitfld.long 0x270 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x270 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x270 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x274 "PINCTRL158,Pin 158 Control Register"
|
|
bitfld.long 0x274 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x274 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x274 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x278 "PINCTRL159,Pin 159 Control Register"
|
|
bitfld.long 0x278 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x278 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x278 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x27C "PINCTRL160,Pin 160 Control Register"
|
|
bitfld.long 0x27C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x27C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x27C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x280 "PINCTRL161,Pin 161 Control Register"
|
|
bitfld.long 0x280 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x280 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x280 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x284 "PINCTRL162,Pin 162 Control Register"
|
|
bitfld.long 0x284 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x284 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x284 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x288 "PINCTRL163,Pin 163 Control Register"
|
|
bitfld.long 0x288 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x288 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x288 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x28C "PINCTRL164,Pin 164 Control Register"
|
|
bitfld.long 0x28C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x28C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x28C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x290 "PINCTRL165,Pin 165 Control Register"
|
|
bitfld.long 0x290 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x290 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x290 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x294 "PINCTRL166,Pin 166 Control Register"
|
|
bitfld.long 0x294 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x294 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x294 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x298 "PINCTRL167,Pin 167 Control Register"
|
|
bitfld.long 0x298 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x298 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x298 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x29C "PINCTRL168,Pin 168 Control Register"
|
|
bitfld.long 0x29C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x29C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x29C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2A0 "PINCTRL169,Pin 169 Control Register"
|
|
bitfld.long 0x2A0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2A0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2A0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2A4 "PINCTRL170,Pin 170 Control Register"
|
|
bitfld.long 0x2A4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2A4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2A4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2A8 "PINCTRL171,Pin 171 Control Register"
|
|
bitfld.long 0x2A8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2A8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2A8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2AC "PINCTRL172,Pin 172 Control Register"
|
|
bitfld.long 0x2AC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2AC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2AC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2B0 "PINCTRL173,Pin 173 Control Register"
|
|
bitfld.long 0x2B0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2B0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2B0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2B4 "PINCTRL174,Pin 174 Control Register"
|
|
bitfld.long 0x2B4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2B4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2B4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2B8 "PINCTRL175,Pin 175 Control Register"
|
|
bitfld.long 0x2B8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2B8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2B8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2BC "PINCTRL176,Pin 176 Control Register"
|
|
bitfld.long 0x2BC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2BC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2BC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2C0 "PINCTRL177,Pin 177 Control Register"
|
|
bitfld.long 0x2C0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2C0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2C0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2C4 "PINCTRL178,Pin 178 Control Register"
|
|
bitfld.long 0x2C4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2C4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2C4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2C8 "PINCTRL179,Pin 179 Control Register"
|
|
bitfld.long 0x2C8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2C8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2C8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2CC "PINCTRL180,Pin 180 Control Register"
|
|
bitfld.long 0x2CC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2CC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2CC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2D0 "PINCTRL181,Pin 181 Control Register"
|
|
bitfld.long 0x2D0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2D0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2D0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2D4 "PINCTRL182,Pin 182 Control Register"
|
|
bitfld.long 0x2D4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2D4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2D4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2D8 "PINCTRL183,Pin 183 Control Register"
|
|
bitfld.long 0x2D8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2D8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2D8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2DC "PINCTRL184,Pin 184 Control Register"
|
|
bitfld.long 0x2DC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2DC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2DC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2E0 "PINCTRL185,Pin 185 Control Register"
|
|
bitfld.long 0x2E0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2E0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2E0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2E4 "PINCTRL186,Pin 186 Control Register"
|
|
bitfld.long 0x2E4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2E4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2E4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2E8 "PINCTRL187,Pin 187 Control Register"
|
|
bitfld.long 0x2E8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2E8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2E8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2EC "PINCTRL188,Pin 188 Control Register"
|
|
bitfld.long 0x2EC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2EC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2EC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2F0 "PINCTRL189,Pin 189 Control Register"
|
|
bitfld.long 0x2F0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2F0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2F0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2F4 "PINCTRL190,Pin 190 Control Register"
|
|
bitfld.long 0x2F4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2F4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2F4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2F8 "PINCTRL191,Pin 191 Control Register"
|
|
bitfld.long 0x2F8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2F8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2F8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2FC "PINCTRL192,Pin 192 Control Register"
|
|
bitfld.long 0x2FC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2FC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2FC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x300 "PINCTRL193,Pin 193 Control Register"
|
|
bitfld.long 0x300 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x300 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x300 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x304 "PINCTRL194,Pin 194 Control Register"
|
|
bitfld.long 0x304 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x304 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x304 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x308 "PINCTRL195,Pin 195 Control Register"
|
|
bitfld.long 0x308 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x308 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x308 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x30C "PINCTRL196,Pin 196 Control Register"
|
|
bitfld.long 0x30C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x30C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x30C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x310 "PINCTRL197,Pin 197 Control Register"
|
|
bitfld.long 0x310 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x310 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x310 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x314 "PINCTRL198,Pin 198 Control Register"
|
|
bitfld.long 0x314 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x314 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x314 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x318 "PINCTRL199,Pin 199 Control Register"
|
|
bitfld.long 0x318 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x318 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x318 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x31C "PINCTRL200,Pin 200 Control Register"
|
|
bitfld.long 0x31C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x31C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x31C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x320 "PINCTRL201,Pin 201 Control Register"
|
|
bitfld.long 0x320 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x320 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x320 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x324 "PINCTRL202,Pin 202 Control Register"
|
|
bitfld.long 0x324 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x324 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x324 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x328 "PINCTRL203,Pin 203 Control Register"
|
|
bitfld.long 0x328 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x328 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x328 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x32C "PINCTRL204,Pin 204 Control Register"
|
|
bitfld.long 0x32C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x32C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x32C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x330 "PINCTRL205,Pin 205 Control Register"
|
|
bitfld.long 0x330 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x330 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x330 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x334 "PINCTRL206,Pin 206 Control Register"
|
|
bitfld.long 0x334 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x334 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x334 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x338 "PINCTRL207,Pin 207 Control Register"
|
|
bitfld.long 0x338 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x338 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x338 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x33C "PINCTRL208,Pin 208 Control Register"
|
|
bitfld.long 0x33C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x33C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x33C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x340 "PINCTRL209,Pin 209 Control Register"
|
|
bitfld.long 0x340 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x340 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x340 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x344 "PINCTRL210,Pin 210 Control Register"
|
|
bitfld.long 0x344 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x344 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x344 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x348 "PINCTRL211,Pin 211 Control Register"
|
|
bitfld.long 0x348 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x348 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x348 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x34C "PINCTRL212,Pin 212 Control Register"
|
|
bitfld.long 0x34C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x34C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x34C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x350 "PINCTRL213,Pin 213 Control Register"
|
|
bitfld.long 0x350 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x350 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x350 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x354 "PINCTRL214,Pin 214 Control Register"
|
|
bitfld.long 0x354 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x354 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x354 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x358 "PINCTRL215,Pin 215 Control Register"
|
|
bitfld.long 0x358 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x358 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x358 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x35C "PINCTRL216,Pin 216 Control Register"
|
|
bitfld.long 0x35C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x35C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x35C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x360 "PINCTRL217,Pin 217 Control Register"
|
|
bitfld.long 0x360 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x360 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x360 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x364 "PINCTRL218,Pin 218 Control Register"
|
|
bitfld.long 0x364 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x364 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x364 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x368 "PINCTRL219,Pin 219 Control Register"
|
|
bitfld.long 0x368 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x368 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x368 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x36C "PINCTRL220,Pin 220 Control Register"
|
|
bitfld.long 0x36C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x36C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x36C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x370 "PINCTRL221,Pin 221 Control Register"
|
|
bitfld.long 0x370 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x370 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x370 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x374 "PINCTRL222,Pin 222 Control Register"
|
|
bitfld.long 0x374 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x374 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x374 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x378 "PINCTRL223,Pin 223 Control Register"
|
|
bitfld.long 0x378 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x378 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x378 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x37C "PINCTRL224,Pin 224 Control Register"
|
|
bitfld.long 0x37C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x37C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x37C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x380 "PINCTRL225,Pin 225 Control Register"
|
|
bitfld.long 0x380 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x380 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x380 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x384 "PINCTRL226,Pin 226 Control Register"
|
|
bitfld.long 0x384 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x384 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x384 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x388 "PINCTRL227,Pin 227 Control Register"
|
|
bitfld.long 0x388 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x388 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x388 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x38C "PINCTRL228,Pin 228 Control Register"
|
|
bitfld.long 0x38C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x38C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x38C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x390 "PINCTRL229,Pin 229 Control Register"
|
|
bitfld.long 0x390 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x390 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x390 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x394 "PINCTRL230,Pin 230 Control Register"
|
|
bitfld.long 0x394 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x394 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x394 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x398 "PINCTRL231,Pin 231 Control Register"
|
|
bitfld.long 0x398 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x398 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x398 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x39C "PINCTRL232,Pin 232 Control Register"
|
|
bitfld.long 0x39C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x39C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x39C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3A0 "PINCTRL233,Pin 233 Control Register"
|
|
bitfld.long 0x3A0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3A0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3A0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3A4 "PINCTRL234,Pin 234 Control Register"
|
|
bitfld.long 0x3A4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3A4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3A4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3A8 "PINCTRL235,Pin 235 Control Register"
|
|
bitfld.long 0x3A8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3A8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3A8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3AC "PINCTRL236,Pin 236 Control Register"
|
|
bitfld.long 0x3AC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3AC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3AC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3B0 "PINCTRL237,Pin 237 Control Register"
|
|
bitfld.long 0x3B0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3B0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3B0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3B4 "PINCTRL238,Pin 238 Control Register"
|
|
bitfld.long 0x3B4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3B4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3B4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3B8 "PINCTRL239,Pin 239 Control Register"
|
|
bitfld.long 0x3B8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3B8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3B8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3BC "PINCTRL240,Pin 240 Control Register"
|
|
bitfld.long 0x3BC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3BC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3BC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3C0 "PINCTRL241,Pin 241 Control Register"
|
|
bitfld.long 0x3C0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3C0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3C0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3C4 "PINCTRL242,Pin 242 Control Register"
|
|
bitfld.long 0x3C4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3C4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3C4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3C8 "PINCTRL243,Pin 243 Control Register"
|
|
bitfld.long 0x3C8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3C8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3C8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3CC "PINCTRL244,Pin 244 Control Register"
|
|
bitfld.long 0x3CC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3CC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3CC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3D0 "PINCTRL245,Pin 245 Control Register"
|
|
bitfld.long 0x3D0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3D0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3D0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3D4 "PINCTRL246,Pin 246 Control Register"
|
|
bitfld.long 0x3D4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3D4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3D4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3D8 "PINCTRL247,Pin 247 Control Register"
|
|
bitfld.long 0x3D8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3D8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3D8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3DC "PINCTRL248,Pin 248 Control Register"
|
|
bitfld.long 0x3DC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3DC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3DC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3E0 "PINCTRL249,Pin 249 Control Register"
|
|
bitfld.long 0x3E0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3E0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3E0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3E4 "PINCTRL250,Pin 250 Control Register"
|
|
bitfld.long 0x3E4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3E4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3E4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3E8 "PINCTRL251,Pin 251 Control Register"
|
|
bitfld.long 0x3E8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3E8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3E8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3EC "PINCTRL252,Pin 252 Control Register"
|
|
bitfld.long 0x3EC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3EC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3EC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3F0 "PINCTRL253,Pin 253 Control Register"
|
|
bitfld.long 0x3F0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3F0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3F0 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3F4 "PINCTRL254,Pin 254 Control Register"
|
|
bitfld.long 0x3F4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3F4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3F4 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3F8 "PINCTRL255,Pin 255 Control Register"
|
|
bitfld.long 0x3F8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3F8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3F8 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3FC "PINCTRL256,Pin 256 Control Register"
|
|
bitfld.long 0x3FC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3FC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3FC 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x400 "PINCTRL257,Pin 257 Control Register"
|
|
bitfld.long 0x400 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x400 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x400 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x404 "PINCTRL258,Pin 258 Control Register"
|
|
bitfld.long 0x404 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x404 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x404 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x408 "PINCTRL259,Pin 259 Control Register"
|
|
bitfld.long 0x408 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x408 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x408 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x40C "PINCTRL260,Pin 260 Control Register"
|
|
bitfld.long 0x40C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x40C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x40C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x410 "PINCTRL261,Pin 261 Control Register"
|
|
bitfld.long 0x410 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x410 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x410 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x414 "PINCTRL262,Pin 262 Control Register"
|
|
bitfld.long 0x414 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x414 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x414 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x418 "PINCTRL263,Pin 263 Control Register"
|
|
bitfld.long 0x418 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x418 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x418 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x41C "PINCTRL264,Pin 264 Control Register"
|
|
bitfld.long 0x41C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x41C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x41C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x420 "PINCTRL265,Pin 265 Control Register"
|
|
bitfld.long 0x420 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x420 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x420 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x424 "PINCTRL266,Pin 266 Control Register"
|
|
bitfld.long 0x424 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x424 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x424 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x428 "PINCTRL267,Pin 267 Control Register"
|
|
bitfld.long 0x428 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x428 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x428 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x42C "PINCTRL268,Pin 268 Control Register"
|
|
bitfld.long 0x42C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x42C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x42C 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x430 "PINCTRL269,Pin 269 Control Register"
|
|
bitfld.long 0x430 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x430 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x430 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x434 "PINCTRL270,Pin 270 Control Register"
|
|
bitfld.long 0x434 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x434 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x434 0.--10. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
tree.end
|
|
rgroup.long 0xe00++0x3
|
|
line.long 0x00 "CQDETECT_STATUS,CQDETECT STATUS Register"
|
|
bitfld.long 0x00 12. " CQO ,IO group O voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 11. " CQN ,IO group N voltage mode" "1.8V,3.3V"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CQM ,IO group M voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 9. " CQL ,IO group L voltage mode" "1.8V,3.3V"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CQI ,IO group I voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 7. " CQH ,IO group H voltage mode" "1.8V,3.3V"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CQG ,IO group G voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 5. " CQF ,IO group F voltage mode" "1.8V,3.3V"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CQE ,IO group E voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 3. " CQD ,IO group D voltage mode" "1.8V,3.3V"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CQC ,IO group C voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 1. " CQB ,IO group B voltage mode" "1.8V,3.3V"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CQA ,IO group A voltage mode" "1.8V,3.3V"
|
|
group.long 0xe04++0x03
|
|
line.long 0x00 "DDR0_IO_CTRL,DDR0 IO Control Register"
|
|
bitfld.long 0x00 31. " DDR3_RST_DEF_VAL ,DDR3 reset default value" "0,1"
|
|
bitfld.long 0x00 30. " DDR_WUCLK_DISABLE ,Slow clock to WUCLKIN and ISOCLKIN of DDR0 and DDR1 emif SS and I/O's disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MDDR_SEL ,PHY to work in mDDR mode select" "Low,High"
|
|
bitfld.long 0x00 26.--27. " CKE_PULL ,Pull of CKE pin select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " DATA_PULL ,Pull of data pins select" "0,1,2,3"
|
|
bitfld.long 0x00 19.--20. " CS_SLEW ,Slew rate of CS pins select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " CS_IMPEDENCE ,Impedence of chip select pins select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11.--12. " CMD_SLEW ,Slew rate of command/address pins select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CMD_IMPEDENCE ,Impedence of command/address pins select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " DATA_SLEW ,Slew rate of data pins select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DATA_IMPEDENCE ,Impedence of data pins select" "0,1,2,3,4,5,6,7"
|
|
group.long 0xe0c++0x03
|
|
line.long 0x00 "VTP0_CTRL,VTP0 Control Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " PCIN ,P or MMR values from efuse"
|
|
hexmask.long.byte 0x00 8.--14. 1. " NCIN ,N or MMR values from efuse"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENABLE ,Active high enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " READY ,Training sequence complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOCK ,High freeze dynamic update pwrdn controller" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--3. " FILTER ,Digital filter" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLRZ ,Clear flops and start count again" "No effect,Cleared"
|
|
group.long 0xe14++0x03
|
|
line.long 0x00 "VREF_CTRL,VREF Control Register"
|
|
bitfld.long 0x00 3.--4. " DDR0_VREF_CCAP ,Coupling cap for DDR10 select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " DDR0_VREF_TAP ,Int ref for DDR0 select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DDR0_VREF_EN ,Internal reference enable for DDR0 select" "Disabled,Enabled"
|
|
group.long 0xe18++0x0f
|
|
line.long 0x00 "MLBP_SIG_IO_CTRL,MLBP SIG IO Control Register"
|
|
bitfld.long 0x00 16.--21. " NC_IN ,MLB LVDS Output Drive Trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " PC_IN ,MLB LVDS Output Drive Trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWRDNRX ,Powerdown MLB LVDS receiver" "No,Yes"
|
|
bitfld.long 0x00 4. " PWRDNTX ,Powerdown MLB LVDS transmitter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN_EXT_RES ,Internal resistors disable" "No,Yes"
|
|
bitfld.long 0x00 2. " ENLVCMOS ,Enable 2 lvcmos buffers mode" "MLB 6pin,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENN ,Enable padn receiver" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENP ,Enable padp receiver" "Disabled,Enabled"
|
|
line.long 0x04 "MLBP_DAT_IO_CTRL,MLBP DAT IO Control Register"
|
|
bitfld.long 0x04 16.--21. " NC_IN ,MLB LVDS Output Drive Trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 8.--13. " PC_IN ,MLB LVDS Output Drive Trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PWRDNRX ,Powerdown MLB LVDS receiver" "No,Yes"
|
|
bitfld.long 0x04 4. " PWRDNTX ,Powerdown MLB LVDS transmitter" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EN_EXT_RES ,Internal resistors disable" "No,Yes"
|
|
bitfld.long 0x04 2. " ENLVCMOS ,Enable 2 lvcmos buffers mode" "MLB 6pin,GPIO"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ENN ,Enable padn receiver" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ENP ,Enable padp receiver" "Disabled,Enabled"
|
|
line.long 0x08 "MLBP_CLK_BG_CTRL,MLBP Clock/BG Control Register"
|
|
bitfld.long 0x08 2.--7. " BG_TRIM ,MLB LVDS Bandgap Trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 1. " BG_PWRDN ,Powerdown bandgap for MLBP" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CLK_PWRDN ,Powerdown clock IO for MLBP" "No,Yes"
|
|
line.long 0x0c "SERDES_REFCLK_CTL,SerDes Refclk Powerdown Control Register"
|
|
bitfld.long 0x0c 1. " PWRDN_SE ,Powerdown both refclkp/n single ended receiver" "No,Yes"
|
|
bitfld.long 0x0c 0. " PWRDN ,Powerdown both refclkp/n receiver" "No,Yes"
|
|
tree "DSP Interrupt Mux"
|
|
width 18.
|
|
group.long 0xf00++0x53
|
|
line.long 0x0 "DSP_INTMUX_15_18,DSP Interrupt Mux Register for Interrupt 15 to 18"
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bitfld.long 0x0 24.--29. " INT_MUX_18 ,Interrupt mux for DSP's interrupt number 18" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x0 16.--21. " INT_MUX_17 ,Interrupt mux for DSP's interrupt number 17" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x0 8.--13. " INT_MUX_16 ,Interrupt mux for DSP's interrupt number 16" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x0 0.--5. " INT_MUX_15 ,Interrupt mux for DSP's interrupt number 15" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x4 "DSP_INTMUX_19_22,DSP Interrupt Mux Register for Interrupt 19 to 22"
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bitfld.long 0x4 24.--29. " INT_MUX_22 ,Interrupt mux for DSP's interrupt number 22" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x4 16.--21. " INT_MUX_21 ,Interrupt mux for DSP's interrupt number 21" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x4 8.--13. " INT_MUX_20 ,Interrupt mux for DSP's interrupt number 20" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x4 0.--5. " INT_MUX_19 ,Interrupt mux for DSP's interrupt number 19" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x8 "DSP_INTMUX_23_26,DSP Interrupt Mux Register for Interrupt 23 to 26"
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bitfld.long 0x8 24.--29. " INT_MUX_26 ,Interrupt mux for DSP's interrupt number 26" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x8 16.--21. " INT_MUX_25 ,Interrupt mux for DSP's interrupt number 25" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x8 8.--13. " INT_MUX_24 ,Interrupt mux for DSP's interrupt number 24" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x8 0.--5. " INT_MUX_23 ,Interrupt mux for DSP's interrupt number 23" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0xC "DSP_INTMUX_27_30,DSP Interrupt Mux Register for Interrupt 27 to 30"
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bitfld.long 0xC 24.--29. " INT_MUX_30 ,Interrupt mux for DSP's interrupt number 30" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0xC 16.--21. " INT_MUX_29 ,Interrupt mux for DSP's interrupt number 29" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0xC 8.--13. " INT_MUX_28 ,Interrupt mux for DSP's interrupt number 28" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0xC 0.--5. " INT_MUX_27 ,Interrupt mux for DSP's interrupt number 27" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x10 "DSP_INTMUX_31_34,DSP Interrupt Mux Register for Interrupt 31 to 34"
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bitfld.long 0x10 24.--29. " INT_MUX_34 ,Interrupt mux for DSP's interrupt number 34" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x10 16.--21. " INT_MUX_33 ,Interrupt mux for DSP's interrupt number 33" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x10 8.--13. " INT_MUX_32 ,Interrupt mux for DSP's interrupt number 32" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x10 0.--5. " INT_MUX_31 ,Interrupt mux for DSP's interrupt number 31" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x14 "DSP_INTMUX_35_38,DSP Interrupt Mux Register for Interrupt 35 to 38"
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bitfld.long 0x14 24.--29. " INT_MUX_38 ,Interrupt mux for DSP's interrupt number 38" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x14 16.--21. " INT_MUX_37 ,Interrupt mux for DSP's interrupt number 37" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x14 8.--13. " INT_MUX_36 ,Interrupt mux for DSP's interrupt number 36" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x14 0.--5. " INT_MUX_35 ,Interrupt mux for DSP's interrupt number 35" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x18 "DSP_INTMUX_39_42,DSP Interrupt Mux Register for Interrupt 39 to 42"
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bitfld.long 0x18 24.--29. " INT_MUX_42 ,Interrupt mux for DSP's interrupt number 42" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x18 16.--21. " INT_MUX_41 ,Interrupt mux for DSP's interrupt number 41" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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textline " "
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bitfld.long 0x18 8.--13. " INT_MUX_40 ,Interrupt mux for DSP's interrupt number 40" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x18 0.--5. " INT_MUX_39 ,Interrupt mux for DSP's interrupt number 39" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x1C "DSP_INTMUX_43_46,DSP Interrupt Mux Register for Interrupt 43 to 46"
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bitfld.long 0x1C 24.--29. " INT_MUX_46 ,Interrupt mux for DSP's interrupt number 46" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x1C 16.--21. " INT_MUX_45 ,Interrupt mux for DSP's interrupt number 45" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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textline " "
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bitfld.long 0x1C 8.--13. " INT_MUX_44 ,Interrupt mux for DSP's interrupt number 44" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x1C 0.--5. " INT_MUX_43 ,Interrupt mux for DSP's interrupt number 43" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x20 "DSP_INTMUX_47_50,DSP Interrupt Mux Register for Interrupt 47 to 50"
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bitfld.long 0x20 24.--29. " INT_MUX_50 ,Interrupt mux for DSP's interrupt number 50" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x20 16.--21. " INT_MUX_49 ,Interrupt mux for DSP's interrupt number 49" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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textline " "
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bitfld.long 0x20 8.--13. " INT_MUX_48 ,Interrupt mux for DSP's interrupt number 48" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x20 0.--5. " INT_MUX_47 ,Interrupt mux for DSP's interrupt number 47" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x24 "DSP_INTMUX_51_54,DSP Interrupt Mux Register for Interrupt 51 to 54"
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bitfld.long 0x24 24.--29. " INT_MUX_54 ,Interrupt mux for DSP's interrupt number 54" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x24 16.--21. " INT_MUX_53 ,Interrupt mux for DSP's interrupt number 53" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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textline " "
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bitfld.long 0x24 8.--13. " INT_MUX_52 ,Interrupt mux for DSP's interrupt number 52" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x24 0.--5. " INT_MUX_51 ,Interrupt mux for DSP's interrupt number 51" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x28 "DSP_INTMUX_55_58,DSP Interrupt Mux Register for Interrupt 55 to 58"
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bitfld.long 0x28 24.--29. " INT_MUX_58 ,Interrupt mux for DSP's interrupt number 58" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x28 16.--21. " INT_MUX_57 ,Interrupt mux for DSP's interrupt number 57" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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textline " "
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bitfld.long 0x28 8.--13. " INT_MUX_56 ,Interrupt mux for DSP's interrupt number 56" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x28 0.--5. " INT_MUX_55 ,Interrupt mux for DSP's interrupt number 55" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x2C "DSP_INTMUX_59_62,DSP Interrupt Mux Register for Interrupt 59 to 62"
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bitfld.long 0x2C 24.--29. " INT_MUX_62 ,Interrupt mux for DSP's interrupt number 62" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x2C 16.--21. " INT_MUX_61 ,Interrupt mux for DSP's interrupt number 61" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x2C 8.--13. " INT_MUX_60 ,Interrupt mux for DSP's interrupt number 60" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x2C 0.--5. " INT_MUX_59 ,Interrupt mux for DSP's interrupt number 59" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x30 "DSP_INTMUX_63_66,DSP Interrupt Mux Register for Interrupt 63 to 66"
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bitfld.long 0x30 24.--29. " INT_MUX_66 ,Interrupt mux for DSP's interrupt number 66" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x30 16.--21. " INT_MUX_65 ,Interrupt mux for DSP's interrupt number 65" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x30 8.--13. " INT_MUX_64 ,Interrupt mux for DSP's interrupt number 64" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x30 0.--5. " INT_MUX_63 ,Interrupt mux for DSP's interrupt number 63" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x34 "DSP_INTMUX_67_70,DSP Interrupt Mux Register for Interrupt 67 to 70"
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bitfld.long 0x34 24.--29. " INT_MUX_70 ,Interrupt mux for DSP's interrupt number 70" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x34 16.--21. " INT_MUX_69 ,Interrupt mux for DSP's interrupt number 69" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x34 8.--13. " INT_MUX_68 ,Interrupt mux for DSP's interrupt number 68" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x34 0.--5. " INT_MUX_67 ,Interrupt mux for DSP's interrupt number 67" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x38 "DSP_INTMUX_71_74,DSP Interrupt Mux Register for Interrupt 71 to 74"
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bitfld.long 0x38 24.--29. " INT_MUX_74 ,Interrupt mux for DSP's interrupt number 74" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x38 16.--21. " INT_MUX_73 ,Interrupt mux for DSP's interrupt number 73" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x38 8.--13. " INT_MUX_72 ,Interrupt mux for DSP's interrupt number 72" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x38 0.--5. " INT_MUX_71 ,Interrupt mux for DSP's interrupt number 71" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x3C "DSP_INTMUX_75_78,DSP Interrupt Mux Register for Interrupt 75 to 78"
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bitfld.long 0x3C 24.--29. " INT_MUX_78 ,Interrupt mux for DSP's interrupt number 78" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x3C 16.--21. " INT_MUX_77 ,Interrupt mux for DSP's interrupt number 77" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x3C 8.--13. " INT_MUX_76 ,Interrupt mux for DSP's interrupt number 76" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x3C 0.--5. " INT_MUX_75 ,Interrupt mux for DSP's interrupt number 75" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x40 "DSP_INTMUX_79_82,DSP Interrupt Mux Register for Interrupt 79 to 82"
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bitfld.long 0x40 24.--29. " INT_MUX_82 ,Interrupt mux for DSP's interrupt number 82" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x40 16.--21. " INT_MUX_81 ,Interrupt mux for DSP's interrupt number 81" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x40 8.--13. " INT_MUX_80 ,Interrupt mux for DSP's interrupt number 80" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x40 0.--5. " INT_MUX_79 ,Interrupt mux for DSP's interrupt number 79" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x44 "DSP_INTMUX_83_86,DSP Interrupt Mux Register for Interrupt 83 to 86"
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bitfld.long 0x44 24.--29. " INT_MUX_86 ,Interrupt mux for DSP's interrupt number 86" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x44 16.--21. " INT_MUX_85 ,Interrupt mux for DSP's interrupt number 85" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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textline " "
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bitfld.long 0x44 8.--13. " INT_MUX_84 ,Interrupt mux for DSP's interrupt number 84" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x44 0.--5. " INT_MUX_83 ,Interrupt mux for DSP's interrupt number 83" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x48 "DSP_INTMUX_87_90,DSP Interrupt Mux Register for Interrupt 87 to 90"
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bitfld.long 0x48 24.--29. " INT_MUX_90 ,Interrupt mux for DSP's interrupt number 90" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x48 16.--21. " INT_MUX_89 ,Interrupt mux for DSP's interrupt number 89" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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textline " "
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bitfld.long 0x48 8.--13. " INT_MUX_88 ,Interrupt mux for DSP's interrupt number 88" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x48 0.--5. " INT_MUX_87 ,Interrupt mux for DSP's interrupt number 87" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x4C "DSP_INTMUX_91_94,DSP Interrupt Mux Register for Interrupt 91 to 94"
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bitfld.long 0x4C 24.--29. " INT_MUX_94 ,Interrupt mux for DSP's interrupt number 94" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x4C 16.--21. " INT_MUX_93 ,Interrupt mux for DSP's interrupt number 93" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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textline " "
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bitfld.long 0x4C 8.--13. " INT_MUX_92 ,Interrupt mux for DSP's interrupt number 92" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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bitfld.long 0x4C 0.--5. " INT_MUX_91 ,Interrupt mux for DSP's interrupt number 91" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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line.long 0x50 "DSP_INTMUX_95,DSP Interrupt Mux Register for Interrupt 95"
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bitfld.long 0x50 0.--5. " INT_MUX_95 ,Interrupt mux for DSP's interrupt number 95" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT1,DCAN1PARITY,DCAN1PARITY,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMAMPERR,TINT8,WDTINT0,USBSSINT,USBINT0,USBINT1,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,Reserved,ADC_TSC_GENINT,MB2INT3,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,EQEP0INT,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,?..."
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tree.end
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tree "MEDIACTL Interrupt Mux"
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width 23.
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group.long 0xf54++0x3b
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line.long 0x0 "MEDIACTL_INTMUX_0_3,MEDIACTL Interrupt Mux Register for Interrupt 0 to 3"
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bitfld.long 0x0 24.--30. " INT_MUX_3 ,Interrupt mux for MEDIACTL's interrupt number 3 " "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x0 16.--22. " INT_MUX_2 ,Interrupt mux for MEDIACTL's interrupt number 2 " "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0x0 8.--14. " INT_MUX_1 ,Interrupt mux for MEDIACTL's interrupt number 1 " "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x0 0.--6. " INT_MUX_0 ,Interrupt mux for MEDIACTL's interrupt number 0 " "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0x4 "MEDIACTL_INTMUX_4_7,MEDIACTL Interrupt Mux Register for Interrupt 4 to 7"
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bitfld.long 0x4 24.--30. " INT_MUX_7 ,Interrupt mux for MEDIACTL's interrupt number 7 " "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x4 16.--22. " INT_MUX_6 ,Interrupt mux for MEDIACTL's interrupt number 6 " "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0x4 8.--14. " INT_MUX_5 ,Interrupt mux for MEDIACTL's interrupt number 5 " "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x4 0.--6. " INT_MUX_4 ,Interrupt mux for MEDIACTL's interrupt number 4 " "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0x8 "MEDIACTL_INTMUX_8_11,MEDIACTL Interrupt Mux Register for Interrupt 8 to 11"
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bitfld.long 0x8 24.--30. " INT_MUX_11 ,Interrupt mux for MEDIACTL's interrupt number 11" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x8 16.--22. " INT_MUX_10 ,Interrupt mux for MEDIACTL's interrupt number 10" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0x8 8.--14. " INT_MUX_9 ,Interrupt mux for MEDIACTL's interrupt number 9 " "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x8 0.--6. " INT_MUX_8 ,Interrupt mux for MEDIACTL's interrupt number 8 " "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0xC "MEDIACTL_INTMUX_12_15,MEDIACTL Interrupt Mux Register for Interrupt 12 to 15"
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bitfld.long 0xC 24.--30. " INT_MUX_15 ,Interrupt mux for MEDIACTL's interrupt number 15" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0xC 16.--22. " INT_MUX_14 ,Interrupt mux for MEDIACTL's interrupt number 14" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0xC 8.--14. " INT_MUX_13 ,Interrupt mux for MEDIACTL's interrupt number 13" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0xC 0.--6. " INT_MUX_12 ,Interrupt mux for MEDIACTL's interrupt number 12" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0x10 "MEDIACTL_INTMUX_16_19,MEDIACTL Interrupt Mux Register for Interrupt 16 to 19"
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bitfld.long 0x10 24.--30. " INT_MUX_19 ,Interrupt mux for MEDIACTL's interrupt number 19" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x10 16.--22. " INT_MUX_18 ,Interrupt mux for MEDIACTL's interrupt number 18" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0x10 8.--14. " INT_MUX_17 ,Interrupt mux for MEDIACTL's interrupt number 17" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x10 0.--6. " INT_MUX_16 ,Interrupt mux for MEDIACTL's interrupt number 16" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0x14 "MEDIACTL_INTMUX_20_23,MEDIACTL Interrupt Mux Register for Interrupt 20 to 23"
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bitfld.long 0x14 24.--30. " INT_MUX_23 ,Interrupt mux for MEDIACTL's interrupt number 23" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x14 16.--22. " INT_MUX_22 ,Interrupt mux for MEDIACTL's interrupt number 22" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0x14 8.--14. " INT_MUX_21 ,Interrupt mux for MEDIACTL's interrupt number 21" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x14 0.--6. " INT_MUX_20 ,Interrupt mux for MEDIACTL's interrupt number 20" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0x18 "MEDIACTL_INTMUX_24_27,MEDIACTL Interrupt Mux Register for Interrupt 24 to 27"
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bitfld.long 0x18 24.--30. " INT_MUX_27 ,Interrupt mux for MEDIACTL's interrupt number 27" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x18 16.--22. " INT_MUX_26 ,Interrupt mux for MEDIACTL's interrupt number 26" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0x18 8.--14. " INT_MUX_25 ,Interrupt mux for MEDIACTL's interrupt number 25" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x18 0.--6. " INT_MUX_24 ,Interrupt mux for MEDIACTL's interrupt number 24" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0x1C "MEDIACTL_INTMUX_28_31,MEDIACTL Interrupt Mux Register for Interrupt 28 to 31"
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bitfld.long 0x1C 24.--30. " INT_MUX_31 ,Interrupt mux for MEDIACTL's interrupt number 31" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x1C 16.--22. " INT_MUX_30 ,Interrupt mux for MEDIACTL's interrupt number 30" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0x1C 8.--14. " INT_MUX_29 ,Interrupt mux for MEDIACTL's interrupt number 29" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x1C 0.--6. " INT_MUX_28 ,Interrupt mux for MEDIACTL's interrupt number 28" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0x20 "MEDIACTL_INTMUX_32_35,MEDIACTL Interrupt Mux Register for Interrupt 32 to 35"
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bitfld.long 0x20 24.--30. " INT_MUX_35 ,Interrupt mux for MEDIACTL's interrupt number 35" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x20 16.--22. " INT_MUX_34 ,Interrupt mux for MEDIACTL's interrupt number 34" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0x20 8.--14. " INT_MUX_33 ,Interrupt mux for MEDIACTL's interrupt number 33" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x20 0.--6. " INT_MUX_32 ,Interrupt mux for MEDIACTL's interrupt number 32" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0x24 "MEDIACTL_INTMUX_36_39,MEDIACTL Interrupt Mux Register for Interrupt 36 to 39"
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bitfld.long 0x24 24.--30. " INT_MUX_39 ,Interrupt mux for MEDIACTL's interrupt number 39" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x24 16.--22. " INT_MUX_38 ,Interrupt mux for MEDIACTL's interrupt number 38" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0x24 8.--14. " INT_MUX_37 ,Interrupt mux for MEDIACTL's interrupt number 37" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x24 0.--6. " INT_MUX_36 ,Interrupt mux for MEDIACTL's interrupt number 36" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0x28 "MEDIACTL_INTMUX_40_43,MEDIACTL Interrupt Mux Register for Interrupt 40 to 43"
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bitfld.long 0x28 24.--30. " INT_MUX_43 ,Interrupt mux for MEDIACTL's interrupt number 43" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x28 16.--22. " INT_MUX_42 ,Interrupt mux for MEDIACTL's interrupt number 42" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0x28 8.--14. " INT_MUX_41 ,Interrupt mux for MEDIACTL's interrupt number 41" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x28 0.--6. " INT_MUX_40 ,Interrupt mux for MEDIACTL's interrupt number 40" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0x2C "MEDIACTL_INTMUX_44_47,MEDIACTL Interrupt Mux Register for Interrupt 44 to 47"
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bitfld.long 0x2C 24.--30. " INT_MUX_47 ,Interrupt mux for MEDIACTL's interrupt number 47" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x2C 16.--22. " INT_MUX_46 ,Interrupt mux for MEDIACTL's interrupt number 46" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0x2C 8.--14. " INT_MUX_45 ,Interrupt mux for MEDIACTL's interrupt number 45" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x2C 0.--6. " INT_MUX_44 ,Interrupt mux for MEDIACTL's interrupt number 44" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0x30 "MEDIACTL_INTMUX_48_51,MEDIACTL Interrupt Mux Register for Interrupt 48 to 51"
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bitfld.long 0x30 24.--30. " INT_MUX_51 ,Interrupt mux for MEDIACTL's interrupt number 51" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x30 16.--22. " INT_MUX_50 ,Interrupt mux for MEDIACTL's interrupt number 50" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0x30 8.--14. " INT_MUX_49 ,Interrupt mux for MEDIACTL's interrupt number 49" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x30 0.--6. " INT_MUX_48 ,Interrupt mux for MEDIACTL's interrupt number 48" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0x34 "MEDIACTL_INTMUX_52_55,MEDIACTL Interrupt Mux Register for Interrupt 52 to 55"
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bitfld.long 0x34 24.--30. " INT_MUX_55 ,Interrupt mux for MEDIACTL's interrupt number 55" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x34 16.--22. " INT_MUX_54 ,Interrupt mux for MEDIACTL's interrupt number 54" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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textline " "
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bitfld.long 0x34 8.--14. " INT_MUX_53 ,Interrupt mux for MEDIACTL's interrupt number 53" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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bitfld.long 0x34 0.--6. " INT_MUX_52 ,Interrupt mux for MEDIACTL's interrupt number 52" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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line.long 0x38 "MEDIACTL_INTMUX_56,MEDIACTL Interrupt Mux Register for Interrupt 56"
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bitfld.long 0x38 0.--6. " INT_MUX_56 ,Interrupt mux for MEDIACTL's interrupt number 56" "Default,Reserved,SDINT1,SDINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,Reserved,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0INT0,DCAN0INT1,DCAN0PARITY,DCAN1INT0,DCAN1INT0,DCAN1INT1,DCAN1PARITY,MLBSYSINT0,MLBSYSINT1,MLBINT,RTCINT,RTCALARMINT,Reserved,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT1,SPIINT2,SPIINT3,Reserved,Reserved,PRUSS_EVTOUT0,PRUSS_EVTOUT1,PRUSS_EVTOUT2,PRUSS_EVTOUT3,PRUSS_EVTOUT4,PRUSS_EVTOUT5,PRUSS_EVTOUT6,PRUSS_EVTOUT7,EPWM0_TZINT,EPWM1_TZINT,EPWM2_TZINT,EPWM0INT,EPWM1INT,EPWM2INT,Reserved,EQEP1INT,EQEP2INT,ECAP0INT,ECAP1INT,ECAP2INT,GPIOINT4A,GPIOINT4B,GPIOINT5A,GPIOINT5B,ADC_TSC_GENINT,UARTINT6,UARTINT7,2DHWAINT,2DHWAMMU,EQEP0INT,MB3INT2,MB3INT1,?..."
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tree.end
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tree "EDMA3CC Event Mux"
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width 22.
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group.long 0xf90++0x3f
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line.long 0x0 "EDMA3CC_EVTMUX_0_3,TPCC Event Mux Register for Event 0 to 3"
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bitfld.long 0x0 24.--29. " EVT_MUX_3 ,Event Mux for TPCC Event number 3 " "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x0 16.--22. " EVT_MUX_2 ,Event Mux for TPCC Event number 2 " "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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textline " "
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bitfld.long 0x0 8.--13. " EVT_MUX_1 ,Event Mux for TPCC Event number 1 " "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x0 0.--5. " EVT_MUX_0 ,Event Mux for TPCC Event number 0 " "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x4 "EDMA3CC_EVTMUX_4_7,TPCC Event Mux Register for Event 4 to 7"
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bitfld.long 0x4 24.--29. " EVT_MUX_7 ,Event Mux for TPCC Event number 7 " "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x4 16.--22. " EVT_MUX_6 ,Event Mux for TPCC Event number 6 " "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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textline " "
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bitfld.long 0x4 8.--13. " EVT_MUX_5 ,Event Mux for TPCC Event number 5 " "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x4 0.--5. " EVT_MUX_4 ,Event Mux for TPCC Event number 4 " "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x8 "EDMA3CC_EVTMUX_8_11,TPCC Event Mux Register for Event 8 to 11"
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bitfld.long 0x8 24.--29. " EVT_MUX_11 ,Event Mux for TPCC Event number 11" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x8 16.--22. " EVT_MUX_10 ,Event Mux for TPCC Event number 10" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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textline " "
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bitfld.long 0x8 8.--13. " EVT_MUX_9 ,Event Mux for TPCC Event number 9 " "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x8 0.--5. " EVT_MUX_8 ,Event Mux for TPCC Event number 8 " "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0xC "EDMA3CC_EVTMUX_12_15,TPCC Event Mux Register for Event 12 to 15"
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bitfld.long 0xC 24.--29. " EVT_MUX_15 ,Event Mux for TPCC Event number 15" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0xC 16.--22. " EVT_MUX_14 ,Event Mux for TPCC Event number 14" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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textline " "
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bitfld.long 0xC 8.--13. " EVT_MUX_13 ,Event Mux for TPCC Event number 13" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0xC 0.--5. " EVT_MUX_12 ,Event Mux for TPCC Event number 12" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x10 "EDMA3CC_EVTMUX_16_19,TPCC Event Mux Register for Event 16 to 19"
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bitfld.long 0x10 24.--29. " EVT_MUX_19 ,Event Mux for TPCC Event number 19" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x10 16.--22. " EVT_MUX_18 ,Event Mux for TPCC Event number 18" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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textline " "
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bitfld.long 0x10 8.--13. " EVT_MUX_17 ,Event Mux for TPCC Event number 17" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x10 0.--5. " EVT_MUX_16 ,Event Mux for TPCC Event number 16" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x14 "EDMA3CC_EVTMUX_20_23,TPCC Event Mux Register for Event 20 to 23"
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bitfld.long 0x14 24.--29. " EVT_MUX_23 ,Event Mux for TPCC Event number 23" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x14 16.--22. " EVT_MUX_22 ,Event Mux for TPCC Event number 22" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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textline " "
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bitfld.long 0x14 8.--13. " EVT_MUX_21 ,Event Mux for TPCC Event number 21" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x14 0.--5. " EVT_MUX_20 ,Event Mux for TPCC Event number 20" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x18 "EDMA3CC_EVTMUX_24_27,TPCC Event Mux Register for Event 24 to 27"
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bitfld.long 0x18 24.--29. " EVT_MUX_27 ,Event Mux for TPCC Event number 27" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x18 16.--22. " EVT_MUX_26 ,Event Mux for TPCC Event number 26" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x18 8.--13. " EVT_MUX_25 ,Event Mux for TPCC Event number 25" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x18 0.--5. " EVT_MUX_24 ,Event Mux for TPCC Event number 24" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x1C "EDMA3CC_EVTMUX_28_31,TPCC Event Mux Register for Event 28 to 31"
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bitfld.long 0x1C 24.--29. " EVT_MUX_31 ,Event Mux for TPCC Event number 31" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x1C 16.--22. " EVT_MUX_30 ,Event Mux for TPCC Event number 30" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x1C 8.--13. " EVT_MUX_29 ,Event Mux for TPCC Event number 29" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x1C 0.--5. " EVT_MUX_28 ,Event Mux for TPCC Event number 28" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x20 "EDMA3CC_EVTMUX_32_35,TPCC Event Mux Register for Event 32 to 35"
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bitfld.long 0x20 24.--29. " EVT_MUX_35 ,Event Mux for TPCC Event number 35" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x20 16.--22. " EVT_MUX_34 ,Event Mux for TPCC Event number 34" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x20 8.--13. " EVT_MUX_33 ,Event Mux for TPCC Event number 33" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x20 0.--5. " EVT_MUX_32 ,Event Mux for TPCC Event number 32" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x24 "EDMA3CC_EVTMUX_36_39,TPCC Event Mux Register for Event 36 to 39"
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bitfld.long 0x24 24.--29. " EVT_MUX_39 ,Event Mux for TPCC Event number 39" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x24 16.--22. " EVT_MUX_38 ,Event Mux for TPCC Event number 38" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x24 8.--13. " EVT_MUX_37 ,Event Mux for TPCC Event number 37" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x24 0.--5. " EVT_MUX_36 ,Event Mux for TPCC Event number 36" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x28 "EDMA3CC_EVTMUX_40_43,TPCC Event Mux Register for Event 40 to 43"
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bitfld.long 0x28 24.--29. " EVT_MUX_43 ,Event Mux for TPCC Event number 43" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x28 16.--22. " EVT_MUX_42 ,Event Mux for TPCC Event number 42" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x28 8.--13. " EVT_MUX_41 ,Event Mux for TPCC Event number 41" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x28 0.--5. " EVT_MUX_40 ,Event Mux for TPCC Event number 40" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x2C "EDMA3CC_EVTMUX_44_47,TPCC Event Mux Register for Event 44 to 47"
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bitfld.long 0x2C 24.--29. " EVT_MUX_47 ,Event Mux for TPCC Event number 47" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x2C 16.--22. " EVT_MUX_46 ,Event Mux for TPCC Event number 46" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x2C 8.--13. " EVT_MUX_45 ,Event Mux for TPCC Event number 45" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x2C 0.--5. " EVT_MUX_44 ,Event Mux for TPCC Event number 44" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x30 "EDMA3CC_EVTMUX_48_51,TPCC Event Mux Register for Event 48 to 51"
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bitfld.long 0x30 24.--29. " EVT_MUX_51 ,Event Mux for TPCC Event number 51" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x30 16.--22. " EVT_MUX_50 ,Event Mux for TPCC Event number 50" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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|
textline " "
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bitfld.long 0x30 8.--13. " EVT_MUX_49 ,Event Mux for TPCC Event number 49" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x30 0.--5. " EVT_MUX_48 ,Event Mux for TPCC Event number 48" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x34 "EDMA3CC_EVTMUX_52_55,TPCC Event Mux Register for Event 52 to 55"
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bitfld.long 0x34 24.--29. " EVT_MUX_55 ,Event Mux for TPCC Event number 55" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x34 16.--22. " EVT_MUX_54 ,Event Mux for TPCC Event number 54" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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textline " "
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bitfld.long 0x34 8.--13. " EVT_MUX_53 ,Event Mux for TPCC Event number 53" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x34 0.--5. " EVT_MUX_52 ,Event Mux for TPCC Event number 52" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x38 "EDMA3CC_EVTMUX_56_59,TPCC Event Mux Register for Event 56 to 59"
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bitfld.long 0x38 24.--29. " EVT_MUX_59 ,Event Mux for TPCC Event number 59" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x38 16.--22. " EVT_MUX_58 ,Event Mux for TPCC Event number 58" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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textline " "
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bitfld.long 0x38 8.--13. " EVT_MUX_57 ,Event Mux for TPCC Event number 57" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x38 0.--5. " EVT_MUX_56 ,Event Mux for TPCC Event number 56" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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line.long 0x3C "EDMA3CC_EVTMUX_60_63,TPCC Event Mux Register for Event 60 to 63"
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bitfld.long 0x3C 24.--29. " EVT_MUX_63 ,Event Mux for TPCC Event number 63" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x3C 16.--22. " EVT_MUX_62 ,Event Mux for TPCC Event number 62" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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textline " "
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bitfld.long 0x3C 8.--13. " EVT_MUX_61 ,Event Mux for TPCC Event number 61" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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bitfld.long 0x3C 0.--5. " EVT_MUX_60 ,Event Mux for TPCC Event number 60" "Default,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3,ADCFIFOEVT,ADCFIFO1EVT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,UTXEVT6,URXEVT6,UTXEVT7,URXEVT7,GPIOEVT4,GPIOEVT5,?..."
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tree.end
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group.long 0xfd0++0xb
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line.long 0x00 "TIMER_EVTCAPT,Timer 5/6/7 Event Capture Mux Register"
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bitfld.long 0x00 16.--21. " TIMER7_EVTCAPT ,Timer 7 event capture mux" "Timer IO pin,UART0INT,UART1INT,UART2INT,UART3INT,UART4INT,UART5INT,EMACSWRXTHR,EMACSWRXINT,EMACSWTXINT,EMACSWMISC,MCATXINT0,MCARXINT0,MCATXINT1,MCARXINT1,MCATXINT2,MCARXINT2,GPIOINT0A,GPIOINT0B,GPIOINT1A,GPIOINT1B,GPIOINT2A,GPIOINT2B,GPIOINT3A,GPIOINT3B,DCAN0_INT0,DCAN0_INT1,DCAN0_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AXEVT3,AXEVT4,AXEVT5,?..."
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bitfld.long 0x00 8.--13. " TIMER6_EVTCAPT ,Timer 6 event capture mux" "Timer IO pin,UART0INT,UART1INT,UART2INT,UART3INT,UART4INT,UART5INT,EMACSWRXTHR,EMACSWRXINT,EMACSWTXINT,EMACSWMISC,MCATXINT0,MCARXINT0,MCATXINT1,MCARXINT1,MCATXINT2,MCARXINT2,GPIOINT0A,GPIOINT0B,GPIOINT1A,GPIOINT1B,GPIOINT2A,GPIOINT2B,GPIOINT3A,GPIOINT3B,DCAN0_INT0,DCAN0_INT1,DCAN0_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AXEVT3,AXEVT4,AXEVT5,?..."
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textline " "
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bitfld.long 0x00 0.--5. " TIMER5_EVTCAPT ,Timer 5 event capture mux" "Timer IO pin,UART0INT,UART1INT,UART2INT,UART3INT,UART4INT,UART5INT,EMACSWRXTHR,EMACSWRXINT,EMACSWTXINT,EMACSWMISC,MCATXINT0,MCARXINT0,MCATXINT1,MCARXINT1,MCATXINT2,MCARXINT2,GPIOINT0A,GPIOINT0B,GPIOINT1A,GPIOINT1B,GPIOINT2A,GPIOINT2B,GPIOINT3A,GPIOINT3B,DCAN0_INT0,DCAN0_INT1,DCAN0_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AXEVT3,AXEVT4,AXEVT5,?..."
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line.long 0x04 "GPIO_MUX,GPIO Mux Register"
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bitfld.long 0x04 5. " GPIO1_5_MUX ,GPIO1_5 input mux" "Pad,USB1 charge detect"
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bitfld.long 0x04 4. " GPIO1_4_MUX ,GPIO1_4 input mux" "Pad,USB0 charge detect"
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textline " "
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bitfld.long 0x04 3. " GPIO1_3_MUX ,GPIO1_3 input mux" "Pad,Bandgap1 Tshut"
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bitfld.long 0x04 2. " GPIO1_2_MUX ,GPIO1_2 input mux" "Pad,Bandgap0 Tshut"
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textline " "
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bitfld.long 0x04 1. " GPIO1_1_MUX ,GPIO1_1 input mux" "Pad,Vdac_tvint"
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bitfld.long 0x04 0. " GPIO1_0_MUX ,GPIO1_0 input mux" "Pad,Vdac_tvint"
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line.long 0x08 "ADC_EVT_CAPT,ADC Event Capture Select Register"
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bitfld.long 0x08 0.--3. " ADC_EVTCAPT ,ADC event capture mux select" "PRUSS Host Event 0,TIMER4,TIMER5,TIMER6,TIMER7,?..."
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group.long 0x1000++0x3
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line.long 0x00 "RESET_ISO,Reset Isolation Register"
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bitfld.long 0x00 3. " RMII_ISO1 ,Isolate EMAC_RMREFCLK, EMAC[1]_RMx (Option 1), EMAC[0]_RMx, and MDIO/MDCLK" "Not isolated,Isolated"
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bitfld.long 0x00 1. " GMII_ISO ,Isolate EMAC[1]_Mx/Other, EMAC[0]_Mx/EMAC[1:0]_RGx, and MDIO/MDCLK" "Not isolated,Isolated"
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textline " "
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bitfld.long 0x00 2. " RMII_ISO0 ,Isolate EMAC_RMREFCLK, EMAC[1]_RMx (Option 0), EMAC[0]_RMx, and MDIO/MDCLK" "Not isolated,Isolated"
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bitfld.long 0x00 0. " ISO_CONTROL ,Ethernet Reset Isolation control" "Not isolated,Isolated"
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group.long 0x1318++0x03
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line.long 0x00 "DCAN_RX_CNTRL,DCAN RX Pin Mux Select Register"
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bitfld.long 0x00 1. " DCAN_1_RXD_MUX ,DCAN1_RX_IN vs RTC_EXT_WAKEUP[1] pin mux control" "DCAN1_RX_IN,RTC_EXT_WAKEUP[1]"
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bitfld.long 0x00 0. " DCAN_0_RXD_MUX ,DCAN0_RX_IN vs RTC_EXT_WAKEUP[0] pin mux control" "DCAN0_RX_IN,RTC_EXT_WAKEUP[0]"
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group.long 0x1348++0x03
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line.long 0x00 "RTC_IDLE,RTC Idle Register"
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bitfld.long 0x00 1.--2. " SIDLE_ACK ,Idle Status Acknowledge" "FUNCT,IDLETRANS,Reserved,IDLE"
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bitfld.long 0x00 0. " SIDLE_REQ ,Idle Status Request" "Not requested,Requested"
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tree "MPU Interrupt Mux"
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width 20.
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group.long 0x1600++0x77
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line.long 0x0 "MPU_INTMUX_11 _8 ,MPU INTMUX 11 42 Register"
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hexmask.long.byte 0x0 24.--31. 1. " INT_MUX_11 ,Interrupt mux for MPU interrupt number 11 "
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hexmask.long.byte 0x0 16.--23. 1. " INT_MUX_10 ,Interrupt mux for MPU interrupt number 10 "
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textline " "
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hexmask.long.byte 0x0 8.--15. 1. " INT_MUX_9 ,Interrupt mux for MPU interrupt number 9 "
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hexmask.long.byte 0x0 0.--7. 1. " INT_MUX_8 ,Interrupt mux for MPU interrupt number 8 "
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line.long 0x4 "MPU_INTMUX_15 _12 ,MPU INTMUX 15 42 Register"
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hexmask.long.byte 0x4 24.--31. 1. " INT_MUX_15 ,Interrupt mux for MPU interrupt number 15 "
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hexmask.long.byte 0x4 16.--23. 1. " INT_MUX_14 ,Interrupt mux for MPU interrupt number 14 "
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textline " "
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hexmask.long.byte 0x4 8.--15. 1. " INT_MUX_13 ,Interrupt mux for MPU interrupt number 13 "
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hexmask.long.byte 0x4 0.--7. 1. " INT_MUX_12 ,Interrupt mux for MPU interrupt number 12 "
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line.long 0x8 "MPU_INTMUX_19 _16 ,MPU INTMUX 19 42 Register"
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hexmask.long.byte 0x8 24.--31. 1. " INT_MUX_19 ,Interrupt mux for MPU interrupt number 19 "
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hexmask.long.byte 0x8 16.--23. 1. " INT_MUX_18 ,Interrupt mux for MPU interrupt number 18 "
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textline " "
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hexmask.long.byte 0x8 8.--15. 1. " INT_MUX_17 ,Interrupt mux for MPU interrupt number 17 "
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hexmask.long.byte 0x8 0.--7. 1. " INT_MUX_16 ,Interrupt mux for MPU interrupt number 16 "
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line.long 0xC "MPU_INTMUX_23 _20 ,MPU INTMUX 23 42 Register"
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hexmask.long.byte 0xC 24.--31. 1. " INT_MUX_23 ,Interrupt mux for MPU interrupt number 23 "
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hexmask.long.byte 0xC 16.--23. 1. " INT_MUX_22 ,Interrupt mux for MPU interrupt number 22 "
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textline " "
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hexmask.long.byte 0xC 8.--15. 1. " INT_MUX_21 ,Interrupt mux for MPU interrupt number 21 "
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hexmask.long.byte 0xC 0.--7. 1. " INT_MUX_20 ,Interrupt mux for MPU interrupt number 20 "
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line.long 0x10 "MPU_INTMUX_27 _24 ,MPU INTMUX 27 42 Register"
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hexmask.long.byte 0x10 24.--31. 1. " INT_MUX_27 ,Interrupt mux for MPU interrupt number 27 "
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hexmask.long.byte 0x10 16.--23. 1. " INT_MUX_26 ,Interrupt mux for MPU interrupt number 26 "
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textline " "
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hexmask.long.byte 0x10 8.--15. 1. " INT_MUX_25 ,Interrupt mux for MPU interrupt number 25 "
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hexmask.long.byte 0x10 0.--7. 1. " INT_MUX_24 ,Interrupt mux for MPU interrupt number 24 "
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line.long 0x14 "MPU_INTMUX_31 _28 ,MPU INTMUX 31 42 Register"
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hexmask.long.byte 0x14 24.--31. 1. " INT_MUX_31 ,Interrupt mux for MPU interrupt number 31 "
|
|
hexmask.long.byte 0x14 16.--23. 1. " INT_MUX_30 ,Interrupt mux for MPU interrupt number 30 "
|
|
textline " "
|
|
hexmask.long.byte 0x14 8.--15. 1. " INT_MUX_29 ,Interrupt mux for MPU interrupt number 29 "
|
|
hexmask.long.byte 0x14 0.--7. 1. " INT_MUX_28 ,Interrupt mux for MPU interrupt number 28 "
|
|
line.long 0x18 "MPU_INTMUX_35 _32 ,MPU INTMUX 35 42 Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " INT_MUX_35 ,Interrupt mux for MPU interrupt number 35 "
|
|
hexmask.long.byte 0x18 16.--23. 1. " INT_MUX_34 ,Interrupt mux for MPU interrupt number 34 "
|
|
textline " "
|
|
hexmask.long.byte 0x18 8.--15. 1. " INT_MUX_33 ,Interrupt mux for MPU interrupt number 33 "
|
|
hexmask.long.byte 0x18 0.--7. 1. " INT_MUX_32 ,Interrupt mux for MPU interrupt number 32 "
|
|
line.long 0x1C "MPU_INTMUX_39 _36 ,MPU INTMUX 39 42 Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " INT_MUX_39 ,Interrupt mux for MPU interrupt number 39 "
|
|
hexmask.long.byte 0x1C 16.--23. 1. " INT_MUX_38 ,Interrupt mux for MPU interrupt number 38 "
|
|
textline " "
|
|
hexmask.long.byte 0x1C 8.--15. 1. " INT_MUX_37 ,Interrupt mux for MPU interrupt number 37 "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " INT_MUX_36 ,Interrupt mux for MPU interrupt number 36 "
|
|
line.long 0x20 "MPU_INTMUX_43 _40 ,MPU INTMUX 43 42 Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " INT_MUX_43 ,Interrupt mux for MPU interrupt number 43 "
|
|
hexmask.long.byte 0x20 16.--23. 1. " INT_MUX_42 ,Interrupt mux for MPU interrupt number 42 "
|
|
textline " "
|
|
hexmask.long.byte 0x20 8.--15. 1. " INT_MUX_41 ,Interrupt mux for MPU interrupt number 41 "
|
|
hexmask.long.byte 0x20 0.--7. 1. " INT_MUX_40 ,Interrupt mux for MPU interrupt number 40 "
|
|
line.long 0x24 "MPU_INTMUX_47 _44 ,MPU INTMUX 47 42 Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " INT_MUX_47 ,Interrupt mux for MPU interrupt number 47 "
|
|
hexmask.long.byte 0x24 16.--23. 1. " INT_MUX_46 ,Interrupt mux for MPU interrupt number 46 "
|
|
textline " "
|
|
hexmask.long.byte 0x24 8.--15. 1. " INT_MUX_45 ,Interrupt mux for MPU interrupt number 45 "
|
|
hexmask.long.byte 0x24 0.--7. 1. " INT_MUX_44 ,Interrupt mux for MPU interrupt number 44 "
|
|
line.long 0x28 "MPU_INTMUX_51 _48 ,MPU INTMUX 51 42 Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " INT_MUX_51 ,Interrupt mux for MPU interrupt number 51 "
|
|
hexmask.long.byte 0x28 16.--23. 1. " INT_MUX_50 ,Interrupt mux for MPU interrupt number 50 "
|
|
textline " "
|
|
hexmask.long.byte 0x28 8.--15. 1. " INT_MUX_49 ,Interrupt mux for MPU interrupt number 49 "
|
|
hexmask.long.byte 0x28 0.--7. 1. " INT_MUX_48 ,Interrupt mux for MPU interrupt number 48 "
|
|
line.long 0x2C "MPU_INTMUX_55 _52 ,MPU INTMUX 55 42 Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " INT_MUX_55 ,Interrupt mux for MPU interrupt number 55 "
|
|
hexmask.long.byte 0x2C 16.--23. 1. " INT_MUX_54 ,Interrupt mux for MPU interrupt number 54 "
|
|
textline " "
|
|
hexmask.long.byte 0x2C 8.--15. 1. " INT_MUX_53 ,Interrupt mux for MPU interrupt number 53 "
|
|
hexmask.long.byte 0x2C 0.--7. 1. " INT_MUX_52 ,Interrupt mux for MPU interrupt number 52 "
|
|
line.long 0x30 "MPU_INTMUX_59 _56 ,MPU INTMUX 59 42 Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " INT_MUX_59 ,Interrupt mux for MPU interrupt number 59 "
|
|
hexmask.long.byte 0x30 16.--23. 1. " INT_MUX_58 ,Interrupt mux for MPU interrupt number 58 "
|
|
textline " "
|
|
hexmask.long.byte 0x30 8.--15. 1. " INT_MUX_57 ,Interrupt mux for MPU interrupt number 57 "
|
|
hexmask.long.byte 0x30 0.--7. 1. " INT_MUX_56 ,Interrupt mux for MPU interrupt number 56 "
|
|
line.long 0x34 "MPU_INTMUX_63 _60 ,MPU INTMUX 63 42 Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " INT_MUX_63 ,Interrupt mux for MPU interrupt number 63 "
|
|
hexmask.long.byte 0x34 16.--23. 1. " INT_MUX_62 ,Interrupt mux for MPU interrupt number 62 "
|
|
textline " "
|
|
hexmask.long.byte 0x34 8.--15. 1. " INT_MUX_61 ,Interrupt mux for MPU interrupt number 61 "
|
|
hexmask.long.byte 0x34 0.--7. 1. " INT_MUX_60 ,Interrupt mux for MPU interrupt number 60 "
|
|
line.long 0x38 "MPU_INTMUX_67 _64 ,MPU INTMUX 67 42 Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " INT_MUX_67 ,Interrupt mux for MPU interrupt number 67 "
|
|
hexmask.long.byte 0x38 16.--23. 1. " INT_MUX_66 ,Interrupt mux for MPU interrupt number 66 "
|
|
textline " "
|
|
hexmask.long.byte 0x38 8.--15. 1. " INT_MUX_65 ,Interrupt mux for MPU interrupt number 65 "
|
|
hexmask.long.byte 0x38 0.--7. 1. " INT_MUX_64 ,Interrupt mux for MPU interrupt number 64 "
|
|
line.long 0x3C "MPU_INTMUX_71 _68 ,MPU INTMUX 71 42 Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " INT_MUX_71 ,Interrupt mux for MPU interrupt number 71 "
|
|
hexmask.long.byte 0x3C 16.--23. 1. " INT_MUX_70 ,Interrupt mux for MPU interrupt number 70 "
|
|
textline " "
|
|
hexmask.long.byte 0x3C 8.--15. 1. " INT_MUX_69 ,Interrupt mux for MPU interrupt number 69 "
|
|
hexmask.long.byte 0x3C 0.--7. 1. " INT_MUX_68 ,Interrupt mux for MPU interrupt number 68 "
|
|
line.long 0x40 "MPU_INTMUX_75 _72 ,MPU INTMUX 75 42 Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " INT_MUX_75 ,Interrupt mux for MPU interrupt number 75 "
|
|
hexmask.long.byte 0x40 16.--23. 1. " INT_MUX_74 ,Interrupt mux for MPU interrupt number 74 "
|
|
textline " "
|
|
hexmask.long.byte 0x40 8.--15. 1. " INT_MUX_73 ,Interrupt mux for MPU interrupt number 73 "
|
|
hexmask.long.byte 0x40 0.--7. 1. " INT_MUX_72 ,Interrupt mux for MPU interrupt number 72 "
|
|
line.long 0x44 "MPU_INTMUX_79 _76 ,MPU INTMUX 79 42 Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " INT_MUX_79 ,Interrupt mux for MPU interrupt number 79 "
|
|
hexmask.long.byte 0x44 16.--23. 1. " INT_MUX_78 ,Interrupt mux for MPU interrupt number 78 "
|
|
textline " "
|
|
hexmask.long.byte 0x44 8.--15. 1. " INT_MUX_77 ,Interrupt mux for MPU interrupt number 77 "
|
|
hexmask.long.byte 0x44 0.--7. 1. " INT_MUX_76 ,Interrupt mux for MPU interrupt number 76 "
|
|
line.long 0x48 "MPU_INTMUX_83 _80 ,MPU INTMUX 83 42 Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " INT_MUX_83 ,Interrupt mux for MPU interrupt number 83 "
|
|
hexmask.long.byte 0x48 16.--23. 1. " INT_MUX_82 ,Interrupt mux for MPU interrupt number 82 "
|
|
textline " "
|
|
hexmask.long.byte 0x48 8.--15. 1. " INT_MUX_81 ,Interrupt mux for MPU interrupt number 81 "
|
|
hexmask.long.byte 0x48 0.--7. 1. " INT_MUX_80 ,Interrupt mux for MPU interrupt number 80 "
|
|
line.long 0x4C "MPU_INTMUX_87 _84 ,MPU INTMUX 87 42 Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " INT_MUX_87 ,Interrupt mux for MPU interrupt number 87 "
|
|
hexmask.long.byte 0x4C 16.--23. 1. " INT_MUX_86 ,Interrupt mux for MPU interrupt number 86 "
|
|
textline " "
|
|
hexmask.long.byte 0x4C 8.--15. 1. " INT_MUX_85 ,Interrupt mux for MPU interrupt number 85 "
|
|
hexmask.long.byte 0x4C 0.--7. 1. " INT_MUX_84 ,Interrupt mux for MPU interrupt number 84 "
|
|
line.long 0x50 "MPU_INTMUX_91 _88 ,MPU INTMUX 91 42 Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " INT_MUX_91 ,Interrupt mux for MPU interrupt number 91 "
|
|
hexmask.long.byte 0x50 16.--23. 1. " INT_MUX_90 ,Interrupt mux for MPU interrupt number 90 "
|
|
textline " "
|
|
hexmask.long.byte 0x50 8.--15. 1. " INT_MUX_89 ,Interrupt mux for MPU interrupt number 89 "
|
|
hexmask.long.byte 0x50 0.--7. 1. " INT_MUX_88 ,Interrupt mux for MPU interrupt number 88 "
|
|
line.long 0x54 "MPU_INTMUX_95 _92 ,MPU INTMUX 95 42 Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " INT_MUX_95 ,Interrupt mux for MPU interrupt number 95 "
|
|
hexmask.long.byte 0x54 16.--23. 1. " INT_MUX_94 ,Interrupt mux for MPU interrupt number 94 "
|
|
textline " "
|
|
hexmask.long.byte 0x54 8.--15. 1. " INT_MUX_93 ,Interrupt mux for MPU interrupt number 93 "
|
|
hexmask.long.byte 0x54 0.--7. 1. " INT_MUX_92 ,Interrupt mux for MPU interrupt number 92 "
|
|
line.long 0x58 "MPU_INTMUX_99 _96 ,MPU INTMUX 99 42 Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " INT_MUX_99 ,Interrupt mux for MPU interrupt number 99 "
|
|
hexmask.long.byte 0x58 16.--23. 1. " INT_MUX_98 ,Interrupt mux for MPU interrupt number 98 "
|
|
textline " "
|
|
hexmask.long.byte 0x58 8.--15. 1. " INT_MUX_97 ,Interrupt mux for MPU interrupt number 97 "
|
|
hexmask.long.byte 0x58 0.--7. 1. " INT_MUX_96 ,Interrupt mux for MPU interrupt number 96 "
|
|
line.long 0x5C "MPU_INTMUX_103_100,MPU INTMUX 103 42 Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " INT_MUX_103 ,Interrupt mux for MPU interrupt number 103"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " INT_MUX_102 ,Interrupt mux for MPU interrupt number 102"
|
|
textline " "
|
|
hexmask.long.byte 0x5C 8.--15. 1. " INT_MUX_101 ,Interrupt mux for MPU interrupt number 101"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " INT_MUX_100 ,Interrupt mux for MPU interrupt number 100"
|
|
line.long 0x60 "MPU_INTMUX_107_104,MPU INTMUX 107 42 Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " INT_MUX_107 ,Interrupt mux for MPU interrupt number 107"
|
|
hexmask.long.byte 0x60 16.--23. 1. " INT_MUX_106 ,Interrupt mux for MPU interrupt number 106"
|
|
textline " "
|
|
hexmask.long.byte 0x60 8.--15. 1. " INT_MUX_105 ,Interrupt mux for MPU interrupt number 105"
|
|
hexmask.long.byte 0x60 0.--7. 1. " INT_MUX_104 ,Interrupt mux for MPU interrupt number 104"
|
|
line.long 0x64 "MPU_INTMUX_111_108,MPU INTMUX 111 42 Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " INT_MUX_111 ,Interrupt mux for MPU interrupt number 111"
|
|
hexmask.long.byte 0x64 16.--23. 1. " INT_MUX_110 ,Interrupt mux for MPU interrupt number 110"
|
|
textline " "
|
|
hexmask.long.byte 0x64 8.--15. 1. " INT_MUX_109 ,Interrupt mux for MPU interrupt number 109"
|
|
hexmask.long.byte 0x64 0.--7. 1. " INT_MUX_108 ,Interrupt mux for MPU interrupt number 108"
|
|
line.long 0x68 "MPU_INTMUX_115_112,MPU INTMUX 115 42 Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " INT_MUX_115 ,Interrupt mux for MPU interrupt number 115"
|
|
hexmask.long.byte 0x68 16.--23. 1. " INT_MUX_114 ,Interrupt mux for MPU interrupt number 114"
|
|
textline " "
|
|
hexmask.long.byte 0x68 8.--15. 1. " INT_MUX_113 ,Interrupt mux for MPU interrupt number 113"
|
|
hexmask.long.byte 0x68 0.--7. 1. " INT_MUX_112 ,Interrupt mux for MPU interrupt number 112"
|
|
line.long 0x6C "MPU_INTMUX_119_116,MPU INTMUX 119 42 Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " INT_MUX_119 ,Interrupt mux for MPU interrupt number 119"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " INT_MUX_118 ,Interrupt mux for MPU interrupt number 118"
|
|
textline " "
|
|
hexmask.long.byte 0x6C 8.--15. 1. " INT_MUX_117 ,Interrupt mux for MPU interrupt number 117"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " INT_MUX_116 ,Interrupt mux for MPU interrupt number 116"
|
|
line.long 0x70 "MPU_INTMUX_123_120,MPU INTMUX 123 42 Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " INT_MUX_123 ,Interrupt mux for MPU interrupt number 123"
|
|
hexmask.long.byte 0x70 16.--23. 1. " INT_MUX_122 ,Interrupt mux for MPU interrupt number 122"
|
|
textline " "
|
|
hexmask.long.byte 0x70 8.--15. 1. " INT_MUX_121 ,Interrupt mux for MPU interrupt number 121"
|
|
hexmask.long.byte 0x70 0.--7. 1. " INT_MUX_120 ,Interrupt mux for MPU interrupt number 120"
|
|
line.long 0x74 "MPU_INTMUX_127_124,MPU INTMUX 127 42 Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " INT_MUX_127 ,Interrupt mux for MPU interrupt number 127"
|
|
hexmask.long.byte 0x74 16.--23. 1. " INT_MUX_126 ,Interrupt mux for MPU interrupt number 126"
|
|
textline " "
|
|
hexmask.long.byte 0x74 8.--15. 1. " INT_MUX_125 ,Interrupt mux for MPU interrupt number 125"
|
|
hexmask.long.byte 0x74 0.--7. 1. " INT_MUX_124 ,Interrupt mux for MPU interrupt number 124"
|
|
tree.end
|
|
tree "Initiator Prority Registers"
|
|
width 17.
|
|
group.long 0x16C0++0x13
|
|
line.long 0x00 "INITIATOR_PRIO_0,Initiator Priority 0 Register"
|
|
bitfld.long 0x00 24.--26. " DSP_MDMA ,DSP MDMA port initiator priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " DSP_CFG ,DSP_CFG port initiator priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SYS_MMU ,System MMU initiator priority" "0,1,2,3,4,5,6,7"
|
|
sif (!cpuis("DRA623"))
|
|
bitfld.long 0x00 12.--14. " SGX530 ,SGX530 initiator priority" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BITBLT_MMU ,BitBlt MMU initiator priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " HOST_ARM1 ,Host Cortex A8 initiator priority (128b port)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " HOST_ARM0 ,Host Cortex A8 initiator priority (54b port)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "INITIATOR_PRIO_1,Initiator Priority 1 Register"
|
|
bitfld.long 0x04 28.--30. " TCWR3 ,EDMA3TC 3 Write Port initiator priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 24.--26. " TCRD3 ,EDMA3TC 3 Read Port initiator priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 20.--22. " TCWR2 ,EDMA3TC 2 Write Port initiator priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " TCRD2 ,EDMA3TC 2 Read Port initiator priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " TCWR1 ,EDMA3TC 1 Write Port initiator priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. " TCRD1 ,EDMA3TC 1 Read Port initiator priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " TCWR0 ,EDMA3TC 0 Write Port initiator priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " TCRD0 ,EDMA3TC 0 Read Port initiator priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "INITIATOR_PRIO_2,Initiator Priority 2 Register"
|
|
bitfld.long 0x08 24.--26. " DEBUG ,DEBUG Port initiator priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 20.--22. " GMAC_SW ,EDMA3TC 2 Write Port initiator priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " SECSS ,SECSS Port initiator priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 12.--14. " PCIE ,PCIe Port initiator priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " ISS ,ISS Port initiator priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0c "INITIATOR_PRIO_3,Initiator Priority 3 Register"
|
|
bitfld.long 0x0c 4.--6. " PRUSS1 ,PRUSS1 initiator priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 0.--2. " PRUSS0 ,PRUSS0 initiator priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "INITIATOR_PRIO_4,Initiator Priority 4 Register"
|
|
bitfld.long 0x10 12.--14. " P1500 ,P1500 initiator priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 8.--10. " MLB ,MLB initiator priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 4.--6. " USB1 ,USB1 initiator priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. " USB0 ,USB0 initiator priority" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
group.long 0x16F0++0x07
|
|
line.long 0x00 "DMAOBS,DMA Debug Observability Control Register"
|
|
bitfld.long 0x00 31. " DMAOBS2_EN ,DMA Observation 2 Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DMAOBS2_SEL ,DMA Observation 2- selects event source to drive onto the dmaobs2 output"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DMAOBS1_EN ,DMA Observation 1 Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DMAOBS1_SEL ,DMA Observation 1- selects event source to drive onto the dmaobs1 output"
|
|
line.long 0x04 "INTOBS,Interrupt Debug Observability Control Register"
|
|
bitfld.long 0x04 31. " INTOBS2_EN ,INT Observation 2 Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 16.--23. 1. " INTOBS2_SEL ,INT Observation 2- selects interrupt source to drive onto the intobs2 output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTOBS1_EN ,INT Observation 1 Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 0.--7. 1. " INTOBS1_SEL ,INT Observation 1- selects interrupt source to drive onto the intobs1 output"
|
|
tree "DTC Registers"
|
|
width 12.
|
|
group.long 0x1700++0x03
|
|
line.long 0x00 "DTC0_CTRL,DTC0 Control Register"
|
|
bitfld.long 0x00 31. " DTC_RESET ,Resets the DTC module" "No reset,Reset"
|
|
bitfld.long 0x00 16. " PCLK_INV ,PCLK Invert control:" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TCON_LOAD3_POL ,TFT Control LOAD3 Polarity [DEASSERTED/ASSERTED]" "Low/High,High/Low"
|
|
bitfld.long 0x00 14. " TCON_LOAD2_POL ,TFT Control LOAD2 Polarity [DEASSERTED/ASSERTED]" "Low/High,High/Low"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TCON_LOAD1_POL ,TFT Control LOAD1 Polarity [DEASSERTED/ASSERTED]" "Low/High,High/Low"
|
|
bitfld.long 0x00 12. " TCON_LOAD0_POL ,TFT Control LOAD0 Polarity [DEASSERTED/ASSERTED]" "Low/High,High/Low"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TCON_VCOM_ALT ,TFT Control VCOMP Alternate" "No,Yes"
|
|
bitfld.long 0x00 9. " TCON_VCOM_POL ,TFT Control VCOM Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TCON_VCOM_EN ,TFT Control VCOM Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " DITHER_MODE ,Dither Mode configuration" "RGB24-RGB16,RGB24-RGB18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " DITHER_ACTVID_POL ,Dither ACTVID polarity setting" "Active High,Active Low"
|
|
bitfld.long 0x00 0. " DITHER_ENABLE ,Dither Enable" "Disabled,Enabled"
|
|
sif (cpu()=="DRA623"||cpu()=="DRA626"||cpu()=="DRA628"||cpu()=="DRA623DSP"||cpu()=="DRA626DSP"||cpu()=="DRA628DSP")
|
|
group.long 0x1704++0x03
|
|
line.long 0x00 "DTC1_CTRL,DTC1 Control Register"
|
|
bitfld.long 0x00 31. " DTC_RESET ,Resets the DTC module" "No reset,Reset"
|
|
bitfld.long 0x00 16. " PCLK_INV ,PCLK Invert control:" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TCON_LOAD3_POL ,TFT Control LOAD3 Polarity [DEASSERTED/ASSERTED]" "Low/High,High/Low"
|
|
bitfld.long 0x00 14. " TCON_LOAD2_POL ,TFT Control LOAD2 Polarity [DEASSERTED/ASSERTED]" "Low/High,High/Low"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TCON_LOAD1_POL ,TFT Control LOAD1 Polarity [DEASSERTED/ASSERTED]" "Low/High,High/Low"
|
|
bitfld.long 0x00 12. " TCON_LOAD0_POL ,TFT Control LOAD0 Polarity [DEASSERTED/ASSERTED]" "Low/High,High/Low"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TCON_VCOM_ALT ,TFT Control VCOMP Alternate" "No,Yes"
|
|
bitfld.long 0x00 9. " TCON_VCOM_POL ,TFT Control VCOM Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TCON_VCOM_EN ,TFT Control VCOM Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " DITHER_MODE ,Dither Mode configuration" "RGB24-RGB16,RGB24-RGB18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " DITHER_ACTVID_POL ,Dither ACTVID polarity setting" "Active High,Active Low"
|
|
bitfld.long 0x00 0. " DITHER_ENABLE ,Dither Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x1708++0x1f
|
|
line.long 0x0 "DTC0_LOAD0,DTC0 Load0 Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " TCON_LOAD_WIDTH ,Width of TCON LOAD ASSERTION in pixel clocks"
|
|
hexmask.long.word 0x0 0.--10. 1. " TCON_LOAD_ON ,Number of pixel clocks before LOAD asserts after HS rising edge"
|
|
line.long 0x4 "DTC0_LOAD1,DTC0 Load1 Register"
|
|
hexmask.long.word 0x4 16.--26. 1. " TCON_LOAD_WIDTH ,Width of TCON LOAD ASSERTION in pixel clocks"
|
|
hexmask.long.word 0x4 0.--10. 1. " TCON_LOAD_ON ,Number of pixel clocks before LOAD asserts after HS rising edge"
|
|
line.long 0x8 "DTC0_LOAD2,DTC0 Load2 Register"
|
|
hexmask.long.word 0x8 16.--26. 1. " TCON_LOAD_WIDTH ,Width of TCON LOAD ASSERTION in pixel clocks"
|
|
hexmask.long.word 0x8 0.--10. 1. " TCON_LOAD_ON ,Number of pixel clocks before LOAD asserts after HS rising edge"
|
|
line.long 0x0c "DTC0_LOAD3,DTC0 Load3 Register"
|
|
bitfld.long 0x0c 31. " LOAD3_VSMOD ,Load Vertical Sync Modify" "Not modified,Modified"
|
|
bitfld.long 0x0c 27.--30. " LOAD3_VSCNT ,Load VS Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x0c 16.--26. 1. " TCON_LOAD_WIDTH ,Width of TCON LOAD ASSERTION in pixel clocks"
|
|
hexmask.long.word 0x0c 0.--10. 1. " TCON_LOAD_ON ,Number of pixel clocks before LOAD asserts after HS rising edge"
|
|
line.long 0x10 "DTC1_LOAD0,DTC0 Load0 Register"
|
|
hexmask.long.word 0x10 16.--26. 1. " TCON_LOAD_WIDTH ,Width of TCON LOAD ASSERTION in pixel clocks"
|
|
hexmask.long.word 0x10 0.--10. 1. " TCON_LOAD_ON ,Number of pixel clocks before LOAD asserts after HS rising edge"
|
|
line.long 0x14 "DTC1_LOAD1,DTC0 Load1 Register"
|
|
hexmask.long.word 0x14 16.--26. 1. " TCON_LOAD_WIDTH ,Width of TCON LOAD ASSERTION in pixel clocks"
|
|
hexmask.long.word 0x14 0.--10. 1. " TCON_LOAD_ON ,Number of pixel clocks before LOAD asserts after HS rising edge"
|
|
line.long 0x18 "DTC1_LOAD2,DTC0 Load2 Register"
|
|
hexmask.long.word 0x18 16.--26. 1. " TCON_LOAD_WIDTH ,Width of TCON LOAD ASSERTION in pixel clocks"
|
|
hexmask.long.word 0x18 0.--10. 1. " TCON_LOAD_ON ,Number of pixel clocks before LOAD asserts after HS rising edge"
|
|
line.long 0x1c "DTC1_LOAD3,DTC1 Load3 Register"
|
|
bitfld.long 0x1c 31. " LOAD3_VSMOD ,Load Vertical Sync Modify" "Not modified,Modified"
|
|
bitfld.long 0x1c 27.--30. " LOAD3_VSCNT ,Load VS Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x1c 16.--26. 1. " TCON_LOAD_WIDTH ,Width of TCON LOAD ASSERTION in pixel clocks"
|
|
hexmask.long.word 0x1c 0.--10. 1. " TCON_LOAD_ON ,Number of pixel clocks before LOAD asserts after HS rising edge"
|
|
tree.end
|
|
tree "PRUSS Interrupt Mux"
|
|
width 20.
|
|
group.long 0x1750++0x1f
|
|
line.long 0x0 "PRUSS_INTMUX_35_32,PRUSS INT MUX 35-32 Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " INT_MUX_35 ,PRUSS Interrupt Mux Register for interupt no. 35"
|
|
hexmask.long.byte 0x0 16.--23. 1. " INT_MUX_34 ,PRUSS Interrupt Mux Register for interupt no. 34"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " INT_MUX_33 ,PRUSS Interrupt Mux Register for interupt no. 33"
|
|
hexmask.long.byte 0x0 0.--7. 1. " INT_MUX_32 ,PRUSS Interrupt Mux Register for interupt no. 32"
|
|
line.long 0x4 "PRUSS_INTMUX_39_36,PRUSS INT MUX 39-36 Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " INT_MUX_39 ,PRUSS Interrupt Mux Register for interupt no. 39"
|
|
hexmask.long.byte 0x4 16.--23. 1. " INT_MUX_38 ,PRUSS Interrupt Mux Register for interupt no. 38"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--15. 1. " INT_MUX_37 ,PRUSS Interrupt Mux Register for interupt no. 37"
|
|
hexmask.long.byte 0x4 0.--7. 1. " INT_MUX_36 ,PRUSS Interrupt Mux Register for interupt no. 36"
|
|
line.long 0x8 "PRUSS_INTMUX_43_40,PRUSS INT MUX 43-40 Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " INT_MUX_43 ,PRUSS Interrupt Mux Register for interupt no. 43"
|
|
hexmask.long.byte 0x8 16.--23. 1. " INT_MUX_42 ,PRUSS Interrupt Mux Register for interupt no. 42"
|
|
textline " "
|
|
hexmask.long.byte 0x8 8.--15. 1. " INT_MUX_41 ,PRUSS Interrupt Mux Register for interupt no. 41"
|
|
hexmask.long.byte 0x8 0.--7. 1. " INT_MUX_40 ,PRUSS Interrupt Mux Register for interupt no. 40"
|
|
line.long 0xC "PRUSS_INTMUX_47_44,PRUSS INT MUX 47-44 Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " INT_MUX_47 ,PRUSS Interrupt Mux Register for interupt no. 47"
|
|
hexmask.long.byte 0xC 16.--23. 1. " INT_MUX_46 ,PRUSS Interrupt Mux Register for interupt no. 46"
|
|
textline " "
|
|
hexmask.long.byte 0xC 8.--15. 1. " INT_MUX_45 ,PRUSS Interrupt Mux Register for interupt no. 45"
|
|
hexmask.long.byte 0xC 0.--7. 1. " INT_MUX_44 ,PRUSS Interrupt Mux Register for interupt no. 44"
|
|
line.long 0x10 "PRUSS_INTMUX_51_48,PRUSS INT MUX 51-48 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " INT_MUX_51 ,PRUSS Interrupt Mux Register for interupt no. 51"
|
|
hexmask.long.byte 0x10 16.--23. 1. " INT_MUX_50 ,PRUSS Interrupt Mux Register for interupt no. 50"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " INT_MUX_49 ,PRUSS Interrupt Mux Register for interupt no. 49"
|
|
hexmask.long.byte 0x10 0.--7. 1. " INT_MUX_48 ,PRUSS Interrupt Mux Register for interupt no. 48"
|
|
line.long 0x14 "PRUSS_INTMUX_55_52,PRUSS INT MUX 55-52 Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " INT_MUX_55 ,PRUSS Interrupt Mux Register for interupt no. 55"
|
|
hexmask.long.byte 0x14 16.--23. 1. " INT_MUX_54 ,PRUSS Interrupt Mux Register for interupt no. 54"
|
|
textline " "
|
|
hexmask.long.byte 0x14 8.--15. 1. " INT_MUX_53 ,PRUSS Interrupt Mux Register for interupt no. 53"
|
|
hexmask.long.byte 0x14 0.--7. 1. " INT_MUX_52 ,PRUSS Interrupt Mux Register for interupt no. 52"
|
|
line.long 0x18 "PRUSS_INTMUX_59_56,PRUSS INT MUX 59-56 Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " INT_MUX_59 ,PRUSS Interrupt Mux Register for interupt no. 59"
|
|
hexmask.long.byte 0x18 16.--23. 1. " INT_MUX_58 ,PRUSS Interrupt Mux Register for interupt no. 58"
|
|
textline " "
|
|
hexmask.long.byte 0x18 8.--15. 1. " INT_MUX_57 ,PRUSS Interrupt Mux Register for interupt no. 57"
|
|
hexmask.long.byte 0x18 0.--7. 1. " INT_MUX_56 ,PRUSS Interrupt Mux Register for interupt no. 56"
|
|
line.long 0x1C "PRUSS_INTMUX_63_60,PRUSS INT MUX 63-60 Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " INT_MUX_63 ,PRUSS Interrupt Mux Register for interupt no. 63"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " INT_MUX_62 ,PRUSS Interrupt Mux Register for interupt no. 62"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 8.--15. 1. " INT_MUX_61 ,PRUSS Interrupt Mux Register for interupt no. 61"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " INT_MUX_60 ,PRUSS Interrupt Mux Register for interupt no. 60"
|
|
tree.end
|
|
group.long 0x1870++0x03
|
|
line.long 0x00 "CHIP_HW_DBG_SEL,Hardware debug observability control"
|
|
bitfld.long 0x00 0.--2. " CHIP_DBG_SEL ,Chip Debug Select" "0,1,2,3,4,5,6,7"
|
|
width 0xb
|
|
else
|
|
width 21.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "CONTROL_REVISION,Control Module Revision Register"
|
|
bitfld.long 0x00 30.--31. " IP_REV_SCHEME ,Register scheme" "Legacy,New,?..."
|
|
hexmask.long.word 0x00 16.--27. 1. " IP_REV_FUNC ,Software compatible module family function"
|
|
bitfld.long 0x00 11.--15. " IP_REV_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " IP_REV_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " IP_REV_CUSTOM ,Special version for a particular device" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " IP_REV_MINOR ,Minor Revision (Y)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CONTROL_HWINFO,Module Hardware Configuration Register"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "CONTROL_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Configure module slave interface state management" "Force Idle,No Idle,Smart Idle,Smart Idle wakeup capable"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x00 1. " FREEEMU ,Sensitivity to Emulation suspend input" "Sensitive,Not sensitive"
|
|
else
|
|
bitfld.long 0x00 1. " FREEEMU ,Sensitivity to Emulation suspend input" "Reserved,Not sensitive"
|
|
endif
|
|
group.long 0x40++0xb
|
|
line.long 0x00 "CONTROL_STATUS,Control Status Register"
|
|
bitfld.long 0x00 26. " BOOT[11] ,Reset output (RSTOUT) configuration" "OR of 3 WD Timer,3 WD timer reset + PRCM"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x00 25. " BOOT[10] ,Read customer programmable IDs from efuse for PCIe/USB and NAND ROM" "Not read,Read"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ADMUX ,GPMC CS0 Default Address Muxing" "No Addr/Data,Addr/Data,Addr/Addr/Data,?..."
|
|
bitfld.long 0x00 17. " WAITEN ,GPMC CS0 Default Wait Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BW ,GPMC CS0 Default Bus Width" "8-bit,16-bit"
|
|
textline " "
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x00 8.--10. " DEVTYPE ,Device Type" "Test,EMUL,HSL,General purpose,Bad,HS,EMU,Bad"
|
|
else
|
|
bitfld.long 0x00 8.--10. " DEVTYPE ,Device Type" "Reserved,Reserved,Reserved,General purpose,Reserved,Reserved,Reserved,Bad"
|
|
endif
|
|
bitfld.long 0x00 0.--4. " SYSBOOT ,System Boot Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "BOOTSTAT,Boot Status Register"
|
|
bitfld.long 0x04 16.--19. " BOOTERR ,Boot Error" "No error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error"
|
|
bitfld.long 0x04 0. " BC ,Boot Complete" "Not completed,Completed"
|
|
line.long 0x08 "DSPBOOTADDR,DSP Boot Address Register"
|
|
hexmask.long.tbyte 0x08 10.--31. 0x4 " BOOTADDR ,DSP Boot Address (upper 22 bits)"
|
|
bitfld.long 0x08 0. " RSTDONE ,DSP Reset Done" "Not done,Done"
|
|
width 21.
|
|
group.long 0x60++0x13
|
|
line.long 0x00 "MMR_LOCK0,Lock/Unlock Register for Region 0x0400 - 0x05FF"
|
|
line.long 0x04 "MMR_LOCK1,Lock/Unlock Register for Region 0x0600 - 0x07FF"
|
|
line.long 0x08 "MMR_LOCK2,Lock/Unlock Register for Region 0x0800 - 0x0fFF"
|
|
line.long 0x0c "MMR_LOCK3,Lock/Unlock Register for Region 0x1000 - 0x12FF"
|
|
line.long 0x10 "MMR_LOCK4,Lock/Unlock Register for Region 0x1300 - 0x17FF"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CONTROL_SEC_CTRL,Security Control Register"
|
|
bitfld.long 0x00 3. " WD0OPDISABLE ,MPU Watchdog (WDT 0) Operation Enable" "Enabled,Disabled"
|
|
endif
|
|
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
|
|
group.long 0x408++0x3
|
|
line.long 0x00 "SGX_VBBLDO_CTRL,SGX530 VBB LDO Control Register"
|
|
bitfld.long 0x00 21.--25. " VSETFBB ,FBB trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " VSETRBB ,RBB trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " LDOBYPASSZ ,Low is bypass mode" "Low,High"
|
|
bitfld.long 0x00 4. " LOWPWR ,Low power mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HZ ,Vbbnw HZ mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BBSEL ,FBB enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NOCAP ,External cap disable" "No,Yes"
|
|
bitfld.long 0x00 0. " NOVBGBYR ,IREF1U is not a VBG/R current" "Low,High"
|
|
group.long 0x414++0xb
|
|
line.long 0x00 "HDVICP_VBBLDO_CTRL,HDVICP VBB LDO Control Register"
|
|
bitfld.long 0x00 21.--25. " VSETFBB ,FBB trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " VSETRBB ,RBB trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " LDOBYPASSZ ,Low is bypass mode" "Low,High"
|
|
bitfld.long 0x00 4. " LOWPWR ,Low power mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HZ ,Vbbnw HZ mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BBSEL ,FBB enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NOCAP ,External cap disable" "No,Yes"
|
|
bitfld.long 0x00 0. " NOVBGBYR ,IREF1U is not a VBG/R current" "Low,High"
|
|
line.long 0x04 "DSP_VBBLDO_CTRL,DSP VBB LDO Control Register"
|
|
bitfld.long 0x04 21.--25. " VSETFBB ,FBB trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--20. " VSETRBB ,RBB trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 5. " LDOBYPASSZ ,Low is bypass mode" "Low,High"
|
|
bitfld.long 0x04 4. " LOWPWR ,Low power mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HZ ,Vbbnw HZ mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " BBSEL ,FBB enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " NOCAP ,External cap disable" "No,Yes"
|
|
bitfld.long 0x04 0. " NOVBGBYR ,IREF1U is not a VBG/R current" "Low,High"
|
|
line.long 0x08 "CORTEX_VBBLDO_CTRL,Cortex VBB LDO Control Register"
|
|
bitfld.long 0x08 21.--25. " VSETFBB ,FBB trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " VSETRBB ,RBB trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 5. " LDOBYPASSZ ,Low is bypass mode" "Low,High"
|
|
bitfld.long 0x08 4. " LOWPWR ,Low power mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HZ ,Vbbnw HZ mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " BBSEL ,FBB enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " NOCAP ,External cap disable" "No,Yes"
|
|
bitfld.long 0x08 0. " NOVBGBYR ,IREF1U is not a VBG/R current" "Low,High"
|
|
group.long 0x428++0x1b
|
|
line.long 0x0 "RAMLDO_CTRL0,RAM LDO Control Register 0"
|
|
hexmask.long.word 0x0 16.--25. 1. " VSET ,VDDAR trim"
|
|
bitfld.long 0x0 7. " AIPOFF ,LDO disable (IDDQ mode enable)" "No,Yes"
|
|
bitfld.long 0x0 6. " SRAMALLRET ,VDDAR in retention mode" "Low,High"
|
|
bitfld.long 0x0 5. " ABBOFF ,Short VDDAR to VNWA" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " ENFUNC5 ,Short ckt protection disable" "No,Yes"
|
|
bitfld.long 0x0 3. " ENFUNC4 ,Sub regulation disable" "No,Yes"
|
|
bitfld.long 0x0 2. " ENFUNC3 ,High perf capless mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " ENFUNC2 ,Capless mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " ENFUNC1 ,2.2uF support enable" "Disabled,Enabled"
|
|
line.long 0x4 "RAMLDO_CTRL1,RAM LDO Control Register 1"
|
|
hexmask.long.word 0x4 16.--25. 1. " VSET ,VDDAR trim"
|
|
bitfld.long 0x4 7. " AIPOFF ,LDO disable (IDDQ mode enable)" "No,Yes"
|
|
bitfld.long 0x4 6. " SRAMALLRET ,VDDAR in retention mode" "Low,High"
|
|
bitfld.long 0x4 5. " ABBOFF ,Short VDDAR to VNWA" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 4. " ENFUNC5 ,Short ckt protection disable" "No,Yes"
|
|
bitfld.long 0x4 3. " ENFUNC4 ,Sub regulation disable" "No,Yes"
|
|
bitfld.long 0x4 2. " ENFUNC3 ,High perf capless mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 1. " ENFUNC2 ,Capless mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0. " ENFUNC1 ,2.2uF support enable" "Disabled,Enabled"
|
|
line.long 0x8 "RAMLDO_CTRL2,RAM LDO Control Register 2"
|
|
hexmask.long.word 0x8 16.--25. 1. " VSET ,VDDAR trim"
|
|
bitfld.long 0x8 7. " AIPOFF ,LDO disable (IDDQ mode enable)" "No,Yes"
|
|
bitfld.long 0x8 6. " SRAMALLRET ,VDDAR in retention mode" "Low,High"
|
|
bitfld.long 0x8 5. " ABBOFF ,Short VDDAR to VNWA" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 4. " ENFUNC5 ,Short ckt protection disable" "No,Yes"
|
|
bitfld.long 0x8 3. " ENFUNC4 ,Sub regulation disable" "No,Yes"
|
|
bitfld.long 0x8 2. " ENFUNC3 ,High perf capless mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 1. " ENFUNC2 ,Capless mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0. " ENFUNC1 ,2.2uF support enable" "Disabled,Enabled"
|
|
line.long 0xC "RAMLDO_CTRL3,RAM LDO Control Register 3"
|
|
hexmask.long.word 0xC 16.--25. 1. " VSET ,VDDAR trim"
|
|
bitfld.long 0xC 7. " AIPOFF ,LDO disable (IDDQ mode enable)" "No,Yes"
|
|
bitfld.long 0xC 6. " SRAMALLRET ,VDDAR in retention mode" "Low,High"
|
|
bitfld.long 0xC 5. " ABBOFF ,Short VDDAR to VNWA" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 4. " ENFUNC5 ,Short ckt protection disable" "No,Yes"
|
|
bitfld.long 0xC 3. " ENFUNC4 ,Sub regulation disable" "No,Yes"
|
|
bitfld.long 0xC 2. " ENFUNC3 ,High perf capless mode enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 1. " ENFUNC2 ,Capless mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0. " ENFUNC1 ,2.2uF support enable" "Disabled,Enabled"
|
|
line.long 0x10 "RAMLDO_CTRL4,RAM LDO Control Register 4"
|
|
hexmask.long.word 0x10 16.--25. 1. " VSET ,VDDAR trim"
|
|
bitfld.long 0x10 7. " AIPOFF ,LDO disable (IDDQ mode enable)" "No,Yes"
|
|
bitfld.long 0x10 6. " SRAMALLRET ,VDDAR in retention mode" "Low,High"
|
|
bitfld.long 0x10 5. " ABBOFF ,Short VDDAR to VNWA" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 4. " ENFUNC5 ,Short ckt protection disable" "No,Yes"
|
|
bitfld.long 0x10 3. " ENFUNC4 ,Sub regulation disable" "No,Yes"
|
|
bitfld.long 0x10 2. " ENFUNC3 ,High perf capless mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " ENFUNC2 ,Capless mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " ENFUNC1 ,2.2uF support enable" "Disabled,Enabled"
|
|
line.long 0x14 "RAMLDO_CTRL5,RAM LDO Control Register 5"
|
|
hexmask.long.word 0x14 16.--25. 1. " VSET ,VDDAR trim"
|
|
bitfld.long 0x14 7. " AIPOFF ,LDO disable (IDDQ mode enable)" "No,Yes"
|
|
bitfld.long 0x14 6. " SRAMALLRET ,VDDAR in retention mode" "Low,High"
|
|
bitfld.long 0x14 5. " ABBOFF ,Short VDDAR to VNWA" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 4. " ENFUNC5 ,Short ckt protection disable" "No,Yes"
|
|
bitfld.long 0x14 3. " ENFUNC4 ,Sub regulation disable" "No,Yes"
|
|
bitfld.long 0x14 2. " ENFUNC3 ,High perf capless mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " ENFUNC2 ,Capless mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ENFUNC1 ,2.2uF support enable" "Disabled,Enabled"
|
|
line.long 0x18 "REFCLK_LJCBLDO_CTRL,RLDO Control Register for LJCB buffer of REFCLK"
|
|
hexmask.long.word 0x18 16.--25. 1. " VSET ,VDDAR trim"
|
|
bitfld.long 0x18 7. " AIPOFF ,LDO disable (IDDQ mode enable)" "No,Yes"
|
|
bitfld.long 0x18 6. " SRAMALLRET ,VDDAR in retention mode" "Low,High"
|
|
bitfld.long 0x18 5. " ABBOFF ,Short VDDAR to VNWA" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 4. " ENFUNC5 ,Short ckt protection disable" "No,Yes"
|
|
bitfld.long 0x18 3. " ENFUNC4 ,Sub regulation disable" "No,Yes"
|
|
bitfld.long 0x18 2. " ENFUNC3 ,High perf capless mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " ENFUNC2 ,Capless mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " ENFUNC1 ,2.2uF support enable" "Disabled,Enabled"
|
|
group.long 0x448++0xf
|
|
line.long 0x0 "BANDGAP0_CTRL,Bandgap 0 Control Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " DTEMP ,Temperature data from ADC"
|
|
bitfld.long 0x0 7. " CBIASSEL ,Register divider reference enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " BGROFF ,Bandgap disable" "No,Yes"
|
|
bitfld.long 0x0 5. " TMPSOFF ,Temperature sensor disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 4. " SOC ,New ADC conversion cycle start" "Not started,Started"
|
|
bitfld.long 0x0 3. " CLRZ ,Digital outputs reset" "Reset,No reset"
|
|
bitfld.long 0x0 2. " CONTCONV ,Conversion mode" "Single,Continuous"
|
|
bitfld.long 0x0 1. " ECOZ ,DTEMP is valid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TSHUT ,Thermal shutdown event (>147C)" "Low,High"
|
|
line.long (0x0+0x4) "BANDGAP0_TRIM,Bandgap 0 Trim Register"
|
|
hexmask.long.byte (0x0+0x4) 24.--31. 1. " DTRBGAPC ,Output voltage of bandgap trim"
|
|
hexmask.long.byte (0x0+0x4) 16.--23. 1. " DTRBGAPV ,Output voltage of bandgap trim"
|
|
hexmask.long.byte (0x0+0x4) 8.--15. 1. " DTRTEMPS ,Temperature sensor trim"
|
|
hexmask.long.byte (0x0+0x4) 0.--7. 1. " DTRTEMPSC ,Temperature sensor trim"
|
|
line.long 0x8 "BANDGAP1_CTRL,Bandgap 1 Control Register"
|
|
hexmask.long.byte 0x8 8.--15. 1. " DTEMP ,Temperature data from ADC"
|
|
bitfld.long 0x8 7. " CBIASSEL ,Register divider reference enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 6. " BGROFF ,Bandgap disable" "No,Yes"
|
|
bitfld.long 0x8 5. " TMPSOFF ,Temperature sensor disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x8 4. " SOC ,New ADC conversion cycle start" "Not started,Started"
|
|
bitfld.long 0x8 3. " CLRZ ,Digital outputs reset" "Reset,No reset"
|
|
bitfld.long 0x8 2. " CONTCONV ,Conversion mode" "Single,Continuous"
|
|
bitfld.long 0x8 1. " ECOZ ,DTEMP is valid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x8 0. " TSHUT ,Thermal shutdown event (>147C)" "Low,High"
|
|
line.long (0x8+0x4) "BANDGAP1_TRIM,Bandgap 1 Trim Register"
|
|
hexmask.long.byte (0x8+0x4) 24.--31. 1. " DTRBGAPC ,Output voltage of bandgap trim"
|
|
hexmask.long.byte (0x8+0x4) 16.--23. 1. " DTRBGAPV ,Output voltage of bandgap trim"
|
|
hexmask.long.byte (0x8+0x4) 8.--15. 1. " DTRTEMPS ,Temperature sensor trim"
|
|
hexmask.long.byte (0x8+0x4) 0.--7. 1. " DTRTEMPSC ,Temperature sensor trim"
|
|
endif
|
|
group.long 0x468++0x7
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
line.long 0x00 "DEVOSC,Oscillator 0 Control Register"
|
|
else
|
|
line.long 0x00 "OSC0_CTRL,Oscillator 0 Control Register"
|
|
endif
|
|
bitfld.long 0x00 0. " RESELECT ,Internal feedback resistor select" "Used,Not used"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
line.long 0x04 "AUXOSC,Oscilator 1 Control Register"
|
|
else
|
|
line.long 0x04 "OSC1_CTRL,Oscilator 1 Control Register"
|
|
endif
|
|
bitfld.long 0x04 3. " GZ ,Oscillator disable" "No,Yes"
|
|
bitfld.long 0x04 2. " SW2 ,Select 15-35 MHz range" "Low,High"
|
|
bitfld.long 0x04 1. " SW1 ,Select 15-35 MHz range" "Low,High"
|
|
bitfld.long 0x04 0. " RESELECT ,Internal feedback resistor select" "Used,Not used"
|
|
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
|
|
group.long 0x500++0xf
|
|
line.long 0x00 "PE_SCRATCHPAD_0,PE Scratch Register 0"
|
|
line.long 0x04 "PE_SCRATCHPAD_1,PE Scratch Register 1"
|
|
line.long 0x08 "PE_SCRATCHPAD_2,PE Scratch Register 2"
|
|
line.long 0x0c "PE_SCRATCHPAD_3,PE Scratch Register 3"
|
|
endif
|
|
rgroup.long 0x600++0x7
|
|
line.long 0x00 "DEVICE_ID,Device Identification Register"
|
|
bitfld.long 0x00 28.--31. " DEVREV ,Device revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 12.--27. 1. " PARTNUM ,Device part number"
|
|
hexmask.long.word 0x00 1.--11. 1. " MFGR ,Manufacturer's JTAG ID"
|
|
line.long 0x04 "DEVICE_FEATURE,Device Feature Set Register"
|
|
bitfld.long 0x04 31. " DSP ,C674x DSP Enable" "Disabled,Enabled"
|
|
sif (cpu()=="DM8147DSP")
|
|
bitfld.long 0x04 28. " DDR1 ,2nd DDR Interface (DDR1) Enable" "Disabled,Enabled"
|
|
elif (cpu()=="DM8148DSP")
|
|
bitfld.long 0x04 29. " SGX530 ,SGX530 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " DDR1 ,2nd DDR Interface (DDR1) Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 30. " TPP ,Transport Packet Processor (TPPSS) Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " 3DGRPH ,SGX530 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " DDR1 ,2nd DDR Interface (DDR1) Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 27. " HD-VICP0 ,HD-VICP0 Co-Processing Engine Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " FDIF ,Face Detect Enable" "Disabled,Enabled"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x04 25. " ISP5 ,ISP5 Pin Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 25. " MEDIACTL5 ,MEDIACTL5 Pin Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CSI2 ,CSI2 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 23. " PCIE ,PCIE Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " SATA ,SATA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " HDMI ,HDMI Enable" "Disabled,Enabled"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x04 20. " CUST_1500 ,Customer Efuse 1500 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 19. " VCP ,VCP2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " MLB ,MLB Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " ATL ,ATL Enable" "Disabled,Enabled"
|
|
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
|
|
bitfld.long 0x04 16. " TPP_NDS ,NDS Mode in TPP Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
|
|
bitfld.long 0x04 15. " TPP_IRD ,Irdeto Mode in TPP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " TPP_MUL2 ,Multi2 Mode in TPP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " TPP_CIPH ,TPP Ciphers Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " SEC_AES ,Security Subsystem AES Ciphers Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SEC_DES ,Security Subsystem DES Ciphers Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " SEC_PKA ,Security Subsystem Secure Feature (PKA) Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " SEC_RNG ,Security Subsystem Secure Feature (RNG) Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " SEC_SHA ,Security Subsystem Secure Feature (SHA) Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " HP ,HP Features Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " NIKON ,Nikon Features Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " KODAK ,Kodak Features Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 3. " 3CC ,3CC Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " VIP2 ,Enable VIP2 pins" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " GMII1_RMII1 ,Enable GMII1/RMII1 pins" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MACROV ,Macrovision Enable" "Disabled,Enabled"
|
|
group.long 0x608++0xf
|
|
line.long 0x00 "INIT_PRIORITY_0,Initiator Priority 0 Register"
|
|
bitfld.long 0x00 30.--31. " TCWR3 ,TPTC 3 Write Port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " TCRD3 ,TPTC 3 Read Port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " TCWR2 ,TPTC 2 Write Port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " TCRD2 ,TPTC 2 Read Port initiator priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " TCWR1 ,TPTC 1 Write Port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " TCRD1 ,TPTC 1 Read Port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " TCWR0 ,TPTC 0 Write Port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " TCRD0 ,TPTC 0 Read Port initiator priority" "0,1,2,3"
|
|
textline " "
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x00 14.--15. " P1500 ,P1500 Port Initiator priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10.--11. " HDVPSS1 ,Display Subsystem Port 1 initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " HDVPSS0 ,Display Subsystem Port 0 initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " MMU ,System MMU initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " DSP_CFG ,DSP CFG port initiator priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DSP_MDMA ,DSP MDMA port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " HOST_ARM ,Host Cortex A8 initiator priority" "0,1,2,3"
|
|
line.long 0x04 "INIT_PRIORITY_1,Initiator Priority 1 Register"
|
|
bitfld.long 0x04 30.--31. " FDIF ,FDIF initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 28.--29. " PATA ,PATA initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 26.--27. " HDVICP ,HD-VICP initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 24.--25. " DEBUG ,Debug Subsystem initiator priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " EXP ,Expansion Slot Port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 20.--21. " GRFX ,SGX530 initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 16.--17. " PCIE ,PCIe initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " MEDIA_CTLR ,Media Controller (MEDIACTL) initiator priority" "0,1,2,3"
|
|
textline " "
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x04 8.--9. " SATA ,SATA initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " USB_QMGR ,USB Queue Manager initiator priority" "0,1,2,3"
|
|
else
|
|
bitfld.long 0x04 12.--13. " SECURITYSS ,Security Subsystem initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 10.--11. " TPPSS ,TPP Subsystem initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 8.--9. " SATA ,SATA initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " USB_QMGR ,USB Queue Manager initiator priority" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " USB_DMA ,USB DMA port initiator priority" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " 3PGSW ,3PGSW initiator priority" "0,1,2,3"
|
|
line.long 0x08 "MMU_CFG,MMU Configuration Register"
|
|
bitfld.long 0x08 15. " MMU_ABORT ,MMU abort operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " MMU_EN ,MMU Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TC1MMU ,TPTC1 Uses MMU" "Low,High"
|
|
bitfld.long 0x08 0. " TC0MMU ,TPTC0 Uses MMU" "Low,High"
|
|
line.long 0x0c "TPTC_CFG,TPTC Configuration Register"
|
|
bitfld.long 0x0C 6.--7. " TC3DBS ,TC3 Default Burst Size" "16 byte,32 byte,64 byte,128 byte"
|
|
bitfld.long 0x0C 4.--5. " TC2DBS ,TC2 Default Burst Size" "16 byte,32 byte,64 byte,128 byte"
|
|
bitfld.long 0x0C 2.--3. " TC1DBS ,TC1 Default Burst Size" "16 byte,32 byte,64 byte,128 byte"
|
|
bitfld.long 0x0C 0.--1. " TC0DBS ,TC0 Default Burst Size" "16 byte,32 byte,64 byte,128 byte"
|
|
width 21.
|
|
group.long 0x61c++0x3
|
|
line.long 0x00 "DSP_IDLE_CFG,DSP Standby/Idle Management Register"
|
|
bitfld.long 0x00 15. " DSPSTBY ,Assert DSP Standby" "De-asserted,Asserted"
|
|
bitfld.long 0x00 4.--5. " STBYMODE ,Initiator state management mode" "Force-standby,No-standby,Smart-standby,Smart-standby wakeup-capable"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
|
|
width 21.
|
|
group.long 0x620++0x3
|
|
line.long 0x00 "USB_CTRL0,USB Control Register 0"
|
|
bitfld.long 0x00 31. " SPAREIN7 ,PHY SPAREIN7 ports" "Low,High"
|
|
bitfld.long 0x00 30. " SPAREIN6 ,PHY SPAREIN6 ports" "Low,High"
|
|
bitfld.long 0x00 29. " SPAREIN5 ,PHY SPAREIN5 ports" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPAREIN4 ,PHY SPAREIN4 ports" "Low,High"
|
|
bitfld.long 0x00 27. " SPAREIN3 ,PHY SPAREIN3 ports" "Low,High"
|
|
bitfld.long 0x00 26. " SPAREIN2 ,PHY SPAREIN2 ports" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPAREIN1 ,PHY SPAREIN1 ports" "Low,High"
|
|
bitfld.long 0x00 24. " SPAREIN0 ,PHY SPAREIN0 ports" "Low,High"
|
|
bitfld.long 0x00 23. " DATAPOLARITY_INV ,Data Polarity Invert" "Not inverted (DP/DM),Inverted (DM/DP)"
|
|
textline " "
|
|
bitfld.long 0x00 20. " OTGSESSENDEN ,Session End Detect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " OTGVDET_EN ,VBUS Detect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DMGPIO_PD ,Pull-down on DM in GPIO Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DPGPIO_PD ,Pull-down on DP in GPIO Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DMINPUT ,DM Input in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 15. " DPINPUT ,DP Input in GPIO Mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMOPBUFCTL ,DM Output Buffer Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 13. " DPOPBUFCTL ,DP Output Buffer Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " GPIOMODE ,GPIO Mode" "USB,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CDET_EXTCTL ,Bypass the charger detection state machine" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 9. " DPPULLUP ,Pull-up on DP line" "No effect,Pull-up"
|
|
bitfld.long 0x00 8. " DMPULLUP ,Pull-up on DM line" "No effect,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHGVSRC_EN ,Enable VSRC on DP line" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHGISINK_EN ,Enable ISINK on DM line" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SINKONDP ,Sink on DP" "DM,DP"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SRCONDM ,Source on DM" "DP,DM"
|
|
bitfld.long 0x00 3. " CHGDET_RSTRT ,Restart Charger Detect" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " CHGDET_DIS ,Charger Detect Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OTG_PWRDN ,Power down the USB OTG PHY" "Not powered down,Powered down"
|
|
bitfld.long 0x00 0. " CM_PWRDN ,Power down the USB CM PHY" "Not powered down,Powered down"
|
|
rgroup.long (0x620+0x4)++0x3
|
|
line.long 0x00 "USB_STS0,USB Status Register 0"
|
|
bitfld.long 0x00 13. " GPIO_DMOUT ,Data on DM in GPIO mode" "No data,Data"
|
|
bitfld.long 0x00 12. " GPIO_DPOUT ,Data on DP in GPIO mode" "No data,Data"
|
|
bitfld.long 0x00 5.--7. " CHGDETSTS ,Charge Detection Status" "Wait State,No Contact,PS/2,Error,Dedicated,HOST,PC,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CDET_DMDET ,DM Comparator Output Detection" "Not deteced,Detected"
|
|
bitfld.long 0x00 3. " CDET_DPDET ,DP Comparator Output Detection" "Not deteced,Detected"
|
|
bitfld.long 0x00 2. " CDET_DATADET ,Charger Comparator Output Detection" "Not deteced,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHGDETECT ,Charger Detection Status" "Not deteced,Detected"
|
|
bitfld.long 0x00 0. " CHGDETDONE ,Charger Detection Protocol Done" "Not done,Done"
|
|
group.long 0x628++0x3
|
|
line.long 0x00 "USB_CTRL1,USB Control Register 1"
|
|
bitfld.long 0x00 31. " SPAREIN7 ,PHY SPAREIN7 ports" "Low,High"
|
|
bitfld.long 0x00 30. " SPAREIN6 ,PHY SPAREIN6 ports" "Low,High"
|
|
bitfld.long 0x00 29. " SPAREIN5 ,PHY SPAREIN5 ports" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPAREIN4 ,PHY SPAREIN4 ports" "Low,High"
|
|
bitfld.long 0x00 27. " SPAREIN3 ,PHY SPAREIN3 ports" "Low,High"
|
|
bitfld.long 0x00 26. " SPAREIN2 ,PHY SPAREIN2 ports" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPAREIN1 ,PHY SPAREIN1 ports" "Low,High"
|
|
bitfld.long 0x00 24. " SPAREIN0 ,PHY SPAREIN0 ports" "Low,High"
|
|
bitfld.long 0x00 23. " DATAPOLARITY_INV ,Data Polarity Invert" "Not inverted (DP/DM),Inverted (DM/DP)"
|
|
textline " "
|
|
bitfld.long 0x00 20. " OTGSESSENDEN ,Session End Detect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " OTGVDET_EN ,VBUS Detect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DMGPIO_PD ,Pull-down on DM in GPIO Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DPGPIO_PD ,Pull-down on DP in GPIO Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DMINPUT ,DM Input in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 15. " DPINPUT ,DP Input in GPIO Mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMOPBUFCTL ,DM Output Buffer Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 13. " DPOPBUFCTL ,DP Output Buffer Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " GPIOMODE ,GPIO Mode" "USB,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CDET_EXTCTL ,Bypass the charger detection state machine" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 9. " DPPULLUP ,Pull-up on DP line" "No effect,Pull-up"
|
|
bitfld.long 0x00 8. " DMPULLUP ,Pull-up on DM line" "No effect,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHGVSRC_EN ,Enable VSRC on DP line" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHGISINK_EN ,Enable ISINK on DM line" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SINKONDP ,Sink on DP" "DM,DP"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SRCONDM ,Source on DM" "DP,DM"
|
|
bitfld.long 0x00 3. " CHGDET_RSTRT ,Restart Charger Detect" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " CHGDET_DIS ,Charger Detect Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OTG_PWRDN ,Power down the USB OTG PHY" "Not powered down,Powered down"
|
|
bitfld.long 0x00 0. " CM_PWRDN ,Power down the USB CM PHY" "Not powered down,Powered down"
|
|
rgroup.long (0x628+0x4)++0x3
|
|
line.long 0x00 "USB_STS1,USB Status Register 1"
|
|
bitfld.long 0x00 13. " GPIO_DMOUT ,Data on DM in GPIO mode" "No data,Data"
|
|
bitfld.long 0x00 12. " GPIO_DPOUT ,Data on DP in GPIO mode" "No data,Data"
|
|
bitfld.long 0x00 5.--7. " CHGDETSTS ,Charge Detection Status" "Wait State,No Contact,PS/2,Error,Dedicated,HOST,PC,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CDET_DMDET ,DM Comparator Output Detection" "Not deteced,Detected"
|
|
bitfld.long 0x00 3. " CDET_DPDET ,DP Comparator Output Detection" "Not deteced,Detected"
|
|
bitfld.long 0x00 2. " CDET_DATADET ,Charger Comparator Output Detection" "Not deteced,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHGDETECT ,Charger Detection Status" "Not deteced,Detected"
|
|
bitfld.long 0x00 0. " CHGDETDONE ,Charger Detection Protocol Done" "Not done,Done"
|
|
rgroup.long 0x630++0x13
|
|
line.long 0x0 "MAC_ID0_LO,Ethernet MAC ID0 Low Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " MACADDR[7:0] ,MAC0 Address - Byte 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MACADDR[15:8] ,MAC0 Address - Byte 1"
|
|
line.long (0x0+0x4) "MAC_ID0_HI,Ethernet MAC ID0 High Register"
|
|
hexmask.long.byte (0x0+0x4) 24.--31. 1. " MACADDR[23:16] ,MAC0 Address - Byte 2"
|
|
hexmask.long.byte (0x0+0x4) 16.--23. 1. " MACADDR[31:24] ,MAC0 Address - Byte 3"
|
|
hexmask.long.byte (0x0+0x4) 8.--15. 1. " MACADDR[39:32] ,MAC0 Address - Byte 4"
|
|
textline " "
|
|
hexmask.long.byte (0x0+0x4) 0.--7. 1. " MACADDR[47:40] ,MAC0 Address - Byte 5"
|
|
line.long 0x8 "MAC_ID0_LO,Ethernet MAC ID1 Low Register"
|
|
hexmask.long.byte 0x8 8.--15. 1. " MACADDR[7:0] ,MAC1 Address - Byte 0"
|
|
hexmask.long.byte 0x8 0.--7. 1. " MACADDR[15:8] ,MAC1 Address - Byte 1"
|
|
line.long (0x8+0x4) "MAC_ID0_HI,Ethernet MAC ID1 High Register"
|
|
hexmask.long.byte (0x8+0x4) 24.--31. 1. " MACADDR[23:16] ,MAC1 Address - Byte 2"
|
|
hexmask.long.byte (0x8+0x4) 16.--23. 1. " MACADDR[31:24] ,MAC1 Address - Byte 3"
|
|
hexmask.long.byte (0x8+0x4) 8.--15. 1. " MACADDR[39:32] ,MAC1 Address - Byte 4"
|
|
textline " "
|
|
hexmask.long.byte (0x8+0x4) 0.--7. 1. " MACADDR[47:40] ,MAC1 Address - Byte 5"
|
|
line.long 0x10 "SW_REVISION,SW Revision Register"
|
|
width 21.
|
|
group.long 0x644++0x3
|
|
line.long 0x00 "DCAN_RAMINIT,DCAN RAM Init Register"
|
|
bitfld.long 0x00 9. " DCAN1_RAMINIT_DONE ,DCAN1 RAM Initialization complete" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " DCAN0_RAMINIT_DONE ,DCAN0 RAM Initialization complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DCAN1_RAMINIT_START ,Start DCAN1 RAM initialization sequence" "Not started,Started"
|
|
bitfld.long 0x00 0. " DCAN0_RAMINIT_START ,Start DCAN0 RAM initialization sequence" "Not started,Started"
|
|
width 21.
|
|
group.long 0x64c++0x7
|
|
line.long 0x00 "AUD_CTRL,Audio Interface Control Register"
|
|
bitfld.long 0x00 1. " MCB_LBFSX ,McBSP FSX Loopback enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MCB_LBCLKX ,McBSP CLKX Loopback enable" "Disabled,Enabled"
|
|
line.long 0x04 "GMII_SEL,MII Mode Selection Register"
|
|
bitfld.long 0x04 9. " RGMII1_EN ,Enable RGMII1 PIN selection" "PINCTRL,RGMII"
|
|
bitfld.long 0x04 8. " RGMII0_EN ,Enable RGMII0 PIN selection" "PINCTRL,RGMII"
|
|
bitfld.long 0x04 5. " RGMII1_ID_MODE ,Port 1 CPRGMII Internal Delay Mode" "Internal delay,No internal delay"
|
|
textline " "
|
|
bitfld.long 0x04 4. " RGMII0_ID_MODE ,Port 0 CPRGMII Internal Delay Mode" "Internal delay,No internal delay"
|
|
bitfld.long 0x04 2.--3. " GMII1_SEL ,Port 1 functionality" "GMII/MII,RMII,RGMII,?..."
|
|
bitfld.long 0x04 0.--1. " GMII0_SEL ,Port 0 functionality" "GMII/MII,RMII,RGMII,?..."
|
|
group.long 0x480++0x3
|
|
line.long 0x00 "PCIE_CFG,PCIE Configuration Register"
|
|
bitfld.long 0x00 31. " PCIE_TERM_ENABLE ,PCIE Termination enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " PCIE_TERM_VALUE ,PCIE Termination value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. " PCIDEVTYPE ,PCI device type" "0,1,2,3"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "OCMEM_PWRDN,OCMEM Powerdown Register"
|
|
bitfld.long 0x00 1. " MEM_PWRDN_STATUS ,Power down status from the OCMEM" "Not powered down,Powered down"
|
|
bitfld.long 0x00 0. " MEM_PWRDN ,Power down request to the OCMEM" "Not requested,Requested"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "MPU_MEM_PWRDN,MPU_MEM Powerdown Register"
|
|
bitfld.long 0x00 1. " MEM_PWRDN_STATUS ,Power down status from the MPU_MEM" "Not powered down,Powered down"
|
|
bitfld.long 0x00 0. " MEM_PWRDN ,Power down request to the MPU_MEM" "Not requested,Requested"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "MEDIACTL_MEM_PWRDN,MEDIACTL_MEM Powerdown Register"
|
|
bitfld.long 0x00 1. " MEM_PWRDN_STATUS ,Power down status from the MEDIACTL_MEM" "Not powered down,Powered down"
|
|
bitfld.long 0x00 0. " MEM_PWRDN ,Power down request to the MEDIACTL_MEM" "Not requested,Requested"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "TPPSS_MEM_PWRDN,TPPSS_MEM Powerdown Register"
|
|
bitfld.long 0x00 1. " MEM_PWRDN_STATUS ,Power down status from the TPPSS_MEM" "Not powered down,Powered down"
|
|
bitfld.long 0x00 0. " MEM_PWRDN ,Power down request to the TPPSS_MEM" "Not requested,Requested"
|
|
group.long 0x670++0x1b
|
|
line.long 0x00 "SD_DAC_CTRL,SD DAC Control Register"
|
|
bitfld.long 0x00 25. " DAC1_CM4 ,Channel configuration" "Low,High"
|
|
bitfld.long 0x00 24. " DAC1_CM3 ,Channel configuration" "Single,Dual"
|
|
bitfld.long 0x00 23. " DAC1_CM2 ,Channel configuration (dual/single)" "Luma/Composite video,Chroma video"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DAC1_CM1 ,Lower output swing control (full-scale)" "High,Low"
|
|
bitfld.long 0x00 21. " DAC1_CM0 ,IInternal current reference control" "External,?..."
|
|
bitfld.long 0x00 20. " DAC0_CM4 ,Channel configuration" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DAC0_CM3 ,Channel configuration" "Single,Dual"
|
|
bitfld.long 0x00 18. " DAC0_CM2 ,Channel configuration (dual/single)" "Luma/Composite video,Chroma video"
|
|
bitfld.long 0x00 17. " DAC0_CM1 ,Lower output swing control (full-scale)" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DAC0_CM0 ,IInternal current reference control" "External,?..."
|
|
bitfld.long 0x00 8. " TVOUTBYPASS ,TVOUT Bypass Signal" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 7. " ACEN ,AC coupling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INPUTINV ,Inversion of din[9:0]" "Inverted,Not inverted"
|
|
bitfld.long 0x00 5. " DEMEN ,Dynamic Element Matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PBNDACZ ,DAC Power-Down Control Input" "Powered down,Not powered down"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PBNBGZ ,Bandgap Power-Down Control" "Powered down,Not powered down"
|
|
bitfld.long 0x00 2. " OFFMODE ,Master power-down" "Not powered down,Powered down"
|
|
bitfld.long 0x00 1. " SD_CALSEL ,SD DAC Calibration Select" "Normal,Calibration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESETZ ,Reset signal" "Reset,No reset"
|
|
line.long 0x04 "SD_DAC0_CAL,SD DAC 0 Calibration Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " SDDAC_0_CAL ,SD DAC 0 calibration value"
|
|
line.long 0x08 "SD_DAC1_CAL,SD DAC 1 Calibration Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " SDDAC_1_CAL ,SD DAC 1 calibration value"
|
|
line.long 0x0c "SD_DAC0_REGCTRL,SD DAC 0 Internal Register Control Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " SDDAC_0_CTL ,CTL interface for the AVDAC"
|
|
line.long 0x10 "SD_DAC0_REGSTATUS,SD DAC 0 Internal Register Status Register"
|
|
eventfld.long 0x10 0. " STATUS ,Write status for the AVDAC" "Pending,Acknowledged"
|
|
line.long 0x14 "SD_DAC1_REGCTRL,SD DAC 1 Internal Register Control Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " SDDAC_1_CTL ,CTL interface for the AVDAC"
|
|
line.long 0x18 "SD_DAC1_REGSTATUS,SD DAC 1 Internal Register Status Register"
|
|
eventfld.long 0x18 0. " STATUS ,Write status for the AVDAC" "Pending,Acknowledged"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
width 21.
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "EMIF_CLK_GATE,EMIF_CLK_GATE Register"
|
|
rbitfld.long 0x00 3. " DDR1_CKE_STATUS ,CKE ststus for DDR1" "No Self Refresh,Self Refresh"
|
|
rbitfld.long 0x00 2. " DDR0_CKE_STATUS ,CKE ststus for DDR0" "No Self Refresh,Self Refresh"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DDRPHY1_CLK_GATE ,DDR1 PHY Clock Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " DDRPHY0_CLK_GATE ,DDR0 PHY Clock Enable" "Enabled,Disabled"
|
|
endif
|
|
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
|
|
width 21.
|
|
group.long 0x69c++0x03
|
|
line.long 0x00 "CONTROL_CAMERA_RX,CSI2PHY Control Register"
|
|
bitfld.long 0x00 31. " CAMERARX_WUCLK_DISABLE ,Slow clock disable" "No,Yes"
|
|
bitfld.long 0x00 30. " SMA30 ,SMA30" "Low,High"
|
|
bitfld.long 0x00 29. " SMA29 ,SMA29" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SMA28 ,SMA28" "Low,High"
|
|
bitfld.long 0x00 27. " ADDON3Y_PIPU_CTRL ,Pull control" "Low,High"
|
|
bitfld.long 0x00 26. " ADDON3Y_PIPD_CTRL ,Pull control" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ADDON3X_PIPU_CTRL ,Pull control" "Low,High"
|
|
bitfld.long 0x00 24. " ADDON3X_PIPD_CTRL ,Pull control" "Low,High"
|
|
bitfld.long 0x00 23. " ADDON2Y_PIPU_CTRL ,Pull control" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ADDON2Y_PIPD_CTRL ,Pull control" "Low,High"
|
|
bitfld.long 0x00 21. " ADDON2X_PIPU_CTRL ,Pull control" "Low,High"
|
|
bitfld.long 0x00 20. " ADDON2X_PIPD_CTRL ,Pull control" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ADDON1Y_PIPU_CTRL ,Pull control" "Low,High"
|
|
bitfld.long 0x00 18. " ADDON1Y_PIPD_CTRL ,Pull control" "Low,High"
|
|
bitfld.long 0x00 17. " ADDON1X_PIPU_CTRL ,Pull control" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDON1X_PIPD_CTRL ,Pull control" "Low,High"
|
|
bitfld.long 0x00 15. " COREYB_PIPU_CTRL ,Pull control" "Low,High"
|
|
bitfld.long 0x00 14. " COREYB_PIPD_CTRL ,Pull control" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " COREXB_PIPU_CTRL ,Pull control" "Low,High"
|
|
bitfld.long 0x00 12. " COREXB_PIPD_CTRL ,Pull control" "Low,High"
|
|
bitfld.long 0x00 11. " COREYA_PIPU_CTRL ,Pull control" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " COREYA_PIPD_CTRL ,Pull control" "Low,High"
|
|
bitfld.long 0x00 9. " COREXA_PIPU_CTRL ,Pull control" "Low,High"
|
|
bitfld.long 0x00 8. " COREXA_PIPD_CTRL ,Pull control" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAMERARX_CSI2_LANEENABLE4 ,Lane 4 module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAMERARX_CSI2_LANEENABLE3 ,Lane 3 module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CAMERARX_CSI2_LANEENABLE2 ,Lane 2 module enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CAMERARX_CSI2_LANEENABLE1 ,Lane 1 module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAMERARX_CSI2_LANEENABLE0 ,Lane 0 module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CAMERARX_CSI2_CTRLCLKEN ,CSI2 CTRLCLK enable" "Disabled,Enabled"
|
|
endif
|
|
width 21.
|
|
group.long 0x6A0++0x07
|
|
line.long 0x00 "SMRT_CTRL,Smart Reflex Control Register"
|
|
bitfld.long 0x00 3. " SR3_SRSLLEP ,Sensor 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SR2_SRSLLEP ,Sensor 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SR1_SRSLLEP ,Sensor 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SR0_SRSLLEP ,Sensor 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "ARM_HW_DBG_SEL,ARM Hardware Debug Selection Register"
|
|
bitfld.long 0x04 9. " HW_DBG_GATE_EN ,Debug info not gated off" "Gated off,Not gated off"
|
|
bitfld.long 0x04 8. " HW_DBG_READ_EN ,Read of ARM_HW_DBG_INFO" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--3. " HW_DBG_SEL ,Group of signals sent out to the ARM_HW_DBG_INFO" "Group 0,Group 1,Group 2,Group 3,Group 4,Group 5,Group 6,Group 7,?..."
|
|
width 29.
|
|
group.long 0x6b0++0x7
|
|
line.long 0x00 "PRCM_DEBUG_ALWON_DEFAULT,PRCM Debug AlwaysOn Default Register"
|
|
rbitfld.long 0x00 29. " USB_CLK_OFF ,USB Clock OFF" "ON,OFF"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rbitfld.long 0x00 27. " PCI_CLK_OFF ,PCI Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 26. " SATASS_CLK_OFF ,SATASS Clock OFF" "ON,OFF"
|
|
else
|
|
rbitfld.long 0x00 28. " TPPSS_CLK_OFF ,TPPSS Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 27. " PCI_CLK_OFF ,PCI Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 26. " SATASS_CLK_OFF ,SATASS Clock OFF" "ON,OFF"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 25. " DMM_EMIF_CLK_OFF ,DMM_EMIF Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 24. " MEDIACTL_CLK_OFF ,MEDIACTL Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 22. " RTC_CLK_OFF ,RTC_ Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 21. " VCP_CLK_OFF ,VCP Clock OFF" "ON,OFF"
|
|
textline " "
|
|
rbitfld.long 0x00 20. " OCMC_RAM_CLK_OFF ,OCMC_RAM Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 19. " MPU_CLK_OFF ,MPU Clock OFF" "ON,OFF"
|
|
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
|
|
rbitfld.long 0x00 18. " MMU_CFG_CLK_OFF ,MMU_CFG Clock OFF" "ON,OFF"
|
|
endif
|
|
rbitfld.long 0x00 17. " MMU_CLK_OFF ,MMU Clock OFF" "ON,OFF"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ETHERNET_CLK_OFF ,ETHERNET Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 14. " L3_SLOW_CLK_OFF ,L3_SLOW Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 13. " L3_MED_CLK_OFF ,L3_MED Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 12. " L3_FAST_CLK_OFF ,L3_FAST Clock OFF" "ON,OFF"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " SYSCLK6_CLK_OFF ,SYSCLK6 Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 9. " SYSCLK5_CLK_OFF ,SYSCLK5 Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 8. " SYSCLK4_CLK_OFF ,SYSCLK4 Clock OFF" "ON,OFF"
|
|
rbitfld.long 0x00 4. " DEF_PWR_ON ,Default domain power up" "Powered down,Powered up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HW_DBG_READ_EN ,PRCM_DEBUG_ALWON_DEFAULT read enable" "Disabled,Enabled"
|
|
width 29.
|
|
line.long 0x04 "PRCM_DEBUG_PD_DOMAIN_STATUS,PRCM Debug Power Domain Status Register"
|
|
sif cpuis("DM8147DSP")
|
|
rbitfld.long 0x04 26. " HDVPSS_PD_HDMI_CLK_STATUS_GLUE ,HDMI clk is idled status from glue" "Not idled,Idled"
|
|
else
|
|
rbitfld.long 0x04 31. " SGX_PD_HDVPSS_CLK_STATUS_GLUE ,SGX clk is idled status from glue" "Not idled,Idled"
|
|
rbitfld.long 0x04 30. " SGX_PD_CLK_STATUS_PRCM ,SGX domain clks are idled" "Not idled,Idled"
|
|
textline " "
|
|
rbitfld.long 0x04 29. " SGX_PD_MEM_ON_GLUE ,SGX domain memories are off" "ON,OFF"
|
|
rbitfld.long 0x04 28. " SGX_PD_SWITCH_ON_GLUE ,SGX domain switches are off" "ON,OFF"
|
|
textline " "
|
|
rbitfld.long 0x04 27. " SGX_PD_ON_PRCM ,SGX domain is not powered up" "Powered up,Powered down"
|
|
rbitfld.long 0x04 26. " HDVPSS_PD_HDMI_CLK_STATUS_GLUE ,HDMI clk is idled status from glue" "Not idled,Idled"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x04 25. " HDVPSS_PD_HDVPSS_CLK_STATUS_GLUE ,HDVPSS clk is idled status from glue" "Not idled,Idled"
|
|
rbitfld.long 0x04 24. " HDVPSS_PD_CLK_STATUS_PRCM ,HDVPSS domain clks are idled" "Not idled,Idled"
|
|
textline " "
|
|
rbitfld.long 0x04 23. " HDVPSS_PD_MEM_ON_GLUE ,HDVPSS domain memories are off" "ON,OFF"
|
|
rbitfld.long 0x04 22. " HDVPSS_PD_SWITCH_ON_GLUE ,HDVPSS domain switches are off" "ON,OFF"
|
|
textline " "
|
|
rbitfld.long 0x04 21. " HDVPSS_PD_ON_PRCM ,HDVPSS domain is not powered up" "Powered up,Powered down"
|
|
rbitfld.long 0x04 20. " MEDIACTL_PD_FDIF_CLK_STATUS_GLUE ,FDIF clk is idled status from glue" "Not idled,Idled"
|
|
textline " "
|
|
rbitfld.long 0x04 19. " MEDIACTL_PD_MEDIACTL_CLK_STATUS_GLUE ,MEDIACTL clk is idled status from glue" "Not idled,Idled"
|
|
rbitfld.long 0x04 18. " MEDIACTL_PD_CLK_STATUS_PRCM ,MEDIACTL domain clks are idled" "Not idled,Idled"
|
|
textline " "
|
|
rbitfld.long 0x04 17. " MEDIACTL_PD_MEM_ON_GLUE ,MEDIACTL domain memories are off" "ON,OFF"
|
|
rbitfld.long 0x04 16. " MEDIACTL_PD_SWITCH_ON_GLUE ,MEDIACTL domain switches are off" "ON,OFF"
|
|
textline " "
|
|
rbitfld.long 0x04 15. " MEDIACTL_PD_ON_PRCM ,MEDIACTL domain is not powered up" "Powered up,Powered down"
|
|
rbitfld.long 0x04 14. " HDVICP_PD_SLX_CLK_STATUS_GLUE ,HDVICP slx clk is idled status from glue" "Not idled,Idled"
|
|
textline " "
|
|
rbitfld.long 0x04 13. " HDVICP_PD_HDVICP_CLK_STATUS_GLUE ,HDVICP clk is idled status from glue" "Not idled,Idled"
|
|
rbitfld.long 0x04 12. " HDVICP_PD_HDVICP_CLK_STATUS_PRCM ,HDVICP domain clks are idled" "Not idled,Idled"
|
|
textline " "
|
|
rbitfld.long 0x04 11. " HDVICP_PD_MEM_ON_GLUE ,HDVICP domain memories are off" "ON,OFF"
|
|
rbitfld.long 0x04 10. " HDVICP_PD_SWITCH_ON_GLUE ,HDVICP domain switches are off" "ON,OFF"
|
|
textline " "
|
|
rbitfld.long 0x04 9. " HDVICP_PD_ON_PRCM ,HDVICP domain is not powered up" "Powered up,Powered down"
|
|
rbitfld.long 0x04 8. " ACTIVE_PD_DSP_CLK_STATUS_GLUE ,DSP clk is idled status from glue" "Not idled,Idled"
|
|
textline " "
|
|
rbitfld.long 0x04 7. " ACTIVE_PD_DSP_CLK_STATUS_PRCM ,DSP clk is idled" "Not idled,Idled"
|
|
rbitfld.long 0x04 6. " ACTIVE_PD_MEM_ON_GLUE ,Active domain memories are off" "ON,OFF"
|
|
textline " "
|
|
rbitfld.long 0x04 5. " ACTIVE_PD_SWITCH_ON_GLUE ,Active domain switches are off" "ON,OFF"
|
|
rbitfld.long 0x04 4. " ACTIVE_PD_ON_PRCM ,Active domain is not powered up" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HW_DBG_READ_EN ,Read of PRCM_DEBUG_PD_DOMAIN_STATUS enable" "Disabled,Enabled"
|
|
width 16.
|
|
group.long 0x6d8++0x13
|
|
line.long 0x00 "PCIE_PLLCFG0,PCIe PLL Configuration 0 Register"
|
|
bitfld.long 0x00 31. " SEL_IN_FREQ ,Select input frequency" "100 MHz,20 MHz"
|
|
bitfld.long 0x00 30. " DIGCLRZ ,CLRZ for APLL DIG and DLL DIG" "No reset,Reset"
|
|
textline " "
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x00 27. " AMUXSEL ,AMUX Select" "KVCO,VRTRIM"
|
|
bitfld.long 0x00 26. " TESTCLKMUXSEL ,Test clock mux" "REF clock,Divided clock"
|
|
else
|
|
bitfld.long 0x00 28.--29. " PCIE_PLL_CFGPLL0[29:28] ,PCIE_PLL_CFGPLL0[29:28]" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " PCIE_PLL_CFGPLL0[27:26] ,PCIE_PLL_CFGPLL0[27:26]" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 25. " APLL_MISC_CTRL[25] ,APLL DIG lock speed" "128 clock,256 clock"
|
|
bitfld.long 0x00 24. " APLL_MISC_CTRL[24] ,APLL DIG 50 MHz rtrim disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " APLL_MISC_CTRL[23] ,APLL DIG divider select" "Fixed,Programmable"
|
|
bitfld.long 0x00 22. " APLL_MISC_CTRL[22] ,APLL DIG Power saving mode" "Default,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " APLL_MISC_CTRL[21:20] ,APLL DIG step" "No step,75%-100%,75%-87.5%-100% 60/20/20,75%-87.5%-100% 40/40/40"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DIS_REFCLK ,Enable/disable reference clock " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EN_3P ,Single phase output generation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PFD_CLR ,Reset for phase-frequency detector" "No reset,Reset"
|
|
bitfld.long 0x00 16. " CLK_FLIP ,Output clock phase flip enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_RTRIM ,Enable resistor calibration" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EN_MEAS ,Enable measurement circuit inside APLL ANA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " EN_LATCH ,Output latch in differential ring enable" "All on,-33%,-16%,-50%"
|
|
bitfld.long 0x00 8.--11. " CP_CTRL ,Charge pump control (+/- 50%)" "Nom,+13%,+27%,+50%,-20%,Reserved,Reserved,Reserved,-27%,Reserved,-50%,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RESVALUE ,Loop filter resistor value" "1 kOhm PCIe,1.67 kOhm eSATA,2.5 kOhm SSC,?..."
|
|
bitfld.long 0x00 5. " C1_2X ,Increase filter capacitance by 2x in low reference (20 MHz) clock" "No INC,INC"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDIGLDO ,Enable DIG LDO" "Disabled,Enabled"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x00 3. " APLL_CP_CURR ,APLL CP current increase" "No INC,INC"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENBGSC_REF ,Enable switched cap bias current module/REFGEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENPLLLDO ,Enable PLL LDO" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 3. " SELSC ,SELSC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENBGSC_REF ,ENBGSC_REF" "Low,High"
|
|
bitfld.long 0x00 1. " ENPLLLDO ,Enable PLL LDO" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENPLL ,Enable PLL" "Disabled,Enabled"
|
|
line.long 0x04 "PCIE_PLLCFG1,PCIe PLL Configuration 1 Register"
|
|
bitfld.long 0x04 31. " ENSATAMODE ,Enable SATA Mode" "PCIe (2.5 GHz),SATA (1.5 GHz)"
|
|
bitfld.long 0x04 30. " PLLREFSEL ,PLL reference clock value" "100 MHz,20 MHz"
|
|
textline " "
|
|
bitfld.long 0x04 26.--29. " NP1_DIV_INT ,Integer value of N+1 divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 18.--25. 1. " MDIVINT ,Integer portion of feedback divider"
|
|
textline " "
|
|
hexmask.long.word 0x04 6.--17. 1. " MDIVFRAC ,Fractional portion of feedback divider"
|
|
bitfld.long 0x04 5. " EN_CLKAUX ,Enable/disable auxilary clock" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " EN_CLK125M ,Enable for 125MHz clock" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " EN_CLK100M ,Enable for 100MHz clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EN_CLK50M ,Enable for 50MHz clock" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " ENSSC ,Enable spread specturm support" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MDIVPULSE ,Update M div when pulse is high" "Low,High"
|
|
line.long 0x08 "PCIE_PLLCFG2,PCIe PLL Configuration 2 Register"
|
|
bitfld.long 0x08 31. " SSCDNSPREAD ,SSC downspread" "Low,High"
|
|
hexmask.long.byte 0x08 24.--30. 1. " SSCMANT ,Mantesa portion of the modified frequency in SSC operation"
|
|
textline " "
|
|
bitfld.long 0x08 21.--23. " SSCEXPO ,Exponent portion of the modified frequency in SSC operation" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x08 0.--20. 1. " SSCFRSPREAD ,SSC frequency spread"
|
|
line.long 0x0c "PCIE_PLLCFG3,PCIe PLL Configuration 3 Register"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x0C 27. " DIGLDO_BYPASS ,DIG LDO Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x0C 26. " DIGLDO_PULLDOWNZ ,DIG LDO pulldown paths disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " DIGLDO_DIS_SC_PROT ,DIG LDO Short Circuit Protection Disable" "No,Yes"
|
|
bitfld.long 0x0C 24. " DIGLDO_EN_SUB_REGULATION ,DIG LDO Sub Regulation Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " DIGLDO_EN_HP_CAPLESSMODE ,DIG LDO High Performance Capless Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " DIGLDO_EN_CAPLESSMODE ,DIG LDO Capless Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " DIGLDO_EN_LP_CAPLESSMODE ,DIG LDO Low Power Capless Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--20. " DIGLDO_VSET ,DIG LDO VSET Value" "1.21,1.22,1.23,1.24,1.25,1.26,1.27,1.28,1.29,1.30,1.31,1.32,1.33,1.34,1.35,1.36,1.05,1.06,1.07,1.08,1.09,1.10,1.11,1.12,1.13,1.14,1.15,1.16,1.17,1.18,1.19,1.20"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PLLLDO_EN_RETENTION ,Enable retention mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PLLLDO_EN_LDO_STABLE ,LDO Stable Signal" "Unstable,Stable"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PLLLDO_EN_BYPASS ,Enable bypass mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PLLLDO_EN_SC_PROT ,Enable short circuit protection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PLLLDO_EN_EXT_CAP ,Enable external cap mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PLLLDO_EN_BUF_CUR ,Enable Increased Buffer Current" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PLLLDO_EN_LP ,Enable Low Power" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " PLLLDO_CTRL_TRIM ,Trim bits vout" "1.000,1.025,1.050,1.075,1.100,1.125,1.150,1.175,1.200,1.225,1.250,1.275,1.300,1.325,1.350,1.375,1.400,1.425,1.450,1.475,1.500,1.525,1.550,1.575,1.600,?..."
|
|
else
|
|
bitfld.long 0x0C 26. " DIGLDO_PULLDOWNZ ,DIG LDO test mode" "Low,High"
|
|
bitfld.long 0x0C 25. " DIGLDO_ENFUNC5 ,DIG LDO test mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " DIGLDO_ENFUNC4 ,DIG LDO test mode" "Low,High"
|
|
bitfld.long 0x0C 23. " DIGLDO_ENFUNC3 ,DIG LDO test mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " DIGLDO_ENFUNC2 ,DIG LDO test mode" "Low,High"
|
|
bitfld.long 0x0C 21. " DIGLDO_ENFUNC1 ,DIG LDO test mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--20. " DIGLDO_VSET ,DIG LDO test mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x0C 0.--12. 1. " PLLLDO_CTRL ,PLL LDO test mode"
|
|
endif
|
|
line.long 0x10 "PCIE_PLLCFG4,PCIe PLL Configuration 4 Register"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x10 25. " AUX_CLK_SEL ,AUX Clock Select" "Divided,Ref-clk"
|
|
textline " "
|
|
bitfld.long 0x10 20.--24. " AUX_DIV ,Aux divider control" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x10 18.--19. " RTRIM_RANGE ,Range for rtrim" "0.9-0.8,1.0-0.9,1.1-1.0,1.1-0.9"
|
|
else
|
|
bitfld.long 0x10 25. " PCIE_PLL_CFGPLL4[25] ,PCIE_PLL_CFGPLL4[25]" "Low,High"
|
|
bitfld.long 0x10 24. " AUX_CLK_SEL ,AUX Clock Select" "Divided,Ref-clk"
|
|
textline " "
|
|
bitfld.long 0x10 20.--23. " AUX_DIV ,Aux divider control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 18.--19. " RTRIM_RANGE ,Range for rtrim" "0.9-0.8,1.0-0.9,1.1-1.0,1.1-0.9"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 17. " RTRIM_EXT_EN ,Select loop starting point" "Mid-code,External"
|
|
bitfld.long 0x10 16. " RTRIM_SPEED ,Selection on wait for # REFCLKs after previous update" "128,256"
|
|
textline " "
|
|
bitfld.long 0x10 14.--15. " RTRIM_MODE ,Loop mode" "OFF,OFF,ON (freeze),ON (continouos)"
|
|
bitfld.long 0x10 10.--13. " RTRIM_EXT_VAL ,2's compliment vtune control loop value" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
|
|
textline " "
|
|
bitfld.long 0x10 8.--9. " VTUNE_RANGE ,Range for Vtune" "0.9-0.8,1.0-0.9,1.1-1.0,1.1-0.9"
|
|
bitfld.long 0x10 7. " VTUNE_EXT_EN ,Select loop starting point" "Mid-code,External"
|
|
textline " "
|
|
bitfld.long 0x10 6. " VTUNE_SPEED ,Selection on wait for # REFCLKs after previous update" "128,256"
|
|
bitfld.long 0x10 4.--5. " VTUNE_MODE ,Loop mode" "OFF,OFF,ON (freeze),ON (continouos)"
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " VTUNE_EXT_VAL ,2's compliment vtune control loop value" "0,1,2,3,4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,-4,-3,-2-,1"
|
|
width 16.
|
|
rgroup.long 0x6ec++0x0B
|
|
line.long 0x00 "PCIE_PLLSTATUS,PCIe PLL Status Register"
|
|
bitfld.long 0x00 8.--11. " RTRIMSTS ,Value of the rtrim loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " VTUNESTS ,Value of the vtune control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLLDIG_EN ,Digital enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PLLANA_EN ,Analog enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLSSC_EN ,SSC is engaged" "Not engaged,Engaged"
|
|
bitfld.long 0x00 0. " PLL_LOCK ,APLL locked" "Unlocked,Locked"
|
|
line.long 0x04 "PCIE_RXSTATUS,PCIe RX Status Register"
|
|
bitfld.long 0x04 0. " TESTFAIL ,Test failure" "No error,Error"
|
|
line.long 0x08 "PCIE_TXSTATUS,PCIe TX Status Register"
|
|
bitfld.long 0x08 0. " TESTFAIL ,Test failure" "No error,Error"
|
|
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
|
|
group.long 0x6F8++0x07
|
|
line.long 0x00 "PCIE_TESTCFG,PCIe TEST Config Register"
|
|
bitfld.long 0x00 0.--2. " RX_TESTPATT ,Enables and selects test patterns" "Reserved,Alternating 0/1 pattern with a period of 2 UI,7-bit LFSR with feedback polynomial x7+x6+1,23-bit LFSR with feedback polynomial x23+x18+1,31-bit LFSR with feedback polynomial x31+x28+1,?..."
|
|
line.long 0x04 "PCIE_MISCCFG,PCIe MISC configuration Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " PCIE_SERDES_CFG_MISC[12:0] ,PCIE_SERDES_CFG_MISC[12:0]"
|
|
endif
|
|
width 16.
|
|
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
|
|
group.long 0x720++0x13
|
|
line.long 0x00 "SATA_PLLCFG0,SATA PLL Configuration 0 Register"
|
|
bitfld.long 0x00 31. " SEL_IN_FREQ ,Select input frequency" "100 MHz,20 MHz"
|
|
bitfld.long 0x00 30. " DIGCLRZ ,CLRZ for APLL DIG and DLL DIG" "No reset,Reset"
|
|
bitfld.long 0x00 26.--27. " PCIE_PLL_CFGPLL0[27:26] ,PCIE_PLL_CFGPLL0[27:26]" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--25. " APLL_MISC_CTRL ,APLL_MISC_CTRL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19. " DIS_REFCLK ,Enable/disable reference clock " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EN_3P ,Single phase output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PFD_CLR ,Reset for phase-frequency detector" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CLK_FLIP ,Output clock phase flip enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_RTRIM ,Enable resistor calibration" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EN_MEAS ,Enable measurement circuit inside APLL ANA" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " EN_LATCH ,Output latch in differential ring enable" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CP_CTRL ,Charge pump control (+/- 50%)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. " RESVALUE ,Loop filter resistor value" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C1_2X ,Increase filter capacitance by 2x in low reference (20 MHz) clock" "No INC,INC"
|
|
bitfld.long 0x00 4. " ENDIGLDO ,Enable DIG LDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SELSC ,SELSC" "Low,High"
|
|
bitfld.long 0x00 2. " ENBGSC_REF ,ENBGSC_REF" "Low,High"
|
|
bitfld.long 0x00 1. " ENPLLLDO ,Enable PLL LDO" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENPLL ,Enable PLL" "Disabled,Enabled"
|
|
line.long 0x04 "SATA_PLLCFG1,SATA PLL Configuration 1 Register"
|
|
bitfld.long 0x04 31. " ENSATAMODE ,Enable SATA Mode" "PCIe (2.5 GHz),SATA (1.5 GHz)"
|
|
bitfld.long 0x04 30. " PLLREFSEL ,PLL reference clock value" "100 MHz,20 MHz"
|
|
bitfld.long 0x04 26.--29. " NP1_DIV_INT ,Integer value of N+1 divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 18.--25. 1. " MDIVINT ,Integer portion of feedback divider"
|
|
textline " "
|
|
hexmask.long.word 0x04 6.--17. 1. " MDIVFRAC ,Fractional portion of feedback divider"
|
|
bitfld.long 0x04 5. " EN_CLKAUX ,Enable/disable auxilary clock" "Enabled,Disabled"
|
|
bitfld.long 0x04 4. " EN_CLK125M ,Enable for 125MHz clock" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " EN_CLK100M ,Enable for 100MHz clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EN_CLK50M ,Enable for 50MHz clock" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " ENSSC ,Enable spread specturm support" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MDIVPULSE ,Update M div when pulse is high" "Low,High"
|
|
line.long 0x08 "SATA_PLLCFG2,SATA PLL Configuration 2 Register"
|
|
bitfld.long 0x08 31. " SSCDNSPREAD ,SSC downspread" "Low,High"
|
|
hexmask.long.byte 0x08 24.--30. 1. " SSCMANT ,Mantesa portion of the modified frequency in SSC operation"
|
|
bitfld.long 0x08 21.--23. " SSCEXPO ,Exponent portion of the modified frequency in SSC operation" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x08 0.--20. 1. " SSCFRSPREAD ,SSC frequency spread"
|
|
line.long 0x0c "SATA_PLLCFG3,SATA PLL Configuration 3 Register"
|
|
bitfld.long 0x0C 26. " DIGLDO_PULLDOWNZ ,DIG LDO test mode" "Low,High"
|
|
bitfld.long 0x0C 25. " DIGLDO_ENFUNC5 ,DIG LDO test mode" "Low,High"
|
|
bitfld.long 0x0C 24. " DIGLDO_ENFUNC4 ,DIG LDO test mode" "Low,High"
|
|
bitfld.long 0x0C 23. " DIGLDO_ENFUNC3 ,DIG LDO test mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " DIGLDO_ENFUNC2 ,DIG LDO test mode" "Low,High"
|
|
bitfld.long 0x0C 21. " DIGLDO_ENFUNC1 ,DIG LDO test mode" "Low,High"
|
|
bitfld.long 0x0C 16.--20. " DIGLDO_VSET ,DIG LDO test mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x0C 0.--12. 1. " PLLLDO_CTRL ,PLL LDO test mode"
|
|
line.long 0x10 "SATA_PLLCFG4,SATA PLL Configuration 4 Register"
|
|
bitfld.long 0x10 25. " CFGPLL4[25] ,CFGPLL4[25]" "Low,High"
|
|
bitfld.long 0x10 24. " AUX_CLK_SEL ,AUX Clock Select" "Divided,Ref-clk"
|
|
bitfld.long 0x10 20.--23. " AUX_DIV ,Aux divider control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 18.--19. " RTRIM_RANGE ,Range for rtrim" "0.9-0.8,1.0-0.9,1.1-1.0,1.1-0.9"
|
|
textline " "
|
|
bitfld.long 0x10 17. " RTRIM_EXT_EN ,Select loop starting point" "Mid-code,External"
|
|
bitfld.long 0x10 16. " RTRIM_SPEED ,Selection on wait for # REFCLKs after previous update" "128,256"
|
|
bitfld.long 0x10 14.--15. " RTRIM_MODE ,Loop mode" "OFF,OFF,ON (freeze),ON (continouos)"
|
|
bitfld.long 0x10 10.--13. " RTRIM_EXT_VAL ,2's compliment vtune control loop value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 8.--9. " VTUNE_RANGE ,Range for Vtune" "0.9-0.8,1.0-0.9,1.1-1.0,1.1-0.9"
|
|
bitfld.long 0x10 7. " VTUNE_EXT_EN ,Select loop starting point" "Mid-code,External"
|
|
bitfld.long 0x10 6. " VTUNE_SPEED ,Selection on wait for # REFCLKs after previous update" "128,256"
|
|
bitfld.long 0x10 4.--5. " VTUNE_MODE ,Loop mode" "OFF,OFF,ON (freeze),ON (continouos)"
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " VTUNE_EXT_VAL ,2's compliment vtune control loop value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x734++0xf
|
|
line.long 0x00 "SATA_PLLSTATUS,SATA PLL Status Register"
|
|
bitfld.long 0x00 8.--11. " RTRIMSTS ,Value of the rtrim loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " VTUNESTS ,Value of the vtune control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " APLLDIGSTS1 ,SSC is engaged" "Not engaged,Engaged"
|
|
bitfld.long 0x00 0. " APLLDIGSTS0 ,APLL locked" "Unlocked,Locked"
|
|
line.long 0x04 "SATA_RXSTATUS,SATA RX Status Register"
|
|
bitfld.long 0x04 0. " TESTFAIL ,Test failure" "No error,Error"
|
|
line.long 0x08 "SATA_TXSTATUS,SATA TX Status Register"
|
|
bitfld.long 0x08 0. " TESTFAIL ,Test failure" "No error,Error"
|
|
line.long 0x0c "SATA_TESTCFG,SATA TEST Config Register"
|
|
bitfld.long 0x0C 0.--2. " RX_TESTPATT ,Enables and selects test patterns" "Reserved,Alternating 0/1 pattern with a period of 2 UI,7-bit LFSR with feedback polynomial x7+x6+1,23-bit LFSR with feedback polynomial x23+x18+1,31-bit LFSR with feedback polynomial x31+x28+1,?..."
|
|
endif
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
width 23.
|
|
group.long 0x770++0x0F
|
|
line.long 0x00 "VDD_MPU_OPP_050,Ntarget value for OPP50"
|
|
hexmask.long.tbyte 0x00 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP50"
|
|
line.long 0x04 "VDD_MPU_OPP_100,Ntarget value for OPP100"
|
|
hexmask.long.tbyte 0x04 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP100"
|
|
line.long 0x08 "VDD_MPU_OPP_120,Ntarget value for OPP120"
|
|
hexmask.long.tbyte 0x08 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP120"
|
|
line.long 0x0C "VDD_MPU_OPP_166,Ntarget value for OPP166"
|
|
hexmask.long.tbyte 0x0C 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP166"
|
|
group.long 0x788++0x0F
|
|
line.long 0x00 "VDD_C674x_DSP_OPP_050,Ntarget value for OPP50"
|
|
hexmask.long.tbyte 0x00 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP50"
|
|
line.long 0x04 "VDD_C674x_DSP_OPP_100,Ntarget value for OPP100"
|
|
hexmask.long.tbyte 0x04 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP100"
|
|
line.long 0x08 "VDD_C674x_DSP_OPP_120,Ntarget value for OPP120"
|
|
hexmask.long.tbyte 0x08 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP120"
|
|
line.long 0x0C "VDD_C674x_DSP_OPP_166,Ntarget value for OPP166"
|
|
hexmask.long.tbyte 0x0C 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP166"
|
|
group.long 0x7A0++0x0F
|
|
line.long 0x00 "VDD_HDVICP_OPP_050,Ntarget value for OPP50"
|
|
hexmask.long.tbyte 0x00 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP50"
|
|
line.long 0x04 "VDD_HDVICP_OPP_100,Ntarget value for OPP100"
|
|
hexmask.long.tbyte 0x04 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP100"
|
|
line.long 0x08 "VDD_HDVICP_OPP_120,Ntarget value for OPP120"
|
|
hexmask.long.tbyte 0x08 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP120"
|
|
line.long 0x0C "VDD_HDVICP_OPP_166,Ntarget value for OPP166"
|
|
hexmask.long.tbyte 0x0C 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP166"
|
|
group.long 0x7B8++0x0F
|
|
line.long 0x00 "VDD_CORE_OPP_050,Ntarget value for OPP50"
|
|
hexmask.long.tbyte 0x00 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP50"
|
|
line.long 0x04 "VDD_CORE_OPP_100,Ntarget value for OPP100"
|
|
hexmask.long.tbyte 0x04 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP100"
|
|
line.long 0x08 "VDD_CORE_OPP_120,Ntarget value for OPP120"
|
|
hexmask.long.tbyte 0x08 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP120"
|
|
line.long 0x0C "VDD_CORE_OPP_166,Ntarget value for OPP166"
|
|
hexmask.long.tbyte 0x0C 0.--23. 0x1 " NTARGET ,Ntarget value for MPU Voltage domain s OPP166"
|
|
endif
|
|
width 16.
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rgroup.long 0x7D0++0x03
|
|
line.long 0x00 "BB_SCALE,Back Bias and Dynamic Core Voltage Scaling Register"
|
|
bitfld.long 0x00 8.--11. " SCALE ,Dynamic Core Voltage Scaling For class 0 smart reflex" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. " BBIAS ,BBIAS value from Efuse" "0,1,2,3"
|
|
endif
|
|
rgroup.long 0x7f4++0xb
|
|
line.long 0x00 "USB_VID_PID,USB VID/PID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " USB_VID ,USB Vendor ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " USB_PID ,USB Product ID"
|
|
line.long 0x04 "PCIE_VID_PID,PCIE VID/PID Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " PCIE_VID ,PCIE Vendor ID"
|
|
hexmask.long.word 0x04 0.--15. 1. " PCIE_PID ,PCIE Product ID"
|
|
line.long 0x08 "EFUSE_SMA,EFUSE SMA Register"
|
|
width 12.
|
|
tree "Pin Control Registers"
|
|
group.long 0x800++0x103
|
|
line.long 0x0 "PINCTRL1,Pin 1 Control Register"
|
|
bitfld.long 0x0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x4 "PINCTRL2,Pin 2 Control Register"
|
|
bitfld.long 0x4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x8 "PINCTRL3,Pin 3 Control Register"
|
|
bitfld.long 0x8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xC "PINCTRL4,Pin 4 Control Register"
|
|
bitfld.long 0xC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x10 "PINCTRL5,Pin 5 Control Register"
|
|
bitfld.long 0x10 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x10 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x10 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x14 "PINCTRL6,Pin 6 Control Register"
|
|
bitfld.long 0x14 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x14 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x14 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x18 "PINCTRL7,Pin 7 Control Register"
|
|
bitfld.long 0x18 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x18 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x18 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1C "PINCTRL8,Pin 8 Control Register"
|
|
bitfld.long 0x1C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x20 "PINCTRL9,Pin 9 Control Register"
|
|
bitfld.long 0x20 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x20 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x20 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x24 "PINCTRL10,Pin 10 Control Register"
|
|
bitfld.long 0x24 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x24 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x24 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x28 "PINCTRL11,Pin 11 Control Register"
|
|
bitfld.long 0x28 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x28 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x28 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2C "PINCTRL12,Pin 12 Control Register"
|
|
bitfld.long 0x2C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x30 "PINCTRL13,Pin 13 Control Register"
|
|
bitfld.long 0x30 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x30 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x30 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x34 "PINCTRL14,Pin 14 Control Register"
|
|
bitfld.long 0x34 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x34 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x34 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x38 "PINCTRL15,Pin 15 Control Register"
|
|
bitfld.long 0x38 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x38 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x38 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3C "PINCTRL16,Pin 16 Control Register"
|
|
bitfld.long 0x3C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x40 "PINCTRL17,Pin 17 Control Register"
|
|
bitfld.long 0x40 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x40 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x40 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x44 "PINCTRL18,Pin 18 Control Register"
|
|
bitfld.long 0x44 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x44 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x44 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x48 "PINCTRL19,Pin 19 Control Register"
|
|
bitfld.long 0x48 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x48 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x48 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x4C "PINCTRL20,Pin 20 Control Register"
|
|
bitfld.long 0x4C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x4C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x50 "PINCTRL21,Pin 21 Control Register"
|
|
bitfld.long 0x50 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x50 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x50 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x54 "PINCTRL22,Pin 22 Control Register"
|
|
bitfld.long 0x54 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x54 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x54 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x58 "PINCTRL23,Pin 23 Control Register"
|
|
bitfld.long 0x58 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x58 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x58 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x5C "PINCTRL24,Pin 24 Control Register"
|
|
bitfld.long 0x5C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x5C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x60 "PINCTRL25,Pin 25 Control Register"
|
|
bitfld.long 0x60 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x60 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x60 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x64 "PINCTRL26,Pin 26 Control Register"
|
|
bitfld.long 0x64 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x64 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x64 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x68 "PINCTRL27,Pin 27 Control Register"
|
|
bitfld.long 0x68 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x68 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x68 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x6C "PINCTRL28,Pin 28 Control Register"
|
|
bitfld.long 0x6C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x6C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x70 "PINCTRL29,Pin 29 Control Register"
|
|
bitfld.long 0x70 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x70 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x70 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x74 "PINCTRL30,Pin 30 Control Register"
|
|
bitfld.long 0x74 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x74 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x74 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x78 "PINCTRL31,Pin 31 Control Register"
|
|
bitfld.long 0x78 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x78 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x78 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x7C "PINCTRL32,Pin 32 Control Register"
|
|
bitfld.long 0x7C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x7C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x80 "PINCTRL33,Pin 33 Control Register"
|
|
bitfld.long 0x80 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x80 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x80 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x84 "PINCTRL34,Pin 34 Control Register"
|
|
bitfld.long 0x84 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x84 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x84 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x88 "PINCTRL35,Pin 35 Control Register"
|
|
bitfld.long 0x88 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x88 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x88 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x8C "PINCTRL36,Pin 36 Control Register"
|
|
bitfld.long 0x8C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x8C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x90 "PINCTRL37,Pin 37 Control Register"
|
|
bitfld.long 0x90 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x90 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x90 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x94 "PINCTRL38,Pin 38 Control Register"
|
|
bitfld.long 0x94 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x94 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x94 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x98 "PINCTRL39,Pin 39 Control Register"
|
|
bitfld.long 0x98 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x98 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x98 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x9C "PINCTRL40,Pin 40 Control Register"
|
|
bitfld.long 0x9C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x9C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xA0 "PINCTRL41,Pin 41 Control Register"
|
|
bitfld.long 0xA0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xA0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xA4 "PINCTRL42,Pin 42 Control Register"
|
|
bitfld.long 0xA4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xA4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xA8 "PINCTRL43,Pin 43 Control Register"
|
|
bitfld.long 0xA8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xA8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xAC "PINCTRL44,Pin 44 Control Register"
|
|
bitfld.long 0xAC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xAC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xB0 "PINCTRL45,Pin 45 Control Register"
|
|
bitfld.long 0xB0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xB0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xB4 "PINCTRL46,Pin 46 Control Register"
|
|
bitfld.long 0xB4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xB4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xB8 "PINCTRL47,Pin 47 Control Register"
|
|
bitfld.long 0xB8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xB8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xBC "PINCTRL48,Pin 48 Control Register"
|
|
bitfld.long 0xBC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xBC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xC0 "PINCTRL49,Pin 49 Control Register"
|
|
bitfld.long 0xC0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xC0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xC4 "PINCTRL50,Pin 50 Control Register"
|
|
bitfld.long 0xC4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xC4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xC8 "PINCTRL51,Pin 51 Control Register"
|
|
bitfld.long 0xC8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xC8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xCC "PINCTRL52,Pin 52 Control Register"
|
|
bitfld.long 0xCC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xCC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xD0 "PINCTRL53,Pin 53 Control Register"
|
|
bitfld.long 0xD0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xD0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xD4 "PINCTRL54,Pin 54 Control Register"
|
|
bitfld.long 0xD4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xD4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xD8 "PINCTRL55,Pin 55 Control Register"
|
|
bitfld.long 0xD8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xD8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xDC "PINCTRL56,Pin 56 Control Register"
|
|
bitfld.long 0xDC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xDC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xE0 "PINCTRL57,Pin 57 Control Register"
|
|
bitfld.long 0xE0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xE0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xE4 "PINCTRL58,Pin 58 Control Register"
|
|
bitfld.long 0xE4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xE4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xE8 "PINCTRL59,Pin 59 Control Register"
|
|
bitfld.long 0xE8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xE8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xEC "PINCTRL60,Pin 60 Control Register"
|
|
bitfld.long 0xEC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xEC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xF0 "PINCTRL61,Pin 61 Control Register"
|
|
bitfld.long 0xF0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xF0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xF0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xF4 "PINCTRL62,Pin 62 Control Register"
|
|
bitfld.long 0xF4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xF4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xF4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xF8 "PINCTRL63,Pin 63 Control Register"
|
|
bitfld.long 0xF8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xF8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xF8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xFC "PINCTRL64,Pin 64 Control Register"
|
|
bitfld.long 0xFC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xFC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xFC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x100 "PINCTRL65,Pin 65 Control Register"
|
|
bitfld.long 0x100 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x100 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x100 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
group.long 0x904++0x07
|
|
line.long 0x0 "PINCTRL66,Pin 66 Control Register"
|
|
bitfld.long 0x0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x4 "PINCTRL67,Pin 67 Control Register"
|
|
bitfld.long 0x4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
sif cpu()!="DM8147DSP"&&cpu()!="DM8148DSP"
|
|
group.long 0x90C++0x313
|
|
line.long 0x0 "PINCTRL68,Pin 68 Control Register"
|
|
bitfld.long 0x0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x4 "PINCTRL69,Pin 69 Control Register"
|
|
bitfld.long 0x4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x8 "PINCTRL70,Pin 70 Control Register"
|
|
bitfld.long 0x8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xC "PINCTRL71,Pin 71 Control Register"
|
|
bitfld.long 0xC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x10 "PINCTRL72,Pin 72 Control Register"
|
|
bitfld.long 0x10 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x10 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x10 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x14 "PINCTRL73,Pin 73 Control Register"
|
|
bitfld.long 0x14 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x14 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x14 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x18 "PINCTRL74,Pin 74 Control Register"
|
|
bitfld.long 0x18 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x18 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x18 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1C "PINCTRL75,Pin 75 Control Register"
|
|
bitfld.long 0x1C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x20 "PINCTRL76,Pin 76 Control Register"
|
|
bitfld.long 0x20 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x20 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x20 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x24 "PINCTRL77,Pin 77 Control Register"
|
|
bitfld.long 0x24 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x24 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x24 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x28 "PINCTRL78,Pin 78 Control Register"
|
|
bitfld.long 0x28 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x28 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x28 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2C "PINCTRL79,Pin 79 Control Register"
|
|
bitfld.long 0x2C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x30 "PINCTRL80,Pin 80 Control Register"
|
|
bitfld.long 0x30 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x30 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x30 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x34 "PINCTRL81,Pin 81 Control Register"
|
|
bitfld.long 0x34 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x34 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x34 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x38 "PINCTRL82,Pin 82 Control Register"
|
|
bitfld.long 0x38 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x38 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x38 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x3C "PINCTRL83,Pin 83 Control Register"
|
|
bitfld.long 0x3C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x3C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x40 "PINCTRL84,Pin 84 Control Register"
|
|
bitfld.long 0x40 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x40 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x40 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x44 "PINCTRL85,Pin 85 Control Register"
|
|
bitfld.long 0x44 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x44 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x44 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x48 "PINCTRL86,Pin 86 Control Register"
|
|
bitfld.long 0x48 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x48 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x48 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x4C "PINCTRL87,Pin 87 Control Register"
|
|
bitfld.long 0x4C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x4C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x50 "PINCTRL88,Pin 88 Control Register"
|
|
bitfld.long 0x50 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x50 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x50 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x54 "PINCTRL89,Pin 89 Control Register"
|
|
bitfld.long 0x54 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x54 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x54 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x58 "PINCTRL90,Pin 90 Control Register"
|
|
bitfld.long 0x58 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x58 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x58 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x5C "PINCTRL91,Pin 91 Control Register"
|
|
bitfld.long 0x5C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x5C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x60 "PINCTRL92,Pin 92 Control Register"
|
|
bitfld.long 0x60 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x60 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x60 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x64 "PINCTRL93,Pin 93 Control Register"
|
|
bitfld.long 0x64 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x64 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x64 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x68 "PINCTRL94,Pin 94 Control Register"
|
|
bitfld.long 0x68 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x68 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x68 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x6C "PINCTRL95,Pin 95 Control Register"
|
|
bitfld.long 0x6C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x6C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x70 "PINCTRL96,Pin 96 Control Register"
|
|
bitfld.long 0x70 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x70 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x70 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x74 "PINCTRL97,Pin 97 Control Register"
|
|
bitfld.long 0x74 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x74 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x74 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x78 "PINCTRL98,Pin 98 Control Register"
|
|
bitfld.long 0x78 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x78 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x78 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x7C "PINCTRL99,Pin 99 Control Register"
|
|
bitfld.long 0x7C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x7C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x80 "PINCTRL100,Pin 100 Control Register"
|
|
bitfld.long 0x80 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x80 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x80 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x84 "PINCTRL101,Pin 101 Control Register"
|
|
bitfld.long 0x84 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x84 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x84 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x88 "PINCTRL102,Pin 102 Control Register"
|
|
bitfld.long 0x88 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x88 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x88 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x8C "PINCTRL103,Pin 103 Control Register"
|
|
bitfld.long 0x8C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x8C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x90 "PINCTRL104,Pin 104 Control Register"
|
|
bitfld.long 0x90 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x90 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x90 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x94 "PINCTRL105,Pin 105 Control Register"
|
|
bitfld.long 0x94 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x94 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x94 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x98 "PINCTRL106,Pin 106 Control Register"
|
|
bitfld.long 0x98 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x98 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x98 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x9C "PINCTRL107,Pin 107 Control Register"
|
|
bitfld.long 0x9C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x9C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xA0 "PINCTRL108,Pin 108 Control Register"
|
|
bitfld.long 0xA0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xA0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xA4 "PINCTRL109,Pin 109 Control Register"
|
|
bitfld.long 0xA4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xA4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xA8 "PINCTRL110,Pin 110 Control Register"
|
|
bitfld.long 0xA8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xA8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xAC "PINCTRL111,Pin 111 Control Register"
|
|
bitfld.long 0xAC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xAC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xB0 "PINCTRL112,Pin 112 Control Register"
|
|
bitfld.long 0xB0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xB0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xB4 "PINCTRL113,Pin 113 Control Register"
|
|
bitfld.long 0xB4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xB4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xB8 "PINCTRL114,Pin 114 Control Register"
|
|
bitfld.long 0xB8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xB8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xBC "PINCTRL115,Pin 115 Control Register"
|
|
bitfld.long 0xBC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xBC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xC0 "PINCTRL116,Pin 116 Control Register"
|
|
bitfld.long 0xC0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xC0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xC4 "PINCTRL117,Pin 117 Control Register"
|
|
bitfld.long 0xC4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xC4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xC8 "PINCTRL118,Pin 118 Control Register"
|
|
bitfld.long 0xC8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xC8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xCC "PINCTRL119,Pin 119 Control Register"
|
|
bitfld.long 0xCC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xCC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xD0 "PINCTRL120,Pin 120 Control Register"
|
|
bitfld.long 0xD0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xD0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xD4 "PINCTRL121,Pin 121 Control Register"
|
|
bitfld.long 0xD4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xD4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xD8 "PINCTRL122,Pin 122 Control Register"
|
|
bitfld.long 0xD8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xD8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xDC "PINCTRL123,Pin 123 Control Register"
|
|
bitfld.long 0xDC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xDC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xE0 "PINCTRL124,Pin 124 Control Register"
|
|
bitfld.long 0xE0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xE0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xE4 "PINCTRL125,Pin 125 Control Register"
|
|
bitfld.long 0xE4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xE4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xE8 "PINCTRL126,Pin 126 Control Register"
|
|
bitfld.long 0xE8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xE8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xEC "PINCTRL127,Pin 127 Control Register"
|
|
bitfld.long 0xEC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xEC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xF0 "PINCTRL128,Pin 128 Control Register"
|
|
bitfld.long 0xF0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xF0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xF0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xF4 "PINCTRL129,Pin 129 Control Register"
|
|
bitfld.long 0xF4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xF4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xF4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xF8 "PINCTRL130,Pin 130 Control Register"
|
|
bitfld.long 0xF8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xF8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xF8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xFC "PINCTRL131,Pin 131 Control Register"
|
|
bitfld.long 0xFC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xFC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xFC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x100 "PINCTRL132,Pin 132 Control Register"
|
|
bitfld.long 0x100 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x100 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x100 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x104 "PINCTRL133,Pin 133 Control Register"
|
|
bitfld.long 0x104 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x104 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x104 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x108 "PINCTRL134,Pin 134 Control Register"
|
|
bitfld.long 0x108 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x108 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x108 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x10C "PINCTRL135,Pin 135 Control Register"
|
|
bitfld.long 0x10C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x10C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x10C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x110 "PINCTRL136,Pin 136 Control Register"
|
|
bitfld.long 0x110 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x110 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x110 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x114 "PINCTRL137,Pin 137 Control Register"
|
|
bitfld.long 0x114 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x114 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x114 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x118 "PINCTRL138,Pin 138 Control Register"
|
|
bitfld.long 0x118 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x118 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x118 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x11C "PINCTRL139,Pin 139 Control Register"
|
|
bitfld.long 0x11C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x11C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x11C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x120 "PINCTRL140,Pin 140 Control Register"
|
|
bitfld.long 0x120 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x120 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x120 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x124 "PINCTRL141,Pin 141 Control Register"
|
|
bitfld.long 0x124 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x124 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x124 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x128 "PINCTRL142,Pin 142 Control Register"
|
|
bitfld.long 0x128 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x128 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x128 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x12C "PINCTRL143,Pin 143 Control Register"
|
|
bitfld.long 0x12C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x12C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x12C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x130 "PINCTRL144,Pin 144 Control Register"
|
|
bitfld.long 0x130 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x130 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x130 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x134 "PINCTRL145,Pin 145 Control Register"
|
|
bitfld.long 0x134 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x134 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x134 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x138 "PINCTRL146,Pin 146 Control Register"
|
|
bitfld.long 0x138 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x138 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x138 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x13C "PINCTRL147,Pin 147 Control Register"
|
|
bitfld.long 0x13C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x13C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x13C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x140 "PINCTRL148,Pin 148 Control Register"
|
|
bitfld.long 0x140 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x140 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x140 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x144 "PINCTRL149,Pin 149 Control Register"
|
|
bitfld.long 0x144 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x144 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x144 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x148 "PINCTRL150,Pin 150 Control Register"
|
|
bitfld.long 0x148 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x148 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x148 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x14C "PINCTRL151,Pin 151 Control Register"
|
|
bitfld.long 0x14C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x14C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x14C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x150 "PINCTRL152,Pin 152 Control Register"
|
|
bitfld.long 0x150 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x150 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x150 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x154 "PINCTRL153,Pin 153 Control Register"
|
|
bitfld.long 0x154 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x154 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x154 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x158 "PINCTRL154,Pin 154 Control Register"
|
|
bitfld.long 0x158 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x158 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x158 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x15C "PINCTRL155,Pin 155 Control Register"
|
|
bitfld.long 0x15C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x15C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x15C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x160 "PINCTRL156,Pin 156 Control Register"
|
|
bitfld.long 0x160 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x160 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x160 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x164 "PINCTRL157,Pin 157 Control Register"
|
|
bitfld.long 0x164 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x164 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x164 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x168 "PINCTRL158,Pin 158 Control Register"
|
|
bitfld.long 0x168 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x168 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x168 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x16C "PINCTRL159,Pin 159 Control Register"
|
|
bitfld.long 0x16C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x16C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x16C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x170 "PINCTRL160,Pin 160 Control Register"
|
|
bitfld.long 0x170 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x170 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x170 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x174 "PINCTRL161,Pin 161 Control Register"
|
|
bitfld.long 0x174 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x174 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x174 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x178 "PINCTRL162,Pin 162 Control Register"
|
|
bitfld.long 0x178 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x178 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x178 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x17C "PINCTRL163,Pin 163 Control Register"
|
|
bitfld.long 0x17C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x17C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x17C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x180 "PINCTRL164,Pin 164 Control Register"
|
|
bitfld.long 0x180 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x180 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x180 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x184 "PINCTRL165,Pin 165 Control Register"
|
|
bitfld.long 0x184 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x184 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x184 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x188 "PINCTRL166,Pin 166 Control Register"
|
|
bitfld.long 0x188 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x188 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x188 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x18C "PINCTRL167,Pin 167 Control Register"
|
|
bitfld.long 0x18C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x18C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x18C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x190 "PINCTRL168,Pin 168 Control Register"
|
|
bitfld.long 0x190 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x190 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x190 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x194 "PINCTRL169,Pin 169 Control Register"
|
|
bitfld.long 0x194 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x194 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x194 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x198 "PINCTRL170,Pin 170 Control Register"
|
|
bitfld.long 0x198 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x198 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x198 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x19C "PINCTRL171,Pin 171 Control Register"
|
|
bitfld.long 0x19C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x19C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x19C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1A0 "PINCTRL172,Pin 172 Control Register"
|
|
bitfld.long 0x1A0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1A0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1A0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1A4 "PINCTRL173,Pin 173 Control Register"
|
|
bitfld.long 0x1A4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1A4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1A4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1A8 "PINCTRL174,Pin 174 Control Register"
|
|
bitfld.long 0x1A8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1A8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1A8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1AC "PINCTRL175,Pin 175 Control Register"
|
|
bitfld.long 0x1AC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1AC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1AC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1B0 "PINCTRL176,Pin 176 Control Register"
|
|
bitfld.long 0x1B0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1B0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1B0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1B4 "PINCTRL177,Pin 177 Control Register"
|
|
bitfld.long 0x1B4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1B4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1B4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1B8 "PINCTRL178,Pin 178 Control Register"
|
|
bitfld.long 0x1B8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1B8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1B8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1BC "PINCTRL179,Pin 179 Control Register"
|
|
bitfld.long 0x1BC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1BC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1BC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1C0 "PINCTRL180,Pin 180 Control Register"
|
|
bitfld.long 0x1C0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1C0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1C0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1C4 "PINCTRL181,Pin 181 Control Register"
|
|
bitfld.long 0x1C4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1C4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1C4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1C8 "PINCTRL182,Pin 182 Control Register"
|
|
bitfld.long 0x1C8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1C8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1C8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1CC "PINCTRL183,Pin 183 Control Register"
|
|
bitfld.long 0x1CC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1CC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1CC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1D0 "PINCTRL184,Pin 184 Control Register"
|
|
bitfld.long 0x1D0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1D0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1D0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1D4 "PINCTRL185,Pin 185 Control Register"
|
|
bitfld.long 0x1D4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1D4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1D4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1D8 "PINCTRL186,Pin 186 Control Register"
|
|
bitfld.long 0x1D8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1D8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1D8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1DC "PINCTRL187,Pin 187 Control Register"
|
|
bitfld.long 0x1DC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1DC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1DC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1E0 "PINCTRL188,Pin 188 Control Register"
|
|
bitfld.long 0x1E0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1E0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1E0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1E4 "PINCTRL189,Pin 189 Control Register"
|
|
bitfld.long 0x1E4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1E4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1E4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1E8 "PINCTRL190,Pin 190 Control Register"
|
|
bitfld.long 0x1E8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1E8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1E8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1EC "PINCTRL191,Pin 191 Control Register"
|
|
bitfld.long 0x1EC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1EC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1EC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1F0 "PINCTRL192,Pin 192 Control Register"
|
|
bitfld.long 0x1F0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1F0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1F0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1F4 "PINCTRL193,Pin 193 Control Register"
|
|
bitfld.long 0x1F4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1F4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1F4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1F8 "PINCTRL194,Pin 194 Control Register"
|
|
bitfld.long 0x1F8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1F8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1F8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x1FC "PINCTRL195,Pin 195 Control Register"
|
|
bitfld.long 0x1FC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x1FC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1FC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x200 "PINCTRL196,Pin 196 Control Register"
|
|
bitfld.long 0x200 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x200 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x200 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x204 "PINCTRL197,Pin 197 Control Register"
|
|
bitfld.long 0x204 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x204 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x204 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x208 "PINCTRL198,Pin 198 Control Register"
|
|
bitfld.long 0x208 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x208 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x208 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x20C "PINCTRL199,Pin 199 Control Register"
|
|
bitfld.long 0x20C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x20C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x20C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x210 "PINCTRL200,Pin 200 Control Register"
|
|
bitfld.long 0x210 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x210 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x210 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x214 "PINCTRL201,Pin 201 Control Register"
|
|
bitfld.long 0x214 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x214 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x214 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x218 "PINCTRL202,Pin 202 Control Register"
|
|
bitfld.long 0x218 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x218 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x218 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x21C "PINCTRL203,Pin 203 Control Register"
|
|
bitfld.long 0x21C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x21C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x21C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x220 "PINCTRL204,Pin 204 Control Register"
|
|
bitfld.long 0x220 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x220 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x220 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x224 "PINCTRL205,Pin 205 Control Register"
|
|
bitfld.long 0x224 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x224 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x224 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x228 "PINCTRL206,Pin 206 Control Register"
|
|
bitfld.long 0x228 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x228 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x228 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x22C "PINCTRL207,Pin 207 Control Register"
|
|
bitfld.long 0x22C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x22C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x22C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x230 "PINCTRL208,Pin 208 Control Register"
|
|
bitfld.long 0x230 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x230 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x230 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x234 "PINCTRL209,Pin 209 Control Register"
|
|
bitfld.long 0x234 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x234 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x234 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x238 "PINCTRL210,Pin 210 Control Register"
|
|
bitfld.long 0x238 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x238 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x238 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x23C "PINCTRL211,Pin 211 Control Register"
|
|
bitfld.long 0x23C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x23C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x23C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x240 "PINCTRL212,Pin 212 Control Register"
|
|
bitfld.long 0x240 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x240 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x240 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x244 "PINCTRL213,Pin 213 Control Register"
|
|
bitfld.long 0x244 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x244 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x244 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x248 "PINCTRL214,Pin 214 Control Register"
|
|
bitfld.long 0x248 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x248 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x248 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x24C "PINCTRL215,Pin 215 Control Register"
|
|
bitfld.long 0x24C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x24C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x24C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x250 "PINCTRL216,Pin 216 Control Register"
|
|
bitfld.long 0x250 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x250 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x250 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x254 "PINCTRL217,Pin 217 Control Register"
|
|
bitfld.long 0x254 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x254 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x254 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x258 "PINCTRL218,Pin 218 Control Register"
|
|
bitfld.long 0x258 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x258 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x258 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x25C "PINCTRL219,Pin 219 Control Register"
|
|
bitfld.long 0x25C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x25C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x25C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x260 "PINCTRL220,Pin 220 Control Register"
|
|
bitfld.long 0x260 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x260 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x260 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x264 "PINCTRL221,Pin 221 Control Register"
|
|
bitfld.long 0x264 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x264 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x264 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x268 "PINCTRL222,Pin 222 Control Register"
|
|
bitfld.long 0x268 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x268 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x268 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x26C "PINCTRL223,Pin 223 Control Register"
|
|
bitfld.long 0x26C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x26C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x26C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x270 "PINCTRL224,Pin 224 Control Register"
|
|
bitfld.long 0x270 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x270 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x270 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x274 "PINCTRL225,Pin 225 Control Register"
|
|
bitfld.long 0x274 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x274 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x274 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x278 "PINCTRL226,Pin 226 Control Register"
|
|
bitfld.long 0x278 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x278 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x278 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x27C "PINCTRL227,Pin 227 Control Register"
|
|
bitfld.long 0x27C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x27C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x27C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x280 "PINCTRL228,Pin 228 Control Register"
|
|
bitfld.long 0x280 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x280 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x280 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x284 "PINCTRL229,Pin 229 Control Register"
|
|
bitfld.long 0x284 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x284 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x284 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x288 "PINCTRL230,Pin 230 Control Register"
|
|
bitfld.long 0x288 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x288 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x288 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x28C "PINCTRL231,Pin 231 Control Register"
|
|
bitfld.long 0x28C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x28C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x28C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x290 "PINCTRL232,Pin 232 Control Register"
|
|
bitfld.long 0x290 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x290 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x290 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x294 "PINCTRL233,Pin 233 Control Register"
|
|
bitfld.long 0x294 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x294 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x294 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x298 "PINCTRL234,Pin 234 Control Register"
|
|
bitfld.long 0x298 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x298 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x298 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x29C "PINCTRL235,Pin 235 Control Register"
|
|
bitfld.long 0x29C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x29C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x29C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2A0 "PINCTRL236,Pin 236 Control Register"
|
|
bitfld.long 0x2A0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2A0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2A0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2A4 "PINCTRL237,Pin 237 Control Register"
|
|
bitfld.long 0x2A4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2A4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2A4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2A8 "PINCTRL238,Pin 238 Control Register"
|
|
bitfld.long 0x2A8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2A8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2A8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2AC "PINCTRL239,Pin 239 Control Register"
|
|
bitfld.long 0x2AC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2AC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2AC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2B0 "PINCTRL240,Pin 240 Control Register"
|
|
bitfld.long 0x2B0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2B0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2B0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2B4 "PINCTRL241,Pin 241 Control Register"
|
|
bitfld.long 0x2B4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2B4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2B4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2B8 "PINCTRL242,Pin 242 Control Register"
|
|
bitfld.long 0x2B8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2B8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2B8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2BC "PINCTRL243,Pin 243 Control Register"
|
|
bitfld.long 0x2BC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2BC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2BC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2C0 "PINCTRL244,Pin 244 Control Register"
|
|
bitfld.long 0x2C0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2C0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2C0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2C4 "PINCTRL245,Pin 245 Control Register"
|
|
bitfld.long 0x2C4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2C4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2C4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2C8 "PINCTRL246,Pin 246 Control Register"
|
|
bitfld.long 0x2C8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2C8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2C8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2CC "PINCTRL247,Pin 247 Control Register"
|
|
bitfld.long 0x2CC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2CC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2CC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2D0 "PINCTRL248,Pin 248 Control Register"
|
|
bitfld.long 0x2D0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2D0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2D0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2D4 "PINCTRL249,Pin 249 Control Register"
|
|
bitfld.long 0x2D4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2D4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2D4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2D8 "PINCTRL250,Pin 250 Control Register"
|
|
bitfld.long 0x2D8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2D8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2D8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2DC "PINCTRL251,Pin 251 Control Register"
|
|
bitfld.long 0x2DC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2DC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2DC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2E0 "PINCTRL252,Pin 252 Control Register"
|
|
bitfld.long 0x2E0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2E0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2E0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2E4 "PINCTRL253,Pin 253 Control Register"
|
|
bitfld.long 0x2E4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2E4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2E4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2E8 "PINCTRL254,Pin 254 Control Register"
|
|
bitfld.long 0x2E8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2E8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2E8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2EC "PINCTRL255,Pin 255 Control Register"
|
|
bitfld.long 0x2EC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2EC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2EC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2F0 "PINCTRL256,Pin 256 Control Register"
|
|
bitfld.long 0x2F0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2F0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2F0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2F4 "PINCTRL257,Pin 257 Control Register"
|
|
bitfld.long 0x2F4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2F4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2F4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2F8 "PINCTRL258,Pin 258 Control Register"
|
|
bitfld.long 0x2F8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2F8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2F8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x2FC "PINCTRL259,Pin 259 Control Register"
|
|
bitfld.long 0x2FC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x2FC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x2FC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x300 "PINCTRL260,Pin 260 Control Register"
|
|
bitfld.long 0x300 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x300 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x300 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x304 "PINCTRL261,Pin 261 Control Register"
|
|
bitfld.long 0x304 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x304 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x304 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x308 "PINCTRL262,Pin 262 Control Register"
|
|
bitfld.long 0x308 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x308 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x308 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x30C "PINCTRL263,Pin 263 Control Register"
|
|
bitfld.long 0x30C 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x30C 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x30C 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x310 "PINCTRL264,Pin 264 Control Register"
|
|
bitfld.long 0x310 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x310 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x310 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
endif
|
|
sif cpu()!="DM8147DSP"&&cpu()!="DM8148DSP"
|
|
group.long 0xC20++0x13
|
|
line.long 0x0 "PINCTRL265,Pin 265 Control Register"
|
|
bitfld.long 0x0 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x0 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x4 "PINCTRL266,Pin 266 Control Register"
|
|
bitfld.long 0x4 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x4 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x8 "PINCTRL267,Pin 267 Control Register"
|
|
bitfld.long 0x8 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x8 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x8 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0xC "PINCTRL268,Pin 268 Control Register"
|
|
bitfld.long 0xC 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0xC 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xC 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
line.long 0x10 "PINCTRL269,Pin 269 Control Register"
|
|
bitfld.long 0x10 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x10 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x10 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
endif
|
|
group.long 0xC34++0x03
|
|
line.long 0x00 "PINCTRL270,Pin 270 Control Register"
|
|
bitfld.long 0x00 17. " PULLTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup"
|
|
bitfld.long 0x00 16. " PULLUDEN ,Pad Pullup / Pulldown Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MUXMODE ,Pad Functional Signal Mux Select"
|
|
tree.end
|
|
width 19.
|
|
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
|
|
rgroup.long 0xe00++0x3
|
|
line.long 0x00 "CQDETECT_STATUS,CQDETECT STATUS Register"
|
|
bitfld.long 0x00 10. " CQM ,IO group M voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 9. " CQL ,IO group L voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 8. " CQI ,IO group I voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 7. " CQH ,IO group H voltage mode" "1.8V,3.3V"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CQG ,IO group G voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 5. " CQF ,IO group F voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 4. " CQE ,IO group E voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 3. " CQD ,IO group D voltage mode" "1.8V,3.3V"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CQC ,IO group C voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 1. " CQB ,IO group B voltage mode" "1.8V,3.3V"
|
|
bitfld.long 0x00 0. " CQA ,IO group A voltage mode" "1.8V,3.3V"
|
|
group.long 0xe04++0x13
|
|
line.long 0x00 "DDR0_IO_CTRL,DDR0 IO Control Register"
|
|
bitfld.long 0x00 31. " DDR3_RST_DEF_VAL ,DDR3 reset default value" "0,1"
|
|
bitfld.long 0x00 30. " DDR_WUCLK_DISABLE ,Slow clock to WUCLKIN and ISOCLKIN of DDR0 and DDR1 emif SS and I/O's disable" "No,Yes"
|
|
bitfld.long 0x00 28. " MDDR_SEL ,PHY to work in mDDR mode select" "Low,High"
|
|
bitfld.long 0x00 26.--27. " CKE_PULL ,Pull of CKE pin select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " DATA_PULL ,Pull of data pins select" "0,1,2,3"
|
|
bitfld.long 0x00 19.--20. " CS_SLEW ,Slew rate of CS pins select" "0,1,2,3"
|
|
bitfld.long 0x00 16.--18. " CS_IMPEDENCE ,Impedence of chip select pins select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11.--12. " CMD_SLEW ,Slew rate of command/address pins select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CMD_IMPEDENCE ,Impedence of command/address pins select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " DATA_SLEW ,Slew rate of data pins select" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " DATA_IMPEDENCE ,Impedence of data pins select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "DDR1_IO_CTRL,DDR1 IO Control Register"
|
|
bitfld.long 0x04 31. " DDR3_RST_DEF_VAL ,DDR3 reset default value" "0,1"
|
|
bitfld.long 0x04 28. " MDDR_SEL ,PHY to work in mDDR mode select" "Low,High"
|
|
bitfld.long 0x04 26.--27. " CKE_PULL ,Pull of CKE pin select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 24.--25. " DATA_PULL ,Pull of data pins select" "0,1,2,3"
|
|
bitfld.long 0x04 19.--20. " CS_SLEW ,Slew rate of CS pins select" "0,1,2,3"
|
|
bitfld.long 0x04 16.--18. " CS_IMPEDENCE ,Impedence of chip select pins select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 11.--12. " CMD_SLEW ,Slew rate of command/address pins select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " CMD_IMPEDENCE ,Impedence of command/address pins select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 3.--4. " DATA_SLEW ,Slew rate of data pins select" "0,1,2,3"
|
|
bitfld.long 0x04 0.--2. " DATA_IMPEDENCE ,Impedence of data pins select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "VTP0_CTRL,VTP0 Control Register"
|
|
hexmask.long.byte 0x08 16.--22. 1. " PCIN ,P values from efuse or MMR"
|
|
hexmask.long.byte 0x08 8.--14. 1. " NCIN ,N values from efuse or MMR"
|
|
bitfld.long 0x08 6. " ENABLE ,Active high enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " READY ,Training sequence complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x08 4. " LOCK ,High freeze dynamic update pwrdn controller" "Unlocked,Locked"
|
|
bitfld.long 0x08 1.--3. " FILTER ,Digital filter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0. " CLRZ ,Clear flops and start count again" "No effect,Cleared"
|
|
line.long 0x0c "VTP0_CTRL,VTP0 Control Register"
|
|
hexmask.long.byte 0x0c 16.--22. 1. " PCIN ,P values from efuse or MMR"
|
|
hexmask.long.byte 0x0c 8.--14. 1. " NCIN ,N values from efuse or MMR"
|
|
bitfld.long 0x0c 6. " ENABLE ,Active high enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " READY ,Training sequence complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " LOCK ,High freeze dynamic update pwrdn controller" "Unlocked,Locked"
|
|
bitfld.long 0x0c 1.--3. " FILTER ,Digital filter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 0. " CLRZ ,Clear flops and start count again" "No effect,Cleared"
|
|
line.long 0x10 "VREF_CTRL,VREF Control Register"
|
|
bitfld.long 0x10 11.--12. " DDR1_VREF_CCAP ,Coupling cap for DDR1 select" "0,1,2,3"
|
|
bitfld.long 0x10 9.--10. " DDR1_VREF_TAP ,Int ref for DDR1 select" "0,1,2,3"
|
|
bitfld.long 0x10 8. " DDR1_VREF_EN ,Internal reference enable for DDR1 select" "Disabled,Enabled"
|
|
bitfld.long 0x10 3.--4. " DDR0_VREF_CCAP ,Coupling cap for DDR0 select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x10 1.--2. " DDR0_VREF_TAP ,Int ref for DDR0 select" "0,1,2,3"
|
|
bitfld.long 0x10 0. " DDR0_VREF_EN ,Internal reference enable for DDR0 select" "Disabled,Enabled"
|
|
endif
|
|
width 19.
|
|
group.long 0xE18++0x07
|
|
line.long 0x00 "MLBP_SIG_IO_CTRL,MLBP SIG IO Control Register"
|
|
bitfld.long 0x00 16.--21. " NC_IN ,Efuse trim for Nmos impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " PC_IN ,Efuse trim for Pmos impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 5. " PWRDNRX ,Powerdown receiver" "Not powered down,Powered down"
|
|
bitfld.long 0x00 4. " PWRDNTX ,Powerdown transmitter" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN_EXT_RES ,Internal resistors disable" "No,Yes"
|
|
bitfld.long 0x00 2. " ENLVCMOS ,Enable 2 lvcmos buffers mode" "MLB 6pin,GPIO"
|
|
bitfld.long 0x00 1. " ENN ,Enable padn receiver" "MLB 6pin,GPIO"
|
|
bitfld.long 0x00 0. " ENP ,Enable padp receiver" "MLB 6pin,GPIO"
|
|
line.long 0x04 "MLBP_DAT_IO_CTRL,MLBP DAT IO Control Register"
|
|
bitfld.long 0x04 16.--21. " NC_IN ,Efuse trim for Nmos impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 8.--13. " PC_IN ,Efuse trim for Pmos impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 5. " PWRDNRX ,Powerdown receiver" "Not powered down,Powered down"
|
|
bitfld.long 0x04 4. " PWRDNTX ,Powerdown transmitter" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EN_EXT_RES ,Internal resistors disable" "No,Yes"
|
|
bitfld.long 0x04 2. " ENLVCMOS ,Enable 2 lvcmos buffers mode" "MLB 6pin,GPIO"
|
|
bitfld.long 0x04 1. " ENN ,Enable padn receiver" "MLB 6pin,GPIO"
|
|
bitfld.long 0x04 0. " ENP ,Enable padp receiver" "MLB 6pin,GPIO"
|
|
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
|
|
group.long 0xE20++0x03
|
|
line.long 0x00 "MLBP_CLK_BG_CTRL,MLBP Clock/BG Control Register"
|
|
bitfld.long 0x00 2.--7. " BG_TRIM ,Trim values for MLBP BG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 1. " BG_PWRDN ,Powerdown bandgap for MLBP" "Not powered down,Powered down"
|
|
bitfld.long 0x00 0. " CLK_PWRDN ,Powerdown clock IO for MLBP" "Not powered down,Powered down"
|
|
endif
|
|
group.long 0xE24++0x03
|
|
line.long 0x00 "SERDES_REFCLK_CTL,SerDes Refclk Powerdown Control Register"
|
|
bitfld.long 0x00 1. " PWRDN_SE ,Powerdown both refclkp/n single ended receiver" "Not powered down,Powered down"
|
|
bitfld.long 0x00 0. " PWRDN ,Powerdown both refclkp/n receiver" "Not powered down,Powered down"
|
|
width 18.
|
|
tree "DSP Interrupt Mux"
|
|
group.long 0xf00++0x53
|
|
line.long 0x0 "DSP_INTMUX_15_18,DSP Interrupt Mux Register for Interrupt 15 to 18"
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|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
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bitfld.long 0x0 24.--28. " INT_MUX_18 ,Interrupt mux for DSP's interrupt number 18" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
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bitfld.long 0x0 16.--20. " INT_MUX_17 ,Interrupt mux for DSP's interrupt number 17" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
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bitfld.long 0x0 8.--12. " INT_MUX_16 ,Interrupt mux for DSP's interrupt number 16" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
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|
bitfld.long 0x0 0.--4. " INT_MUX_15 ,Interrupt mux for DSP's interrupt number 15" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
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|
else
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|
bitfld.long 0x0 24.--28. " INT_MUX_18 ,Interrupt mux for DSP's interrupt number 18" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
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bitfld.long 0x0 16.--20. " INT_MUX_17 ,Interrupt mux for DSP's interrupt number 17" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
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|
bitfld.long 0x0 8.--12. " INT_MUX_16 ,Interrupt mux for DSP's interrupt number 16" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
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bitfld.long 0x0 0.--4. " INT_MUX_15 ,Interrupt mux for DSP's interrupt number 15" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
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|
endif
|
|
line.long 0x4 "DSP_INTMUX_19_22,DSP Interrupt Mux Register for Interrupt 19 to 22"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
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|
bitfld.long 0x4 24.--28. " INT_MUX_22 ,Interrupt mux for DSP's interrupt number 22" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
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|
bitfld.long 0x4 16.--20. " INT_MUX_21 ,Interrupt mux for DSP's interrupt number 21" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
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|
bitfld.long 0x4 8.--12. " INT_MUX_20 ,Interrupt mux for DSP's interrupt number 20" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
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bitfld.long 0x4 0.--4. " INT_MUX_19 ,Interrupt mux for DSP's interrupt number 19" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x4 24.--28. " INT_MUX_22 ,Interrupt mux for DSP's interrupt number 22" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x4 16.--20. " INT_MUX_21 ,Interrupt mux for DSP's interrupt number 21" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x4 8.--12. " INT_MUX_20 ,Interrupt mux for DSP's interrupt number 20" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x4 0.--4. " INT_MUX_19 ,Interrupt mux for DSP's interrupt number 19" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x8 "DSP_INTMUX_23_26,DSP Interrupt Mux Register for Interrupt 23 to 26"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x8 24.--28. " INT_MUX_26 ,Interrupt mux for DSP's interrupt number 26" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
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|
bitfld.long 0x8 16.--20. " INT_MUX_25 ,Interrupt mux for DSP's interrupt number 25" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x8 8.--12. " INT_MUX_24 ,Interrupt mux for DSP's interrupt number 24" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
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|
bitfld.long 0x8 0.--4. " INT_MUX_23 ,Interrupt mux for DSP's interrupt number 23" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x8 24.--28. " INT_MUX_26 ,Interrupt mux for DSP's interrupt number 26" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x8 16.--20. " INT_MUX_25 ,Interrupt mux for DSP's interrupt number 25" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x8 8.--12. " INT_MUX_24 ,Interrupt mux for DSP's interrupt number 24" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x8 0.--4. " INT_MUX_23 ,Interrupt mux for DSP's interrupt number 23" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0xC "DSP_INTMUX_27_30,DSP Interrupt Mux Register for Interrupt 27 to 30"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0xC 24.--28. " INT_MUX_30 ,Interrupt mux for DSP's interrupt number 30" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0xC 16.--20. " INT_MUX_29 ,Interrupt mux for DSP's interrupt number 29" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0xC 8.--12. " INT_MUX_28 ,Interrupt mux for DSP's interrupt number 28" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0xC 0.--4. " INT_MUX_27 ,Interrupt mux for DSP's interrupt number 27" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0xC 24.--28. " INT_MUX_30 ,Interrupt mux for DSP's interrupt number 30" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0xC 16.--20. " INT_MUX_29 ,Interrupt mux for DSP's interrupt number 29" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0xC 8.--12. " INT_MUX_28 ,Interrupt mux for DSP's interrupt number 28" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0xC 0.--4. " INT_MUX_27 ,Interrupt mux for DSP's interrupt number 27" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x10 "DSP_INTMUX_31_34,DSP Interrupt Mux Register for Interrupt 31 to 34"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x10 24.--28. " INT_MUX_34 ,Interrupt mux for DSP's interrupt number 34" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x10 16.--20. " INT_MUX_33 ,Interrupt mux for DSP's interrupt number 33" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x10 8.--12. " INT_MUX_32 ,Interrupt mux for DSP's interrupt number 32" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x10 0.--4. " INT_MUX_31 ,Interrupt mux for DSP's interrupt number 31" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x10 24.--28. " INT_MUX_34 ,Interrupt mux for DSP's interrupt number 34" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x10 16.--20. " INT_MUX_33 ,Interrupt mux for DSP's interrupt number 33" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x10 8.--12. " INT_MUX_32 ,Interrupt mux for DSP's interrupt number 32" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x10 0.--4. " INT_MUX_31 ,Interrupt mux for DSP's interrupt number 31" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x14 "DSP_INTMUX_35_38,DSP Interrupt Mux Register for Interrupt 35 to 38"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x14 24.--28. " INT_MUX_38 ,Interrupt mux for DSP's interrupt number 38" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x14 16.--20. " INT_MUX_37 ,Interrupt mux for DSP's interrupt number 37" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x14 8.--12. " INT_MUX_36 ,Interrupt mux for DSP's interrupt number 36" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x14 0.--4. " INT_MUX_35 ,Interrupt mux for DSP's interrupt number 35" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x14 24.--28. " INT_MUX_38 ,Interrupt mux for DSP's interrupt number 38" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x14 16.--20. " INT_MUX_37 ,Interrupt mux for DSP's interrupt number 37" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x14 8.--12. " INT_MUX_36 ,Interrupt mux for DSP's interrupt number 36" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x14 0.--4. " INT_MUX_35 ,Interrupt mux for DSP's interrupt number 35" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x18 "DSP_INTMUX_39_42,DSP Interrupt Mux Register for Interrupt 39 to 42"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x18 24.--28. " INT_MUX_42 ,Interrupt mux for DSP's interrupt number 42" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x18 16.--20. " INT_MUX_41 ,Interrupt mux for DSP's interrupt number 41" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x18 8.--12. " INT_MUX_40 ,Interrupt mux for DSP's interrupt number 40" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x18 0.--4. " INT_MUX_39 ,Interrupt mux for DSP's interrupt number 39" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x18 24.--28. " INT_MUX_42 ,Interrupt mux for DSP's interrupt number 42" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x18 16.--20. " INT_MUX_41 ,Interrupt mux for DSP's interrupt number 41" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x18 8.--12. " INT_MUX_40 ,Interrupt mux for DSP's interrupt number 40" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x18 0.--4. " INT_MUX_39 ,Interrupt mux for DSP's interrupt number 39" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x1C "DSP_INTMUX_43_46,DSP Interrupt Mux Register for Interrupt 43 to 46"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x1C 24.--28. " INT_MUX_46 ,Interrupt mux for DSP's interrupt number 46" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x1C 16.--20. " INT_MUX_45 ,Interrupt mux for DSP's interrupt number 45" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x1C 8.--12. " INT_MUX_44 ,Interrupt mux for DSP's interrupt number 44" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x1C 0.--4. " INT_MUX_43 ,Interrupt mux for DSP's interrupt number 43" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x1C 24.--28. " INT_MUX_46 ,Interrupt mux for DSP's interrupt number 46" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x1C 16.--20. " INT_MUX_45 ,Interrupt mux for DSP's interrupt number 45" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x1C 8.--12. " INT_MUX_44 ,Interrupt mux for DSP's interrupt number 44" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x1C 0.--4. " INT_MUX_43 ,Interrupt mux for DSP's interrupt number 43" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x20 "DSP_INTMUX_47_50,DSP Interrupt Mux Register for Interrupt 47 to 50"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x20 24.--28. " INT_MUX_50 ,Interrupt mux for DSP's interrupt number 50" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x20 16.--20. " INT_MUX_49 ,Interrupt mux for DSP's interrupt number 49" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x20 8.--12. " INT_MUX_48 ,Interrupt mux for DSP's interrupt number 48" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x20 0.--4. " INT_MUX_47 ,Interrupt mux for DSP's interrupt number 47" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x20 24.--28. " INT_MUX_50 ,Interrupt mux for DSP's interrupt number 50" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x20 16.--20. " INT_MUX_49 ,Interrupt mux for DSP's interrupt number 49" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x20 8.--12. " INT_MUX_48 ,Interrupt mux for DSP's interrupt number 48" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x20 0.--4. " INT_MUX_47 ,Interrupt mux for DSP's interrupt number 47" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x24 "DSP_INTMUX_51_54,DSP Interrupt Mux Register for Interrupt 51 to 54"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x24 24.--28. " INT_MUX_54 ,Interrupt mux for DSP's interrupt number 54" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x24 16.--20. " INT_MUX_53 ,Interrupt mux for DSP's interrupt number 53" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x24 8.--12. " INT_MUX_52 ,Interrupt mux for DSP's interrupt number 52" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x24 0.--4. " INT_MUX_51 ,Interrupt mux for DSP's interrupt number 51" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x24 24.--28. " INT_MUX_54 ,Interrupt mux for DSP's interrupt number 54" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x24 16.--20. " INT_MUX_53 ,Interrupt mux for DSP's interrupt number 53" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x24 8.--12. " INT_MUX_52 ,Interrupt mux for DSP's interrupt number 52" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x24 0.--4. " INT_MUX_51 ,Interrupt mux for DSP's interrupt number 51" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x28 "DSP_INTMUX_55_58,DSP Interrupt Mux Register for Interrupt 55 to 58"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x28 24.--28. " INT_MUX_58 ,Interrupt mux for DSP's interrupt number 58" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x28 16.--20. " INT_MUX_57 ,Interrupt mux for DSP's interrupt number 57" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x28 8.--12. " INT_MUX_56 ,Interrupt mux for DSP's interrupt number 56" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x28 0.--4. " INT_MUX_55 ,Interrupt mux for DSP's interrupt number 55" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x28 24.--28. " INT_MUX_58 ,Interrupt mux for DSP's interrupt number 58" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x28 16.--20. " INT_MUX_57 ,Interrupt mux for DSP's interrupt number 57" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x28 8.--12. " INT_MUX_56 ,Interrupt mux for DSP's interrupt number 56" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x28 0.--4. " INT_MUX_55 ,Interrupt mux for DSP's interrupt number 55" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x2C "DSP_INTMUX_59_62,DSP Interrupt Mux Register for Interrupt 59 to 62"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x2C 24.--28. " INT_MUX_62 ,Interrupt mux for DSP's interrupt number 62" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x2C 16.--20. " INT_MUX_61 ,Interrupt mux for DSP's interrupt number 61" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x2C 8.--12. " INT_MUX_60 ,Interrupt mux for DSP's interrupt number 60" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
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|
bitfld.long 0x2C 0.--4. " INT_MUX_59 ,Interrupt mux for DSP's interrupt number 59" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x2C 24.--28. " INT_MUX_62 ,Interrupt mux for DSP's interrupt number 62" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x2C 16.--20. " INT_MUX_61 ,Interrupt mux for DSP's interrupt number 61" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x2C 8.--12. " INT_MUX_60 ,Interrupt mux for DSP's interrupt number 60" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x2C 0.--4. " INT_MUX_59 ,Interrupt mux for DSP's interrupt number 59" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x30 "DSP_INTMUX_63_66,DSP Interrupt Mux Register for Interrupt 63 to 66"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x30 24.--28. " INT_MUX_66 ,Interrupt mux for DSP's interrupt number 66" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x30 16.--20. " INT_MUX_65 ,Interrupt mux for DSP's interrupt number 65" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x30 8.--12. " INT_MUX_64 ,Interrupt mux for DSP's interrupt number 64" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x30 0.--4. " INT_MUX_63 ,Interrupt mux for DSP's interrupt number 63" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x30 24.--28. " INT_MUX_66 ,Interrupt mux for DSP's interrupt number 66" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x30 16.--20. " INT_MUX_65 ,Interrupt mux for DSP's interrupt number 65" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x30 8.--12. " INT_MUX_64 ,Interrupt mux for DSP's interrupt number 64" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x30 0.--4. " INT_MUX_63 ,Interrupt mux for DSP's interrupt number 63" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x34 "DSP_INTMUX_67_70,DSP Interrupt Mux Register for Interrupt 67 to 70"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x34 24.--28. " INT_MUX_70 ,Interrupt mux for DSP's interrupt number 70" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x34 16.--20. " INT_MUX_69 ,Interrupt mux for DSP's interrupt number 69" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x34 8.--12. " INT_MUX_68 ,Interrupt mux for DSP's interrupt number 68" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x34 0.--4. " INT_MUX_67 ,Interrupt mux for DSP's interrupt number 67" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x34 24.--28. " INT_MUX_70 ,Interrupt mux for DSP's interrupt number 70" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x34 16.--20. " INT_MUX_69 ,Interrupt mux for DSP's interrupt number 69" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x34 8.--12. " INT_MUX_68 ,Interrupt mux for DSP's interrupt number 68" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x34 0.--4. " INT_MUX_67 ,Interrupt mux for DSP's interrupt number 67" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x38 "DSP_INTMUX_71_74,DSP Interrupt Mux Register for Interrupt 71 to 74"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x38 24.--28. " INT_MUX_74 ,Interrupt mux for DSP's interrupt number 74" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x38 16.--20. " INT_MUX_73 ,Interrupt mux for DSP's interrupt number 73" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x38 8.--12. " INT_MUX_72 ,Interrupt mux for DSP's interrupt number 72" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x38 0.--4. " INT_MUX_71 ,Interrupt mux for DSP's interrupt number 71" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x38 24.--28. " INT_MUX_74 ,Interrupt mux for DSP's interrupt number 74" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x38 16.--20. " INT_MUX_73 ,Interrupt mux for DSP's interrupt number 73" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x38 8.--12. " INT_MUX_72 ,Interrupt mux for DSP's interrupt number 72" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x38 0.--4. " INT_MUX_71 ,Interrupt mux for DSP's interrupt number 71" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x3C "DSP_INTMUX_75_78,DSP Interrupt Mux Register for Interrupt 75 to 78"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x3C 24.--28. " INT_MUX_78 ,Interrupt mux for DSP's interrupt number 78" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x3C 16.--20. " INT_MUX_77 ,Interrupt mux for DSP's interrupt number 77" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x3C 8.--12. " INT_MUX_76 ,Interrupt mux for DSP's interrupt number 76" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x3C 0.--4. " INT_MUX_75 ,Interrupt mux for DSP's interrupt number 75" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x3C 24.--28. " INT_MUX_78 ,Interrupt mux for DSP's interrupt number 78" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x3C 16.--20. " INT_MUX_77 ,Interrupt mux for DSP's interrupt number 77" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x3C 8.--12. " INT_MUX_76 ,Interrupt mux for DSP's interrupt number 76" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x3C 0.--4. " INT_MUX_75 ,Interrupt mux for DSP's interrupt number 75" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x40 "DSP_INTMUX_79_82,DSP Interrupt Mux Register for Interrupt 79 to 82"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x40 24.--28. " INT_MUX_82 ,Interrupt mux for DSP's interrupt number 82" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x40 16.--20. " INT_MUX_81 ,Interrupt mux for DSP's interrupt number 81" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x40 8.--12. " INT_MUX_80 ,Interrupt mux for DSP's interrupt number 80" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x40 0.--4. " INT_MUX_79 ,Interrupt mux for DSP's interrupt number 79" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x40 24.--28. " INT_MUX_82 ,Interrupt mux for DSP's interrupt number 82" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x40 16.--20. " INT_MUX_81 ,Interrupt mux for DSP's interrupt number 81" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x40 8.--12. " INT_MUX_80 ,Interrupt mux for DSP's interrupt number 80" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x40 0.--4. " INT_MUX_79 ,Interrupt mux for DSP's interrupt number 79" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x44 "DSP_INTMUX_83_86,DSP Interrupt Mux Register for Interrupt 83 to 86"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x44 24.--28. " INT_MUX_86 ,Interrupt mux for DSP's interrupt number 86" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x44 16.--20. " INT_MUX_85 ,Interrupt mux for DSP's interrupt number 85" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x44 8.--12. " INT_MUX_84 ,Interrupt mux for DSP's interrupt number 84" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x44 0.--4. " INT_MUX_83 ,Interrupt mux for DSP's interrupt number 83" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x44 24.--28. " INT_MUX_86 ,Interrupt mux for DSP's interrupt number 86" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x44 16.--20. " INT_MUX_85 ,Interrupt mux for DSP's interrupt number 85" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x44 8.--12. " INT_MUX_84 ,Interrupt mux for DSP's interrupt number 84" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x44 0.--4. " INT_MUX_83 ,Interrupt mux for DSP's interrupt number 83" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x48 "DSP_INTMUX_87_90,DSP Interrupt Mux Register for Interrupt 87 to 90"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x48 24.--28. " INT_MUX_90 ,Interrupt mux for DSP's interrupt number 90" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x48 16.--20. " INT_MUX_89 ,Interrupt mux for DSP's interrupt number 89" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x48 8.--12. " INT_MUX_88 ,Interrupt mux for DSP's interrupt number 88" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x48 0.--4. " INT_MUX_87 ,Interrupt mux for DSP's interrupt number 87" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x48 24.--28. " INT_MUX_90 ,Interrupt mux for DSP's interrupt number 90" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x48 16.--20. " INT_MUX_89 ,Interrupt mux for DSP's interrupt number 89" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x48 8.--12. " INT_MUX_88 ,Interrupt mux for DSP's interrupt number 88" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x48 0.--4. " INT_MUX_87 ,Interrupt mux for DSP's interrupt number 87" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x4C "DSP_INTMUX_91_94,DSP Interrupt Mux Register for Interrupt 91 to 94"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x4C 24.--28. " INT_MUX_94 ,Interrupt mux for DSP's interrupt number 94" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x4C 16.--20. " INT_MUX_93 ,Interrupt mux for DSP's interrupt number 93" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x4C 8.--12. " INT_MUX_92 ,Interrupt mux for DSP's interrupt number 92" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x4C 0.--4. " INT_MUX_91 ,Interrupt mux for DSP's interrupt number 91" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x4C 24.--28. " INT_MUX_94 ,Interrupt mux for DSP's interrupt number 94" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x4C 16.--20. " INT_MUX_93 ,Interrupt mux for DSP's interrupt number 93" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x4C 8.--12. " INT_MUX_92 ,Interrupt mux for DSP's interrupt number 92" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
bitfld.long 0x4C 0.--4. " INT_MUX_91 ,Interrupt mux for DSP's interrupt number 91" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
line.long 0x50 "DSP_INTMUX_95,DSP Interrupt Mux Register for Interrupt 95"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x50 0.--4. " INT_MUX_95 ,Interrupt mux for DSP's interrupt number 95" "Default,DCAN0INT0,DCAN0INT1,DCAN0PARIT,DCAN1INT0,DCAN1INT1,DCAN1PARIT,MLBSYSINT0,MLBSYSINT1,MLBINT,Reserved,L3DEBUG,L3APPINT,EDMA3CC_MPINT,TINT8,WDTINT,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,Reserved,Reserved,DDRERR0,DDRERR1,?..."
|
|
else
|
|
bitfld.long 0x50 0.--4. " INT_MUX_95 ,Interrupt mux for DSP's interrupt number 95" "Line specific,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,SEC_EVNT,L3DEBUG,L3APPINT,EDMAMPERR,Reserved,Reserved,USBSSINT,USBINT0,USBINT1,RTCINT,RTCALARMINT,SMCDINT0,SMCDINT1,DDRERR0,DDRERR1,?..."
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
|
|
width 23.
|
|
tree "MEDIACTL Interrupt Mux"
|
|
group.long 0xf54++0x3b
|
|
line.long 0x0 "MEDIACTL_INTMUX_0_3,MEDIACTL Interrupt Mux Register for Interrupt 0 to 3"
|
|
bitfld.long 0x0 24.--29. " INT_MUX_3 ,Interrupt mux for MEDIACTL's interrupt number 3 " "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
|
|
bitfld.long 0x0 16.--21. " INT_MUX_2 ,Interrupt mux for MEDIACTL's interrupt number 2 " "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
|
|
bitfld.long 0x0 8.--13. " INT_MUX_1 ,Interrupt mux for MEDIACTL's interrupt number 1 " "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
|
|
bitfld.long 0x0 0.--5. " INT_MUX_0 ,Interrupt mux for MEDIACTL's interrupt number 0 " "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
|
|
line.long 0x4 "MEDIACTL_INTMUX_4_7,MEDIACTL Interrupt Mux Register for Interrupt 4 to 7"
|
|
bitfld.long 0x4 24.--29. " INT_MUX_7 ,Interrupt mux for MEDIACTL's interrupt number 7 " "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
|
|
bitfld.long 0x4 16.--21. " INT_MUX_6 ,Interrupt mux for MEDIACTL's interrupt number 6 " "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
|
|
bitfld.long 0x4 8.--13. " INT_MUX_5 ,Interrupt mux for MEDIACTL's interrupt number 5 " "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
|
|
bitfld.long 0x4 0.--5. " INT_MUX_4 ,Interrupt mux for MEDIACTL's interrupt number 4 " "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
|
|
line.long 0x8 "MEDIACTL_INTMUX_8_11,MEDIACTL Interrupt Mux Register for Interrupt 8 to 11"
|
|
bitfld.long 0x8 24.--29. " INT_MUX_11 ,Interrupt mux for MEDIACTL's interrupt number 11" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
|
|
bitfld.long 0x8 16.--21. " INT_MUX_10 ,Interrupt mux for MEDIACTL's interrupt number 10" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x8 8.--13. " INT_MUX_9 ,Interrupt mux for MEDIACTL's interrupt number 9 " "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x8 0.--5. " INT_MUX_8 ,Interrupt mux for MEDIACTL's interrupt number 8 " "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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line.long 0xC "MEDIACTL_INTMUX_12_15,MEDIACTL Interrupt Mux Register for Interrupt 12 to 15"
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bitfld.long 0xC 24.--29. " INT_MUX_15 ,Interrupt mux for MEDIACTL's interrupt number 15" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0xC 16.--21. " INT_MUX_14 ,Interrupt mux for MEDIACTL's interrupt number 14" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0xC 8.--13. " INT_MUX_13 ,Interrupt mux for MEDIACTL's interrupt number 13" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0xC 0.--5. " INT_MUX_12 ,Interrupt mux for MEDIACTL's interrupt number 12" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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line.long 0x10 "MEDIACTL_INTMUX_16_19,MEDIACTL Interrupt Mux Register for Interrupt 16 to 19"
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bitfld.long 0x10 24.--29. " INT_MUX_19 ,Interrupt mux for MEDIACTL's interrupt number 19" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x10 16.--21. " INT_MUX_18 ,Interrupt mux for MEDIACTL's interrupt number 18" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x10 8.--13. " INT_MUX_17 ,Interrupt mux for MEDIACTL's interrupt number 17" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x10 0.--5. " INT_MUX_16 ,Interrupt mux for MEDIACTL's interrupt number 16" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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line.long 0x14 "MEDIACTL_INTMUX_20_23,MEDIACTL Interrupt Mux Register for Interrupt 20 to 23"
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bitfld.long 0x14 24.--29. " INT_MUX_23 ,Interrupt mux for MEDIACTL's interrupt number 23" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x14 16.--21. " INT_MUX_22 ,Interrupt mux for MEDIACTL's interrupt number 22" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x14 8.--13. " INT_MUX_21 ,Interrupt mux for MEDIACTL's interrupt number 21" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x14 0.--5. " INT_MUX_20 ,Interrupt mux for MEDIACTL's interrupt number 20" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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line.long 0x18 "MEDIACTL_INTMUX_24_27,MEDIACTL Interrupt Mux Register for Interrupt 24 to 27"
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bitfld.long 0x18 24.--29. " INT_MUX_27 ,Interrupt mux for MEDIACTL's interrupt number 27" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x18 16.--21. " INT_MUX_26 ,Interrupt mux for MEDIACTL's interrupt number 26" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x18 8.--13. " INT_MUX_25 ,Interrupt mux for MEDIACTL's interrupt number 25" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x18 0.--5. " INT_MUX_24 ,Interrupt mux for MEDIACTL's interrupt number 24" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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line.long 0x1C "MEDIACTL_INTMUX_28_31,MEDIACTL Interrupt Mux Register for Interrupt 28 to 31"
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bitfld.long 0x1C 24.--29. " INT_MUX_31 ,Interrupt mux for MEDIACTL's interrupt number 31" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x1C 16.--21. " INT_MUX_30 ,Interrupt mux for MEDIACTL's interrupt number 30" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x1C 8.--13. " INT_MUX_29 ,Interrupt mux for MEDIACTL's interrupt number 29" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x1C 0.--5. " INT_MUX_28 ,Interrupt mux for MEDIACTL's interrupt number 28" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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line.long 0x20 "MEDIACTL_INTMUX_32_35,MEDIACTL Interrupt Mux Register for Interrupt 32 to 35"
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bitfld.long 0x20 24.--29. " INT_MUX_35 ,Interrupt mux for MEDIACTL's interrupt number 35" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x20 16.--21. " INT_MUX_34 ,Interrupt mux for MEDIACTL's interrupt number 34" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x20 8.--13. " INT_MUX_33 ,Interrupt mux for MEDIACTL's interrupt number 33" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x20 0.--5. " INT_MUX_32 ,Interrupt mux for MEDIACTL's interrupt number 32" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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line.long 0x24 "MEDIACTL_INTMUX_36_39,MEDIACTL Interrupt Mux Register for Interrupt 36 to 39"
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bitfld.long 0x24 24.--29. " INT_MUX_39 ,Interrupt mux for MEDIACTL's interrupt number 39" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x24 16.--21. " INT_MUX_38 ,Interrupt mux for MEDIACTL's interrupt number 38" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x24 8.--13. " INT_MUX_37 ,Interrupt mux for MEDIACTL's interrupt number 37" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x24 0.--5. " INT_MUX_36 ,Interrupt mux for MEDIACTL's interrupt number 36" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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line.long 0x28 "MEDIACTL_INTMUX_40_43,MEDIACTL Interrupt Mux Register for Interrupt 40 to 43"
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bitfld.long 0x28 24.--29. " INT_MUX_43 ,Interrupt mux for MEDIACTL's interrupt number 43" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x28 16.--21. " INT_MUX_42 ,Interrupt mux for MEDIACTL's interrupt number 42" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x28 8.--13. " INT_MUX_41 ,Interrupt mux for MEDIACTL's interrupt number 41" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x28 0.--5. " INT_MUX_40 ,Interrupt mux for MEDIACTL's interrupt number 40" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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line.long 0x2C "MEDIACTL_INTMUX_44_47,MEDIACTL Interrupt Mux Register for Interrupt 44 to 47"
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bitfld.long 0x2C 24.--29. " INT_MUX_47 ,Interrupt mux for MEDIACTL's interrupt number 47" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x2C 16.--21. " INT_MUX_46 ,Interrupt mux for MEDIACTL's interrupt number 46" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x2C 8.--13. " INT_MUX_45 ,Interrupt mux for MEDIACTL's interrupt number 45" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x2C 0.--5. " INT_MUX_44 ,Interrupt mux for MEDIACTL's interrupt number 44" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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line.long 0x30 "MEDIACTL_INTMUX_48_51,MEDIACTL Interrupt Mux Register for Interrupt 48 to 51"
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bitfld.long 0x30 24.--29. " INT_MUX_51 ,Interrupt mux for MEDIACTL's interrupt number 51" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x30 16.--21. " INT_MUX_50 ,Interrupt mux for MEDIACTL's interrupt number 50" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x30 8.--13. " INT_MUX_49 ,Interrupt mux for MEDIACTL's interrupt number 49" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x30 0.--5. " INT_MUX_48 ,Interrupt mux for MEDIACTL's interrupt number 48" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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line.long 0x34 "MEDIACTL_INTMUX_52_55,MEDIACTL Interrupt Mux Register for Interrupt 52 to 55"
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bitfld.long 0x34 24.--29. " INT_MUX_55 ,Interrupt mux for MEDIACTL's interrupt number 55" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x34 16.--21. " INT_MUX_54 ,Interrupt mux for MEDIACTL's interrupt number 54" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x34 8.--13. " INT_MUX_53 ,Interrupt mux for MEDIACTL's interrupt number 53" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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bitfld.long 0x34 0.--5. " INT_MUX_52 ,Interrupt mux for MEDIACTL's interrupt number 52" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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line.long 0x38 "MEDIACTL_INTMUX_56,MEDIACTL Interrupt Mux Register for Interrupt 56"
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bitfld.long 0x38 0.--5. " INT_MUX_56 ,Interrupt mux for MEDIACTL's interrupt number 56" "Line specific,SATAINT,SDINT1,SDINT2,I2CINT2,I2CINT3,GPIOINT3A,GPIOINT3B,GFXINT,UARTINT3,UARTINT4,UARTINT5,FDIF_IRQ1,PCIINT0,PCIINT1,PCIINT2,PCIINT3,DCAN0_INT0,DCAN0_INT1,DCAN1_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,MLB_SYS_INT0,MLB_SYS_INT1,MLB_INT,RTCINT,RTCALARMINT,IDEINTR,MCATXINT2,MCARXINT2,MCBSPINT,GPMCINT,MCATXINT3,MCARXINT3,MCATXINT4,MCARXINT4,MCATXINT5,MCARXINT5,TCERRINT0,TCERRINT1,TCERRINT2,TCERRINT3,SPIINT,SPIINT,SPIINT,SMRFLX_ACTIVE,SMRFLX_HDVICP,?..."
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tree.end
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endif
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sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
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width 22.
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tree "EDMA3CC Event Mux"
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group.long 0xF90++0x3F
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line.long 0x0 "EDMA3CC_EVTMUX_0_3,TPCC Event Mux Register for Event 0 to 3"
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bitfld.long 0x0 24.--28. " EVT_MUX_3 ,Event Mux for TPCC Event number 3 " "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x0 16.--20. " EVT_MUX_2 ,Event Mux for TPCC Event number 2 " "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x0 8.--12. " EVT_MUX_1 ,Event Mux for TPCC Event number 1 " "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x0 0.--4. " EVT_MUX_0 ,Event Mux for TPCC Event number 0 " "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x4 "EDMA3CC_EVTMUX_4_7,TPCC Event Mux Register for Event 4 to 7"
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bitfld.long 0x4 24.--28. " EVT_MUX_7 ,Event Mux for TPCC Event number 7 " "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x4 16.--20. " EVT_MUX_6 ,Event Mux for TPCC Event number 6 " "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x4 8.--12. " EVT_MUX_5 ,Event Mux for TPCC Event number 5 " "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x4 0.--4. " EVT_MUX_4 ,Event Mux for TPCC Event number 4 " "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x8 "EDMA3CC_EVTMUX_8_11,TPCC Event Mux Register for Event 8 to 11"
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bitfld.long 0x8 24.--28. " EVT_MUX_11 ,Event Mux for TPCC Event number 11" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x8 16.--20. " EVT_MUX_10 ,Event Mux for TPCC Event number 10" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x8 8.--12. " EVT_MUX_9 ,Event Mux for TPCC Event number 9 " "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x8 0.--4. " EVT_MUX_8 ,Event Mux for TPCC Event number 8 " "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0xC "EDMA3CC_EVTMUX_12_15,TPCC Event Mux Register for Event 12 to 15"
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bitfld.long 0xC 24.--28. " EVT_MUX_15 ,Event Mux for TPCC Event number 15" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0xC 16.--20. " EVT_MUX_14 ,Event Mux for TPCC Event number 14" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0xC 8.--12. " EVT_MUX_13 ,Event Mux for TPCC Event number 13" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0xC 0.--4. " EVT_MUX_12 ,Event Mux for TPCC Event number 12" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x10 "EDMA3CC_EVTMUX_16_19,TPCC Event Mux Register for Event 16 to 19"
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bitfld.long 0x10 24.--28. " EVT_MUX_19 ,Event Mux for TPCC Event number 19" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x10 16.--20. " EVT_MUX_18 ,Event Mux for TPCC Event number 18" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x10 8.--12. " EVT_MUX_17 ,Event Mux for TPCC Event number 17" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x10 0.--4. " EVT_MUX_16 ,Event Mux for TPCC Event number 16" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x14 "EDMA3CC_EVTMUX_20_23,TPCC Event Mux Register for Event 20 to 23"
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bitfld.long 0x14 24.--28. " EVT_MUX_23 ,Event Mux for TPCC Event number 23" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x14 16.--20. " EVT_MUX_22 ,Event Mux for TPCC Event number 22" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x14 8.--12. " EVT_MUX_21 ,Event Mux for TPCC Event number 21" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x14 0.--4. " EVT_MUX_20 ,Event Mux for TPCC Event number 20" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x18 "EDMA3CC_EVTMUX_24_27,TPCC Event Mux Register for Event 24 to 27"
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bitfld.long 0x18 24.--28. " EVT_MUX_27 ,Event Mux for TPCC Event number 27" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x18 16.--20. " EVT_MUX_26 ,Event Mux for TPCC Event number 26" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x18 8.--12. " EVT_MUX_25 ,Event Mux for TPCC Event number 25" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x18 0.--4. " EVT_MUX_24 ,Event Mux for TPCC Event number 24" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x1C "EDMA3CC_EVTMUX_28_31,TPCC Event Mux Register for Event 28 to 31"
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bitfld.long 0x1C 24.--28. " EVT_MUX_31 ,Event Mux for TPCC Event number 31" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x1C 16.--20. " EVT_MUX_30 ,Event Mux for TPCC Event number 30" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x1C 8.--12. " EVT_MUX_29 ,Event Mux for TPCC Event number 29" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x1C 0.--4. " EVT_MUX_28 ,Event Mux for TPCC Event number 28" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x20 "EDMA3CC_EVTMUX_32_35,TPCC Event Mux Register for Event 32 to 35"
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bitfld.long 0x20 24.--28. " EVT_MUX_35 ,Event Mux for TPCC Event number 35" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x20 16.--20. " EVT_MUX_34 ,Event Mux for TPCC Event number 34" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x20 8.--12. " EVT_MUX_33 ,Event Mux for TPCC Event number 33" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x20 0.--4. " EVT_MUX_32 ,Event Mux for TPCC Event number 32" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x24 "EDMA3CC_EVTMUX_36_39,TPCC Event Mux Register for Event 36 to 39"
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bitfld.long 0x24 24.--28. " EVT_MUX_39 ,Event Mux for TPCC Event number 39" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x24 16.--20. " EVT_MUX_38 ,Event Mux for TPCC Event number 38" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x24 8.--12. " EVT_MUX_37 ,Event Mux for TPCC Event number 37" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x24 0.--4. " EVT_MUX_36 ,Event Mux for TPCC Event number 36" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x28 "EDMA3CC_EVTMUX_40_43,TPCC Event Mux Register for Event 40 to 43"
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bitfld.long 0x28 24.--28. " EVT_MUX_43 ,Event Mux for TPCC Event number 43" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x28 16.--20. " EVT_MUX_42 ,Event Mux for TPCC Event number 42" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x28 8.--12. " EVT_MUX_41 ,Event Mux for TPCC Event number 41" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x28 0.--4. " EVT_MUX_40 ,Event Mux for TPCC Event number 40" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x2C "EDMA3CC_EVTMUX_44_47,TPCC Event Mux Register for Event 44 to 47"
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bitfld.long 0x2C 24.--28. " EVT_MUX_47 ,Event Mux for TPCC Event number 47" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x2C 16.--20. " EVT_MUX_46 ,Event Mux for TPCC Event number 46" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x2C 8.--12. " EVT_MUX_45 ,Event Mux for TPCC Event number 45" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x2C 0.--4. " EVT_MUX_44 ,Event Mux for TPCC Event number 44" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x30 "EDMA3CC_EVTMUX_48_51,TPCC Event Mux Register for Event 48 to 51"
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bitfld.long 0x30 24.--28. " EVT_MUX_51 ,Event Mux for TPCC Event number 51" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x30 16.--20. " EVT_MUX_50 ,Event Mux for TPCC Event number 50" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x30 8.--12. " EVT_MUX_49 ,Event Mux for TPCC Event number 49" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x30 0.--4. " EVT_MUX_48 ,Event Mux for TPCC Event number 48" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x34 "EDMA3CC_EVTMUX_52_55,TPCC Event Mux Register for Event 52 to 55"
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bitfld.long 0x34 24.--28. " EVT_MUX_55 ,Event Mux for TPCC Event number 55" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x34 16.--20. " EVT_MUX_54 ,Event Mux for TPCC Event number 54" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x34 8.--12. " EVT_MUX_53 ,Event Mux for TPCC Event number 53" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x34 0.--4. " EVT_MUX_52 ,Event Mux for TPCC Event number 52" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x38 "EDMA3CC_EVTMUX_56_59,TPCC Event Mux Register for Event 56 to 59"
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bitfld.long 0x38 24.--28. " EVT_MUX_59 ,Event Mux for TPCC Event number 59" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x38 16.--20. " EVT_MUX_58 ,Event Mux for TPCC Event number 58" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x38 8.--12. " EVT_MUX_57 ,Event Mux for TPCC Event number 57" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x38 0.--4. " EVT_MUX_56 ,Event Mux for TPCC Event number 56" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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line.long 0x3C "EDMA3CC_EVTMUX_60_63,TPCC Event Mux Register for Event 60 to 63"
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bitfld.long 0x3C 24.--28. " EVT_MUX_63 ,Event Mux for TPCC Event number 63" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x3C 16.--20. " EVT_MUX_62 ,Event Mux for TPCC Event number 62" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x3C 8.--12. " EVT_MUX_61 ,Event Mux for TPCC Event number 61" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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bitfld.long 0x3C 0.--4. " EVT_MUX_60 ,Event Mux for TPCC Event number 60" "DMA specific,SDTXEVT2,SDRXEVT2,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPI2XEVT0,SPI2REVT0,SPI2XEVT1,SPI2REVT1,SPI3XEVT0,SPI3REVT0,Reserved,TINT1,TINT2,TINT3,AXEVT5,AREVT5,EDMAEVT0,EDMAEVT1,EDMAEVT2,EDMAEVT3"
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tree.end
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width 19.
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tree "TPCC Event Mux"
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group.long 0xf90++0x3f
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line.long 0x0 "TPCC_INTMUX_0_3,TPCC Event Mux Register for Event 0 to 3"
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bitfld.long 0x0 24.--28. " EVT_MUX_3 ,Event Mux for TPCC Event number 3 " "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x0 16.--20. " EVT_MUX_2 ,Event Mux for TPCC Event number 2 " "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x0 8.--12. " EVT_MUX_1 ,Event Mux for TPCC Event number 1 " "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x0 0.--4. " EVT_MUX_0 ,Event Mux for TPCC Event number 0 " "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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line.long 0x4 "TPCC_INTMUX_4_7,TPCC Event Mux Register for Event 4 to 7"
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bitfld.long 0x4 24.--28. " EVT_MUX_7 ,Event Mux for TPCC Event number 7 " "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x4 16.--20. " EVT_MUX_6 ,Event Mux for TPCC Event number 6 " "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x4 8.--12. " EVT_MUX_5 ,Event Mux for TPCC Event number 5 " "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x4 0.--4. " EVT_MUX_4 ,Event Mux for TPCC Event number 4 " "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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line.long 0x8 "TPCC_INTMUX_8_11,TPCC Event Mux Register for Event 8 to 11"
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bitfld.long 0x8 24.--28. " EVT_MUX_11 ,Event Mux for TPCC Event number 11" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x8 16.--20. " EVT_MUX_10 ,Event Mux for TPCC Event number 10" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x8 8.--12. " EVT_MUX_9 ,Event Mux for TPCC Event number 9 " "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x8 0.--4. " EVT_MUX_8 ,Event Mux for TPCC Event number 8 " "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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line.long 0xC "TPCC_INTMUX_12_15,TPCC Event Mux Register for Event 12 to 15"
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bitfld.long 0xC 24.--28. " EVT_MUX_15 ,Event Mux for TPCC Event number 15" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0xC 16.--20. " EVT_MUX_14 ,Event Mux for TPCC Event number 14" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0xC 8.--12. " EVT_MUX_13 ,Event Mux for TPCC Event number 13" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0xC 0.--4. " EVT_MUX_12 ,Event Mux for TPCC Event number 12" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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line.long 0x10 "TPCC_INTMUX_16_19,TPCC Event Mux Register for Event 16 to 19"
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bitfld.long 0x10 24.--28. " EVT_MUX_19 ,Event Mux for TPCC Event number 19" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x10 16.--20. " EVT_MUX_18 ,Event Mux for TPCC Event number 18" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x10 8.--12. " EVT_MUX_17 ,Event Mux for TPCC Event number 17" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x10 0.--4. " EVT_MUX_16 ,Event Mux for TPCC Event number 16" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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line.long 0x14 "TPCC_INTMUX_20_23,TPCC Event Mux Register for Event 20 to 23"
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bitfld.long 0x14 24.--28. " EVT_MUX_23 ,Event Mux for TPCC Event number 23" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x14 16.--20. " EVT_MUX_22 ,Event Mux for TPCC Event number 22" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x14 8.--12. " EVT_MUX_21 ,Event Mux for TPCC Event number 21" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x14 0.--4. " EVT_MUX_20 ,Event Mux for TPCC Event number 20" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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line.long 0x18 "TPCC_INTMUX_24_27,TPCC Event Mux Register for Event 24 to 27"
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bitfld.long 0x18 24.--28. " EVT_MUX_27 ,Event Mux for TPCC Event number 27" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x18 16.--20. " EVT_MUX_26 ,Event Mux for TPCC Event number 26" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x18 8.--12. " EVT_MUX_25 ,Event Mux for TPCC Event number 25" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x18 0.--4. " EVT_MUX_24 ,Event Mux for TPCC Event number 24" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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line.long 0x1C "TPCC_INTMUX_28_31,TPCC Event Mux Register for Event 28 to 31"
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bitfld.long 0x1C 24.--28. " EVT_MUX_31 ,Event Mux for TPCC Event number 31" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x1C 16.--20. " EVT_MUX_30 ,Event Mux for TPCC Event number 30" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x1C 8.--12. " EVT_MUX_29 ,Event Mux for TPCC Event number 29" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x1C 0.--4. " EVT_MUX_28 ,Event Mux for TPCC Event number 28" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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line.long 0x20 "TPCC_INTMUX_32_35,TPCC Event Mux Register for Event 32 to 35"
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bitfld.long 0x20 24.--28. " EVT_MUX_35 ,Event Mux for TPCC Event number 35" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x20 16.--20. " EVT_MUX_34 ,Event Mux for TPCC Event number 34" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x20 8.--12. " EVT_MUX_33 ,Event Mux for TPCC Event number 33" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x20 0.--4. " EVT_MUX_32 ,Event Mux for TPCC Event number 32" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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line.long 0x24 "TPCC_INTMUX_36_39,TPCC Event Mux Register for Event 36 to 39"
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bitfld.long 0x24 24.--28. " EVT_MUX_39 ,Event Mux for TPCC Event number 39" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x24 16.--20. " EVT_MUX_38 ,Event Mux for TPCC Event number 38" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x24 8.--12. " EVT_MUX_37 ,Event Mux for TPCC Event number 37" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x24 0.--4. " EVT_MUX_36 ,Event Mux for TPCC Event number 36" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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line.long 0x28 "TPCC_INTMUX_40_43,TPCC Event Mux Register for Event 40 to 43"
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bitfld.long 0x28 24.--28. " EVT_MUX_43 ,Event Mux for TPCC Event number 43" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x28 16.--20. " EVT_MUX_42 ,Event Mux for TPCC Event number 42" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x28 8.--12. " EVT_MUX_41 ,Event Mux for TPCC Event number 41" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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bitfld.long 0x28 0.--4. " EVT_MUX_40 ,Event Mux for TPCC Event number 40" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
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line.long 0x2C "TPCC_INTMUX_44_47,TPCC Event Mux Register for Event 44 to 47"
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bitfld.long 0x2C 24.--28. " EVT_MUX_47 ,Event Mux for TPCC Event number 47" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x2C 16.--20. " EVT_MUX_46 ,Event Mux for TPCC Event number 46" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x2C 8.--12. " EVT_MUX_45 ,Event Mux for TPCC Event number 45" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x2C 0.--4. " EVT_MUX_44 ,Event Mux for TPCC Event number 44" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
line.long 0x30 "TPCC_INTMUX_48_51,TPCC Event Mux Register for Event 48 to 51"
|
|
bitfld.long 0x30 24.--28. " EVT_MUX_51 ,Event Mux for TPCC Event number 51" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x30 16.--20. " EVT_MUX_50 ,Event Mux for TPCC Event number 50" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x30 8.--12. " EVT_MUX_49 ,Event Mux for TPCC Event number 49" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x30 0.--4. " EVT_MUX_48 ,Event Mux for TPCC Event number 48" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
line.long 0x34 "TPCC_INTMUX_52_55,TPCC Event Mux Register for Event 52 to 55"
|
|
bitfld.long 0x34 24.--28. " EVT_MUX_55 ,Event Mux for TPCC Event number 55" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x34 16.--20. " EVT_MUX_54 ,Event Mux for TPCC Event number 54" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x34 8.--12. " EVT_MUX_53 ,Event Mux for TPCC Event number 53" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x34 0.--4. " EVT_MUX_52 ,Event Mux for TPCC Event number 52" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
line.long 0x38 "TPCC_INTMUX_56_59,TPCC Event Mux Register for Event 56 to 59"
|
|
bitfld.long 0x38 24.--28. " EVT_MUX_59 ,Event Mux for TPCC Event number 59" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x38 16.--20. " EVT_MUX_58 ,Event Mux for TPCC Event number 58" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x38 8.--12. " EVT_MUX_57 ,Event Mux for TPCC Event number 57" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x38 0.--4. " EVT_MUX_56 ,Event Mux for TPCC Event number 56" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
line.long 0x3C "TPCC_INTMUX_60_63,TPCC Event Mux Register for Event 60 to 63"
|
|
bitfld.long 0x3C 24.--28. " EVT_MUX_63 ,Event Mux for TPCC Event number 63" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x3C 16.--20. " EVT_MUX_62 ,Event Mux for TPCC Event number 62" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x3C 8.--12. " EVT_MUX_61 ,Event Mux for TPCC Event number 61" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
bitfld.long 0x3C 0.--4. " EVT_MUX_60 ,Event Mux for TPCC Event number 60" "DMA specific,SDTXEVT1,SDRXEVT1,I2CTXEVT2,I2CRXEVT2,I2CTXEVT3,I2CRXEVT3,UTXEVT3,URXEVT3,UTXEVT4,URXEVT4,UTXEVT5,URXEVT5,CAN_IF1DMA,CAN_IF2DMA,CAN_IF3DMA,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,TINT0,TINT1,TINT2,TINT3,AXEVT2,AREVT2,XDMA_EVT_0,XDMA_EVT_1,XDMA_EVT_2,XDMA_EVT_3"
|
|
tree.end
|
|
endif
|
|
width 15.
|
|
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
|
|
group.long 0xfd0++0x3
|
|
line.long 0x00 "TIMER_EVTCAPT,Timer 5/6/7 Event Capture Mux Register"
|
|
bitfld.long 0x00 16.--20. " TIMER7_EVTCAPT ,Timer 7 event capture mux" "Timer IO pin,UART0INT,UART1INT,UART2INT,UART3INT,UART4INT,UART5INT,3PGSWRXTHR0,3PGSWRXINT0,3PGSWTXINT0,3PGSWMISC0,MCATXINT0,MCARXINT0,MCATXINT1,MCARXINT1,MCATXINT2,MCARXINT2,GPIOINT0A,GPIOINT0B,GPIOINT1A,GPIOINT1B,GPIOINT2A,GPIOINT2B,GPIOINT3A,GPIOINT3B,DCAN0_INT0,DCAN0_INT1,DCAN0_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,?..."
|
|
bitfld.long 0x00 8.--12. " TIMER6_EVTCAPT ,Timer 6 event capture mux" "Timer IO pin,UART0INT,UART1INT,UART2INT,UART3INT,UART4INT,UART5INT,3PGSWRXTHR0,3PGSWRXINT0,3PGSWTXINT0,3PGSWMISC0,MCATXINT0,MCARXINT0,MCATXINT1,MCARXINT1,MCATXINT2,MCARXINT2,GPIOINT0A,GPIOINT0B,GPIOINT1A,GPIOINT1B,GPIOINT2A,GPIOINT2B,GPIOINT3A,GPIOINT3B,DCAN0_INT0,DCAN0_INT1,DCAN0_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,?..."
|
|
bitfld.long 0x00 0.--4. " TIMER5_EVTCAPT ,Timer 5 event capture mux" "Timer IO pin,UART0INT,UART1INT,UART2INT,UART3INT,UART4INT,UART5INT,3PGSWRXTHR0,3PGSWRXINT0,3PGSWTXINT0,3PGSWMISC0,MCATXINT0,MCARXINT0,MCATXINT1,MCARXINT1,MCATXINT2,MCARXINT2,GPIOINT0A,GPIOINT0B,GPIOINT1A,GPIOINT1B,GPIOINT2A,GPIOINT2B,GPIOINT3A,GPIOINT3B,DCAN0_INT0,DCAN0_INT1,DCAN0_PARITY,DCAN1_INT0,DCAN1_INT1,DCAN1_PARITY,?..."
|
|
endif
|
|
group.long 0xFD4++0x03
|
|
line.long 0x00 "GPIO_MUX,GPIO Mux Register"
|
|
bitfld.long 0x00 5. " GPIO1_5_MUX ,GPIO1_5 input mux" "Pad,USB1 charge detect"
|
|
bitfld.long 0x00 4. " GPIO1_4_MUX ,GPIO1_4 input mux" "Pad,USB0 charge detect"
|
|
bitfld.long 0x00 3. " GPIO1_3_MUX ,GPIO1_3 input mux" "Pad,Bandgap1 Tshut"
|
|
textline " "
|
|
bitfld.long 0x00 2. " GPIO1_2_MUX ,GPIO1_2 input mux" "Pad,Bandgap0 Tshut"
|
|
bitfld.long 0x00 1. " GPIO1_1_MUX ,GPIO1_1 input mux" "Pad,Vdac_tvint"
|
|
bitfld.long 0x00 0. " GPIO1_0_MUX ,GPIO1_0 input mux" "Pad,Vdac_tvint"
|
|
group.long 0x1000++0x3
|
|
line.long 0x00 "RESET_ISO,Reset Isolation Register"
|
|
bitfld.long 0x00 3. " RMII_ISO1 ,Isolate RMII_REFCLK_PINCTRL/RMII1_MUX1_PINCTRL/RMII0_PINCTRL/MDIO_PINCTRL" "Not isolated,Isolated"
|
|
bitfld.long 0x00 2. " RMII_ISO0 ,Isolate RMII_REFCLK_PINCTRL/RMII1_MUX0_PINCTRL/RMII0_PINCTRL/MDIO_PINCTRL" "Not isolated,Isolated"
|
|
bitfld.long 0x00 1. " GMII_ISO/RGMII_ISO ,Isolate GMII1_PINCTRL/GMII1_PINCTRL/MDIO_PINCTRL" "Not isolated,Isolated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ISO_CONTROL ,Isolate Ethernet Switch" "Not isolated,Isolated"
|
|
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
|
|
group.long 0x1300++0x3
|
|
line.long 0x00 "HDMI_PHY_CTRL,HDMI PHY Control Register"
|
|
bitfld.long 0x00 1. " PD_PULLUPDET ,Enable/disable low power Rx detection" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " ENBYPASSCLK ,HFBYPASSCLK enable (instead of HFBITCLK)" "Disabled,Enabled"
|
|
group.long 0x1310++0x17
|
|
line.long 0x00 "DAC0_TRIM,DAC0 Trim Register"
|
|
hexmask.long 0x00 0.--30. 1. " TRIM_0_30 ,DAC0 trim bits 0:30"
|
|
line.long 0x04 "DAC1_TRIM,DAC1 Trim Register"
|
|
hexmask.long 0x04 0.--30. 1. " TRIM_0_30 ,DAC1 trim bits 0:30"
|
|
line.long 0x08 "SMA0,SMA0 Register"
|
|
line.long 0x0c "SMA1,SMA1 Register"
|
|
line.long 0x10 "SMA2,SMA2 Register"
|
|
line.long 0x14 "SMA3,SMA3 Register"
|
|
width 22.
|
|
tree "DDR0 PHY Registers"
|
|
group.long 0x1400++0xf
|
|
line.long 0x00 "DDR0_CMD_CTRL,DDR0 Command Macro Control Register"
|
|
bitfld.long 0x00 14. " CMD_REG_PHY_INVERT_CLKOUT ,polarity of DRAM clock invertion" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 4.--13. 1. " CMD_REG_PHY_CTRL_SLAVE_RATIO ,Ratio value for address/command launch timing"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CMD_REG_PHY_DLL_LOCK_DIFF ,Dll lock within this offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "DDR0_CMD0_IOCTRL,DDR0 Command 0 IO Control Register"
|
|
hexmask.long.word 0x4 21.--31. 1. " IO_CONFIG_GP_WD1 ,Inhibits weak pullup or pulldown"
|
|
hexmask.long.word 0x4 10.--20. 1. " IO_CONFIG_GP_WD0 ,Input that selects pullup or pulldown"
|
|
textline " "
|
|
bitfld.long 0x4 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x4 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x4 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "DDR0_CMD1_IOCTRL,DDR0 Command 1 IO Control Register"
|
|
hexmask.long.word 0x8 21.--31. 1. " IO_CONFIG_GP_WD1 ,Inhibits weak pullup or pulldown"
|
|
hexmask.long.word 0x8 10.--20. 1. " IO_CONFIG_GP_WD0 ,Input that selects pullup or pulldown"
|
|
textline " "
|
|
bitfld.long 0x8 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x8 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x8 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DDR0_CMD2_IOCTRL,DDR0 Command 2 IO Control Register"
|
|
hexmask.long.word 0xC 21.--31. 1. " IO_CONFIG_GP_WD1 ,Inhibits weak pullup or pulldown"
|
|
hexmask.long.word 0xC 10.--20. 1. " IO_CONFIG_GP_WD0 ,Input that selects pullup or pulldown"
|
|
textline " "
|
|
bitfld.long 0xC 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0xC 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0xC 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
width 22.
|
|
rgroup.long 0x1410++0xb
|
|
line.long 0x0 "DDR0_CMD0_STATUS,DDR0 Command Macro 0 Status Register"
|
|
hexmask.long.word 0x0 12.--20. 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in PHY_CTRL Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0x0 3.--11. 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in PHY_CTRL Master DLL"
|
|
textline " "
|
|
bitfld.long 0x0 2. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CMD_PHY_REG_STATUS_PHY_CTRL_DLL_LOCK ,PHY_CTRL Master DLL Status signal" "Unlocked,Locked"
|
|
line.long 0x4 "DDR0_CMD1_STATUS,DDR0 Command Macro 1 Status Register"
|
|
hexmask.long.word 0x4 12.--20. 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in PHY_CTRL Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0x4 3.--11. 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in PHY_CTRL Master DLL"
|
|
textline " "
|
|
bitfld.long 0x4 2. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x4 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CMD_PHY_REG_STATUS_PHY_CTRL_DLL_LOCK ,PHY_CTRL Master DLL Status signal" "Unlocked,Locked"
|
|
line.long 0x8 "DDR0_CMD2_STATUS,DDR0 Command Macro 2 Status Register"
|
|
hexmask.long.word 0x8 12.--20. 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in PHY_CTRL Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0x8 3.--11. 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in PHY_CTRL Master DLL"
|
|
textline " "
|
|
bitfld.long 0x8 2. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x8 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CMD_PHY_REG_STATUS_PHY_CTRL_DLL_LOCK ,PHY_CTRL Master DLL Status signal" "Unlocked,Locked"
|
|
width 22.
|
|
group.long 0x1420++0xf
|
|
line.long 0x00 "DDR0_DATA0_CTRL,DDR0 Data Macro 0 Control Register"
|
|
bitfld.long 0x00 18. " PHY_REG_WR_LVL_BYPASS_DQS_IO ,Data macros control" "Low,High"
|
|
bitfld.long 0x00 17. " PHY_REG_USE_RANK0_DELAYS ,Data macros control" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PHY_REG_RDC_FIFO_RST_ERR_CNT_CLR ,Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]" "No reset,Reset"
|
|
bitfld.long 0x00 15. " PHY_REG_DIS_CALIB_RST ,Disable the resetting of the Read Capture FIFO pointers with dll_calib" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " PHY_REG_DIFF_OFF ,PHY_REG_DIFF_OFF" "0,1,2,3"
|
|
bitfld.long 0x00 11.--12. " PHY_REG_DIFF_ON ,PHY_REG_DIFF_ON" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--10. 1. " PHY_REG_DQ_OFFSET ,Offset value from dqs to dq"
|
|
width 22.
|
|
line.long 0x4 "DDR0_DATA1_CTRL,DDR0 Data Macro 1 Control Register"
|
|
bitfld.long 0x4 16. " PHY_REG_RDC_FIFO_RST_ERR_CNT_CLR ,Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]" "No reset,Reset"
|
|
bitfld.long 0x4 13.--14. " PHY_REG_DIFF_OFF ,PHY_REG_DIFF_OFF" "0,1,2,3"
|
|
bitfld.long 0x4 11.--12. " PHY_REG_DIFF_ON ,PHY_REG_DIFF_ON" "0,1,2,3"
|
|
hexmask.long.byte 0x4 4.--10. 1. " PHY_REG_DQ_OFFSET ,Offset value from dqs to dq"
|
|
line.long 0x8 "DDR0_DATA2_CTRL,DDR0 Data Macro 2 Control Register"
|
|
bitfld.long 0x8 16. " PHY_REG_RDC_FIFO_RST_ERR_CNT_CLR ,Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]" "No reset,Reset"
|
|
bitfld.long 0x8 13.--14. " PHY_REG_DIFF_OFF ,PHY_REG_DIFF_OFF" "0,1,2,3"
|
|
bitfld.long 0x8 11.--12. " PHY_REG_DIFF_ON ,PHY_REG_DIFF_ON" "0,1,2,3"
|
|
hexmask.long.byte 0x8 4.--10. 1. " PHY_REG_DQ_OFFSET ,Offset value from dqs to dq"
|
|
line.long 0xC "DDR0_DATA3_CTRL,DDR0 Data Macro 3 Control Register"
|
|
bitfld.long 0xC 16. " PHY_REG_RDC_FIFO_RST_ERR_CNT_CLR ,Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]" "No reset,Reset"
|
|
bitfld.long 0xC 13.--14. " PHY_REG_DIFF_OFF ,PHY_REG_DIFF_OFF" "0,1,2,3"
|
|
bitfld.long 0xC 11.--12. " PHY_REG_DIFF_ON ,PHY_REG_DIFF_ON" "0,1,2,3"
|
|
hexmask.long.byte 0xC 4.--10. 1. " PHY_REG_DQ_OFFSET ,Offset value from dqs to dq"
|
|
width 22.
|
|
group.long 0x1430++0xf
|
|
line.long 0x0 "DDR0_DATA0_IOCTRL,DDR0 Data Macro 0 IO Control Register"
|
|
bitfld.long 0x0 29. " IO_CONFIG_WD1_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
bitfld.long 0x0 28. " IO_CONFIG_WD1_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0x0 20.--27. 1. " IO_CONFIG_WD1_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0x0 19. " IO_CONFIG_WD0_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 18. " IO_CONFIG_WD0_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0x0 10.--17. 1. " IO_CONFIG_WD0_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0x0 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x0 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DDR0_DATA1_IOCTRL,DDR0 Data Macro 1 IO Control Register"
|
|
bitfld.long 0x4 29. " IO_CONFIG_WD1_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
bitfld.long 0x4 28. " IO_CONFIG_WD1_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0x4 20.--27. 1. " IO_CONFIG_WD1_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0x4 19. " IO_CONFIG_WD0_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 18. " IO_CONFIG_WD0_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0x4 10.--17. 1. " IO_CONFIG_WD0_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0x4 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x4 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x4 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "DDR0_DATA2_IOCTRL,DDR0 Data Macro 2 IO Control Register"
|
|
bitfld.long 0x8 29. " IO_CONFIG_WD1_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
bitfld.long 0x8 28. " IO_CONFIG_WD1_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0x8 20.--27. 1. " IO_CONFIG_WD1_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0x8 19. " IO_CONFIG_WD0_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 18. " IO_CONFIG_WD0_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0x8 10.--17. 1. " IO_CONFIG_WD0_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0x8 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x8 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x8 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DDR0_DATA3_IOCTRL,DDR0 Data Macro 3 IO Control Register"
|
|
bitfld.long 0xC 29. " IO_CONFIG_WD1_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
bitfld.long 0xC 28. " IO_CONFIG_WD1_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0xC 20.--27. 1. " IO_CONFIG_WD1_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0xC 19. " IO_CONFIG_WD0_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 18. " IO_CONFIG_WD0_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0xC 10.--17. 1. " IO_CONFIG_WD0_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0xC 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0xC 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0xC 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
width 22.
|
|
group.long 0x1440++0x3f
|
|
line.long 0x0 "DDR0_DATA0_CS0_CTRL0,DDR0 Data Macro 0 CS0 Control 0 Register"
|
|
hexmask.long.word 0x0 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x0 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x0 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x0+0x4) "DDR0_DATA0_CS0_CTRL1,DDR0 Data Macro 0 CS0 Control 1 Register"
|
|
hexmask.long.word (0x0+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x0+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x0+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x8 "DDR0_DATA0_CS1_CTRL0,DDR0 Data Macro 0 CS1 Control 0 Register"
|
|
hexmask.long.word 0x8 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x8 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x8 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x8+0x4) "DDR0_DATA0_CS1_CTRL1,DDR0 Data Macro 0 CS1 Control 1 Register"
|
|
hexmask.long.word (0x8+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x8+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x8+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x10 "DDR0_DATA1_CS0_CTRL0,DDR0 Data Macro 1 CS0 Control 0 Register"
|
|
hexmask.long.word 0x10 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x10 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x10 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x10+0x4) "DDR0_DATA1_CS0_CTRL1,DDR0 Data Macro 1 CS0 Control 1 Register"
|
|
hexmask.long.word (0x10+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x10+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x10+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x18 "DDR0_DATA1_CS1_CTRL0,DDR0 Data Macro 1 CS1 Control 0 Register"
|
|
hexmask.long.word 0x18 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x18 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x18 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x18+0x4) "DDR0_DATA1_CS1_CTRL1,DDR0 Data Macro 1 CS1 Control 1 Register"
|
|
hexmask.long.word (0x18+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x18+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x18+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x20 "DDR0_DATA2_CS0_CTRL0,DDR0 Data Macro 2 CS0 Control 0 Register"
|
|
hexmask.long.word 0x20 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x20 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x20+0x4) "DDR0_DATA2_CS0_CTRL1,DDR0 Data Macro 2 CS0 Control 1 Register"
|
|
hexmask.long.word (0x20+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x20+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x20+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x28 "DDR0_DATA2_CS1_CTRL0,DDR0 Data Macro 2 CS1 Control 0 Register"
|
|
hexmask.long.word 0x28 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x28 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x28 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x28+0x4) "DDR0_DATA2_CS1_CTRL1,DDR0 Data Macro 2 CS1 Control 1 Register"
|
|
hexmask.long.word (0x28+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x28+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x28+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x30 "DDR0_DATA3_CS0_CTRL0,DDR0 Data Macro 3 CS0 Control 0 Register"
|
|
hexmask.long.word 0x30 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x30 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x30 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x30+0x4) "DDR0_DATA3_CS0_CTRL1,DDR0 Data Macro 3 CS0 Control 1 Register"
|
|
hexmask.long.word (0x30+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x30+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x30+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x38 "DDR0_DATA3_CS1_CTRL0,DDR0 Data Macro 3 CS1 Control 0 Register"
|
|
hexmask.long.word 0x38 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x38 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x38 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x38+0x4) "DDR0_DATA3_CS1_CTRL1,DDR0 Data Macro 3 CS1 Control 1 Register"
|
|
hexmask.long.word (0x38+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x38+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x38+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
rgroup.long 0x1480++0xf
|
|
line.long 0x0 "DDR0_DATA0_STS,DDR0 Data Macro 0 Status Register"
|
|
bitfld.long 0x0 21.--24. " DATA_REG_PHY_RDC_FIFO_RST_ERR_CNT ,Counter of read data capture FIFO errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x0 12.--20. 1. " DATA_REG_PHY_STATUS_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0x0 3.--11. 1. " DATA_REG_PHY_STATUS_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in Master DLL"
|
|
textline " "
|
|
bitfld.long 0x0 2. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0 1. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0 0. " DATA_REG_PHY_STATUS_DLL_LOCK ,Status signal" "Unlocked,Locked"
|
|
line.long 0x4 "DDR0_DATA1_STS,DDR0 Data Macro 1 Status Register"
|
|
bitfld.long 0x4 21.--24. " DATA_REG_PHY_RDC_FIFO_RST_ERR_CNT ,Counter of read data capture FIFO errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x4 12.--20. 1. " DATA_REG_PHY_STATUS_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0x4 3.--11. 1. " DATA_REG_PHY_STATUS_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in Master DLL"
|
|
textline " "
|
|
bitfld.long 0x4 2. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x4 1. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x4 0. " DATA_REG_PHY_STATUS_DLL_LOCK ,Status signal" "Unlocked,Locked"
|
|
line.long 0x8 "DDR0_DATA2_STS,DDR0 Data Macro 2 Status Register"
|
|
bitfld.long 0x8 21.--24. " DATA_REG_PHY_RDC_FIFO_RST_ERR_CNT ,Counter of read data capture FIFO errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x8 12.--20. 1. " DATA_REG_PHY_STATUS_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0x8 3.--11. 1. " DATA_REG_PHY_STATUS_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in Master DLL"
|
|
textline " "
|
|
bitfld.long 0x8 2. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x8 1. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x8 0. " DATA_REG_PHY_STATUS_DLL_LOCK ,Status signal" "Unlocked,Locked"
|
|
line.long 0xC "DDR0_DATA3_STS,DDR0 Data Macro 3 Status Register"
|
|
bitfld.long 0xC 21.--24. " DATA_REG_PHY_RDC_FIFO_RST_ERR_CNT ,Counter of read data capture FIFO errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0xC 12.--20. 1. " DATA_REG_PHY_STATUS_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0xC 3.--11. 1. " DATA_REG_PHY_STATUS_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in Master DLL"
|
|
textline " "
|
|
bitfld.long 0xC 2. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0xC 1. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0xC 0. " DATA_REG_PHY_STATUS_DLL_LOCK ,Status signal" "Unlocked,Locked"
|
|
tree.end
|
|
width 22.
|
|
tree "DDR1 PHY Registers"
|
|
group.long 0x1500++0xf
|
|
line.long 0x00 "DDR1_CMD_CTRL,DDR1 Command Macro Control Register"
|
|
bitfld.long 0x00 14. " CMD_REG_PHY_INVERT_CLKOUT ,polarity of DRAM clock invertion" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 4.--13. 1. " CMD_REG_PHY_CTRL_SLAVE_RATIO ,Ratio value for address/command launch timing"
|
|
bitfld.long 0x00 0.--3. " CMD_REG_PHY_DLL_LOCK_DIFF ,Dll lock within this offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "DDR1_CMD0_IOCTRL,DDR1 Command 0 IO Control Register"
|
|
hexmask.long.word 0x4 21.--31. 1. " IO_CONFIG_GP_WD1 ,Inhibits weak pullup or pulldown"
|
|
hexmask.long.word 0x4 10.--20. 1. " IO_CONFIG_GP_WD0 ,Input that selects pullup or pulldown"
|
|
textline " "
|
|
bitfld.long 0x4 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x4 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x4 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "DDR1_CMD1_IOCTRL,DDR1 Command 1 IO Control Register"
|
|
hexmask.long.word 0x8 21.--31. 1. " IO_CONFIG_GP_WD1 ,Inhibits weak pullup or pulldown"
|
|
hexmask.long.word 0x8 10.--20. 1. " IO_CONFIG_GP_WD0 ,Input that selects pullup or pulldown"
|
|
textline " "
|
|
bitfld.long 0x8 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x8 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x8 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DDR1_CMD2_IOCTRL,DDR1 Command 2 IO Control Register"
|
|
hexmask.long.word 0xC 21.--31. 1. " IO_CONFIG_GP_WD1 ,Inhibits weak pullup or pulldown"
|
|
hexmask.long.word 0xC 10.--20. 1. " IO_CONFIG_GP_WD0 ,Input that selects pullup or pulldown"
|
|
textline " "
|
|
bitfld.long 0xC 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0xC 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0xC 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
width 22.
|
|
rgroup.long 0x1510++0xb
|
|
line.long 0x0 "DDR1_CMD0_STATUS,DDR1 Command Macro 0 Status Register"
|
|
hexmask.long.word 0x0 12.--20. 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in PHY_CTRL Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0x0 3.--11. 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in PHY_CTRL Master DLL"
|
|
textline " "
|
|
bitfld.long 0x0 2. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CMD_PHY_REG_STATUS_PHY_CTRL_DLL_LOCK ,PHY_CTRL Master DLL Status signal" "Unlocked,Locked"
|
|
line.long 0x4 "DDR1_CMD1_STATUS,DDR1 Command Macro 1 Status Register"
|
|
hexmask.long.word 0x4 12.--20. 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in PHY_CTRL Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0x4 3.--11. 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in PHY_CTRL Master DLL"
|
|
textline " "
|
|
bitfld.long 0x4 2. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x4 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CMD_PHY_REG_STATUS_PHY_CTRL_DLL_LOCK ,PHY_CTRL Master DLL Status signal" "Unlocked,Locked"
|
|
line.long 0x8 "DDR1_CMD2_STATUS,DDR1 Command Macro 2 Status Register"
|
|
hexmask.long.word 0x8 12.--20. 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in PHY_CTRL Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0x8 3.--11. 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in PHY_CTRL Master DLL"
|
|
textline " "
|
|
bitfld.long 0x8 2. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x8 1. " CMD_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CMD_PHY_REG_STATUS_PHY_CTRL_DLL_LOCK ,PHY_CTRL Master DLL Status signal" "Unlocked,Locked"
|
|
width 22.
|
|
group.long 0x1520++0xf
|
|
line.long 0x00 "DDR1_DATA0_CTRL,DDR1 Data Macro 0 Control Register"
|
|
bitfld.long 0x00 18. " PHY_REG_WR_LVL_BYPASS_DQS_IO ,Data macros control" "Low,High"
|
|
bitfld.long 0x00 17. " PHY_REG_USE_RANK0_DELAYS ,Data macros control" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PHY_REG_RDC_FIFO_RST_ERR_CNT_CLR ,Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]" "No reset,Reset"
|
|
bitfld.long 0x00 15. " PHY_REG_DIS_CALIB_RST ,Disable the resetting of the Read Capture FIFO pointers with dll_calib" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " PHY_REG_DIFF_OFF ,PHY_REG_DIFF_OFF" "0,1,2,3"
|
|
bitfld.long 0x00 11.--12. " PHY_REG_DIFF_ON ,PHY_REG_DIFF_ON" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--10. 1. " PHY_REG_DQ_OFFSET ,Offset value from dqs to dq"
|
|
width 22.
|
|
line.long 0x4 "DDR1_DATA1_CTRL,DDR1 Data Macro 1 Control Register"
|
|
bitfld.long 0x4 16. " PHY_REG_RDC_FIFO_RST_ERR_CNT_CLR ,Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]" "No reset,Reset"
|
|
bitfld.long 0x4 13.--14. " PHY_REG_DIFF_OFF ,PHY_REG_DIFF_OFF" "0,1,2,3"
|
|
bitfld.long 0x4 11.--12. " PHY_REG_DIFF_ON ,PHY_REG_DIFF_ON" "0,1,2,3"
|
|
hexmask.long.byte 0x4 4.--10. 1. " PHY_REG_DQ_OFFSET ,Offset value from dqs to dq"
|
|
line.long 0x8 "DDR1_DATA2_CTRL,DDR1 Data Macro 2 Control Register"
|
|
bitfld.long 0x8 16. " PHY_REG_RDC_FIFO_RST_ERR_CNT_CLR ,Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]" "No reset,Reset"
|
|
bitfld.long 0x8 13.--14. " PHY_REG_DIFF_OFF ,PHY_REG_DIFF_OFF" "0,1,2,3"
|
|
bitfld.long 0x8 11.--12. " PHY_REG_DIFF_ON ,PHY_REG_DIFF_ON" "0,1,2,3"
|
|
hexmask.long.byte 0x8 4.--10. 1. " PHY_REG_DQ_OFFSET ,Offset value from dqs to dq"
|
|
line.long 0xC "DDR1_DATA3_CTRL,DDR1 Data Macro 3 Control Register"
|
|
bitfld.long 0xC 16. " PHY_REG_RDC_FIFO_RST_ERR_CNT_CLR ,Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]" "No reset,Reset"
|
|
bitfld.long 0xC 13.--14. " PHY_REG_DIFF_OFF ,PHY_REG_DIFF_OFF" "0,1,2,3"
|
|
bitfld.long 0xC 11.--12. " PHY_REG_DIFF_ON ,PHY_REG_DIFF_ON" "0,1,2,3"
|
|
hexmask.long.byte 0xC 4.--10. 1. " PHY_REG_DQ_OFFSET ,Offset value from dqs to dq"
|
|
width 22.
|
|
group.long 0x1530++0xf
|
|
line.long 0x0 "DDR1_DATA0_IOCTRL,DDR1 Data Macro 0 IO Control Register"
|
|
bitfld.long 0x0 29. " IO_CONFIG_WD1_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
bitfld.long 0x0 28. " IO_CONFIG_WD1_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0x0 20.--27. 1. " IO_CONFIG_WD1_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0x0 19. " IO_CONFIG_WD0_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 18. " IO_CONFIG_WD0_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0x0 10.--17. 1. " IO_CONFIG_WD0_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0x0 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x0 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DDR1_DATA1_IOCTRL,DDR1 Data Macro 1 IO Control Register"
|
|
bitfld.long 0x4 29. " IO_CONFIG_WD1_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
bitfld.long 0x4 28. " IO_CONFIG_WD1_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0x4 20.--27. 1. " IO_CONFIG_WD1_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0x4 19. " IO_CONFIG_WD0_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 18. " IO_CONFIG_WD0_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0x4 10.--17. 1. " IO_CONFIG_WD0_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0x4 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x4 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x4 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "DDR1_DATA2_IOCTRL,DDR1 Data Macro 2 IO Control Register"
|
|
bitfld.long 0x8 29. " IO_CONFIG_WD1_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
bitfld.long 0x8 28. " IO_CONFIG_WD1_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0x8 20.--27. 1. " IO_CONFIG_WD1_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0x8 19. " IO_CONFIG_WD0_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 18. " IO_CONFIG_WD0_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0x8 10.--17. 1. " IO_CONFIG_WD0_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0x8 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x8 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0x8 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DDR1_DATA3_IOCTRL,DDR1 Data Macro 3 IO Control Register"
|
|
bitfld.long 0xC 29. " IO_CONFIG_WD1_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
bitfld.long 0xC 28. " IO_CONFIG_WD1_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0xC 20.--27. 1. " IO_CONFIG_WD1_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0xC 19. " IO_CONFIG_WD0_DQS ,Weak drive pullup/pulldown/keeper for dqs pad select" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 18. " IO_CONFIG_WD0_DM ,Weak drive pullup/pulldown/keeper for dm pad select" "Low,High"
|
|
hexmask.long.byte 0xC 10.--17. 1. " IO_CONFIG_WD0_DQ ,Weak drive pullup/pulldown/keeper for dq pad select"
|
|
bitfld.long 0xC 8.--9. " IO_CONFIG_SR_CLK ,Clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0xC 5.--7. " IO_CONFIG_I_CLK ,Clock IO Pads (CK/CK#) Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 3.--4. " IO_CONFIG_SR ,Addr/cmd IO Pads output Slew Rate" "0,1,2,3"
|
|
bitfld.long 0xC 0.--2. " IO_CONFIG_I ,Addr/cmd IO Pad Pull up/Pull down output Impedance" "0,1,2,3,4,5,6,7"
|
|
width 22.
|
|
group.long 0x1540++0x3f
|
|
line.long 0x0 "DDR1_DATA0_CS0_CTRL0,DDR1 Data Macro 0 CS0 Control 0 Register"
|
|
hexmask.long.word 0x0 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x0 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x0 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x0+0x4) "DDR1_DATA0_CS0_CTRL1,DDR1 Data Macro 0 CS0 Control 1 Register"
|
|
hexmask.long.word (0x0+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x0+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x0+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x8 "DDR1_DATA0_CS1_CTRL0,DDR1 Data Macro 0 CS1 Control 0 Register"
|
|
hexmask.long.word 0x8 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x8 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x8 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x8+0x4) "DDR1_DATA0_CS1_CTRL1,DDR1 Data Macro 0 CS1 Control 1 Register"
|
|
hexmask.long.word (0x8+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x8+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x8+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x10 "DDR1_DATA1_CS0_CTRL0,DDR1 Data Macro 1 CS0 Control 0 Register"
|
|
hexmask.long.word 0x10 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x10 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x10 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x10+0x4) "DDR1_DATA1_CS0_CTRL1,DDR1 Data Macro 1 CS0 Control 1 Register"
|
|
hexmask.long.word (0x10+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x10+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x10+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x18 "DDR1_DATA1_CS1_CTRL0,DDR1 Data Macro 1 CS1 Control 0 Register"
|
|
hexmask.long.word 0x18 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x18 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x18 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x18+0x4) "DDR1_DATA1_CS1_CTRL1,DDR1 Data Macro 1 CS1 Control 1 Register"
|
|
hexmask.long.word (0x18+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x18+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x18+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x20 "DDR1_DATA2_CS0_CTRL0,DDR1 Data Macro 2 CS0 Control 0 Register"
|
|
hexmask.long.word 0x20 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x20 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x20+0x4) "DDR1_DATA2_CS0_CTRL1,DDR1 Data Macro 2 CS0 Control 1 Register"
|
|
hexmask.long.word (0x20+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x20+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x20+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x28 "DDR1_DATA2_CS1_CTRL0,DDR1 Data Macro 2 CS1 Control 0 Register"
|
|
hexmask.long.word 0x28 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x28 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x28 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x28+0x4) "DDR1_DATA2_CS1_CTRL1,DDR1 Data Macro 2 CS1 Control 1 Register"
|
|
hexmask.long.word (0x28+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x28+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x28+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x30 "DDR1_DATA3_CS0_CTRL0,DDR1 Data Macro 3 CS0 Control 0 Register"
|
|
hexmask.long.word 0x30 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x30 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x30 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x30+0x4) "DDR1_DATA3_CS0_CTRL1,DDR1 Data Macro 3 CS0 Control 1 Register"
|
|
hexmask.long.word (0x30+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x30+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x30+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
line.long 0x38 "DDR1_DATA3_CS1_CTRL0,DDR1 Data Macro 3 CS1 Control 0 Register"
|
|
hexmask.long.word 0x38 20.--29. 1. " DATA_REG_PHY_WR_DATA_SLAVE_RATIO ,Ratio value for write data slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x38 10.--19. 1. " DATA_REG_PHY_WR_DQS_SLAVE_RATIO ,Ratio value for write DQS slave DLL"
|
|
textline " "
|
|
hexmask.long.word 0x38 0.--9. 1. " DATA_REG_PHY_RD_DQS_SLAVE_RATIO ,Ratio value for read DQS slave DLL"
|
|
line.long (0x38+0x4) "DDR1_DATA3_CS1_CTRL1,DDR1 Data Macro 3 CS1 Control 1 Register"
|
|
hexmask.long.word (0x38+0x4) 21.--31. 1. " DATA_REG_PHY_GATELVL_INIT_RATIO ,Init ratio used by DQS Gate Training FSM"
|
|
textline " "
|
|
hexmask.long.word (0x38+0x4) 11.--20. 1. " DATA_REG_PHY_WRLVL_INIT_RATIO ,Init ratio used by Write Leveling FSM"
|
|
textline " "
|
|
hexmask.long.word (0x38+0x4) 0.--10. 1. " DATA_REG_PHY_FIFO_WE_SLAVE_RATIO ,Ratio value for fifo_we"
|
|
rgroup.long 0x1580++0xf
|
|
line.long 0x0 "DDR1_DATA0_STS,DDR1 Data Macro 0 Status Register"
|
|
bitfld.long 0x0 21.--24. " DATA_REG_PHY_RDC_FIFO_RST_ERR_CNT ,Counter of read data capture FIFO errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x0 12.--20. 1. " DATA_REG_PHY_STATUS_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0x0 3.--11. 1. " DATA_REG_PHY_STATUS_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in Master DLL"
|
|
textline " "
|
|
bitfld.long 0x0 2. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0 1. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0 0. " DATA_REG_PHY_STATUS_DLL_LOCK ,Status signal" "Unlocked,Locked"
|
|
line.long 0x4 "DDR1_DATA1_STS,DDR1 Data Macro 1 Status Register"
|
|
bitfld.long 0x4 21.--24. " DATA_REG_PHY_RDC_FIFO_RST_ERR_CNT ,Counter of read data capture FIFO errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x4 12.--20. 1. " DATA_REG_PHY_STATUS_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0x4 3.--11. 1. " DATA_REG_PHY_STATUS_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in Master DLL"
|
|
textline " "
|
|
bitfld.long 0x4 2. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x4 1. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x4 0. " DATA_REG_PHY_STATUS_DLL_LOCK ,Status signal" "Unlocked,Locked"
|
|
line.long 0x8 "DDR1_DATA2_STS,DDR1 Data Macro 2 Status Register"
|
|
bitfld.long 0x8 21.--24. " DATA_REG_PHY_RDC_FIFO_RST_ERR_CNT ,Counter of read data capture FIFO errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x8 12.--20. 1. " DATA_REG_PHY_STATUS_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0x8 3.--11. 1. " DATA_REG_PHY_STATUS_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in Master DLL"
|
|
textline " "
|
|
bitfld.long 0x8 2. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x8 1. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x8 0. " DATA_REG_PHY_STATUS_DLL_LOCK ,Status signal" "Unlocked,Locked"
|
|
line.long 0xC "DDR1_DATA3_STS,DDR1 Data Macro 3 Status Register"
|
|
bitfld.long 0xC 21.--24. " DATA_REG_PHY_RDC_FIFO_RST_ERR_CNT ,Counter of read data capture FIFO errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0xC 12.--20. 1. " DATA_REG_PHY_STATUS_OF_OUT_DELAY_VALUE ,Coarse and Fine values coming out of the Output Filter in Master DLL"
|
|
textline " "
|
|
hexmask.long.word 0xC 3.--11. 1. " DATA_REG_PHY_STATUS_OF_IN_DELAY_VALUE ,Coarse and Fine values going into the Output Filter in Master DLL"
|
|
textline " "
|
|
bitfld.long 0xC 2. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE1 ,Coarse delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0xC 1. " DATA_REG_PHY_STATUS_OF_IN_LOCK_STATE0 ,Fine delay line lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0xC 0. " DATA_REG_PHY_STATUS_DLL_LOCK ,Status signal" "Unlocked,Locked"
|
|
tree.end
|
|
width 12.
|
|
rgroup.long 0x183c++0x3
|
|
line.long 0x00 "DIE_ID0,DIE Identification bits [31:0]"
|
|
rgroup.long 0x1848++0x3
|
|
line.long 0x00 "DIE_ID1,DIE Identification bits [63:32]"
|
|
rgroup.long 0x1824++0x3
|
|
line.long 0x00 "DIE_ID2,DIE Identification bits [95:64]"
|
|
rgroup.long 0x1850++0x3
|
|
line.long 0x00 "DIE_ID3,DIE Identification bits [127:96]"
|
|
group.long 0x1844++0x3
|
|
line.long 0x00 "ID_UNLOCK0,DIE ID Unlock 0 Register"
|
|
group.long 0x1828++0x7
|
|
line.long 0x00 "ID_UNLOCK1,DIE ID Unlock 1 Register"
|
|
line.long 0x04 "ID_UNLOCK2,DIE ID Unlock 2 Register"
|
|
group.long 0x184c++0x3
|
|
line.long 0x00 "ID_UNLOCK3,DIE ID Unlock 3 Register"
|
|
endif
|
|
width 11.
|
|
endif
|
|
tree.end
|
|
sif (cpuis("AM387*")||cpuis("DRA62*"))
|
|
tree "PLLSS_CENTAURUS"
|
|
base ad:0x481c5000
|
|
width 19.
|
|
tree "MPU PLL"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "CONTROL_REVISION,PLLSS Revision Register"
|
|
bitfld.long 0x00 30.--31. " IP_REV_SCHEME ,Register scheme" "Legacy,Highlander 0.8,?..."
|
|
hexmask.long.word 0x00 16.--27. 1. " IP_REV_FUNC ,Software compatible module family function"
|
|
bitfld.long 0x00 11.--15. " IP_REV_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " IP_REV_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " IP_REV_CUSTOM ,Special version for a particular device" "Non-custom,?..."
|
|
bitfld.long 0x00 0.--5. " IP_REV_MINOR ,Minor Revision (Y)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "CONTROL_HWINFO,CONTROL_HWINFO Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "CONTROL_SYSCONFIG,System Configuration Register"
|
|
rbitfld.long 0x00 4.--5. " STANDBY ,Configure local initiator state management" "Force Standby,No Standby,Smart Standby,Smart Standby wakeup capable"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Configure local initiator state management" "Force Idle,No Idle,Smart Idle,Smart Idle wakeup capable"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FREEEMU ,Sensitivity to Emulation suspend input" "Sensitive,Not sensitive"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "PLLSS_MMR_LOCK,Lock/Unlock Register for Region 0x0008 - 0x0fff"
|
|
sif (cpuis("DRA62*"))
|
|
group.long 0x48++0x1f
|
|
else
|
|
group.long 0x48++0x23
|
|
endif
|
|
line.long 0x00 "MPUPLL_PWRCTRL,MPU PLL Power Control Register"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "MPUPLL_CLKCTRL,MPU PLL Clock Control Register"
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 15. " M3PWDNZ ,Asynchronous power down for M3 divider" "Powered down,Functional"
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x04 14. " STOPMODE ,STOP Mode (when in Lossclk/Stbyret)" "Limp mode,Stopmode"
|
|
bitfld.long 0x04 13. " LOWCURRSTDBY ,LOW current standby (when in Lossclk/Stbyret/Idle)" "Fast relock,Slow relock"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x04 13. " LOWCURRSTDBY ,LOW current standby (when in Lossclk/Stbyret/Idle)" "Fast relock,Slow relock"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 12. " LPMODE ,LP Mode" "Low,High"
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x04 11. " DRIFTGUARDEN ,Recalibration enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " REGM4XEN ,Enable REGM*4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x04 10. " REGM4XEN ,Enable REGM*4" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
endif
|
|
line.long 0x08 "MPUPLL_TENABLE,MPU PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N latch" "Disabled,Enabled"
|
|
line.long 0x0c "MPUPLL_TENABLEDIV,MPU PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "MPUPLL_M2NDIV,MPU PLL M2NDIV Register"
|
|
bitfld.long 0x10 16.--20. " M2 ,Post-divider is REGM2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x10 0.--6. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "MPUPLL_MN2DIV,MPU PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2[20:16] ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "MPUPLL_FRACDIV,MPU PLL Fractonal Divider Register"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "MPUPLL_BWCTRL,MPU PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
sif (!cpuis("DRA62*"))
|
|
line.long 0x20 "MPUPLL_FRACCTRL,MPU PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--19. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
endif
|
|
rgroup.long 0x6c++0x3
|
|
line.long 0x00 "MPUPLL_STATUS,MPU PLL Status Register"
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x00 30. " SSACK ,PODPLL_MPU_SSACK" "Low,High"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
else
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LIMP ,Mode" "Stop,LIMP"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
group.long 0x70++0x7
|
|
line.long 0x00 "MPUPLL_M3DIV,MPU PLL M3 Divider Register"
|
|
bitfld.long 0x00 0.--4. " M3 ,Post Divider Reg M3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "MPUPLL_RAMPCTRL,MPU PLL RAMP Control Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x04 19.--20. " CLKRAMPLEVEL ,Ramp sequence control" "No ramping,Bypass clk /Fout/8 / Fout/4 / Fout/2 / Fout,Bypass clk / Fout/4 / Fout/2 /Fout/1.5/Fout,?..."
|
|
else
|
|
bitfld.long 0x04 19.--20. " CLKRAMPLEVEL ,Ramp sequence control" "No ramping,Bypass clk /Fout/8 / Fout/4 / Fout/2,Bypass clk / Fout/4 / Fout/2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " CLKRAMPRATE ,Time spent on each ramp step control (REFCLKs)" "2,4,8,16,32,64,128,512"
|
|
bitfld.long 0x04 0. " RELOCK_RAMP_EN ,Clock ramping during relock enable" "Disabled,Enabled"
|
|
tree.end
|
|
sif (!cpuis("DRA62*"))
|
|
width 22.
|
|
tree "DSP PLL"
|
|
group.long 0x80++0x23
|
|
line.long 0x00 "DSPPLL_PWRCTRL,DSP PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "DSPPLL_CLKCTRL,DSP PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp mode,Stop mode"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "DSPPLL_TENABLE,DSP PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "DSPPLL_TENABLEDIV,DSP PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "DSPPLL_M2NDIV,DSP PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "DSPPLL_MN2DIV,DSP PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "DSPPLL_FRACDIV,DSP PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "DSPPLL_BWCTRL,DSP PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
line.long 0x20 "DSPPLL_FRACCTRL,DSP PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
rgroup.long (0x80+0x24)++0x3
|
|
line.long 0x00 "DSPPLL_STATUS,DSP PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
width 22.
|
|
tree "SGX PLL"
|
|
group.long 0xb0++0x23
|
|
line.long 0x00 "SGXPLL_PWRCTRL,SGX PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "SGXPLL_CLKCTRL,SGX PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp mode,Stop mode"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "SGXPLL_TENABLE,SGX PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "SGXPLL_TENABLEDIV,SGX PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "SGXPLL_M2NDIV,SGX PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "SGXPLL_MN2DIV,SGX PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "SGXPLL_FRACDIV,SGX PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "SGXPLL_BWCTRL,SGX PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
line.long 0x20 "SGXPLL_FRACCTRL,SGX PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
rgroup.long (0xb0+0x24)++0x3
|
|
line.long 0x00 "SGXPLL_STATUS,SGX PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
width 22.
|
|
tree "HDVICP PLL"
|
|
group.long 0xe0++0x23
|
|
line.long 0x00 "HDVICPPLL_PWRCTRL,HDVICP PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "HDVICPPLL_CLKCTRL,HDVICP PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp mode,Stop mode"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "HDVICPPLL_TENABLE,HDVICP PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "HDVICPPLL_TENABLEDIV,HDVICP PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "HDVICPPLL_M2NDIV,HDVICP PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "HDVICPPLL_MN2DIV,HDVICP PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "HDVICPPLL_FRACDIV,HDVICP PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "HDVICPPLL_BWCTRL,HDVICP PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
line.long 0x20 "HDVICPPLL_FRACCTRL,HDVICP PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
rgroup.long (0xe0+0x24)++0x3
|
|
line.long 0x00 "HDVICPPLL_STATUS,HDVICP PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
width 22.
|
|
tree "L3 PLL"
|
|
group.long 0x110++0x23
|
|
line.long 0x00 "L3PLL_PWRCTRL,L3 PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "L3PLL_CLKCTRL,L3 PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp mode,Stop mode"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "L3PLL_TENABLE,L3 PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "L3PLL_TENABLEDIV,L3 PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "L3PLL_M2NDIV,L3 PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "L3PLL_MN2DIV,L3 PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "L3PLL_FRACDIV,L3 PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "L3PLL_BWCTRL,L3 PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
line.long 0x20 "L3PLL_FRACCTRL,L3 PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
rgroup.long (0x110+0x24)++0x3
|
|
line.long 0x00 "L3PLL_STATUS,L3 PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
width 22.
|
|
tree "ISP PLL"
|
|
group.long 0x140++0x23
|
|
line.long 0x00 "ISPPLL_PWRCTRL,ISP PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "ISPPLL_CLKCTRL,ISP PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp mode,Stop mode"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "ISPPLL_TENABLE,ISP PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "ISPPLL_TENABLEDIV,ISP PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "ISPPLL_M2NDIV,ISP PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "ISPPLL_MN2DIV,ISP PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "ISPPLL_FRACDIV,ISP PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "ISPPLL_BWCTRL,ISP PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
line.long 0x20 "ISPPLL_FRACCTRL,ISP PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
rgroup.long (0x140+0x24)++0x3
|
|
line.long 0x00 "ISPPLL_STATUS,ISP PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
width 22.
|
|
tree "DSS PLL"
|
|
group.long 0x170++0x23
|
|
line.long 0x00 "DSSPLL_PWRCTRL,DSS PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "DSSPLL_CLKCTRL,DSS PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp mode,Stop mode"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "DSSPLL_TENABLE,DSS PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "DSSPLL_TENABLEDIV,DSS PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "DSSPLL_M2NDIV,DSS PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "DSSPLL_MN2DIV,DSS PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "DSSPLL_FRACDIV,DSS PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "DSSPLL_BWCTRL,DSS PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
line.long 0x20 "DSSPLL_FRACCTRL,DSS PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
rgroup.long (0x170+0x24)++0x3
|
|
line.long 0x00 "DSSPLL_STATUS,DSS PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
width 22.
|
|
tree "VIDEO0 PLL"
|
|
group.long 0x1a0++0x23
|
|
line.long 0x00 "VIDEO0PLL_PWRCTRL,VIDEO0 PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "VIDEO0PLL_CLKCTRL,VIDEO0 PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp mode,Stop mode"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "VIDEO0PLL_TENABLE,VIDEO0 PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "VIDEO0PLL_TENABLEDIV,VIDEO0 PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "VIDEO0PLL_M2NDIV,VIDEO0 PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "VIDEO0PLL_MN2DIV,VIDEO0 PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "VIDEO0PLL_FRACDIV,VIDEO0 PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "VIDEO0PLL_BWCTRL,VIDEO0 PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
line.long 0x20 "VIDEO0PLL_FRACCTRL,VIDEO0 PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
rgroup.long (0x1a0+0x24)++0x3
|
|
line.long 0x00 "VIDEO0PLL_STATUS,VIDEO0 PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
width 22.
|
|
tree "VIDEO1 PLL"
|
|
group.long 0x1d0++0x23
|
|
line.long 0x00 "VIDEO1PLL_PWRCTRL,VIDEO1 PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "VIDEO1PLL_CLKCTRL,VIDEO1 PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp mode,Stop mode"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "VIDEO1PLL_TENABLE,VIDEO1 PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "VIDEO1PLL_TENABLEDIV,VIDEO1 PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "VIDEO1PLL_M2NDIV,VIDEO1 PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "VIDEO1PLL_MN2DIV,VIDEO1 PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "VIDEO1PLL_FRACDIV,VIDEO1 PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "VIDEO1PLL_BWCTRL,VIDEO1 PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
line.long 0x20 "VIDEO1PLL_FRACCTRL,VIDEO1 PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
rgroup.long (0x1d0+0x24)++0x3
|
|
line.long 0x00 "VIDEO1PLL_STATUS,VIDEO1 PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
width 22.
|
|
tree "HDMI PLL"
|
|
group.long 0x200++0x23
|
|
line.long 0x00 "HDMIPLL_PWRCTRL,HDMI PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "HDMIPLL_CLKCTRL,HDMI PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp mode,Stop mode"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "HDMIPLL_TENABLE,HDMI PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "HDMIPLL_TENABLEDIV,HDMI PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "HDMIPLL_M2NDIV,HDMI PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "HDMIPLL_MN2DIV,HDMI PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "HDMIPLL_FRACDIV,HDMI PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "HDMIPLL_BWCTRL,HDMI PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
line.long 0x20 "HDMIPLL_FRACCTRL,HDMI PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
rgroup.long (0x200+0x24)++0x3
|
|
line.long 0x00 "HDMIPLL_STATUS,HDMI PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
width 22.
|
|
tree "AUDIO PLL"
|
|
group.long 0x230++0x23
|
|
line.long 0x00 "AUDIOPLL_PWRCTRL,AUDIO PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "AUDIOPLL_CLKCTRL,AUDIO PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp mode,Stop mode"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "AUDIOPLL_TENABLE,AUDIO PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "AUDIOPLL_TENABLEDIV,AUDIO PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "AUDIOPLL_M2NDIV,AUDIO PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "AUDIOPLL_MN2DIV,AUDIO PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "AUDIOPLL_FRACDIV,AUDIO PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "AUDIOPLL_BWCTRL,AUDIO PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
line.long 0x20 "AUDIOPLL_FRACCTRL,AUDIO PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
rgroup.long (0x230+0x24)++0x3
|
|
line.long 0x00 "AUDIOPLL_STATUS,AUDIO PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
width 22.
|
|
tree "USB PLL"
|
|
group.long 0x260++0x23
|
|
line.long 0x00 "USBPLL_PWRCTRL,USB PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "USBPLL_CLKCTRL,USB PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp mode,Stop mode"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "USBPLL_TENABLE,USB PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "USBPLL_TENABLEDIV,USB PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "USBPLL_M2NDIV,USB PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "USBPLL_MN2DIV,USB PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "USBPLL_FRACDIV,USB PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "USBPLL_BWCTRL,USB PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
line.long 0x20 "USBPLL_FRACCTRL,USB PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
rgroup.long (0x260+0x24)++0x3
|
|
line.long 0x00 "USBPLL_STATUS,USB PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
width 22.
|
|
tree "DDR PLL"
|
|
group.long 0x290++0x23
|
|
line.long 0x00 "DDRPLL_PWRCTRL,DDR PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "DDRPLL_CLKCTRL,DDR PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp mode,Stop mode"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "DDRPLL_TENABLE,DDR PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "DDRPLL_TENABLEDIV,DDR PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "DDRPLL_M2NDIV,DDR PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "DDRPLL_MN2DIV,DDR PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "DDRPLL_FRACDIV,DDR PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "DDRPLL_BWCTRL,DDR PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
line.long 0x20 "DDRPLL_FRACCTRL,DDR PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
rgroup.long (0x290+0x24)++0x3
|
|
line.long 0x00 "DDRPLL_STATUS,DDR PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
else
|
|
width 22.
|
|
tree "DSP PLL"
|
|
group.long 0x80++0x1f
|
|
line.long 0x00 "DSPPLL_PWRCTRL,DSP PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "DSPPLL_CLKCTRL,DSP PLL Clock Control Register"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enable"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "DSPPLL_TENABLE,DSP PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "DSPPLL_TENABLEDIV,DSP PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "DSPPLL_M2NDIV,DSP PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "DSPPLL_MN2DIV,DSP PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "DSPPLL_FRACDIV,DSP PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "DSPPLL_BWCTRL,DSP PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
rgroup.long (0x80+0x24)++0x3
|
|
line.long 0x00 "DSPPLL_STATUS,DSP PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
textline " "
|
|
width 22.
|
|
tree "SGX PLL"
|
|
group.long 0xb0++0x1f
|
|
line.long 0x00 "SGXPLL_PWRCTRL,SGX PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "SGXPLL_CLKCTRL,SGX PLL Clock Control Register"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enable"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "SGXPLL_TENABLE,SGX PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "SGXPLL_TENABLEDIV,SGX PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "SGXPLL_M2NDIV,SGX PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "SGXPLL_MN2DIV,SGX PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "SGXPLL_FRACDIV,SGX PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "SGXPLL_BWCTRL,SGX PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
rgroup.long (0xb0+0x24)++0x3
|
|
line.long 0x00 "SGXPLL_STATUS,SGX PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
textline " "
|
|
width 22.
|
|
tree "ISP PLL"
|
|
group.long 0x140++0x1f
|
|
line.long 0x00 "ISPPLL_PWRCTRL,ISP PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "ISPPLL_CLKCTRL,ISP PLL Clock Control Register"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enable"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "ISPPLL_TENABLE,ISP PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "ISPPLL_TENABLEDIV,ISP PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "ISPPLL_M2NDIV,ISP PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "ISPPLL_MN2DIV,ISP PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "ISPPLL_FRACDIV,ISP PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "ISPPLL_BWCTRL,ISP PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
rgroup.long (0x140+0x24)++0x3
|
|
line.long 0x00 "ISPPLL_STATUS,ISP PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
textline " "
|
|
width 22.
|
|
tree "VIDEO0 PLL"
|
|
group.long 0x1a0++0x1f
|
|
line.long 0x00 "VIDEO0PLL_PWRCTRL,VIDEO0 PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "VIDEO0PLL_CLKCTRL,VIDEO0 PLL Clock Control Register"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enable"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "VIDEO0PLL_TENABLE,VIDEO0 PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "VIDEO0PLL_TENABLEDIV,VIDEO0 PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "VIDEO0PLL_M2NDIV,VIDEO0 PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "VIDEO0PLL_MN2DIV,VIDEO0 PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "VIDEO0PLL_FRACDIV,VIDEO0 PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "VIDEO0PLL_BWCTRL,VIDEO0 PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
rgroup.long (0x1a0+0x24)++0x3
|
|
line.long 0x00 "VIDEO0PLL_STATUS,VIDEO0 PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
textline " "
|
|
width 22.
|
|
tree "VIDEO1 PLL"
|
|
group.long 0x1d0++0x1f
|
|
line.long 0x00 "VIDEO1PLL_PWRCTRL,VIDEO1 PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "VIDEO1PLL_CLKCTRL,VIDEO1 PLL Clock Control Register"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enable"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "VIDEO1PLL_TENABLE,VIDEO1 PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "VIDEO1PLL_TENABLEDIV,VIDEO1 PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "VIDEO1PLL_M2NDIV,VIDEO1 PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "VIDEO1PLL_MN2DIV,VIDEO1 PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "VIDEO1PLL_FRACDIV,VIDEO1 PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "VIDEO1PLL_BWCTRL,VIDEO1 PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
rgroup.long (0x1d0+0x24)++0x3
|
|
line.long 0x00 "VIDEO1PLL_STATUS,VIDEO1 PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
textline " "
|
|
width 22.
|
|
tree "HDMI PLL"
|
|
group.long 0x200++0x1f
|
|
line.long 0x00 "HDMIPLL_PWRCTRL,HDMI PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "HDMIPLL_CLKCTRL,HDMI PLL Clock Control Register"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enable"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "HDMIPLL_TENABLE,HDMI PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "HDMIPLL_TENABLEDIV,HDMI PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "HDMIPLL_M2NDIV,HDMI PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "HDMIPLL_MN2DIV,HDMI PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "HDMIPLL_FRACDIV,HDMI PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "HDMIPLL_BWCTRL,HDMI PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
rgroup.long (0x200+0x24)++0x3
|
|
line.long 0x00 "HDMIPLL_STATUS,HDMI PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
textline " "
|
|
width 22.
|
|
tree "AUDIO PLL"
|
|
group.long 0x230++0x1f
|
|
line.long 0x00 "AUDIOPLL_PWRCTRL,AUDIO PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "AUDIOPLL_CLKCTRL,AUDIO PLL Clock Control Register"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enable"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "AUDIOPLL_TENABLE,AUDIO PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "AUDIOPLL_TENABLEDIV,AUDIO PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "AUDIOPLL_M2NDIV,AUDIO PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "AUDIOPLL_MN2DIV,AUDIO PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "AUDIOPLL_FRACDIV,AUDIO PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "AUDIOPLL_BWCTRL,AUDIO PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
rgroup.long (0x230+0x24)++0x3
|
|
line.long 0x00 "AUDIOPLL_STATUS,AUDIO PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
textline " "
|
|
width 22.
|
|
tree "USB PLL"
|
|
group.long 0x260++0x1f
|
|
line.long 0x00 "USBPLL_PWRCTRL,USB PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "USBPLL_CLKCTRL,USB PLL Clock Control Register"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enable"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "USBPLL_TENABLE,USB PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "USBPLL_TENABLEDIV,USB PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "USBPLL_M2NDIV,USB PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "USBPLL_MN2DIV,USB PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "USBPLL_FRACDIV,USB PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "USBPLL_BWCTRL,USB PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
rgroup.long (0x260+0x24)++0x3
|
|
line.long 0x00 "USBPLL_STATUS,USB PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
textline " "
|
|
width 22.
|
|
tree "DDR PLL"
|
|
group.long 0x290++0x1f
|
|
line.long 0x00 "DDRPLL_PWRCTRL,DDR PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "DDRPLL_CLKCTRL,DDR PLL Clock Control Register"
|
|
bitfld.long 0x04 29. " CLKDCOLDOEN ,Synchronously enables/disables CLKDCOLDO" "Disabled,Enable"
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 19. " CLKOUTLDOEN ,Synchronously enables/disables CLKOUTLDO" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "DDRPLL_TENABLE,DDR PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "DDRPLL_TENABLEDIV,DDR PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "DDRPLL_M2NDIV,DDR PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "DDRPLL_MN2DIV,DDR PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "DDRPLL_FRACDIV,DDR PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "DDRPLL_BWCTRL,DDR PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
rgroup.long (0x290+0x24)++0x3
|
|
line.long 0x00 "DDRPLL_STATUS,DDR PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_OPPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
textline " "
|
|
endif
|
|
width 21.
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0x2c0++0x37
|
|
line.long 0x00 "OSC_SRC,Oscillator Source Register"
|
|
bitfld.long 0x00 31. " GEM_PLL_SOURCE ,GEM ADPLLLJ Source Oscillator Select" "OSC0,OSC1"
|
|
bitfld.long 0x00 30. " SGX_PLL_SOURCE ,SGX ADPLLLJ Source Oscillator Select" "OSC0,OSC1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " HDVICP_PLL_SOURCE ,HDVICP ADPLLLJ Source Oscillator Select" "OSC0,OSC1"
|
|
bitfld.long 0x00 28. " ISP_PLL_SOURCE ,ISP ADPLLLJ Source Oscillator Select" "OSC0,OSC1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DSS_PLL_SOURCE ,DSS ADPLLLJ Source Oscillator Select" "OSC0,OSC1"
|
|
bitfld.long 0x00 26. " USB_PLL_SOURCE ,USB ADPLLLJ Source Oscillator Select" "OSC0,OSC1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DDR_PLL_SOURCE ,DDR ADPLLLJ Source Oscillator Select" "OSC0,OSC1"
|
|
bitfld.long 0x00 24. " AUDIO_PLL_SOURCE ,Audio ADPLLLJ Source Oscillator Select" "OSC0,OSC1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " HDMI_PLL_SOURCE ,HDMI ADPLLLJ Source Oscillator Select" "OSC0,OSC1"
|
|
bitfld.long 0x00 17. " VIDEO1_PLL_SOURCE ,Video1 ADPLLLJ Source Oscillator Select" "OSC0,OSC1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VIDEO0_PLL_SOURCE ,Video0 ADPLLLJ Source Oscillator Select" "OSC0,OSC1"
|
|
bitfld.long 0x00 0. " L3_PLL_SOURCE ,L3 ADPLLLJ Source Oscillator Select" "OSC0,OSC1"
|
|
line.long 0x04 "MPU_CLKSRC,ARM Input Clock Source Register"
|
|
bitfld.long 0x04 0. " MPU_SOURCE ,ARM PLL Source Clock Select" "OSC0,RTC DIVIDER OUTPUT"
|
|
line.long 0x08 "VIDEO_PLL_CLKSRC,VIDEO_PLL Clock Source Register"
|
|
bitfld.long 0x08 24. " HD_VENC_G_CLK_SOURCE ,Hd_venc_g_clk selection of DSS" "VIDEO1_PLL_OUT,VIDEO_PLL_CLK2"
|
|
bitfld.long 0x08 18.--19. " TPPSSSTSO_MUX_SOURCE ,Source of Audio PLL CLK2 input of PRCM" "ISP_PLL_OUT/2,ISP_PLL_OUT,Tsi0_dclk,Tsi2_dclk"
|
|
textline " "
|
|
bitfld.long 0x08 16.--17. " TPPSSSTC0_MUX_SOURCE ,Source of SYSCLK14_MUX" "SYSCLK14,XREF_CLK0,XREF_CLK1,XREF_CLK2"
|
|
bitfld.long 0x08 8.--9. " VIDEO_PLL_OUT_MUX_SOURCE ,Source of VIDEO_PLL_OUT mux" "PLL_VIDEO0_OUT,HDMI_PLL_OUT,PLL_VIDEO1_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0. " VIDEO_PLL_CLK2_SOURCE ,Source of VIDEO_PLL_CLK2" "HDMI PLL CLKOUT,VIDEO_M_PCLK"
|
|
line.long 0x0c "MLB_ATL_CLKSRC,MLB_ATL Input Clock Source Register"
|
|
bitfld.long 0x0c 16.--17. " ATL_SOURCE ,Source clock of the ATL" "SYSCLK19,AUDIO_PLL_OUT,VIDEO_PLL_OUT_MUX,?..."
|
|
bitfld.long 0x0c 0. " MLB_SOURCE ,Source clock of the MLB" "MLB_CLK_INPUT,MLBP_CLK_INPUT"
|
|
line.long 0x10 "MCASP345_AUX_CLKSRC,McASP3/4/5 Aux Clock Source Register"
|
|
bitfld.long 0x10 16.--18. " MCASP5_AUX_SOURCE ,Source clock of the MCASP5 AUX clock" "OUTPUT OF MLB MUX,AUDIO_PLL_OUT,VIDEO_PLL_OUT_MUX,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,?..."
|
|
bitfld.long 0x10 8.--10. " MCASP4_AUX_SOURCE ,Source clock of the MCASP4 AUX clock" "OUTPUT OF MLB MUX,AUDIO_PLL_OUT,VIDEO_PLL_OUT_MUX,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MCASP3_AUX_SOURCE ,Source clock of the MCASP3 AUX clock" "OUTPUT OF MLB MUX,AUDIO_PLL_OUT,VIDEO_PLL_OUT_MUX,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,?..."
|
|
line.long 0x14 "MCASP_AHCLK_CLKSRC,McASP AH Clock Source Register"
|
|
bitfld.long 0x14 25.--27. " MCASP5_AHCLKX_SOURCE ,Source clock of the MCASP5 AH clock transmit" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
bitfld.long 0x14 22.--24. " MCASP4_AHCLKX_SOURCE ,Source clock of the MCASP4 AH clock transmit" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
textline " "
|
|
bitfld.long 0x14 19.--21. " MCASP3_AHCLKX_SOURCE ,Source clock of the MCASP3 AH clock transmit" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
bitfld.long 0x14 16.--18. " MCASP2_AHCLKX_SOURCE ,Source clock of the MCASP2 AH clock transmit" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
textline " "
|
|
bitfld.long 0x14 9.--11. " MCASP1_AHCLKR_SOURCE ,Source clock of the MCASP1 AH clock receive" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
bitfld.long 0x14 6.--8. " MCASP1_AHCLKX_SOURCE ,Source clock of the MCASP1 AH clock transmit" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
textline " "
|
|
bitfld.long 0x14 3.--5. " MCASP0_AHCLKR_SOURCE ,Source clock of the MCASP0 AH clock receive" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
bitfld.long 0x14 0.--2. " MCASP0_AHCLKX_SOURCE ,Source clock of the MCASP0 AH clock transmit" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
line.long 0x18 "MCASP_UART_CLKSRC,McBSP/UART Clock Source Register"
|
|
bitfld.long 0x18 7.--8. " UART5_CLK_SOURCE ,Clock source for UART5" "SYSCLK8,SYSCLK10,SYSCLK6,?..."
|
|
bitfld.long 0x18 5.--6. " UART4_CLK_SOURCE ,Clock source for UART4" "SYSCLK8,SYSCLK10,SYSCLK6,?..."
|
|
textline " "
|
|
bitfld.long 0x18 3.--4. " UART3_CLK_SOURCE ,Clock source for UART3" "SYSCLK8,SYSCLK10,SYSCLK6,?..."
|
|
bitfld.long 0x18 0.--2. " MCBSP_CLKS_SOURCE ,Clock source for McBSP CLKS" "PRCM,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,?..."
|
|
line.long 0x1c "HDMI_I2S_CLKSRC,HDMI I2S Clock Source Register"
|
|
bitfld.long 0x1c 0.--2. " HDMI_I2S_SOURCE ,Clock source for HDMI_I2S clock" "PRCM,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,?..."
|
|
line.long 0x20 "DMTIMER_CLKSRC,DMTIMER Clock Source Register"
|
|
bitfld.long 0x20 25.--27. " DMTIMER7_SOURCE ,Clock source for DMTIMER7 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
bitfld.long 0x20 22.--24. " DMTIMER6_SOURCE ,Clock source for DMTIMER6 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
textline " "
|
|
bitfld.long 0x20 19.--21. " DMTIMER5_SOURCE ,Clock source for DMTIMER5 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
bitfld.long 0x20 16.--18. " DMTIMER4_SOURCE ,Clock source for DMTIMER4 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
textline " "
|
|
bitfld.long 0x20 9.--11. " DMTIMER3_SOURCE ,Clock source for DMTIMER3 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
bitfld.long 0x20 6.--8. " DMTIMER2_SOURCE ,Clock source for DMTIMER2 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
textline " "
|
|
bitfld.long 0x20 3.--5. " DMTIMER1_SOURCE ,Clock source for DMTIMER1 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
bitfld.long 0x20 0.--2. " DMTIMER8_SOURCE ,Clock source for DMTIMER8 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
line.long 0x24 "CLKOUT_MUX,CLKOUT MUX Register"
|
|
bitfld.long 0x24 16.--19. " CLKOUT1_MUX ,Clock source for CLKOUT01" "PRCM_SYSCLK_OUT,SATA SERDES OBS CLK,PCIe SERDES OBS CLK,DSS_DPLL_OUT_DIV2,ISP_DPLL_OUT_DIV2,PLL_L3,OSC0 OUT,OSC1 OUT,Modena Func Clock OUT,SGX_DPLL OUT,RCOSC32K OUT,?..."
|
|
bitfld.long 0x24 0.--3. " CLKOUT0_MUX ,Clock source for CLKOUT0" "PRCM_SYSCLK_OUT,SATA SERDES OBS CLK,PCIe SERDES OBS CLK,DSS_DPLL_OUT_DIV2,ISP_DPLL_OUT_DIV2,PLL_L3,OSC0 OUT,OSC1 OUT,Modena Func Clock OUT,SGX_DPLL OUT,RCOSC32K OUT,?..."
|
|
line.long 0x28 "RMII_REFCLK_SRC,RMII Reference Clock Source Register"
|
|
bitfld.long 0x28 1.--3. " CPTS_RFT_CLK ,Clock source for CPTS_RFT_CLK" "VIDEO0_PLL_OUT,VIDEO1_PLL_OUT,AUDIO_PLL_OUT,VIDEO_PLL_CLK2,L3_PLL OUT,?..."
|
|
bitfld.long 0x28 0. " REFCLK_SOURCE ,Clock source for SYSCLK8" "50MHz,REFCLK PIN"
|
|
line.long 0x2c "SECSS_CLK_SRC,SECSS Clock Source Register"
|
|
bitfld.long 0x2c 0. " SECSSCLK_SOURCE ,Clock source for SECSS" "Ducati/2 CLK,USB_DPLL"
|
|
line.long 0x30 "SYSCLK18_SRC,SYSCLK18 Source Register"
|
|
bitfld.long 0x30 0. " SYSCLK18_SOURCE ,Source of SYSCLK18 input to PRCM" "RTCDIVIDER OUT,CLKIN32 PIN"
|
|
line.long 0x34 "WDT0_CLKSRC,WDT0 Clock Source Register"
|
|
bitfld.long 0x34 0. " WDT0_SOURCE ,Clock source of WDT0" "RTCDIVIDER OUT,RCOSC 32K OUT"
|
|
else
|
|
group.long 0x2c0++0x1b
|
|
line.long 0x00 "OSC_SRC,Oscillator Source Register"
|
|
bitfld.long 0x00 31. " GEM_PLL_SOURCE ,GEM ADPLLLJ Source Oscillator Select" "DEVOSC,AUXOSC"
|
|
bitfld.long 0x00 30. " SGX_PLL_SOURCE ,SGX ADPLLLJ Source Oscillator Select" "DEVOSC,AUXOSC"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ISP_PLL_SOURCE ,ISP ADPLLLJ Source Oscillator Select" "DEVOSC,AUXOSC"
|
|
bitfld.long 0x00 26. " USB_PLL_SOURCE ,USB ADPLLLJ Source Oscillator Select" "DEVOSC,AUXOSC"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DDR_PLL_SOURCE ,DDR ADPLLLJ Source Oscillator Select" "DEVOSC,AUXOSC"
|
|
bitfld.long 0x00 24. " DPLL_AUDIO_SOURCE ,Audio ADPLLLJ Source Oscillator Select" "DEVOSC,AUXOSC"
|
|
textline " "
|
|
bitfld.long 0x00 18. " HDMI_PLL_SOURCE ,HDMI ADPLLLJ Source Oscillator Select" "DEVOSC,AUXOSC"
|
|
bitfld.long 0x00 17. " VIDEO1_PLL_SOURCE ,Video1 ADPLLLJ Source Oscillator Select" "DEVOSC,AUXOSC"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VIDEO0_PLL_SOURCE ,Video0 ADPLLLJ Source Oscillator Select" "DEVOSC,AUXOSC"
|
|
line.long 0x04 "MPU_CLKSRC,ARM Input Clock Source Register"
|
|
bitfld.long 0x04 0. " MPU_SOURCE ,ARM PLL Source Clock Select" "DEVOSC,RTC DIVIDER OUTPUT"
|
|
line.long 0x08 "VIDEO_PLL_CLKSRC,VIDEO_PLL Clock Source Register"
|
|
bitfld.long 0x08 24. " HD_VENC_G_CLK_SOURCE ,Hd_venc_g_clk selection of DSS" "DPLL_VIDEO1,DPLL_HDMI"
|
|
bitfld.long 0x08 8.--9. " VIDEO_PLL_OUT_MUX_SOURCE ,Source of VIDEO_PLL_OUT mux" "DPLL_VIDEO0,DPLL_HDMI,DPLL_VIDEO1,?..."
|
|
line.long 0x0c "MLB_ATL_CLKSRC,MLB_ATL Input Clock Source Register"
|
|
bitfld.long 0x0c 16.--17. " ATL_SOURCE ,Source clock of the ATL" "SYSCLK19,DPLL_AUDIO,VIDEO_PLL_OUT_MUX,?..."
|
|
bitfld.long 0x0c 0. " MLB_SOURCE ,Source clock of the MLB" "MLB_CLK input,MLBP_CLK input"
|
|
line.long 0x10 "MCASP345_AUX_CLKSRC,McASP3/4/5 Aux Clock Source Register"
|
|
bitfld.long 0x10 16.--18. " MCASP5_AUX_SOURCE ,Source clock of the MCASP5 AUX clock" "MLB_SOURCE mux output,DPLL_AUDIO,VIDEO_PLL_OUT_MUX,AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,AUXOSC,?..."
|
|
bitfld.long 0x10 8.--10. " MCASP4_AUX_SOURCE ,Source clock of the MCASP4 AUX clock" "MLB_SOURCE mux outpu,DPLL_AUDIO,VIDEO_PLL_OUT_MUX,AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,AUXOSC,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MCASP3_AUX_SOURCE ,Source clock of the MCASP3 AUX clock" "MLB_SOURCE mux outpu,DPLL_AUDIO,VIDEO_PLL_OUT_MUX,AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,AUXOSC,?..."
|
|
line.long 0x14 "MCASP_AHCLK_CLKSRC,McASP AH Clock Source Register"
|
|
bitfld.long 0x14 25.--27. " MCASP5_AHCLKX_SOURCE ,Source clock of the MCASP5 AH clock transmit" "AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,AUXOSC,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
bitfld.long 0x14 22.--24. " MCASP4_AHCLKX_SOURCE ,Source clock of the MCASP4 AH clock transmit" "AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,AUXOSC,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
textline " "
|
|
bitfld.long 0x14 19.--21. " MCASP3_AHCLKX_SOURCE ,Source clock of the MCASP3 AH clock transmit" "AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,AUXOSC,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
bitfld.long 0x14 16.--18. " MCASP2_AHCLKX_SOURCE ,Source clock of the MCASP2 AH clock transmit" "AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,AUXOSC,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
textline " "
|
|
bitfld.long 0x14 9.--11. " MCASP1_AHCLKR_SOURCE ,Source clock of the MCASP1 AH clock receive" "AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,AUXOSC,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
bitfld.long 0x14 6.--8. " MCASP1_AHCLKX_SOURCE ,Source clock of the MCASP1 AH clock transmit" "AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,AUXOSC,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
textline " "
|
|
bitfld.long 0x14 3.--5. " MCASP0_AHCLKR_SOURCE ,Source clock of the MCASP0 AH clock receive" "AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,AUXOSC,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
bitfld.long 0x14 0.--2. " MCASP0_AHCLKX_SOURCE ,Source clock of the MCASP0 AH clock transmit" "AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,AUXOSC,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
line.long 0x18 "MCASP_UART_CLKSRC,McBSP/UART Clock Source Register"
|
|
bitfld.long 0x18 7.--8. " UART5_CLK_SOURCE ,Clock source for UART5/UART6/UART7" "SYSCLK8,SYSCLK10,SYSCLK6,?..."
|
|
bitfld.long 0x18 5.--6. " UART4_CLK_SOURCE ,Clock source for UART4" "SYSCLK8,SYSCLK10,SYSCLK6,?..."
|
|
textline " "
|
|
bitfld.long 0x18 3.--4. " UART3_CLK_SOURCE ,Clock source for UART3" "SYSCLK8,SYSCLK10,SYSCLK6,?..."
|
|
bitfld.long 0x18 0.--2. " MCBSP_CLKS_SOURCE ,Clock source for McBSP CLKS" "PRCM,AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,AUXOSC,?..."
|
|
group.long 0x2e0++0x17
|
|
line.long 0x00 "DMTIMER_CLKSRC,DMTIMER Clock Source Register"
|
|
bitfld.long 0x00 28.--31. " DMTIMER7_SOURCE ,Clock source for DMTIMER7 clock" "SYSCLK18,AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,DEVOSC,AUXOSC,TCLK in,SYSCLK16,SYSCLK14,?..."
|
|
bitfld.long 0x00 24.--27. " DMTIMER6_SOURCE ,Clock source for DMTIMER6 clock" "SYSCLK18,AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,DEVOSC,AUXOSC,TCLK in,SYSCLK16,SYSCLK14,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DMTIMER5_SOURCE ,Clock source for DMTIMER5 clock" "SYSCLK18,AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,DEVOSC,AUXOSC,TCLK in,SYSCLK16,SYSCLK14,?..."
|
|
bitfld.long 0x00 16.--19. " DMTIMER4_SOURCE ,Clock source for DMTIMER4 clock" "SYSCLK18,AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,DEVOSC,AUXOSC,TCLK in,SYSCLK16,SYSCLK14,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DMTIMER3_SOURCE ,Clock source for DMTIMER3 clock" "SYSCLK18,AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,DEVOSC,AUXOSC,TCLK in,SYSCLK16,SYSCLK14,?..."
|
|
bitfld.long 0x00 8.--11. " DMTIMER2_SOURCE ,Clock source for DMTIMER2 clock" "SYSCLK18,AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,DEVOSC,AUXOSC,TCLK in,SYSCLK16,SYSCLK14,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DMTIMER1_SOURCE ,Clock source for DMTIMER1 clock" "SYSCLK18,AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,DEVOSC,AUXOSC,TCLK in,SYSCLK16,SYSCLK14,?..."
|
|
bitfld.long 0x00 0.--3. " DMTIMER8_SOURCE ,Clock source for DMTIMER8 clock" "SYSCLK18,AUD_CLKIN0,AUD_CLKIN1,AUD_CLKIN2,DEVOSC,AUXOSC,TCLK in,SYSCLK16,SYSCLK14,?..."
|
|
line.long 0x04 "CLKOUT_MUX,CLKOUT MUX Register"
|
|
bitfld.long 0x04 16.--19. " CLKOUT1_MUX ,Clock source for CLKOUT01" "SYSCLK_OUT,Reserved,PCIe SERDES OBS CLK,RTCOSC,Reserved,SYSCLK4,DEVOSC,AUXOSC,Reserved,DPLL_SGX,?..."
|
|
bitfld.long 0x04 0.--3. " CLKOUT0_MUX ,Clock source for CLKOUT0" "SYSCLK_OUT,Reserved,PCIe SERDES OBS CLK,RTCOSC,Reserved,SYSCLK4,DEVOSC,AUXOSC,Reserved,DPLL_SGX,?..."
|
|
line.long 0x08 "RMII_REFCLK_SRC,RMII Reference Clock Source Register"
|
|
bitfld.long 0x08 17. " GMAC_50_CLK_MUX_SEL ,Select the source clock of the GMAC_50_CLK_MUX_SEL" "GMAC_125_CLK /4,GMAC_125_CLK /5"
|
|
bitfld.long 0x08 16. " GMAC_125_CLK_MUX_SEL ,Select the source clock of the GMAC_125_CLK_MUX_SEL" "SYSCLK4,CPTS_RFT_CLK"
|
|
textline " "
|
|
bitfld.long 0x08 1.--3. " CPTS_RFT_CLK ,Clock source for CPTS_RFT_CLK" "DPLL_VIDEO0,DPLL_VIDEO1,DPLL_AUDIO,VIDEO_PLL_CLK2,SYSCLK4,?..."
|
|
bitfld.long 0x08 0. " REFCLK_SOURCE ,Clock source for SYSCLK8" "GMAC_50_CLK_MUX_SEL,EMAC_RMREFCLK PIN"
|
|
line.long 0x0c "SECSS_CLK_SRC,SECSS Clock Source Register"
|
|
bitfld.long 0x0c 0. " SECSSCLK_SOURCE ,Clock source for SECSS" "Ducati/2 CLK,USB_DPLL"
|
|
line.long 0x10 "SYSCLK18_SRC,SYSCLK18 Source Register"
|
|
bitfld.long 0x10 0. " SYSCLK18_SOURCE ,Source of SYSCLK18 input to PRCM" "RTCDIVIDER,RTCOSC PIN"
|
|
line.long 0x14 "WDT0_CLKSRC,WDT0 Clock Source Register"
|
|
bitfld.long 0x14 0. " WDT0_SOURCE ,Clock source of WDT0" "RTCDIVIDER,RTCOSC"
|
|
endif
|
|
group.long 0x320++0x7
|
|
line.long 0x00 "DMTIMER_CLK_CHANGE,DMTimer Clock Change Register"
|
|
rbitfld.long 0x00 15. " DMTIMER7_IDLESTATUS ,IDLE Status for DMTIMER7" "Not idle,Idle"
|
|
rbitfld.long 0x00 14. " DMTIMER6_IDLESTATUS ,IDLE Status for DMTIMER6" "Not idle,Idle"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " DMTIMER5_IDLESTATUS ,IDLE Status for DMTIMER5" "Not idle,Idle"
|
|
rbitfld.long 0x00 12. " DMTIMER4_IDLESTATUS ,IDLE Status for DMTIMER4" "Not idle,Idle"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " DMTIMER3_IDLESTATUS ,IDLE Status for DMTIMER3" "Not idle,Idle"
|
|
rbitfld.long 0x00 10. " DMTIMER2_IDLESTATUS ,IDLE Status for DMTIMER2" "Not idle,Idle"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DMTIMER1_IDLESTATUS ,IDLE Status for DMTIMER1" "Not idle,Idle"
|
|
rbitfld.long 0x00 8. " DMTIMER8_IDLESTATUS ,IDLE Status for DMTIMER0" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMTIMER7_IDLEREQ ,IDLE Request for DMTIMER7" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " DMTIMER6_IDLEREQ ,IDLE Request for DMTIMER6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DMTIMER5_IDLEREQ ,IDLE Request for DMTIMER5" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " DMTIMER4_IDLEREQ ,IDLE Request for DMTIMER4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMTIMER3_IDLEREQ ,IDLE Request for DMTIMER3" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " DMTIMER2_IDLEREQ ,IDLE Request for DMTIMER2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DMTIMER1_IDLEREQ ,IDLE Request for DMTIMER1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " DMTIMER8_IDLEREQ ,IDLE Request for DMTIMER0" "Not requested,Requested"
|
|
line.long 0x04 "DEEPSLEEP_CTRL,DEEPSLEEP Control Register"
|
|
bitfld.long 0x04 17. " DSENABLE ,Deep sleep circuitry enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " DSPOLARITY ,Polarity of DEEPSLEEPZ pin control" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " DSCOUNT ,Number of osc clocks needed to see prior to exiting deep sleep mode"
|
|
rgroup.long 0x328++0x3
|
|
line.long 0x00 "DEEPSLEEP_STATUS,DEEPSLEEP Status Register"
|
|
bitfld.long 0x00 0. " DSCOMPLETE ,Deepsleep completed" "Not completed,Completed"
|
|
width 11.
|
|
tree.end
|
|
tree "PRCM (Power Reset and Clock Management)"
|
|
base ad:0x48180000
|
|
width 21.
|
|
tree "PRM (Power Reset Manager)"
|
|
tree "PRM_DEVICE"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "PRM_RSTCTRL,Software Global Cold and Warm Reset Control Register"
|
|
bitfld.long 0x00 1. " RST_GLOBAL_COLD_SW ,Software Global Cold Reset control" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RST_GLOBAL_WARM_SW ,Software Global Warm Reset control" "No reset,Reset"
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PRM_RSTTIME,Reset Duration Control Register"
|
|
bitfld.long 0x00 8.--12. " RSTTIME2 ,Warm and Local Reset Stall Period Timer duration in PRCM clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RSTTIME1 ,Global POR Stall Period Timer duration in PRCM clock cycles"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PRM_RSTST,Global Reset Sources Register"
|
|
bitfld.long 0x00 9. " ICEPICK_RST ,Emulation Warm Reset event" "No reset,Reset"
|
|
bitfld.long 0x00 5. " EXTERNAL_WARM_RST ,External Warm Reset event" "No reset,Reset"
|
|
bitfld.long 0x00 4. " SECURE_WDT_RST ,Secure Watchdog Reset event" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MPU_WDT_RST ,Watchdog Reset event" "No reset,Reset"
|
|
bitfld.long 0x00 2. " MPU_SECURITY_VIOL_RST ,Security Violation Reset event" "No reset,Reset"
|
|
bitfld.long 0x00 1. " GLOBAL_WARM_SW_RST ,Software Global Warm Reset event" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GLOBAL_COLD_RST ,Power-on Reset (POR) event" "No reset,Reset"
|
|
tree.end
|
|
tree "PRM_ACTIVE"
|
|
group.long 0xa00++0x3
|
|
line.long 0x00 "PM_ACTIVE_PWRSTCTRL,Active Power State Control Register"
|
|
rbitfld.long 0x00 16.--17. " ACTIVE_MEM_ONSTATE ,Active Domain memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request (after a sleep transition)" "Not requested,Requested"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,1,2,ON"
|
|
else
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
|
|
endif
|
|
rgroup.long 0xa04++0x3
|
|
line.long 0x00 "PM_ACTIVE_PWRSTST,Active Power State Status Register"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
|
|
bitfld.long 0x00 4.--5. " ACTIVE_MEM_STATEST ,Active domain memory state status" "OFF,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,1,2,ON"
|
|
else
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
|
|
endif
|
|
group.long 0xa10++0x7
|
|
line.long 0x00 "RM_ACTIVE_RSTCTRL,Active Domain Resets Control Register"
|
|
bitfld.long 0x00 1. " GEM_SW_RST ,ACTIVE Domain GEM warm reset control" "No reset,Reset"
|
|
bitfld.long 0x00 0. " GEM_LRST ,ACTIVE Domain GEM local reset control" "No reset,Reset"
|
|
line.long 0x04 "RM_ACTIVE_RSTST,Active Domain Reset Sources Register"
|
|
bitfld.long 0x04 4. " EMULATION_GEM_RST ,GEM Local CPU reset due to emulation reset source" "No reset,Reset"
|
|
bitfld.long 0x04 3. " GEM_LRST_REQ ,Local Reset request (by GEM)" "Not requested,Requested"
|
|
bitfld.long 0x04 1. " GEM_GRST ,GEM warm reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 0. " GEM_LRST ,GEM local SW reset" "No reset,Reset"
|
|
tree.end
|
|
tree "PRM_DEFAULT"
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0xb00++0x7
|
|
line.long 0x00 "RM_DEFAULT_RSTCTRL,Default Domain Resets Control Register"
|
|
bitfld.long 0x00 7. " PCI_LRST ,ACTIVE domain PCI Local reset control" "No reset,Reset"
|
|
bitfld.long 0x00 4. " DUCATI_RST3 ,Ducati logic and MMU reset contro" "No reset,Reset"
|
|
bitfld.long 0x00 3. " DUCATI_M3_RST2 ,Ducati Second M3 reset control" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DUCATI_M3_RST1 ,Ducati First M3 reset control" "No reset,Reset"
|
|
bitfld.long 0x00 1. " TPPSS_SW_RST ,DEFAUL Domain TPPSS reset control" "No reset,Reset"
|
|
bitfld.long 0x00 0. " TPPSS_LRST ,DEFAUL Domain TPPSS ARM local reset control" "No reset,Reset"
|
|
line.long 0x04 "RM_DEFAULT_RSTST,Default Domain Reset Sources Register"
|
|
bitfld.long 0x04 14. " ICECRUSHER_M3_2_RST ,DSS controller M3_2 reset due to ICECRUSHER1 reset" "No reset,Reset"
|
|
bitfld.long 0x04 13. " ICECRUSHER_M3_1_RST ,DSS controller M3_1 reset due to ICECRUSHER1 reset" "No reset,Reset"
|
|
bitfld.long 0x04 12. " EMULATION_M3_2_RST ,DSS controller M3_2 reset due to emulation reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EMULATION_M3_1_RST ,DSS controller M3_1 reset due to emulation reset" "No reset,Reset"
|
|
bitfld.long 0x04 10. " ICECRUSHER_TPPSS_RST ,TPPSS local ARM reset due to ICECRUSHER reset" "No reset,Reset"
|
|
bitfld.long 0x04 9. " EMULATION_TPPSS_RST ,TPPSS local ARM reset due to emulation reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PCI_LRST ,PCI local SW reset" "No reset,Reset"
|
|
bitfld.long 0x04 4. " DUCATI_RST3 ,Ducati logic and MMU SW reset" "No reset,Reset"
|
|
bitfld.long 0x04 3. " DUCATI_M3_RST2 ,Ducati second M3 SW reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DUCATI_M3_RST1 ,Ducati first cortex M3 SW reset" "No reset,Reset"
|
|
bitfld.long 0x04 1. " TPPSS_RST ,TPPSS SW reset" "No reset,Reset"
|
|
bitfld.long 0x04 0. " TPPSS_LRST ,TPPSS local ARM SW reset" "No reset,Reset"
|
|
else
|
|
group.long 0xb00++0x03
|
|
line.long 0x00 "PM_DEFAULT_PWRSTCTRL,Default Power State Control Register"
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,OFF"
|
|
group.long 0xb10++0x07
|
|
line.long 0x00 "RM_DEFAULT_RSTCTRL,Default Domain Resets Control Register"
|
|
bitfld.long 0x00 7. " PCI_LRST ,ACTIVE domain PCI Local reset control" "No reset,Reset"
|
|
bitfld.long 0x00 4. " DUCATI_RST3 ,Ducati logic and MMU reset contro" "No reset,Reset"
|
|
bitfld.long 0x00 3. " DUCATI_M3_RST2 ,Ducati Second M3 reset control" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DUCATI_M3_RST1 ,Ducati First M3 reset control" "No reset,Reset"
|
|
line.long 0x04 "RM_DEFAULT_RSTST,Default Domain Reset Sources Register"
|
|
bitfld.long 0x04 14. " ICECRUSHER_M3_2_RST ,DSS controller M3_2 reset due to ICECRUSHER1 reset" "No reset,Reset"
|
|
bitfld.long 0x04 13. " ICECRUSHER_M3_1_RST ,DSS controller M3_1 reset due to ICECRUSHER1 reset" "No reset,Reset"
|
|
bitfld.long 0x04 12. " EMULATION_M3_2_RST ,DSS controller M3_2 reset due to emulation reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EMULATION_M3_1_RST ,DSS controller M3_1 reset due to emulation reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PCI_LRST ,PCI local SW reset" "No reset,Reset"
|
|
bitfld.long 0x04 4. " DUCATI_RST3 ,Ducati logic and MMU SW reset" "No reset,Reset"
|
|
bitfld.long 0x04 3. " DUCATI_M3_RST2 ,Ducati second M3 SW reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DUCATI_M3_RST1 ,Ducati first cortex M3 SW reset" "No reset,Reset"
|
|
endif
|
|
tree.end
|
|
sif (!cpuis("DRA62*"))
|
|
tree "PRM_HDVICP"
|
|
group.long 0xc00++0x3
|
|
line.long 0x00 "PM_HDVICP_PWRSTCTRL,HDVICP Power State Control Register"
|
|
bitfld.long 0x00 16.--17. " HDVICP_MEM_ONSTATE ,HDVICP memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request (after a sleep transition)" "Not requested,Requested"
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
|
|
rgroup.long 0xc04++0x3
|
|
line.long 0x00 "PM_HDVICP_PWRSTST,HDVICP Power Domain State Status Register"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
|
|
bitfld.long 0x00 4.--5. " HDVICP_MEM_STATEST ,HDVICP memory state status" "OFF,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
|
|
group.long 0xc10++0x7
|
|
line.long 0x00 "RM_HDVICP_RSTCTRL,HDVICP Domain Resets Control Register"
|
|
bitfld.long 0x00 2. " HDVICP_RST3 ,HDVICP logic and SL2 reset control" "No reset,Reset"
|
|
bitfld.long 0x00 1. " HDVICP_RST2 ,HDVICP sequencer2 reset control" "No reset,Reset"
|
|
bitfld.long 0x00 0. " HDVICP_RST1 ,HDVICP sequencer1 reset control" "No reset,Reset"
|
|
line.long 0x04 "RM_HDVICP_RSTST,HDVICP Domain Reset Sources Register"
|
|
bitfld.long 0x04 6. " ICECRUSHER_SEQ2_RST2 ,Sequencer2 CPU reset due to ICECRUSHER1 reset" "No reset,Reset"
|
|
bitfld.long 0x04 5. " ICECRUSHER_SEQ1_RST1 ,Sequencer1 CPU reset due to ICECRUSHER1 reset" "No reset,Reset"
|
|
bitfld.long 0x04 4. " EMULATION_SEQ2_RST2 ,Sequencer2 CPU reset due to emulation reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EMULATION_SEQ1_RST1 ,Sequencer1 CPU reset due to emulation reset" "No reset,Reset"
|
|
bitfld.long 0x04 2. " HDVICP_RST3 ,HDVICP logic and SL2 SW reset" "No reset,Reset"
|
|
bitfld.long 0x04 1. " HDVICP_RST2 ,HDVICP Sequencer2 CPU SW reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 0. " HDVICP_RST1 ,HDVICP Sequencer1 CPU SW reset" "No reset,Reset"
|
|
tree.end
|
|
tree "PRM_ISP"
|
|
group.long 0xd00++0x3
|
|
line.long 0x00 "PM_ISP_PWRSTCTRL,ISP Power State Control Register"
|
|
bitfld.long 0x00 16.--17. " ISP_MEM_ONSTATE ,ISP memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request (after a sleep transition)" "Not requested,Requested"
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
|
|
rgroup.long 0xd04++0x3
|
|
line.long 0x00 "PM_ISP_PWRSTST,ISP Power Domain State Status Register"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
|
|
bitfld.long 0x00 4.--5. " ISP_MEM_STATEST ,ISP memory state status" "OFF,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
|
|
group.long 0xd10++0x7
|
|
line.long 0x00 "RM_ISP_RSTCTRL,ISP Domain Resets Control Register"
|
|
bitfld.long 0x00 2. " ISP_RST ,ISP logic reset control" "No reset,Reset"
|
|
line.long 0x04 "RM_ISP_RSTST,ISP Domain Reset Sources Register"
|
|
bitfld.long 0x04 2. " ISP_RST ,ISP logic and FDIF SW reset" "No reset,Reset"
|
|
tree.end
|
|
endif
|
|
tree "PRM_DSS"
|
|
group.long 0xe00++0x3
|
|
line.long 0x00 "PM_DSS_PWRSTCTRL,DSS Power State Control Register"
|
|
bitfld.long 0x00 16.--17. " DSS_MEM_ONSTATE ,DSS memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request (after a sleep transition)" "Not requested,Requested"
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
|
|
rgroup.long 0xe04++0x3
|
|
line.long 0x00 "PM_DSS_PWRSTST,DSS Power Domain State Status Register"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
|
|
bitfld.long 0x00 4.--5. " DSS_MEM_STATEST ,DSS memory state status" "OFF,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
|
|
group.long 0xe10++0x7
|
|
line.long 0x00 "RM_DSS_RSTCTRL,DSS Domain Resets Control Register"
|
|
bitfld.long 0x00 2. " DSS_RST ,DSS and HDMI reset control" "No reset,Reset"
|
|
line.long 0x04 "RM_DSS_RSTST,DSS Domain Reset Sources Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x04 2. " DSS_RST ,DSS logic and HDMI SW reset" "No reset,Reset"
|
|
else
|
|
bitfld.long 0x04 2. " DSS_RST ,DSS and HDMI logic and FDIF SW reset" "No reset,Reset"
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="DRA623"&&cpu()!="DRA623DSP")
|
|
tree "PRM_SGX"
|
|
group.long 0xf00++0x7
|
|
line.long 0x00 "PM_SGX_PWRSTCTRL,SGX Power State Control Register"
|
|
rbitfld.long 0x00 16.--17. " SGX_MEM_ONSTATE ,SGX memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request (after a sleep transition)" "Not requested,Requested"
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
|
|
line.long 0x04 "RM_SGX_RSTCTRL,SGX Domain Resets Control Register"
|
|
bitfld.long 0x04 0. " SGX_RST ,SGX local reset control" "No reset,Reset"
|
|
rgroup.long 0xf10++0x3
|
|
line.long 0x00 "PM_SGX_PWRSTST,SGX Power Domain State Status Register"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
|
|
bitfld.long 0x00 4.--5. " SGX_MEM_STATEST ,SGX memory state status" "OFF,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
|
|
group.long 0xf14++0x3
|
|
line.long 0x00 "RM_SGX_RSTST,SGX Domain Reset Sources Register"
|
|
bitfld.long 0x00 0. " SGX_RST ,SGX Domain Logic SW Reset" "No reset,Reset"
|
|
tree.end
|
|
endif
|
|
tree "PRM_ALWON"
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0x1800++0x03
|
|
else
|
|
group.long 0x1814++0x03
|
|
endif
|
|
line.long 0x00 "RM_ALWON_RSTST,ALWAYS ON Domain Reset Sources Register"
|
|
eventfld.long 0x00 7. " ICECRUSHER_SEC_M3_RST ,Security SS Local M3 reset due to ICECRUSHER reset" "No reset,Reset"
|
|
eventfld.long 0x00 6. " ICECRUSHER_MPU_RST ,MPU Processor reset due to ICECRUSHER1 reset" "No reset,Reset"
|
|
eventfld.long 0x00 5. " EMULATION_MPU_RST ,MPU Processor reset due to emulation reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 4. " EMULATION_SEC_M3_RST ,Security SS Local M3 reset due to emulation reset" "No reset,Reset"
|
|
tree.end
|
|
tree.end
|
|
tree "CM (Clock Manager)"
|
|
tree "CM_DEVICE"
|
|
width 16.
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "CM_CLKOUT_CTRL,SYS_CLKOUT Output Control Register"
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x00 7. " CLKOUT2EN ,SYS_CLKOUT2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--5. " CLKOUT2DIV ,Clock division factor" "/1,/2,/4,/8,/16,?..."
|
|
bitfld.long 0x00 0.--1. " CLKOUT2SOURCE ,External output clock source" "PLL_DSP,PLL_HDVICP,PLL_VIDEO0,RTCDIVIDER"
|
|
else
|
|
bitfld.long 0x00 7. " CLKOUTEN ,External Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--5. " CLKOUTDIV ,Clock division factor" "/1,/2,/4,/8,/16,?..."
|
|
bitfld.long 0x00 0.--1. " CLKOUTSOURCE ,External output clock source" "DPLL_DSP,DPLL_ARM,DPLL_VIDEO0,RTCDIVIDER"
|
|
endif
|
|
tree.end
|
|
tree "CM_DPLL"
|
|
width 27.
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0x300++0x3
|
|
line.long 0x00 "CM_SYSCLK3_CLKSEL,SYSCLK3 Clock Select Register"
|
|
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value B for SYSCLK3 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
endif
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0x31c++0x3
|
|
else
|
|
group.long 0x324++0x3
|
|
endif
|
|
line.long 0x00 "CM_SYSCLK10_CLKSEL,SYSCLK10 Clock Select Register"
|
|
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value B for SYSCLK10 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0x338++0x1f
|
|
line.long 0x00 "CM_VPB3_CLKSEL,Video PLL B3 Clock Select Register"
|
|
bitfld.long 0x00 0.--1. " CLKSEL ,Divider value B3 for PLL_VIDEO2 select" "/1,/2,/22,?..."
|
|
line.long 0x04 "CM_VPC1_CLKSEL,Video PLL C1 Clock Select Register"
|
|
bitfld.long 0x04 0.--1. " CLKSEL ,Divider value C1 for PLL_VIDEO1 select" "/1,/2,/22,?..."
|
|
line.long 0x08 "CM_VPD1_CLKSEL,Video PLL D1 Clock Select Register"
|
|
bitfld.long 0x08 0.--2. " CLKSEL ,Divider value D1 for PLL_VIDEO0 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x0c "CM_SYSCLK19_CLKSEL,SYSCLK19 Clock Select Register"
|
|
bitfld.long 0x0c 0.--2. " CLKSEL ,Divider value B for SYSCLK19 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x10 "CM_SYSCLK20_CLKSEL,SYSCLK20 Clock Select Register"
|
|
bitfld.long 0x10 0.--2. " CLKSEL ,Divider value C for SYSCLK20 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x14 "CM_SYSCLK21_CLKSEL,SYSCLK21 Clock Select Register"
|
|
bitfld.long 0x14 0.--2. " CLKSEL ,Divider value D for SYSCLK21 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x18 "CM_SYSCLK22_CLKSEL,SYSCLK22 Clock Select Register"
|
|
bitfld.long 0x18 0.--2. " CLKSEL ,Divider value D for SYSCLK22 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x1c "CM_APA_CLKSEL,Audio PLL A Clock Select Register"
|
|
bitfld.long 0x1c 0.--2. " CLKSEL ,Divider value Audio PLL A divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
else
|
|
group.long 0x340++0x17
|
|
line.long 0x00 "CM_VPB3_CLKSEL,Video PLL B3 Clock Select Register"
|
|
bitfld.long 0x00 0.--1. " CLKSEL ,Divider value B3 for PLL_VIDEO2 select" "/1,/2,/22,?..."
|
|
line.long 0x04 "CM_VPC1_CLKSEL,Video PLL C1 Clock Select Register"
|
|
bitfld.long 0x04 0.--1. " CLKSEL ,Divider value C1 for PLL_VIDEO1 select" "/1,/2,/22,?..."
|
|
line.long 0x08 "CM_VPD1_CLKSEL,Video PLL D1 Clock Select Register"
|
|
bitfld.long 0x08 0.--2. " CLKSEL ,Divider value D1 for PLL_VIDEO0 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x0c "CM_SYSCLK19_CLKSEL,SYSCLK19 Clock Select Register"
|
|
bitfld.long 0x0c 0.--2. " CLKSEL ,Divider value B for SYSCLK19 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x10 "CM_SYSCLK20_CLKSEL,SYSCLK20 Clock Select Register"
|
|
bitfld.long 0x10 0.--2. " CLKSEL ,Divider value C for SYSCLK20 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x14 "CM_SYSCLK21_CLKSEL,SYSCLK21 Clock Select Register"
|
|
bitfld.long 0x14 0.--2. " CLKSEL ,Divider value D for SYSCLK21 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
group.long 0x35c++0x03
|
|
line.long 0x00 "CM_APA_CLKSEL,Audio PLL A Clock Select Register"
|
|
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value Audio PLL A divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
endif
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0x368++0x1b
|
|
line.long 0x00 "CM_SYSCLK14_CLKSEL,SYSCLK14 Clock Source Select Register"
|
|
bitfld.long 0x00 0.--1. " CLKSEL ,Clock source for SYSCLK14 select" "B3 div,CLKIN,C1 div,?..."
|
|
line.long 0x04 "CM_SYSCLK16_CLKSEL,SYSCLK16 Clock Source Select Register"
|
|
bitfld.long 0x04 0. " CLKSEL ,Clock source for SYSCLK16 select" "D1 div,B3 div"
|
|
line.long 0x08 "CM_SYSCLK18_CLKSEL,SYSCLK18 Clock Source Select Register"
|
|
bitfld.long 0x08 0. " CLKSEL ,Clock source for SYSCLK18 select" "32 Khz Clock,Audio PLL"
|
|
line.long 0x0c "CM_AUDIOCLK_MCASP0_CLKSEL,McASP0 Audio Clock Source Select Register"
|
|
bitfld.long 0x0c 0.--1. " CLKSEL ,Clock source for McASP0 audio clock select" "SYSCLK20,SYSCLK21,SYSCLK22,?..."
|
|
line.long 0x10 "CM_AUDIOCLK_MCASP1_CLKSEL,McASP1 Audio Clock Source Select Register"
|
|
bitfld.long 0x10 0.--1. " CLKSEL ,Clock source for McASP1 audio clock select" "SYSCLK20,SYSCLK21,SYSCLK22,?..."
|
|
line.long 0x14 "CM_AUDIOCLK_MCASP2_CLKSEL,McASP2 Audio Clock Source Select Register"
|
|
bitfld.long 0x14 0.--1. " CLKSEL ,Clock source for McASP2 audio clock select" "SYSCLK20,SYSCLK21,SYSCLK22,?..."
|
|
line.long 0x18 "CM_AUDIOCLK_MCBSP_CLKSEL,McBSP Audio Clock Source Select Register"
|
|
bitfld.long 0x18 0.--1. " CLKSEL ,Clock source for McBSP audio clock multiplexor with in PRCM" "SYSCLK20,SYSCLK21,SYSCLK22,CLKS"
|
|
group.long 0x388++0x23
|
|
line.long 0x00 "CM_TIMER1_CLKSEL,TIMER1 Clock Source Select Register"
|
|
bitfld.long 0x00 0.--1. " CLKSEL ,Clock source for TIMER1 clock select" "TCLKIN,External 32Khz clock,CLKIN,?..."
|
|
line.long 0x04 "CM_TIMER2_CLKSEL,TIMER2 Clock Source Select Register"
|
|
bitfld.long 0x04 0.--1. " CLKSEL ,Clock source for TIMER2 clock select" "TCLKIN,External 32Khz clock,CLKIN,?..."
|
|
line.long 0x08 "CM_TIMER3_CLKSEL,TIMER3 Clock Source Select Register"
|
|
bitfld.long 0x08 0.--1. " CLKSEL ,Clock source for TIMER3 clock select" "TCLKIN,External 32Khz clock,CLKIN,?..."
|
|
line.long 0x0c "CM_TIMER4_CLKSEL,TIMER4 Clock Source Select Register"
|
|
bitfld.long 0x0c 0.--1. " CLKSEL ,Clock source for TIMER4 clock select" "TCLKIN,External 32Khz clock,CLKIN,?..."
|
|
line.long 0x10 "CM_TIMER5_CLKSEL,TIMER5 Clock Source Select Register"
|
|
bitfld.long 0x10 0.--1. " CLKSEL ,Clock source for TIMER5 clock select" "TCLKIN,External 32Khz clock,CLKIN,?..."
|
|
line.long 0x14 "CM_TIMER6_CLKSEL,TIMER6 Clock Source Select Register"
|
|
bitfld.long 0x14 0.--1. " CLKSEL ,Clock source for TIMER6 clock select" "TCLKIN,External 32Khz clock,CLKIN,?..."
|
|
line.long 0x18 "CM_TIMER7_CLKSEL,TIMER7 Clock Source Select Register"
|
|
bitfld.long 0x18 0.--1. " CLKSEL ,Clock source for TIMER7 clock select" "TCLKIN,External 32Khz clock,CLKIN,?..."
|
|
line.long 0x1c "CM_HDMI_CLKSEL,HDMI Audio Clock Source Select Register"
|
|
bitfld.long 0x1c 0.--1. " CLKSEL ,Clock source for HDMI audio clock select" "SYSCLK20,SYSCLK21,SYSCLK22,?..."
|
|
line.long 0x20 "CM_SYSCLK23_CLKSEL,SYSCLK23 Clock Select Register"
|
|
bitfld.long 0x20 0.--2. " CLKSEL ,Divider value D for SYSCLK23 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
else
|
|
group.long 0x370++0x1b
|
|
line.long 0x00 "CM_SYSCLK14_CLKSEL,SYSCLK14 Clock Source Select Register"
|
|
bitfld.long 0x00 0.--1. " CLKSEL ,Clock source for SYSCLK14 select" "B3 div,DEV clock,C1 div,?..."
|
|
line.long 0x04 "CM_SYSCLK16_CLKSEL,SYSCLK16 Clock Source Select Register"
|
|
bitfld.long 0x04 0. " CLKSEL ,Clock source for SYSCLK16 select" "D1 div,B3 div"
|
|
line.long 0x08 "CM_SYSCLK18_CLKSEL,SYSCLK18 Clock Source Select Register"
|
|
bitfld.long 0x08 0. " CLKSEL ,Clock source for SYSCLK18 select" "Mux,A div"
|
|
line.long 0x0c "CM_AUDIOCLK_MCASP0_CLKSEL,McASP0 Audio Clock Source Select Register"
|
|
bitfld.long 0x0c 0.--1. " CLKSEL ,Clock source for McASP0 audio clock select" "SYSCLK20,SYSCLK21,?..."
|
|
line.long 0x10 "CM_AUDIOCLK_MCASP1_CLKSEL,McASP1 Audio Clock Source Select Register"
|
|
bitfld.long 0x10 0.--1. " CLKSEL ,Clock source for McASP1 audio clock select" "SYSCLK20,SYSCLK21,?..."
|
|
line.long 0x14 "CM_AUDIOCLK_MCASP2_CLKSEL,McASP2 Audio Clock Source Select Register"
|
|
bitfld.long 0x14 0.--1. " CLKSEL ,Clock source for McASP2 audio clock select" "SYSCLK20,SYSCLK21,?..."
|
|
line.long 0x18 "CM_AUDIOCLK_MCBSP_CLKSEL,McBSP Audio Clock Source Select Register"
|
|
bitfld.long 0x18 0.--1. " CLKSEL ,Clock source for McBSP audio clock multiplexor with in PRCM" "SYSCLK20,SYSCLK21,?..."
|
|
group.long 0x3b0++0x03
|
|
line.long 0x00 "CM_SYSCLK23_CLKSEL,SYSCLK23 Clock Select Register"
|
|
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value D for SYSCLK23 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
endif
|
|
tree.end
|
|
tree "CM_ACTIVE"
|
|
width 23.
|
|
group.long 0x400++0x3
|
|
line.long 0x00 "CM_GEM_CLKSTCTRL,GEM Clock Domain State Transitions Control Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,GEM clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
|
|
else
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,GEM clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
endif
|
|
group.long 0x420++0x3
|
|
line.long 0x00 "CM_ACTIVE_GEM_CLKCTRL,GEM Clocks Control Register"
|
|
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
tree "CM_DEFAULT"
|
|
sif (!cpuis("DRA62*"))
|
|
width 29.
|
|
group.long 0x500++0x07
|
|
line.long 0x00 "CM_DEFAULT_TPPSS_CLKSTCTRL,TPPSS Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 14. " CLKACTIVITY_TPPSS_SYSCLK_EN ,State of the TPPSS_SYSCLK_EN clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLKACTIVITY_TPPSS_MTS_GCLK ,State of the TPPSS_MTS_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CLKACTIVITY_TPPSS_TOUT_GCLK ,State of the TPPSS_TOUT_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLKACTIVITY_TPPSS_STC1_GCLK ,State of the TPPSS_STC1_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CLKACTIVITY_TPPSS_STC0_GCLK ,State of the TPPSS_STC0_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKACTIVITY_TPPSS_ARM_GCLK ,State of the TPPSS_ARM_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKACTIVITY_TPPSS_SYS_GCLK ,State of the TPPSS_SYS_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,TPPSS clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
width 29.
|
|
line.long 0x04 "CM_DEFAULT_PCI_CLKSTCTRL,PCI Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x04 0.--1. " CLKTRCTRL ,PCI clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
group.long 0x50c++0x03
|
|
line.long 0x00 "CM_DEFAULT_DUCATI_CLKSTCTRL,DUCATI Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,DUCATI clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
group.long 0x51c++0x3
|
|
line.long 0x00 "CM_DEFAULT_DMM_CLKCTRL,DMM Clocks Control Register"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x548++0x7
|
|
line.long 0x00 "CM_DEFAULT_TPPSS_CLKCTRL,TPPSS Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_DEFAULT_USB_CLKCTRL,USB Clocks Control Register"
|
|
bitfld.long 0x04 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x554++0x3
|
|
line.long 0x00 "CM_DEFAULT_SATA_CLKCTRL,SATA Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x568++0x7
|
|
line.long 0x00 "CM_DEFAULT_DUCATI_CLKCTRL,DUCATI Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_DEFAULT_PCI_CLKCTRL,PCI Clocks Control Register"
|
|
bitfld.long 0x04 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
else
|
|
width 29.
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "CM_DEFAULT_PCI_CLKSTCTRL,PCI Clock Domain State Transitions Control Register"
|
|
rbitfld.long 0x00 8. " CLKACTIVITY_PCI_GCL ,State of the PCI_GCLK clock in the domain" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the PCI clock domain" "Reserved,SW_SLEEP,SW_WKUP,?..."
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "CM_DEFAULT_DUCATI_CLKSTCTRL,DUCATI Clock Domain State Transitions Control Register"
|
|
rbitfld.long 0x00 9. " CLKACTIVITY_DUCATI_GCLKIN200TR ,State of the CLKIN200TR clock in the domain" "Gated,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " CLKACTIVITY_DUCATI_GCLKINTR ,State of the CLKINTR clock in the domain" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,State transition of the DUCATI clock domains" "Reserved,SW_SLEEP,SW_WKUP,?..."
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "CM_DEFAULT_USB_CLKCTRL,USB Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "CM_DEFAULT_DUCATI_CLKCTRL,DUCATI Clocks Control Register"
|
|
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "CM_DEFAULT_PCI_CLKCTRL,PCI Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
endif
|
|
tree.end
|
|
sif (!cpuis("DRA62*"))
|
|
tree "CM_HDVICP"
|
|
width 24.
|
|
group.long 0x600++0x3
|
|
line.long 0x00 "CM_HDVICP_CLKSTCTRL,HDVICP Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_HDVICP_GCLK ,State of the HDVICP_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,HDVICP clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
width 24.
|
|
group.long 0x620++0x7
|
|
line.long 0x00 "CM_HDVICP_CLKCTRL,HDVICP Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_HDVICP_SL2_CLKCTRL,SL2 Clocks Control Register"
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
tree "CM_ISP"
|
|
width 24.
|
|
group.long 0x700++0x3
|
|
line.long 0x00 "CM_ISP_CLKSTCTRL,ISP Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,ISP clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
group.long 0x720++0x7
|
|
line.long 0x00 "CM_ISP_ISP_CLKCTRL,ISP Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_ISP_FDIF_CLKCTRL,FDIF Clocks Control Register"
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
endif
|
|
tree "CM_DSS"
|
|
width 21.
|
|
group.long 0x800++0x3
|
|
line.long 0x00 "CM_DSS_CLKSTCTRL,DSS Clock Domain State Transitions Control Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,DSS clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
|
|
else
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,DSS clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
endif
|
|
group.long 0x820++0x7
|
|
line.long 0x00 "CM_DSS_DSS_CLKCTRL,DSS Clocks Control Register"
|
|
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_DSS_HDMI_CLKCTRL,HDMI Clocks Control Register"
|
|
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
sif (cpu()!="DRA623"&&cpu()!="DRA623DSP")
|
|
tree "CM_SGX"
|
|
width 24.
|
|
group.long 0x900++0x3
|
|
line.long 0x00 "CM_SGX_CLKSTCTRL,GFX Clock Domain State Transitions Control Register"
|
|
rbitfld.long 0x00 8. " CLKACTIVITY_GFX_GCLK ,State of the GFX_GCLK clock" "Gated,Active"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,GFX clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
|
|
else
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,GFX clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
endif
|
|
group.long 0x920++0x3
|
|
line.long 0x00 "CM_SGX_SGX_CLKCTRL,GFX Clocks Control Register"
|
|
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
endif
|
|
tree "CM_ALWON"
|
|
width 30.
|
|
group.long 0x1400++0x7
|
|
line.long 0x00 "CM_ALWON_L3_SLOW_CLKSTCTRL,L3_SLOW Clock Domain State Transitions Control Register"
|
|
rbitfld.long 0x00 27. " CLKACTIVITY_SDIO_CLKADPI_GCLK ,State of the SDIO_ADPI clock" "Gated,Active"
|
|
rbitfld.long 0x00 26. " CLKACTIVITY_TIMER7_GCLK ,State of the TIMER7 clock" "Gated,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " CLKACTIVITY_TIMER6_GCLK ,State of the TIMER6 clock" "Gated,Active"
|
|
rbitfld.long 0x00 24. " CLKACTIVITY_TIMER5_GCLK ,State of the TIMER5 clock" "Gated,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " CLKACTIVITY_TIMER4_GCLK ,State of the TIMER4 clock" "Gated,Active"
|
|
rbitfld.long 0x00 22. " CLKACTIVITY_TIMER3_GCLK ,State of the TIMER3 clock" "Gated,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " CLKACTIVITY_TIMER2_GCLK ,State of the TIMER2 clock" "Gated,Active"
|
|
rbitfld.long 0x00 20. " CLKACTIVITY_TIMER1_GCLK ,State of the TIMER1 clock" "Gated,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " CLKACTIVITY_TIMER0_GCLK ,State of the TIMER0 clock" "Gated,Active"
|
|
rbitfld.long 0x00 17. " CLKACTIVITY_SPI_GSYSCLK ,State of the SPI_GSYSCLK clock" "Gated,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " CLKACTIVITY_I2C_GSYSCLK ,State of the I2C_GSYSCLK clock" "Gated,Active"
|
|
rbitfld.long 0x00 15. " CLKACTIVITY_GPIO_1_GDBCLK ,State of the GPIO_GDBCLK clock" "Gated,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 14. " CLKACTIVITY_GPIO_0_GDBCLK ,State of the GPIO_GDBCLK clock" "Gated,Active"
|
|
rbitfld.long 0x00 13. " CLKACTIVITY_UART_GFCLK ,State of the UART_GFCLK clock" "Gated,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " CLKACTIVITY_MCBSP_AUX_GCLK ,State of the MCBSP_AUX_GCLK clock" "Gated,Active"
|
|
rbitfld.long 0x00 11. " CLKACTIVITY_MCASP2_AUX_GCLK ,State of the MCASP2_AUX_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " CLKACTIVITY_MCASP1_AUX_GCLK ,State of the MCASP1_AUX_GCLK clock" "Gated,Active"
|
|
rbitfld.long 0x00 9. " CLKACTIVITY_MCASP0_AUX_GCLK ,State of the MCASP0_AUX_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3_SLOW clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
|
|
else
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3_SLOW clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
endif
|
|
line.long 0x04 "CM_ETHERNET_CLKSTCTRL,ETHERNET Clock Domain State Transitions Control Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x04 0.--1. " CLKTRCTRL ,ETHERNET clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
|
|
else
|
|
bitfld.long 0x04 0.--1. " CLKTRCTRL ,ETHERNET clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
endif
|
|
rgroup.long 0x1408++0x3
|
|
line.long 0x00 "CM_ALWON_L3_MED_CLKSTCTRL,L3_MED Clock Domain State Transitions Control Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3 Medium clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
|
|
else
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3 Medium clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
endif
|
|
group.long 0x140c++0xf
|
|
line.long 0x00 "CM_MMU_CLKSTCTRL,MMU Clock Domain State Transitions Control Register"
|
|
rbitfld.long 0x00 8. " CLKACTIVITY_MMU_GCLK ,State of the MMU_GICLK clock" "Gated,Active"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,MMU clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
|
|
else
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,MMU clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
endif
|
|
line.long 0x04 "CM_MMUCFG_CLKSTCTRL,MMUCFG Clock Domain State Transitions Control Register"
|
|
rbitfld.long 0x04 8. " CLKACTIVITY_MMUCFG_GCLK ,State of the MMUCFG_GICLK clock" "Gated,Active"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x04 0.--1. " CLKTRCTRL ,MMU CFG clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
|
|
else
|
|
bitfld.long 0x04 0.--1. " CLKTRCTRL ,MMU CFG clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
endif
|
|
line.long 0x08 "CM_ALWON_OCMC_0_CLKSTCTRL,OCMC 0 Clock Domain State Transitions Control Register"
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x08 8. " CLKACTIVITY_OCMC_GCLK ,State of the OCMC_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL ,OCMC clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
|
|
else
|
|
bitfld.long 0x08 8. " CLKACTIVITY_VCP_GCLK ,State of the VCP_GICLK clock" "Gated,Active"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL ,OCMC clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
endif
|
|
line.long 0x0c "CM_ALWON_VCP_CLKSTCTRL,VCP Clock Domain State Transitions Control Register"
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x0c 8. " CLKACTIVITY_VCP_GCLK ,State of the VCP_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x0c 0.--1. " CLKTRCTRL ,VCP clock clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
|
|
else
|
|
bitfld.long 0x0c 8. " CLKACTIVITY_OCMC_1_GCLK ,State of the OCMC_1_GICLK clock" "Gated,Active"
|
|
bitfld.long 0x0c 0.--1. " CLKTRCTRL ,OCMC_2 clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
endif
|
|
rgroup.long 0x141c++0x07
|
|
line.long 0x00 "CM_ALWON_MPU_CLKSTCTRL,MPU Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,MPU (ARM Cortex-A8) clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
|
|
line.long 0x04 "CM_ALWON_SYSCLK4_CLKSTCTRL,SYSCLK4 Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x04 11. " CLKACTIVITY_L3_F_EN_GCLK ,State of the L3_F_EN_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x04 10. " CLKACTIVITY_L3_S_GCLK ,State of the L3_S_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CLKACTIVITY_L3_M_GCLK ,State of the L3_M_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x04 8. " CLKACTIVITY_SYSCLK4_GCLK ,State of the SYSCLK4_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CLKTRCTRL ,SYSCLK4 clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0x1424++0x03
|
|
line.long 0x00 "CM_ALWON_SYSCLK5_CLKSTCTRL,SYSCLK5 Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 9. " CLKACTIVITY_DEBUG_CLKA_GCLK ,State of the Debug clockA clock" "Gated,Active"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_SYSCLK5_GCLK ,State of the SYSCLK5_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,SYSCLK4 clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
|
|
endif
|
|
rgroup.long 0x1428++0x07
|
|
line.long 0x00 "CM_ALWON_SYSCLK6_CLKSTCTRL,SYSCLK6 Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_SYSCLK6_GCLK ,State of the SYSCLK6_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,SYSCLK6 clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
|
|
line.long 0x04 "CM_ALWON_RTC_CLKSTCTRL,RTC Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x04 8. " CLKACTIVITY_RTC_GCLK ,State of the RTC_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x04 0.--1. " CLKTRCTRL ,RTC clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
|
|
group.long 0x1430++0x3
|
|
line.long 0x00 "CM_ALWON_L3_FAST_CLKSTCTRL,L3_FAST Clock Domain State Transitions Control Register"
|
|
rbitfld.long 0x00 8. " CLKACTIVITY_FAST_GCLK ,State of the L3 Fast clock for TPTC and TPCC" "Gated,Active"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3 Fast clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
|
|
else
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3 Fast clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
endif
|
|
width 30.
|
|
group.long 0x1540++0x1b
|
|
line.long 0x0 "CM_ALWON_MCASP0_CLKCTRL,MCASP0 Clocks Control Register"
|
|
rbitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_MCASP1_CLKCTRL,MCASP1 Clocks Control Register"
|
|
rbitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_MCASP2_CLKCTRL,MCASP2 Clocks Control Register"
|
|
rbitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0xC "CM_ALWON_MCBSP_CLKCTRL,MCBSP Clocks Control Register"
|
|
rbitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x10 "CM_ALWON_UART_0_CLKCTRL,UART_0 Clocks Control Register"
|
|
rbitfld.long 0x10 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x14 "CM_ALWON_UART_1_CLKCTRL,UART_1 Clocks Control Register"
|
|
rbitfld.long 0x14 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x18 "CM_ALWON_UART_2_CLKCTRL,UART_2 Clocks Control Register"
|
|
rbitfld.long 0x18 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x155c++0xf
|
|
line.long 0x00 "CM_ALWON_GPIO_0_CLKCTRL,GPIO_0 Clocks Control Register"
|
|
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_ALWON_GPIO_1_CLKCTRL,GPIO1/2/3 Clocks Control Register"
|
|
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x04 8. " OPTFCLKEN_DBCLK ,Optional functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x08 "CM_ALWON_I2C_0_CLKCTRL,I2C_0 Clocks Control Register"
|
|
rbitfld.long 0x08 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x0c "CM_ALWON_I2C_1_CLKCTRL,I2C_1 Clocks Control Register"
|
|
rbitfld.long 0x0c 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
rgroup.long 0x156c++0x3
|
|
line.long 0x00 "CM_ALWON_MCASP_3_4_5_CLKCTRL,MCASP_3_4_5 Clocks Control Register"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x1570++0x7
|
|
line.long 0x00 "CM_ALWON_ATL_CLKCTRL,ATL Clocks Control Register"
|
|
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_ALWON_MLB_CLKCTRL,MLB Clocks Control Register"
|
|
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0x1578++0x3
|
|
line.long 0x00 "CM_ALWON_PATA_CLKCTRL,PATA Clocks Control Register"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
endif
|
|
group.long 0x157c++0x3
|
|
line.long 0x00 "CM_ALWON_TIMER_4_CLKCTRL,TIMER 4 Clocks Control Register"
|
|
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x1580++0xb
|
|
line.long 0x0 "CM_ALWON_UART_3_CLKCTRL,UART_3 Clocks Control Register"
|
|
rbitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_UART_4_CLKCTRL,UART_4 Clocks Control Register"
|
|
rbitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_UART_5_CLKCTRL,UART_5 Clocks Control Register"
|
|
rbitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
rgroup.long 0x158c++0x3
|
|
line.long 0x00 "CM_ALWON_WDTIMER_CLKCTRL,WDTIMER Clocks Control Register"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x1590++0xf
|
|
line.long 0x00 "CM_ALWON_SPI_CLKCTRL,SPI0/1/2/3 Clocks Control Register"
|
|
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_ALWON_MAILBOX_CLKCTRL,MAILBOX Clocks Control Register"
|
|
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x08 "CM_ALWON_SPINBOX_CLKCTRL,SPINBOX Clocks Control Register"
|
|
rbitfld.long 0x08 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x0c "CM_ALWON_MMUDATA_CLKCTRL,MMU Data Clocks Control Register"
|
|
rbitfld.long 0x0c 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x15a8++0x3
|
|
line.long 0x00 "CM_ALWON_MMUCFG_CLKCTRL,MMU Config Clocks Control Register"
|
|
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0x15b0++0x17
|
|
line.long 0x0 "CM_ALWON_SDIO_CLKCTRL,SDIO Clocks Control Register"
|
|
bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_OCMC_0_CLKCTRL,OCMC_0 Clocks Control Register"
|
|
bitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_VCP_CLKCTRL,VCP Clocks Control Register"
|
|
bitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0xC "CM_ALWON_SMARTCARD_0_CLKCTRL,SMARTCARD_0 Clocks Control Register"
|
|
bitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x10 "CM_ALWON_SMARTCARD_1_CLKCTRL,SMARTCARD_1 Clocks Control Register"
|
|
bitfld.long 0x10 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x14 "CM_ALWON_CONTROL_CLKCTRL,CONTROL Clocks Control Register"
|
|
bitfld.long 0x14 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
rgroup.long 0x15c8++0x3
|
|
line.long 0x00 "CM_ALWON_SECSS_CLKCTRL,Security SS Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
else
|
|
group.long 0x15b4++0x0B
|
|
line.long 0x0 "CM_ALWON_OCMC_0_CLKCTRL,OCMC_0 Clocks Control Register"
|
|
rbitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_VCP_CLKCTRL,VCP Clocks Control Register"
|
|
rbitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_CONTROL_CLKCTRL,CONTROL Clocks Control Register"
|
|
rbitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
endif
|
|
group.long 0x15d0++0x7
|
|
line.long 0x00 "CM_ALWON_GPMC_CLKCTRL,GPMC Clocks Control Register"
|
|
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_ALWON_ETHERNET_0_CLKCTRL,ETHERNET_0 Clocks Control Register"
|
|
rbitfld.long 0x04 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0x15d8++0x3
|
|
line.long 0x00 "CM_ALWON_ETHERNET_1_CLKCTRL,ETHERNET_1 Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
endif
|
|
rgroup.long 0x15dc++0x3
|
|
line.long 0x00 "CM_ALWON_MPU_CLKCTRL,MPU Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Reserved,Reserved,Enabled,?..."
|
|
else
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
endif
|
|
width 30.
|
|
group.long 0x15e0++0x3
|
|
line.long 0x00 "CM_ALWON_DEBUGSS_CLKCTRL,DEBUGSS Clocks Control Register"
|
|
bitfld.long 0x00 27.--29. " STM_PMD_CLKDIVSEL ,STM clock divider control" "Reserved,/1,/2,Reserved,/4,?..."
|
|
bitfld.long 0x00 24.--26. " TRC_PMD_CLKDIVSEL ,TPIU clock divider control" "Reserved,/1,/2,Reserved,/4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " STM_PMD_CLKSEL ,Trace clock source selection for STM" "Sys Clk,Ref. Clk A,?..."
|
|
bitfld.long 0x00 20.--21. " TRC_PMD_CLKSEL ,Trace clock source selection for TPIU" "Sys Clk,Ref. Clk A,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OPTCLK_DEBUG_CLKA ,Optional functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " OPTCLK_DEBUG_SYSCLK ,Optional functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Reserved,Reserved,Enabled,?..."
|
|
width 30.
|
|
rgroup.long 0x15e4++0xf
|
|
line.long 0x0 "CM_ALWON_L3_CLKCTRL,L3 Clocks Control Register"
|
|
bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Reserved,Reserved,Enabled,?..."
|
|
else
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
endif
|
|
line.long 0x4 "CM_ALWON_L4HS_CLKCTRL,L4HS Clocks Control Register"
|
|
bitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Reserved,Reserved,Enabled,?..."
|
|
else
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
endif
|
|
line.long 0x8 "CM_ALWON_L4LS_CLKCTRL,L4LS Clocks Control Register"
|
|
bitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Reserved,Reserved,Enabled,?..."
|
|
else
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
endif
|
|
line.long 0xC "CM_ALWON_RTC_CLKCTRL,RTC Clocks Control Register"
|
|
bitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Reserved,Reserved,Enabled,?..."
|
|
else
|
|
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
endif
|
|
group.long 0x15f4++0x3
|
|
line.long 0x00 "CM_ALWON_TPCC_CLKCTRL,TPCC Clocks Control Register"
|
|
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x15f8++0xf
|
|
line.long 0x0 "CM_ALWON_TPTC0_CLKCTRL,TPTC0 Clocks Control Register"
|
|
rbitfld.long 0x0 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
rbitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_TPTC1_CLKCTRL,TPTC1 Clocks Control Register"
|
|
rbitfld.long 0x4 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
rbitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_TPTC2_CLKCTRL,TPTC2 Clocks Control Register"
|
|
rbitfld.long 0x8 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
rbitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0xC "CM_ALWON_TPTC3_CLKCTRL,TPTC3 Clocks Control Register"
|
|
rbitfld.long 0xC 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
rbitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x1608++0xf
|
|
line.long 0x0 "CM_ALWON_SR_0_CLKCTRL,Smart Reflex 0 Clocks Control Register"
|
|
rbitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_SR_1_CLKCTRL,Smart Reflex 1 Clocks Control Register"
|
|
rbitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_SR_2_CLKCTRL,Smart Reflex 2 Clocks Control Register"
|
|
rbitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0xC "CM_ALWON_SR_3_CLKCTRL,Smart Reflex 3 Clocks Control Register"
|
|
rbitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x1618++0x13
|
|
line.long 0x0 "CM_ALWON_DCAN_0_1_CLKCTRL,DCAN_0_1 Clocks Control Register"
|
|
rbitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_MMCHS_0_CLKCTRL,MMCHS_0 Clocks Control Register"
|
|
rbitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_MMCHS_1_CLKCTRL,MMCHS_1 Clocks Control Register"
|
|
rbitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0xC "CM_ALWON_MMCHS_2_CLKCTRL,MMCHS_2 Clocks Control Register"
|
|
rbitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x10 "CM_ALWON_CUST_EFUSE_CLKCTRL,CUST_EFUSE Clocks Control Register"
|
|
rbitfld.long 0x10 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
tree.end
|
|
tree "OCP_SOCKET_PRM"
|
|
width 14.
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x00 "REVISION_PRM,PRCM Revision Code Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,PRCM revision"
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
else
|
|
tree "PLLSS (PLL Subsytem)"
|
|
base ad:0x481c5000
|
|
width 25.
|
|
tree "PLL_ARM"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "CONTROL_REVISION,PLLSS Revision Register"
|
|
bitfld.long 0x00 30.--31. " IP_REV_SCHEME ,Register scheme" "Legacy,Highlander 0.8,?..."
|
|
hexmask.long.word 0x00 16.--27. 1. " IP_REV_FUNC ,Software compatible module family function"
|
|
bitfld.long 0x00 11.--15. " IP_REV_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " IP_REV_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " IP_REV_CUSTOM ,Special version for a particular device" "Non-custom,?..."
|
|
bitfld.long 0x00 0.--5. " IP_REV_MINOR ,Minor Revision (Y)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 25.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "CONTROL_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 4.--5. " STANDBY ,Configure local initiator state management" "Force Standby,No Standby,Smart Standby,Smart Standby wakeup capable"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Configure local initiator state management" "Force Idle,No Idle,Smart Idle,Smart Idle wakeup capable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FREEEMU ,Sensitivity to Emulation suspend input" "Sensitive,Not sensitive"
|
|
width 25.
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "PLLSS_MMR_LOCK0,Lock/Unlock Register for Region 0x0008 - 0x0fff"
|
|
group.long 0x48++0x23
|
|
line.long 0x00 "PLL_ARM_PWRCTRL,PLL_ARM Power Control Register"
|
|
bitfld.long 0x00 0. " OFFMODE ,Switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "PLL_ARM_CLKCTRL,PLL_ARM Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 15. " M3PWDNZ ,Asynchronous power down for M3 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 14. " STOPMODE ,STOP Mode (when in Lossclk/Stbyret)" "Limp mode,Stopmode"
|
|
bitfld.long 0x04 13. " LOWCURRSTDBY ,LOW current standby (when in Lossclk/Stbyret/Idle)" "Fast relock,Slow relock"
|
|
textline " "
|
|
bitfld.long 0x04 12. " LPMODE ,LP Mode" "Low,High"
|
|
bitfld.long 0x04 11. " DRIFTGUARDEN ,Recalibration enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " REGM4XEN ,Enable REGM*4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "PLL_ARM_TENABLE,PLL_ARM TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N latch" "Disabled,Enabled"
|
|
line.long 0x0c "PLL_ARM_TENABLEDIV,PLL_ARM TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "PLL_ARM_M2NDIV,PLL_ARM M2NDIV Register"
|
|
bitfld.long 0x10 16.--20. " M2 ,Post-divider is REGM2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x10 0.--6. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "PLL_ARM_MN2DIV,PLL_ARM MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "PLL_ARM_FRACDIV,PLL_ARM Fractonal Divider Register"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "PLL_ARM_BWCTRL,PLL_ARM LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
width 25.
|
|
line.long 0x20 "PLL_ARM_FRACCTRL,PLL_ARM Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--19. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
width 25.
|
|
rgroup.long 0x6c++0x3
|
|
line.long 0x00 "PLL_ARM_STATUS,PLL_ARM Status Register"
|
|
bitfld.long 0x00 30. " SSACK ,PODPLL_MPU_SSACK" "Low,High"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
textline " "
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LIMP ,Mode" "Stop,LIMP"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
width 25.
|
|
group.long 0x70++0x7
|
|
line.long 0x00 "PLL_ARM_M3DIV,PLL_ARM M3 Divider Register"
|
|
bitfld.long 0x00 0.--4. " M3 ,Post Divider Reg M3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "PLL_ARM_RAMPCTRL,PLL_ARM RAMP Control Register"
|
|
bitfld.long 0x04 19.--20. " CLKRAMPLEVEL ,Ramp sequence control" "No ramping,Bypass clk /Fout/8 / Fout/4 / Fout/2,Bypass clk / Fout/4 / Fout/2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " CLKRAMPRATE ,Time spent on each ramp step control (REFCLKs)" "2,4,8,16,32,64,128,512"
|
|
bitfld.long 0x04 0. " RELOCK_RAMP_EN ,Clock ramping during relock enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "PLL_DSP"
|
|
width 25.
|
|
group.long 0x80++0x23
|
|
line.long 0x00 "PLL_DSP_PWRCTRL,DSP PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "PLL_DSP_CLKCTRL,DSP PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "PLL_DSP_TENABLE,DSP PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "PLL_DSP_TENABLEDIV,DSP PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "PLL_DSP_M2NDIV,DSP PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "PLL_DSP_MN2DIV,DSP PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "PLL_DSP_FRACDIV,DSP PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "PLL_DSP_BWCTRL,DSP PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
width 25.
|
|
line.long 0x20 "PLL_DSP_FRACCTRL,DSP PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
width 25.
|
|
rgroup.long (0x80+0x24)++0x3
|
|
line.long 0x00 "PLL_DSP_STATUS,DSP PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
tree "PLL_SGX"
|
|
width 25.
|
|
group.long 0xb0++0x23
|
|
line.long 0x00 "PLL_SGX_PWRCTRL,SGX PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "PLL_SGX_CLKCTRL,SGX PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "PLL_SGX_TENABLE,SGX PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "PLL_SGX_TENABLEDIV,SGX PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "PLL_SGX_M2NDIV,SGX PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "PLL_SGX_MN2DIV,SGX PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "PLL_SGX_FRACDIV,SGX PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "PLL_SGX_BWCTRL,SGX PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
width 25.
|
|
line.long 0x20 "PLL_SGX_FRACCTRL,SGX PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
width 25.
|
|
rgroup.long (0xb0+0x24)++0x3
|
|
line.long 0x00 "PLL_SGX_STATUS,SGX PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
tree "PLL_HDVICP"
|
|
width 25.
|
|
group.long 0xe0++0x23
|
|
line.long 0x00 "PLL_HDVICP_PWRCTRL,HDVICP PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "PLL_HDVICP_CLKCTRL,HDVICP PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "PLL_HDVICP_TENABLE,HDVICP PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "PLL_HDVICP_TENABLEDIV,HDVICP PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "PLL_HDVICP_M2NDIV,HDVICP PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "PLL_HDVICP_MN2DIV,HDVICP PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "PLL_HDVICP_FRACDIV,HDVICP PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "PLL_HDVICP_BWCTRL,HDVICP PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
width 25.
|
|
line.long 0x20 "PLL_HDVICP_FRACCTRL,HDVICP PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
width 25.
|
|
rgroup.long (0xe0+0x24)++0x3
|
|
line.long 0x00 "PLL_HDVICP_STATUS,HDVICP PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
tree "PLL_L3"
|
|
width 25.
|
|
group.long 0x110++0x23
|
|
line.long 0x00 "PLL_L3_PWRCTRL,L3 PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "PLL_L3_CLKCTRL,L3 PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "PLL_L3_TENABLE,L3 PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "PLL_L3_TENABLEDIV,L3 PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "PLL_L3_M2NDIV,L3 PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "PLL_L3_MN2DIV,L3 PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "PLL_L3_FRACDIV,L3 PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "PLL_L3_BWCTRL,L3 PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
width 25.
|
|
line.long 0x20 "PLL_L3_FRACCTRL,L3 PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
width 25.
|
|
rgroup.long (0x110+0x24)++0x3
|
|
line.long 0x00 "PLL_L3_STATUS,L3 PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
tree "PLL_MEDIACTL"
|
|
width 25.
|
|
group.long 0x140++0x23
|
|
line.long 0x00 "PLL_MEDIACTL_PWRCTRL,MEDIACTL PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "PLL_MEDIACTL_CLKCTRL,MEDIACTL PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "PLL_MEDIACTL_TENABLE,MEDIACTL PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "PLL_MEDIACTL_TENABLEDIV,MEDIACTL PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "PLL_MEDIACTL_M2NDIV,MEDIACTL PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "PLL_MEDIACTL_MN2DIV,MEDIACTL PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "PLL_MEDIACTL_FRACDIV,MEDIACTL PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "PLL_MEDIACTL_BWCTRL,MEDIACTL PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
width 25.
|
|
line.long 0x20 "PLL_MEDIACTL_FRACCTRL,MEDIACTL PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
width 25.
|
|
rgroup.long (0x140+0x24)++0x3
|
|
line.long 0x00 "PLL_MEDIACTL_STATUS,MEDIACTL PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
tree "PLL_HDVPSS"
|
|
width 25.
|
|
group.long 0x170++0x23
|
|
line.long 0x00 "PLL_HDVPSS_PWRCTRL,HDVPSS PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "PLL_HDVPSS_CLKCTRL,HDVPSS PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "PLL_HDVPSS_TENABLE,HDVPSS PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "PLL_HDVPSS_TENABLEDIV,HDVPSS PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "PLL_HDVPSS_M2NDIV,HDVPSS PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "PLL_HDVPSS_MN2DIV,HDVPSS PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "PLL_HDVPSS_FRACDIV,HDVPSS PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "PLL_HDVPSS_BWCTRL,HDVPSS PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
width 25.
|
|
line.long 0x20 "PLL_HDVPSS_FRACCTRL,HDVPSS PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
width 25.
|
|
rgroup.long (0x170+0x24)++0x3
|
|
line.long 0x00 "PLL_HDVPSS_STATUS,HDVPSS PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
tree "PLL_VIDEO0"
|
|
width 25.
|
|
group.long 0x1a0++0x23
|
|
line.long 0x00 "PLL_VIDEO0_PWRCTRL,VIDEO0 PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "PLL_VIDEO0_CLKCTRL,VIDEO0 PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "PLL_VIDEO0_TENABLE,VIDEO0 PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "PLL_VIDEO0_TENABLEDIV,VIDEO0 PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "PLL_VIDEO0_M2NDIV,VIDEO0 PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "PLL_VIDEO0_MN2DIV,VIDEO0 PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "PLL_VIDEO0_FRACDIV,VIDEO0 PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "PLL_VIDEO0_BWCTRL,VIDEO0 PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
width 25.
|
|
line.long 0x20 "PLL_VIDEO0_FRACCTRL,VIDEO0 PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
width 25.
|
|
rgroup.long (0x1a0+0x24)++0x3
|
|
line.long 0x00 "PLL_VIDEO0_STATUS,VIDEO0 PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
tree "PLL_VIDEO1"
|
|
width 25.
|
|
group.long 0x1d0++0x23
|
|
line.long 0x00 "PLL_VIDEO1_PWRCTRL,VIDEO1 PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "PLL_VIDEO1_CLKCTRL,VIDEO1 PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "PLL_VIDEO1_TENABLE,VIDEO1 PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "PLL_VIDEO1_TENABLEDIV,VIDEO1 PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "PLL_VIDEO1_M2NDIV,VIDEO1 PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "PLL_VIDEO1_MN2DIV,VIDEO1 PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "PLL_VIDEO1_FRACDIV,VIDEO1 PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "PLL_VIDEO1_BWCTRL,VIDEO1 PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
width 25.
|
|
line.long 0x20 "PLL_VIDEO1_FRACCTRL,VIDEO1 PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
width 25.
|
|
rgroup.long (0x1d0+0x24)++0x3
|
|
line.long 0x00 "PLL_VIDEO1_STATUS,VIDEO1 PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
tree "PLL_VIDEO2"
|
|
width 25.
|
|
group.long 0x200++0x23
|
|
line.long 0x00 "PLL_VIDEO2_PWRCTRL,VIDEO2 PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "PLL_VIDEO2_CLKCTRL,VIDEO2 PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "PLL_VIDEO2_TENABLE,VIDEO2 PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "PLL_VIDEO2_TENABLEDIV,VIDEO2 PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "PLL_VIDEO2_M2NDIV,VIDEO2 PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "PLL_VIDEO2_MN2DIV,VIDEO2 PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "PLL_VIDEO2_FRACDIV,VIDEO2 PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "PLL_VIDEO2_BWCTRL,VIDEO2 PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
width 25.
|
|
line.long 0x20 "PLL_VIDEO2_FRACCTRL,VIDEO2 PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
width 25.
|
|
rgroup.long (0x200+0x24)++0x3
|
|
line.long 0x00 "PLL_VIDEO2_STATUS,VIDEO2 PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
tree "PLL_AUDIO"
|
|
width 25.
|
|
group.long 0x230++0x23
|
|
line.long 0x00 "PLL_AUDIO_PWRCTRL,AUDIO PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "PLL_AUDIO_CLKCTRL,AUDIO PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "PLL_AUDIO_TENABLE,AUDIO PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "PLL_AUDIO_TENABLEDIV,AUDIO PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "PLL_AUDIO_M2NDIV,AUDIO PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "PLL_AUDIO_MN2DIV,AUDIO PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "PLL_AUDIO_FRACDIV,AUDIO PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "PLL_AUDIO_BWCTRL,AUDIO PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
width 25.
|
|
line.long 0x20 "PLL_AUDIO_FRACCTRL,AUDIO PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
width 25.
|
|
rgroup.long (0x230+0x24)++0x3
|
|
line.long 0x00 "PLL_AUDIO_STATUS,AUDIO PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
tree "PLL_USB"
|
|
width 25.
|
|
group.long 0x260++0x23
|
|
line.long 0x00 "PLL_USB_PWRCTRL,USB PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "PLL_USB_CLKCTRL,USB PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "PLL_USB_TENABLE,USB PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "PLL_USB_TENABLEDIV,USB PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "PLL_USB_M2NDIV,USB PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "PLL_USB_MN2DIV,USB PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "PLL_USB_FRACDIV,USB PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "PLL_USB_BWCTRL,USB PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
width 25.
|
|
line.long 0x20 "PLL_USB_FRACCTRL,USB PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
width 25.
|
|
rgroup.long (0x260+0x24)++0x3
|
|
line.long 0x00 "PLL_USB_STATUS,USB PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
tree "PLL_DDR"
|
|
width 25.
|
|
group.long 0x290++0x23
|
|
line.long 0x00 "PLL_DDR_PWRCTRL,DDR PLL Power Control Register"
|
|
bitfld.long 0x00 5. " PONIN ,ON/OFF control of the weak power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 4. " PGOODIN ,ON/OFF control of the strong power switch digital" "OFF,ON"
|
|
bitfld.long 0x00 3. " RET ,Save/Restore control for Retention mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISORET ,Save/Restore control for Isolation of output pins" "Low,High"
|
|
bitfld.long 0x00 1. " ISOSCAN ,Save/Restore control for Isolation of the Scanout pins" "Low,High"
|
|
bitfld.long 0x00 0. " OFFMODE ,switch OFF the logic on VDDA" "ON,OFF"
|
|
line.long 0x04 "PLL_DDR_CLKCTRL,DDR PLL Clock Control Register"
|
|
bitfld.long 0x04 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENSSC ,Clock Spreading Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " NWELLTRIM ,Trim values for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IDLE ,PLL to Idle mode set" "Active,Idle"
|
|
bitfld.long 0x04 22. " BYPASSACKZ ,Bypass status acknowledge signal" "No ACK,ACK"
|
|
bitfld.long 0x04 21. " STBYRET ,Standby retention control" "Relock,Retention"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW"
|
|
bitfld.long 0x04 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO" "Powered down,Functional"
|
|
textline " "
|
|
bitfld.long 0x04 16. " M2PWDNZ ,Asynchronous power down for M2 divider" "Powered down,Functional"
|
|
bitfld.long 0x04 10.--12. " SELFREQDCO ,DCO frequency range selector" "Reserved,Reserved,500MHz-1000MHz,Reserved,1000MHz-2000MHz,?..."
|
|
bitfld.long 0x04 8. " RELAXED_LOCK ,FREQLOCK assertion conditions (when DC frequency error)" "<1%,<2%"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TINITZ ,PLL core soft reset" "No reset,Reset"
|
|
line.long 0x08 "PLL_DDR_TENABLE,DDR PLL TENABLE Register"
|
|
bitfld.long 0x08 0. " TENABLE ,M/N/SD/SELFREQDCO latch" "Disabled,Enabled"
|
|
line.long 0x0c "PLL_DDR_TENABLEDIV,DDR PLL TENABLEDIV Register"
|
|
bitfld.long 0x0c 0. " TENABLEDIV ,M2 and N2 latch" "Disabled,Enabled"
|
|
line.long 0x10 "PLL_DDR_M2NDIV,DDR PLL M2NDIV Register"
|
|
hexmask.long.byte 0x10 16.--22. 1. " M2 ,Post-divider is REGM2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " N ,Pre-divider is REGN+1"
|
|
line.long 0x14 "PLL_DDR_MN2DIV,DDR PLL MN2DIV Register"
|
|
bitfld.long 0x14 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--11. 1. " M ,Feedback multiplier is REGM"
|
|
line.long 0x18 "PLL_DDR_FRACDIV,DDR PLL Fractonal Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REGSD ,Sigma-Delta Divider"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " FRACTIONALM ,Fractional part of the M divider"
|
|
line.long 0x1c "PLL_DDR_BWCTRL,DDR PLL LOOP Bandwidth Control Register"
|
|
bitfld.long 0x1c 1.--2. " BWCONTROL ,Chane Loop Bandwidth" "0,1,2,3"
|
|
bitfld.long 0x1c 0. " BW_INCR_DECRZ ,Direction of Loop Bandwidth" "Decreased,Increased"
|
|
width 25.
|
|
line.long 0x20 "PLL_DDR_FRACCTRL,DDR PLL Fractonal Control Register"
|
|
bitfld.long 0x20 31. " DOWNSPREAD ,Frequency spread enable" "Low freq,Both sides freq"
|
|
bitfld.long 0x20 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x20 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider"
|
|
bitfld.long 0x20 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--17. 1. " DELTAMSTEPFRACTION ,Fraction part of Frequency Spread control"
|
|
width 25.
|
|
rgroup.long (0x290+0x24)++0x3
|
|
line.long 0x00 "PLL_DDR_STATUS,DDR PLL Status Register"
|
|
bitfld.long 0x00 31. " PONOUT ,Status of the weak power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 30. " PGOODOUT ,Status of the strong power-switch in digital to SOC" "OFF,ON"
|
|
bitfld.long 0x00 29. " LDOPWDN ,ADPLLLJ internal LDO power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECAL_BSTATUS3 ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 27. " RECAL_O/PPIN ,Recalibration status flag" "Not required,Required"
|
|
bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "Low,High"
|
|
bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "Low,High"
|
|
bitfld.long 0x00 7. " STBYRETACK ,State of all internal clocks in ADPLLLJ" "Active,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "No loss,Loss"
|
|
bitfld.long 0x00 5. " CLKOUTENACK ,CLKOUTEN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "No ACK,ACK"
|
|
bitfld.long 0x00 2. " SSCACK ,Spread-spectrum clocking on output clocks enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIGHJITTER ,Phase error between REFCLK & FBCLK" "<=24%,>24%"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed"
|
|
tree.end
|
|
width 21.
|
|
group.long 0x2c0++0x37
|
|
line.long 0x00 "OSC_SRC,Oscillator Source Register"
|
|
bitfld.long 0x00 24. " PLL_AUDIO_SOURCE ,Audio PLL Source Oscillator Select" "OSC0,OSC1"
|
|
bitfld.long 0x00 18. " PLL_VIDEO2_SOURCE ,HDMI PLL Source Oscillator Select" "OSC0,OSC1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PLL_VIDEO1_SOURCE ,Video1 PLL Source Oscillator Select" "OSC0,OSC1"
|
|
bitfld.long 0x00 16. " PLL_VIDEO0_SOURCE ,Video0 PLL Source Oscillator Select" "OSC0,OSC1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PLL_L3_SOURCE ,L3 ADPLLLJ Source Oscillator Select" "OSC0,OSC1"
|
|
line.long 0x04 "ARM_CLKSRC,ARM Input Clock Source Register"
|
|
bitfld.long 0x04 0. " ARM_SOURCE ,ARM PLL Source Clock Select" "OSC0,RTC DIVIDER OUTPUT"
|
|
line.long 0x08 "VIDEO_PLL_CLKSRC,VIDEO_PLL Clock Source Register"
|
|
bitfld.long 0x08 24. " HD_VENC_G_CLK_SOURCE ,Hd_venc_g_clk selection of HDVPSS" "PLL_VIDEO0_OUT,VIDEO_PLL_CLK2"
|
|
bitfld.long 0x08 18.--19. " TPPSSSTSO_MUX_SOURCE ,Source of Audio PLL CLK2 input of PRCM" "PLL_MEDIACTL_OUT/2,PLL_MEDIACTL_OUT,Tsi0_dclk,Tsi2_dclk"
|
|
textline " "
|
|
bitfld.long 0x08 16.--17. " TPPSSSTC0_MUX_SOURCE ,Source of SYSCLK14_MUX" "SYSCLK14,XREF_CLK0,XREF_CLK1,XREF_CLK2"
|
|
bitfld.long 0x08 8.--9. " VIDEO_PLL_OUT_MUX_SOURCE ,Source of VIDEO_PLL_OUT mux" "PLL_VIDEO0_OUT,PLL_VIDEO2_OUT,PLL_VIDEO1_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0. " VIDEO_PLL_CLK2_SOURCE ,Source of VIDEO_PLL_CLK2" "HDMI PLL CLKOUT,VIDEO_M_PCLK"
|
|
line.long 0x0c "MLB_ATL_CLKSRC,MLB_ATL Input Clock Source Register"
|
|
bitfld.long 0x0c 16.--17. " ATL_SOURCE ,Source clock of the ATL" "SYSCLK19,PLL_AUDIO_OUT,VIDEO_PLL_OUT_MUX,?..."
|
|
bitfld.long 0x0c 0. " MLB_SOURCE ,Source clock of the MLB" "MLB_CLK_INPUT,MLBP_CLK_INPUT"
|
|
line.long 0x10 "MCASP345_AUX_CLKSRC,McASP3/4/5 Aux Clock Source Register"
|
|
bitfld.long 0x10 16.--18. " MCASP5_AUX_SOURCE ,Source clock of the MCASP5 AUX clock" "OUTPUT OF MLB MUX,PLL_AUDIO_OUT,VIDEO_PLL_OUT_MUX,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,?..."
|
|
bitfld.long 0x10 8.--10. " MCASP4_AUX_SOURCE ,Source clock of the MCASP4 AUX clock" "OUTPUT OF MLB MUX,PLL_AUDIO_OUT,VIDEO_PLL_OUT_MUX,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MCASP3_AUX_SOURCE ,Source clock of the MCASP3 AUX clock" "OUTPUT OF MLB MUX,PLL_AUDIO_OUT,VIDEO_PLL_OUT_MUX,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,?..."
|
|
line.long 0x14 "MCASP_AHCLK_CLKSRC,McASP AH Clock Source Register"
|
|
bitfld.long 0x14 25.--27. " MCASP5_AHCLKX_SOURCE ,Source clock of the MCASP5 AH clock transmit" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
bitfld.long 0x14 22.--24. " MCASP4_AHCLKX_SOURCE ,Source clock of the MCASP4 AH clock transmit" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
textline " "
|
|
bitfld.long 0x14 19.--21. " MCASP3_AHCLKX_SOURCE ,Source clock of the MCASP3 AH clock transmit" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
bitfld.long 0x14 16.--18. " MCASP2_AHCLKX_SOURCE ,Source clock of the MCASP2 AH clock transmit" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
textline " "
|
|
bitfld.long 0x14 9.--11. " MCASP1_AHCLKR_SOURCE ,Source clock of the MCASP1 AH clock receive" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
bitfld.long 0x14 6.--8. " MCASP1_AHCLKX_SOURCE ,Source clock of the MCASP1 AH clock transmit" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
textline " "
|
|
bitfld.long 0x14 3.--5. " MCASP0_AHCLKR_SOURCE ,Source clock of the MCASP0 AH clock receive" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
bitfld.long 0x14 0.--2. " MCASP0_AHCLKX_SOURCE ,Source clock of the MCASP0 AH clock transmit" "XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,ATCLK0,ATCLK1,ATCLK2,ATCLK3"
|
|
line.long 0x18 "MCASP_UART_CLKSRC,McBSP/UART Clock Source Register"
|
|
bitfld.long 0x18 7.--8. " UART5_CLK_SOURCE ,Clock source for UART5" "SYSCLK8,SYSCLK10,SYSCLK6,?..."
|
|
bitfld.long 0x18 5.--6. " UART4_CLK_SOURCE ,Clock source for UART4" "SYSCLK8,SYSCLK10,SYSCLK6,?..."
|
|
textline " "
|
|
bitfld.long 0x18 3.--4. " UART3_CLK_SOURCE ,Clock source for UART3" "SYSCLK8,SYSCLK10,SYSCLK6,?..."
|
|
bitfld.long 0x18 0.--2. " McBSP_CLKS_SOURCE ,Clock source for McBSP CLKS" "PRCM,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,?..."
|
|
line.long 0x1c "HDMI_I2S_CLKSRC,HDMI I2S Clock Source Register"
|
|
bitfld.long 0x1c 0.--2. " HDMI_I2S_SOURCE ,Clock source for HDMI_I2S clock" "PRCM,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC1_XI,?..."
|
|
line.long 0x20 "DMTIMER_CLKSRC,DMTIMER Clock Source Register"
|
|
bitfld.long 0x20 25.--27. " DMTIMER7_SOURCE ,Clock source for DMTIMER7 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
bitfld.long 0x20 22.--24. " DMTIMER6_SOURCE ,Clock source for DMTIMER6 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
textline " "
|
|
bitfld.long 0x20 19.--21. " DMTIMER5_SOURCE ,Clock source for DMTIMER5 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
bitfld.long 0x20 16.--18. " DMTIMER4_SOURCE ,Clock source for DMTIMER4 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
textline " "
|
|
bitfld.long 0x20 9.--11. " DMTIMER3_SOURCE ,Clock source for DMTIMER3 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
bitfld.long 0x20 6.--8. " DMTIMER2_SOURCE ,Clock source for DMTIMER2 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
textline " "
|
|
bitfld.long 0x20 3.--5. " DMTIMER1_SOURCE ,Clock source for DMTIMER1 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
bitfld.long 0x20 0.--2. " DMTIMER8_SOURCE ,Clock source for DMTIMER8 clock" "SYSCLK18,XREF_CLK0,XREF_CLK1,XREF_CLK2,OSC0 out,OSC1_XI,TCLK in,?..."
|
|
line.long 0x24 "CLKOUT_MUX,CLKOUT MUX Register"
|
|
bitfld.long 0x24 16.--19. " CLKOUT1_MUX ,Clock source for CLKOUT01" "PRCM_SYSCLK_OUT,SATA SERDES OBS CLK,PCIe SERDES OBS CLK,PLL_HDVPSS_OUT_DIV2,PLL_MEDIACTL_OUT_DIV2,PLL_L3,OSC0 OUT,OSC1 OUT,ARM Func Clock OUT,PLL_SGX OUT,RCOSC32K OUT,?..."
|
|
bitfld.long 0x24 0.--3. " CLKOUT0_MUX ,Clock source for CLKOUT0" "PRCM_SYSCLK_OUT,SATA SERDES OBS CLK,PCIe SERDES OBS CLK,PLL_HDVPSS_OUT_DIV2,PLL_MEDIACTL_OUT_DIV2,PLL_L3,OSC0 OUT,OSC1 OUT,ARM Func Clock OUT,PLL_SGX OUT,RCOSC32K OUT,?..."
|
|
line.long 0x28 "RMII_REFCLK_SRC,RMII Reference Clock Source Register"
|
|
bitfld.long 0x28 1.--3. " CPTS_RFT_CLK ,Clock source for CPTS_RFT_CLK" "PLL_VIDEO0_OUT,PLL_VIDEO1_OUT,PLL_AUDIO_OUT,VIDEO_PLL_CLK2,PLL_L3 OUT,?..."
|
|
bitfld.long 0x28 0. " REFCLK_SOURCE ,Clock source for SYSCLK8" "50MHz,REFCLK PIN"
|
|
line.long 0x2c "SECSS_CLK_SRC,SECSS Clock Source Register"
|
|
bitfld.long 0x2c 0. " SECSSCLK_SOURCE ,Clock source for SECSS" "MEDIACTL/2 CLK,PLL_USB"
|
|
line.long 0x30 "SYSCLK18_SRC,SYSCLK18 Source Register"
|
|
bitfld.long 0x30 0. " SYSCLK18_SOURCE ,Source of SYSCLK18 input to PRCM" "RTCDIVIDER OUT,CLKIN32 PIN"
|
|
line.long 0x34 "WDT0_CLKSRC,WDT0 Clock Source Register"
|
|
bitfld.long 0x34 0. " WDT0_SOURCE ,Clock source of WDT0" "RTCDIVIDER OUT,RCOSC 32K OUT"
|
|
group.long 0x30c++0x3
|
|
line.long 0x00 "EMIF_CLK_GATE,EMIF0/1 Clock Gate Register"
|
|
bitfld.long 0x00 1. " DDRPHY1_CLK_GATE ,Gate the clock to DDR PHY1" "Not gated,Gated"
|
|
bitfld.long 0x00 0. " EMIFSS_CLK_GATE ,Gate the clock to EMIF0/1 / DMM / DDR PHY0/1" "Not gated,Gated"
|
|
group.long 0x320++0x7
|
|
line.long 0x00 "DMTIMER_CLK_CHANGE,DMTimer Clock Change Register"
|
|
bitfld.long 0x00 15. " DMTIMER7_IDLESTATUS ,IDLE Status for DMTIMER7" "Not idle,Idle"
|
|
bitfld.long 0x00 14. " DMTIMER6_IDLESTATUS ,IDLE Status for DMTIMER6" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMTIMER5_IDLESTATUS ,IDLE Status for DMTIMER5" "Not idle,Idle"
|
|
bitfld.long 0x00 12. " DMTIMER4_IDLESTATUS ,IDLE Status for DMTIMER4" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DMTIMER3_IDLESTATUS ,IDLE Status for DMTIMER3" "Not idle,Idle"
|
|
bitfld.long 0x00 10. " DMTIMER2_IDLESTATUS ,IDLE Status for DMTIMER2" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DMTIMER1_IDLESTATUS ,IDLE Status for DMTIMER1" "Not idle,Idle"
|
|
bitfld.long 0x00 8. " DMTIMER8_IDLESTATUS ,IDLE Status for DMTIMER0" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMTIMER7_IDLEREQ ,IDLE Request for DMTIMER7" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " DMTIMER6_IDLEREQ ,IDLE Request for DMTIMER6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DMTIMER5_IDLEREQ ,IDLE Request for DMTIMER5" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " DMTIMER4_IDLEREQ ,IDLE Request for DMTIMER4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMTIMER3_IDLEREQ ,IDLE Request for DMTIMER3" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " DMTIMER2_IDLEREQ ,IDLE Request for DMTIMER2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DMTIMER1_IDLEREQ ,IDLE Request for DMTIMER1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " DMTIMER8_IDLEREQ ,IDLE Request for DMTIMER0" "Not requested,Requested"
|
|
line.long 0x04 "DEEPSLEEP_CTRL,DEEPSLEEP Control Register"
|
|
bitfld.long 0x04 17. " DSENABLE ,Deep sleep circuitry enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " DSPOLARITY ,Polarity of DEEPSLEEPZ pin control" "Active low,Active high"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " DSCOUNT ,Number of osc clocks needed to see prior to exiting deep sleep mode"
|
|
rgroup.long 0x328++0x3
|
|
line.long 0x00 "DEEPSLEEP_STATUS,DEEPSLEEP Status Register"
|
|
bitfld.long 0x00 0. " DSCOMPLETE ,Deepsleep comleted" "Not completed,Completed"
|
|
width 11.
|
|
tree.end
|
|
tree "PRCM (Power Reset and Clock Management)"
|
|
base ad:0x48180000
|
|
width 21.
|
|
tree "PRM (Power Reset Manager)"
|
|
tree "PRM_DEVICE"
|
|
group.long 0xa0++0xb
|
|
line.long 0x00 "PRM_RSTCTRL,Software Global Cold and Warm Reset Control Register"
|
|
bitfld.long 0x00 1. " RST_GLOBAL_COLD_SW ,Software Global Cold Reset control" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RST_GLOBAL_WARM_SW ,Software Global Warm Reset control" "No reset,Reset"
|
|
line.long 0x04 "PRM_RSTTIME,Reset Duration Control Register"
|
|
bitfld.long 0x04 8.--12. " RSTTIME2 ,Warm and Local Reset Stall Period Timer duration in PRCM clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RSTTIME1 ,Global POR Stall Period Timer duration in PRCM clock cycles"
|
|
line.long 0x08 "PRM_RSTST,Global Reset Sources Register"
|
|
eventfld.long 0x08 9. " ICEPICK_RST ,Emulation Warm Reset event" "No reset,Reset"
|
|
eventfld.long 0x08 5. " EXTERNAL_WARM_RST ,External Warm Reset event" "No reset,Reset"
|
|
eventfld.long 0x08 4. " SECURE_WDT_RST ,Secure Watchdog Reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 3. " MPU_WDT_RST ,Watchdog Reset event" "No reset,Reset"
|
|
eventfld.long 0x08 2. " MPU_SECURITY_VIOL_RST ,Security Violation Reset event" "No reset,Reset"
|
|
eventfld.long 0x08 1. " GLOBAL_WARM_SW_RST ,Software Global Warm Reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 0. " GLOBAL_COLD_RST ,Power-on Reset (POR) event" "No reset,Reset"
|
|
tree.end
|
|
tree "PRM_DSP"
|
|
group.long 0xa00++0x3
|
|
line.long 0x00 "PM_DSP_PWRSTCTRL,DSP Power State Control Register"
|
|
bitfld.long 0x00 16.--17. " ACTIVE_MEM_ONSTATE ,Active Domain memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request (after a sleep transition)" "Not requested,Requested"
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
|
|
rgroup.long 0xa04++0x3
|
|
line.long 0x00 "PM_DSP_PWRSTST,DSP Power State Status Register"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
|
|
bitfld.long 0x00 4.--5. " ACTIVE_MEM_STATEST ,Active domain memory state status" "OFF,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
|
|
group.long 0xa10++0x7
|
|
line.long 0x00 "RM_DSP_RSTCTRL,DSP Domain Resets Control Register"
|
|
bitfld.long 0x00 1. " GEM_SW_RST ,ACTIVE Domain GEM warm reset control" "No reset,Reset"
|
|
bitfld.long 0x00 0. " GEM_LRST ,ACTIVE Domain GEM local reset control" "No reset,Reset"
|
|
line.long 0x04 "RM_DSP_RSTST,DSP Domain Reset Sources Register"
|
|
eventfld.long 0x04 4. " EMULATION_GEM_RST ,GEM Local CPU reset due to emulation reset source" "No reset,Reset"
|
|
eventfld.long 0x04 3. " GEM_LRST_REQ ,Local Reset request (by GEM)" "Not requested,Requested"
|
|
eventfld.long 0x04 1. " GEM_GRST ,GEM warm reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x04 0. " GEM_LRST ,GEM local SW reset" "No reset,Reset"
|
|
tree.end
|
|
tree "PRM_ALWON2"
|
|
group.long 0xb10++0x7
|
|
line.long 0x00 "RM_ALWON2_RSTCTRL,ALWON2 Domain Resets Control Register"
|
|
bitfld.long 0x00 7. " PCI_LRST ,ACTIVE domain PCI Local reset control" "No reset,Reset"
|
|
bitfld.long 0x00 6. " USB2_LRST ,USB2 local reset control" "No reset,Reset"
|
|
bitfld.long 0x00 5. " USB1_LRST ,USB1 local reset control" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MC_RST3 ,Media Controller logic and MMU reset control" "No reset,Reset"
|
|
bitfld.long 0x00 3. " MC_M3_RST2 ,Media Controller Second M3 reset control" "No reset,Reset"
|
|
bitfld.long 0x00 2. " MC_M3_RST1 ,Media Controller First M3 reset control" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TPPSS_SW_RST ,DEFAUL Domain TPPSS reset control" "No reset,Reset"
|
|
bitfld.long 0x00 0. " TPPSS_LRST ,DEFAUL Domain TPPSS ARM local reset control" "No reset,Reset"
|
|
line.long 0x04 "RM_ALWON2_RSTST,ALWON2 Domain Reset Sources Register"
|
|
eventfld.long 0x04 14. " ICECRUSHER_M3_2_RST ,HDVPSS controller M3_2 reset due to ICECRUSHER1 reset" "No reset,Reset"
|
|
eventfld.long 0x04 13. " ICECRUSHER_M3_1_RST ,HDVPSS controller M3_1 reset due to ICECRUSHER1 reset" "No reset,Reset"
|
|
eventfld.long 0x04 12. " EMULATION_M3_2_RST ,HDVPSS controller M3_2 reset due to emulation reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x04 11. " EMULATION_M3_1_RST ,HDVPSS controller M3_1 reset due to emulation reset" "No reset,Reset"
|
|
eventfld.long 0x04 10. " ,TPPSS local ARM reset due to ICECRUSHER reset" "No reset,Reset"
|
|
eventfld.long 0x04 9. " ,TPPSS local ARM reset due to emulation reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x04 7. " PCI_LRST ,PCI local SW reset" "No reset,Reset"
|
|
eventfld.long 0x04 6. " USB2_LRST ,USB2 Local Reset" "No reset,Reset"
|
|
eventfld.long 0x04 5. " USB1_LRST ,USB1 Local Reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x04 4. " M3_RST3 ,Media Controller logic and MMU SW reset" "No reset,Reset"
|
|
eventfld.long 0x04 3. " M3_M3_RST2 ,Media Controller second M3 SW reset" "No reset,Reset"
|
|
eventfld.long 0x04 2. " M3_M3_RST1 ,Media Controller first cortex M3 SW reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x04 1. " TPPSS_RST ,TPPSS SW reset" "No reset,Reset"
|
|
eventfld.long 0x04 0. " TPPSS_LRST ,TPPSS local ARM SW reset" "No reset,Reset"
|
|
tree.end
|
|
tree "PRM_HDVICP"
|
|
group.long 0xc00++0x3
|
|
line.long 0x00 "PM_HDVICP_PWRSTCTRL,HDVICP Power State Control Register"
|
|
bitfld.long 0x00 16.--17. " HDVICP_MEM_ONSTATE ,HDVICP memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request (after a sleep transition)" "Not requested,Requested"
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
|
|
rgroup.long 0xc04++0x3
|
|
line.long 0x00 "PM_HDVICP_PWRSTST,HDVICP Power Domain State Status Register"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
|
|
bitfld.long 0x00 4.--5. " HDVICP_MEM_STATEST ,HDVICP memory state status" "OFF,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
|
|
group.long 0xc10++0x7
|
|
line.long 0x00 "RM_HDVICP_RSTCTRL,HDVICP Domain Resets Control Register"
|
|
bitfld.long 0x00 2. " HDVICP_RST3 ,HDVICP logic and SL2 reset control" "No reset,Reset"
|
|
bitfld.long 0x00 1. " HDVICP_RST2 ,HDVICP sequencer2 reset control" "No reset,Reset"
|
|
bitfld.long 0x00 0. " HDVICP_RST1 ,HDVICP sequencer1 reset control" "No reset,Reset"
|
|
line.long 0x04 "RM_HDVICP_RSTST,HDVICP Domain Reset Sources Register"
|
|
eventfld.long 0x04 6. " ICECRUSHER_SEQ2_RST2 ,Sequencer2 CPU reset due to ICECRUSHER1 reset" "No reset,Reset"
|
|
eventfld.long 0x04 5. " ICECRUSHER_SEQ1_RST1 ,Sequencer1 CPU reset due to ICECRUSHER1 reset" "No reset,Reset"
|
|
eventfld.long 0x04 4. " EMULATION_SEQ2_RST2 ,Sequencer2 CPU reset due to emulation reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x04 3. " EMULATION_SEQ1_RST1 ,Sequencer1 CPU reset due to emulation reset" "No reset,Reset"
|
|
eventfld.long 0x04 2. " HDVICP_RST3 ,HDVICP logic and SL2 SW reset" "No reset,Reset"
|
|
eventfld.long 0x04 1. " HDVICP_RST2 ,HDVICP Sequencer2 CPU SW reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x04 0. " HDVICP_RST1 ,HDVICP Sequencer1 CPU SW reset" "No reset,Reset"
|
|
tree.end
|
|
tree "PRM_ISP"
|
|
group.long 0xd00++0x3
|
|
line.long 0x00 "PM_ISP_PWRSTCTRL,ISP Power State Control Register"
|
|
bitfld.long 0x00 16.--17. " ISP_MEM_ONSTATE ,ISP memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request (after a sleep transition)" "Not requested,Requested"
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
|
|
rgroup.long 0xd04++0x3
|
|
line.long 0x00 "PM_ISP_PWRSTST,ISP Power Domain State Status Register"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
|
|
bitfld.long 0x00 4.--5. " ISP_MEM_STATEST ,ISP memory state status" "OFF,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
|
|
group.long 0xd10++0x7
|
|
line.long 0x00 "RM_ISP_RSTCTRL,ISP Domain Resets Control Register"
|
|
bitfld.long 0x00 2. " ISP_RST ,ISP logic reset control" "No reset,Reset"
|
|
line.long 0x04 "RM_ISP_RSTST,ISP Domain Reset Sources Register"
|
|
eventfld.long 0x04 2. " ISP_RST ,ISP logic and FDIF SW reset" "No reset,Reset"
|
|
tree.end
|
|
tree "PRM_HDVPSS"
|
|
group.long 0xe00++0x3
|
|
line.long 0x00 "PM_HDVPSS_PWRSTCTRL,HDVPSS Power State Control Register"
|
|
bitfld.long 0x00 16.--17. " HDVPSS_MEM_ONSTATE ,HDVPSS/HDMI memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request (after a sleep transition)" "Not requested,Requested"
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
|
|
rgroup.long 0xe04++0x3
|
|
line.long 0x00 "PM_HDVPSS_PWRSTST,HDVPSS Power Domain State Status Register"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
|
|
bitfld.long 0x00 4.--5. " HDVPSS_MEM_STATEST ,HDVPSS/HDMI memory state status" "OFF,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
|
|
group.long 0xe10++0x7
|
|
line.long 0x00 "RM_HDVPSS_RSTCTRL,HDVPSS/HDMI Domain Resets Control Register"
|
|
bitfld.long 0x00 2. " HDVPSS_RST ,HDVPSS and HDMI reset control" "No reset,Reset"
|
|
line.long 0x04 "RM_HDVPSS_RSTST,HDVPSS Domain Reset Sources Register"
|
|
eventfld.long 0x04 2. " HDVPSS_RST ,HDVPSS and HDMI logic and FDIF SW reset" "No reset,Reset"
|
|
tree.end
|
|
tree "PRM_GFX"
|
|
group.long 0xf00++0x7
|
|
line.long 0x00 "PM_GFX_PWRSTCTRL,GFX Power State Control Register"
|
|
bitfld.long 0x00 16.--17. " GFX_MEM_ONSTATE ,GFX memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request (after a sleep transition)" "Not requested,Requested"
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
|
|
line.long 0x04 "RM_GFX_RSTCTRL,GFX Domain Resets Control Register"
|
|
bitfld.long 0x04 0. " GFX_RST ,GFX local reset control" "No reset,Reset"
|
|
rgroup.long 0xf10++0x3
|
|
line.long 0x00 "PM_GFX_PWRSTST,GFX Power Domain State Status Register"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
|
|
bitfld.long 0x00 4.--5. " GFX_MEM_STATEST ,GFX memory state status" "OFF,Reserved,Reserved,ON"
|
|
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
|
|
group.long 0xf14++0x3
|
|
line.long 0x00 "RM_GFX_RSTST,GFX Domain Reset Sources Register"
|
|
eventfld.long 0x00 0. " GFX_RST ,GFX Domain Logic SW Reset" "No reset,Reset"
|
|
tree.end
|
|
tree "PRM_ALWON"
|
|
group.long 0x1810++0x7
|
|
line.long 0x00 "RM_ALWON_RSTCTRL,ALWAYS ON Domain Resets Control Register"
|
|
bitfld.long 0x00 2. " SECSS_SW_RST ,ALWON2 domain Security SS warm reset control" "No reset,Reset"
|
|
bitfld.long 0x00 0. " SECSS_LRST ,ALWON2 domain Security SS local M3 reset control" "No reset,Reset"
|
|
line.long 0x04 "RM_ALWON_RSTST,ALWAYS ON Domain Reset Sources Register"
|
|
eventfld.long 0x04 7. " ICECRUSHER_SEC_M3_RST ,Security SS Local M3 reset due to ICECRUSHER reset" "No reset,Reset"
|
|
eventfld.long 0x04 6. " ICECRUSHER_MPU_RST ,MPU Processor reset due to ICECRUSHER1 reset" "No reset,Reset"
|
|
eventfld.long 0x04 5. " EMULATION_MPU_RST ,MPU Processor reset due to emulation reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x04 4. " ,Security SS Local M3 reset due to emulation reset" "No reset,Reset"
|
|
eventfld.long 0x04 1. " SEC_M3_RST ,Security SS SW reset" "No reset,Reset"
|
|
eventfld.long 0x04 0. " SEC_M3_LRST ,Security SS local M3 SW reset" "No reset,Reset"
|
|
tree.end
|
|
tree.end
|
|
tree "CM (Clock Manager)"
|
|
tree "CM_DEVICE"
|
|
width 16.
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "CM_CLKOUT_CTRL,SYS_CLKOUT Output Control Register"
|
|
bitfld.long 0x00 7. " SYSCLK_OUT_EN ,SYSCLK_OUT generation control" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--5. " SYSCLK_OUT_DIV ,Clock division factor" "/1,/2,/4,/8,/16,?..."
|
|
bitfld.long 0x00 0.--1. " SYSCLK_OUT_SRC ,Clock source output select" "PLL_DSP,PLL_HDVICP,PLL_VIDEO0,RTCDIVIDER"
|
|
tree.end
|
|
tree "CM_DPLL"
|
|
width 27.
|
|
group.long 0x308++0x3
|
|
line.long 0x00 "CM_SYSCLK3_CLKSEL,SYSCLK3 Clock Select Register"
|
|
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value B for SYSCLK3 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
rgroup.long 0x314++0x3
|
|
line.long 0x00 "CM_SYSCLK6_CLKSEL,SYSCLK6 Clock Select Register"
|
|
bitfld.long 0x00 0. " CLKSEL ,Divider value for SYSCLK6 select" "/2,/4"
|
|
group.long 0x324++0x3
|
|
line.long 0x00 "CM_SYSCLK10_CLKSEL,SYSCLK10 Clock Select Register"
|
|
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value B for SYSCLK10 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
group.long 0x340++0x17
|
|
line.long 0x00 "CM_PV2B3_CLKSEL,PLL_VIDEO2 B3 Clock Select Register"
|
|
bitfld.long 0x00 0.--1. " CLKSEL ,Divider value B3 for PLL_VIDEO2 select" "/1,/2,/22,?..."
|
|
line.long 0x04 "CM_PV1C1_CLKSEL,PLL_VIDEO1 C1 Clock Select Register"
|
|
bitfld.long 0x04 0.--1. " CLKSEL ,Divider value C1 for PLL_VIDEO1 select" "/1,/2,/22,?..."
|
|
line.long 0x08 "CM_PV0D1_CLKSEL,PLL_VIDEO0 D1 Clock Select Register"
|
|
bitfld.long 0x08 0.--2. " CLKSEL ,Divider value D1 for PLL_VIDEO0 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x0c "CM_SYSCLK19_CLKSEL,SYSCLK19 Clock Select Register"
|
|
bitfld.long 0x0c 0.--2. " CLKSEL ,Divider value B for SYSCLK19 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x10 "CM_SYSCLK20_CLKSEL,SYSCLK20 Clock Select Register"
|
|
bitfld.long 0x10 0.--2. " CLKSEL ,Divider value C for SYSCLK20 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x14 "CM_SYSCLK21_CLKSEL,SYSCLK21 Clock Select Register"
|
|
bitfld.long 0x14 0.--2. " CLKSEL ,Divider value D for SYSCLK21 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
group.long 0x35c++0x3
|
|
line.long 0x00 "CM_RTCDIVA_CLKSEL,RTCDIVIDER A Clock Select Register"
|
|
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value A for RTCDIVIDER select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
group.long 0x370++0x1b
|
|
line.long 0x00 "CM_SYSCLK14_CLKSEL,SYSCLK14 Clock Source Select Register"
|
|
bitfld.long 0x00 0.--1. " CLKSEL ,Clock source for SYSCLK14 select" "PLL_VIDEO2 B3 div,DEV Clock,PLL_VIDEO1 C1 div,?..."
|
|
line.long 0x04 "CM_SYSCLK16_CLKSEL,SYSCLK16 Clock Source Select Register"
|
|
bitfld.long 0x04 0. " CLKSEL ,Clock source for SYSCLK16 select" "PLL_VIDEO0 D1 div,PLL_VIDEO2 B3 div"
|
|
line.long 0x08 "CM_SYSCLK18_CLKSEL,SYSCLK18 Clock Source Select Register"
|
|
bitfld.long 0x08 0. " CLKSEL ,Clock source for SYSCLK18 select" "CLKIN32/RTCDIVIDER mux,RTCDIVIDER A div"
|
|
line.long 0x0c "CM_AUDIOCLK_MCASP0_CLKSEL,McASP0 Audio Clock Source Select Register"
|
|
bitfld.long 0x0c 0.--1. " CLKSEL ,Clock source for McASP0 audio clock select" "SYSCLK20,SYSCLK21,SYSCLK22,?..."
|
|
line.long 0x10 "CM_AUDIOCLK_MCASP1_CLKSEL,McASP1 Audio Clock Source Select Register"
|
|
bitfld.long 0x10 0.--1. " CLKSEL ,Clock source for McASP1 audio clock select" "SYSCLK20,SYSCLK21,SYSCLK22,?..."
|
|
line.long 0x14 "CM_AUDIOCLK_MCASP2_CLKSEL,McASP2 Audio Clock Source Select Register"
|
|
bitfld.long 0x14 0.--1. " CLKSEL ,Clock source for McASP2 audio clock select" "SYSCLK20,SYSCLK21,SYSCLK22,?..."
|
|
line.long 0x18 "CM_AUDIOCLK_MCBSP_CLKSEL,McBSP Audio Clock Source Select Register"
|
|
bitfld.long 0x18 0.--1. " CLKSEL ,Clock source for McBSP audio clock multiplexor with in PRCM" "SYSCLK20,SYSCLK21,SYSCLK22,?..."
|
|
group.long 0x3ac++0x7
|
|
line.long 0x00 "CM_HDMI_CLKSEL,HDMI Audio Clock Source Select Register"
|
|
bitfld.long 0x00 0.--1. " CLKSEL ,Clock source for HDMI audio clock select" "SYSCLK20,SYSCLK21,SYSCLK22,?..."
|
|
line.long 0x04 "CM_SYSCLK23_CLKSEL,SYSCLK23 Clock Select Register"
|
|
bitfld.long 0x04 0.--2. " CLKSEL ,Divider value D for SYSCLK23 select" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
tree.end
|
|
tree "CM_DSP"
|
|
width 18.
|
|
group.long 0x400++0x3
|
|
line.long 0x00 "CM_DSP_CLKSTCTRL,DSP Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_DSP_CLK ,State of the DSP clock domain" "Gated,Active"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,DSP clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
group.long 0x420++0x3
|
|
line.long 0x00 "CM_DSP_CLKCTRL,DSP Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
tree "CM_ALWON2"
|
|
width 29.
|
|
group.long 0x504++0x17
|
|
line.long 0x00 "CM_ALWON2_L3_MED_CLKSTCTRL,L3_MED Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_L3_MED_GCLK ,State of the L3_SLOW_GCL clock" "Gated,Active"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3_MED clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
line.long 0x04 "CM_ALWON2_L3_FAST_CLKSTCTRL,L3_FAST Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x04 9. " CLKACTIVITY_DDR_GCLK ,State of the DDR_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x04 8. " CLKACTIVITY_L3_FAST_GCLK ,State of the L3_FAST_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x04 0.--1. " CLKTRCTRL ,L3_FAST clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
line.long 0x08 "CM_ALWON2_TPPSS_CLKSTCTRL,TPPSS Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x08 14. " CLKACTIVITY_TPPSS_SYSCLK_EN ,State of the TPPSS_SYSCLK_EN clock" "Gated,Active"
|
|
bitfld.long 0x08 13. " CLKACTIVITY_TPPSS_MTS_GCLK ,State of the TPPSS_MTS_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x08 12. " CLKACTIVITY_TPPSS_TOUT_GCLK ,State of the TPPSS_TOUT_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x08 11. " CLKACTIVITY_TPPSS_STC1_GCLK ,State of the TPPSS_STC1_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x08 10. " CLKACTIVITY_TPPSS_STC0_GCLK ,State of the TPPSS_STC0_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x08 9. " CLKACTIVITY_TPPSS_ARM_GCLK ,State of the TPPSS_ARM_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CLKACTIVITY_TPPSS_SYS_GCLK ,State of the TPPSS_SYS_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL ,TPPSS clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
line.long 0x0c "CM_ALWON2_PCI_CLKSTCTRL,PCI Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x0c 8. " CLKACTIVITY_PCI_GCLK ,State of the PCI_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x0c 0.--1. " CLKTRCTRL ,PCI clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
line.long 0x10 "CM_ALWON2_L3_SLOW_CLKSTCTRL,L3_SLOW Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x10 8. " CLKACTIVITY_L3_SLOW_GCLK ,State of the L3_SLOW_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x10 0.--1. " CLKTRCTRL ,L3_SLOW clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
line.long 0x14 "CM_ALWON2_MC_CLKSTCTRL,MC Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x14 9. " CLKACTIVITY_MC_GCLKIN200TR ,State of the CLKIN200TR clock" "Gated,Active"
|
|
bitfld.long 0x14 8. " CLKACTIVITY_MC_GCLKINTR ,State of the CLKINTR clock" "Gated,Active"
|
|
bitfld.long 0x14 0.--1. " CLKTRCTRL ,Media Controller clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
width 29.
|
|
group.long 0x528++0x7
|
|
line.long 0x00 "CM_ALWON2_DMM_CLKCTRL,DMM Clocks Control Register"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_ALWON2_FW_CLKCTRL,EMIF FW Clocks Control Register"
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x554++0x7
|
|
line.long 0x00 "CM_ALWON2_TPPSS_CLKCTRL,TPPSS Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_ALWON2_USB_CLKCTRL,USB Clocks Control Register"
|
|
bitfld.long 0x04 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x560++0x3
|
|
line.long 0x00 "CM_ALWON2_SATA_CLKCTRL,SATA Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x574++0x7
|
|
line.long 0x00 "CM_ALWON2_MC_CLKCTRL,Media Controller Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_ALWON2_PCI_CLKCTRL,PCI Clocks Control Register"
|
|
bitfld.long 0x04 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
tree "CM_HDVICP"
|
|
width 24.
|
|
group.long 0x600++0x3
|
|
line.long 0x00 "CM_HDVICP_CLKSTCTRL,HDVICP Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_HDVICP_GCLK ,State of the HDVICP_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,HDVICP clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
width 24.
|
|
group.long 0x620++0x7
|
|
line.long 0x00 "CM_HDVICP_CLKCTRL,HDVICP Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_HDVICP_SL2_CLKCTRL,SL2 Clocks Control Register"
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
tree "CM_ISP"
|
|
width 24.
|
|
group.long 0x700++0x3
|
|
line.long 0x00 "CM_ISP_CLKSTCTRL,ISP Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_ISP_GCLK ,State of the ISP_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,ISP clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
width 24.
|
|
group.long 0x720++0x7
|
|
line.long 0x00 "CM_ISP_CLKCTRL,ISP Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_ISP_FDIF_CLKCTRL,FDIF Clocks Control Register"
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
tree "CM_HDVPSS"
|
|
width 24.
|
|
group.long 0x800++0x3
|
|
line.long 0x00 "CM_HDVPSS_CLKSTCTRL,HDVPSS Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_HDVPSS_GCLK ,State of the HDVPSS_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,HDVPSS clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
width 24.
|
|
group.long 0x820++0x7
|
|
line.long 0x00 "CM_HDVPSS_CLKCTRL,HDVPSS Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_HDVPSS_HDMI_CLKCTRL,HDMI Clocks Control Register"
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
tree "CM_GFX"
|
|
width 24.
|
|
group.long 0x900++0x3
|
|
line.long 0x00 "CM_GFX_CLKSTCTRL,GFX Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_GFX_GCLK ,State of the GFX_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,GFX clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
width 24.
|
|
group.long 0x920++0x3
|
|
line.long 0x00 "CM_GFX_CLKCTRL,GFX Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
tree "CM_ALWON"
|
|
width 30.
|
|
group.long 0x1400++0x7
|
|
line.long 0x00 "CM_ALWON_L3_SLOW_CLKSTCTRL,L3_SLOW Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 27. " CLKACTIVITY_SDIO_CLKADPI_GCLK ,State of the SDIO_ADPI clock" "Gated,Active"
|
|
bitfld.long 0x00 26. " CLKACTIVITY_UART5_GCLK ,State of the UART5 clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CLKACTIVITY_UART4_GCLK ,State of the UART4 clock" "Gated,Active"
|
|
bitfld.long 0x00 24. " CLKACTIVITY_UART3_GCLK ,State of the UART3 clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CLKACTIVITY_PATA_GCLK ,State of the PATA clock" "Gated,Active"
|
|
bitfld.long 0x00 21. " CLKACTIVITY_MLB_GCLK ,State of the MLB clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CLKACTIVITY_ATL_GCLK ,State of the ALT clock" "Gated,Active"
|
|
bitfld.long 0x00 19. " CLKACTIVITY_MCASP345_GCLK ,State of the MCASP 3/4/5 clocks" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CLKACTIVITY_SPI_GSYSCLK ,State of the SPI_GSYSCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 16. " CLKACTIVITY_I2C_GSYSCLK ,State of the I2C_GSYSCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CLKACTIVITY_GPIO_1_GDBCLK ,State of the GPIO_GDBCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 14. " CLKACTIVITY_GPIO_0_GDBCLK ,State of the GPIO_GDBCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLKACTIVITY_UART_GFCLK ,State of the UART_GFCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 12. " CLKACTIVITY_MCBSP_AUX_GCLK ,State of the MCBSP_AUX_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLKACTIVITY_MCASP2_AUX_GCLK ,State of the MCASP2_AUX_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 10. " CLKACTIVITY_MCASP1_AUX_GCLK ,State of the MCASP1_AUX_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKACTIVITY_MCASP0_AUX_GCLK ,State of the MCASP0_AUX_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_L3_SLOW_GCLK ,State of the L3_SLOW_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3_SLOW clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
line.long 0x04 "CM_ETHERNET_CLKSTCTRL,ETHERNET Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x04 9. " CLKACTIVITY_RFT_GCLK ,State of the CPGMAC_RFT_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x04 8. " CLKACTIVITY_ETHERNET_GCLK ,State of the ETHERNET_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CLKTRCTRL ,ETHERNET clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
rgroup.long 0x1408++0x3
|
|
line.long 0x00 "CM_ALWON_L3_MED_CLKSTCTRL,L3_MED Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_SECSS_GCLK ,State of the SECSS_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3 Medium clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
group.long 0x140c++0xf
|
|
line.long 0x00 "CM_MMU_CLKSTCTRL,MMU Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_MMU_GCLK ,State of the MMU_GICLK clock" "Gated,Active"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,MMU clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
line.long 0x04 "CM_MMUCFG_CLKSTCTRL,MMUCFG Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x04 8. " CLKACTIVITY_MMUCFG_GCLK ,State of the MMUCFG_GICLK clock" "Gated,Active"
|
|
bitfld.long 0x04 0.--1. " CLKTRCTRL ,MMU CFG clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
line.long 0x08 "CM_ALWON_OCMC_0_CLKSTCTRL,OCMC 0 Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x08 8. " CLKACTIVITY_OCMC_0_GCLK ,State of the OCMC_0_GICLK clock" "Gated,Active"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL ,OCMC 0 clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
line.long 0x0c "CM_ALWON_VCP_CLKSTCTRL,VCP Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x0c 8. " CLKACTIVITY_VCP_GCLK ,State of the VCP_GICLK clock" "Gated,Active"
|
|
bitfld.long 0x0c 0.--1. " CLKTRCTRL ,VCP clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
rgroup.long 0x141c++0x7
|
|
line.long 0x00 "CM_ALWON_MPU_CLKSTCTRL,MPU Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_MPU_GCLK ,State of the MPU_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,MPU (ARM Cortex-A8) clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
|
|
line.long 0x04 "CM_ALWON_SYSCLK4_CLKSTCTRL,SYSCLK4 Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x04 11. " CLKACTIVITY_L3_F_EN_GCLK ,State of the L3_F_EN_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x04 10. " CLKACTIVITY_L3_S_GCLK ,State of the L3_S_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CLKACTIVITY_L3_M_GCLK ,State of the L3_M_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x04 8. " CLKACTIVITY_SYSCLK4_GCLK ,State of the SYSCLK4_GCLK clock" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CLKTRCTRL ,SYSCLK4 clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
|
|
rgroup.long 0x1428++0x7
|
|
line.long 0x00 "CM_ALWON_SYSCLK6_CLKSTCTRL,SYSCLK6 Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_SYSCLK6_GCLK ,State of the SYSCLK6_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,SYSCLK6 clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
|
|
line.long 0x04 "CM_ALWON_RTC_CLKSTCTRL,RTC Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x04 8. " CLKACTIVITY_RTC_GCLK ,State of the RTC_GCLK clock" "Gated,Active"
|
|
bitfld.long 0x04 0.--1. " CLKTRCTRL ,RTC clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
|
|
group.long 0x1430++0x3
|
|
line.long 0x00 "CM_ALWON_L3_FAST_CLKSTCTRL,L3_FAST Clock Domain State Transitions Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_FAST_GCLK ,State of the L3 Fast clock for TPTC and TPCC" "Gated,Active"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3 Fast clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
width 30.
|
|
group.long 0x1540++0x1b
|
|
line.long 0x0 "CM_ALWON_MCASP0_CLKCTRL,MCASP0 Clocks Control Register"
|
|
bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_MCASP1_CLKCTRL,MCASP1 Clocks Control Register"
|
|
bitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_MCASP2_CLKCTRL,MCASP2 Clocks Control Register"
|
|
bitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0xC "CM_ALWON_MCBSP_CLKCTRL,MCBSP Clocks Control Register"
|
|
bitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x10 "CM_ALWON_UART_0_CLKCTRL,UART_0 Clocks Control Register"
|
|
bitfld.long 0x10 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x14 "CM_ALWON_UART_1_CLKCTRL,UART_1 Clocks Control Register"
|
|
bitfld.long 0x14 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x18 "CM_ALWON_UART_2_CLKCTRL,UART_2 Clocks Control Register"
|
|
bitfld.long 0x18 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x155c++0xf
|
|
line.long 0x00 "CM_ALWON_GPIO_0_CLKCTRL,GPIO_0 Clocks Control Register"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_ALWON_GPIO_1_CLKCTRL,GPIO1/2/3 Clocks Control Register"
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
bitfld.long 0x04 8. " OPTFCLKEN_DBCLK ,Optional functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x08 "CM_ALWON_I2C_02_CLKCTRL,I2C[0] and I2C[2] Clocks Control Register"
|
|
bitfld.long 0x08 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x0c "CM_ALWON_I2C_13_CLKCTRL,I2C[1] and I2C[3] Clocks Control Register"
|
|
bitfld.long 0x0c 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
rgroup.long 0x156c++0x3
|
|
line.long 0x00 "CM_ALWON_MCASP_3_4_5_CLKCTRL,MCASP_3_4_5 Clocks Control Register"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x1570++0xb
|
|
line.long 0x00 "CM_ALWON_ATL_CLKCTRL,ATL Clocks Control Register"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_ALWON_MLB_CLKCTRL,MLB Clocks Control Register"
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x08 "CM_ALWON_PATA_CLKCTRL,PATA Clocks Control Register"
|
|
bitfld.long 0x08 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x1580++0xb
|
|
line.long 0x0 "CM_ALWON_UART_3_CLKCTRL,UART_3 Clocks Control Register"
|
|
bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_UART_4_CLKCTRL,UART_4 Clocks Control Register"
|
|
bitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_UART_5_CLKCTRL,UART_5 Clocks Control Register"
|
|
bitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
rgroup.long 0x158c++0x3
|
|
line.long 0x00 "CM_ALWON_WDTIMER_CLKCTRL,WDTIMER Clocks Control Register"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x1590++0xf
|
|
line.long 0x00 "CM_ALWON_SPI_CLKCTRL,SPI0/1/2/3 Clocks Control Register"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_ALWON_MAILBOX_CLKCTRL,MAILBOX Clocks Control Register"
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x08 "CM_ALWON_SPINBOX_CLKCTRL,SPINBOX Clocks Control Register"
|
|
bitfld.long 0x08 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x0c "CM_ALWON_MMUDATA_CLKCTRL,MMU Data Clocks Control Register"
|
|
bitfld.long 0x0c 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x15a8++0x3
|
|
line.long 0x00 "CM_ALWON_MMUCFG_CLKCTRL,MMU Config Clocks Control Register"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x15b0++0x17
|
|
line.long 0x0 "CM_ALWON_SDIO_CLKCTRL,SDIO Clocks Control Register"
|
|
bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_OCMC_0_CLKCTRL,OCMC_0 Clocks Control Register"
|
|
bitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_VCP_CLKCTRL,VCP Clocks Control Register"
|
|
bitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0xC "CM_ALWON_SMARTCARD_0_CLKCTRL,SMARTCARD_0 Clocks Control Register"
|
|
bitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x10 "CM_ALWON_SMARTCARD_1_CLKCTRL,SMARTCARD_1 Clocks Control Register"
|
|
bitfld.long 0x10 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x14 "CM_ALWON_CONTROL_CLKCTRL,CONTROL Clocks Control Register"
|
|
bitfld.long 0x14 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
rgroup.long 0x15c8++0x3
|
|
line.long 0x00 "CM_ALWON_SECSS_CLKCTRL,Security SS Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x15d0++0x7
|
|
line.long 0x00 "CM_ALWON_GPMC_CLKCTRL,GPMC Clocks Control Register"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x04 "CM_ALWON_ETHERNET_0_CLKCTRL,ETHERNET_0 Clocks Control Register"
|
|
bitfld.long 0x04 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
rgroup.long 0x15dc++0x3
|
|
line.long 0x00 "CM_ALWON_MPU_CLKCTRL,MPU Clocks Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Reserved,Reserved,Enabled,?..."
|
|
width 30.
|
|
group.long 0x15e0++0x3
|
|
line.long 0x00 "CM_ALWON_DEBUGSS_CLKCTRL,DEBUGSS Clocks Control Register"
|
|
bitfld.long 0x00 27.--29. " STM_PMD_CLKDIVSEL ,STM clock divider control" "Reserved,/1,/2,Reserved,/4,?..."
|
|
bitfld.long 0x00 24.--26. " TRC_PMD_CLKDIVSEL ,TPIU clock divider control" "Reserved,/1,/2,Reserved,/4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " STM_PMD_CLKSEL ,Trace clock source selection for STM" "Sys Clk,Ref. Clk A,?..."
|
|
bitfld.long 0x00 20.--21. " TRC_PMD_CLKSEL ,Trace clock source selection for TPIU" "Sys Clk,Ref. Clk A,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OPTCLK_DEBUG_CLKA ,Optional functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " OPTCLK_DEBUG_SYSCLK ,Optional functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Reserved,Reserved,Enabled,?..."
|
|
width 30.
|
|
rgroup.long 0x15e4++0xf
|
|
line.long 0x0 "CM_ALWON_L3_CLKCTRL,L3 Clocks Control Register"
|
|
bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_L4HS_CLKCTRL,L4HS Clocks Control Register"
|
|
bitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_L4LS_CLKCTRL,L4LS Clocks Control Register"
|
|
bitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0xC "CM_ALWON_RTC_CLKCTRL,RTC Clocks Control Register"
|
|
bitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x15f4++0x3
|
|
line.long 0x00 "CM_ALWON_TPCC_CLKCTRL,TPCC Clocks Control Register"
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x15f8++0xf
|
|
line.long 0x0 "CM_ALWON_TPTC0_CLKCTRL,TPTC0 Clocks Control Register"
|
|
bitfld.long 0x0 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_TPTC1_CLKCTRL,TPTC1 Clocks Control Register"
|
|
bitfld.long 0x4 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_TPTC2_CLKCTRL,TPTC2 Clocks Control Register"
|
|
bitfld.long 0x8 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0xC "CM_ALWON_TPTC3_CLKCTRL,TPTC3 Clocks Control Register"
|
|
bitfld.long 0xC 18. " STBYST ,Module standby status" "Functional,Standby"
|
|
textline " "
|
|
bitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x1608++0xf
|
|
line.long 0x0 "CM_ALWON_SR_0_CLKCTRL,Smart Reflex 0 Clocks Control Register"
|
|
bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_SR_1_CLKCTRL,Smart Reflex 1 Clocks Control Register"
|
|
bitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_SR_2_CLKCTRL,Smart Reflex 2 Clocks Control Register"
|
|
bitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0xC "CM_ALWON_SR_3_CLKCTRL,Smart Reflex 3 Clocks Control Register"
|
|
bitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
group.long 0x1618++0xf
|
|
line.long 0x0 "CM_ALWON_DCAN_0_1_CLKCTRL,DCAN_0_1 Clocks Control Register"
|
|
bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x4 "CM_ALWON_MMCHS_0_CLKCTRL,MMCHS_0 Clocks Control Register"
|
|
bitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0x8 "CM_ALWON_MMCHS_1_CLKCTRL,MMCHS_1 Clocks Control Register"
|
|
bitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
line.long 0xC "CM_ALWON_MMCHS_2_CLKCTRL,MMCHS_2 Clocks Control Register"
|
|
bitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
tree.end
|
|
tree "REVISION_PRM"
|
|
width 14.
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x00 "REVISION_PRM,PRCM Revision Code Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,PRCM revision"
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "INTC (Interrupt Controller)"
|
|
base ad:0x48200000
|
|
width 21.
|
|
rgroup.long 0x000++0x03
|
|
line.long 0x00 "INTCPS_REVISION,Revision Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MINOR ,Manor revision"
|
|
group.long 0x010++0x03
|
|
line.long 0x00 "INTCPS_SYSCONFIG,Configuration Register"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Free-running,AutoClkGate"
|
|
rgroup.long 0x014++0x03
|
|
line.long 0x00 "INTCPS_SYSSTATUS,Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x040++0x03
|
|
line.long 0x00 "INTCPS_SIR_IRQ,Active IRQ Interrupt Number Register"
|
|
hexmask.long 0x00 7.--31. 1. " SPURIOUSIRQ ,Spurious IRQ flag"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ACTIVEIRQ ,Active IRQ number"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "INTCPS_SIR_FIQ,Active FIQ Interrupt Number Register"
|
|
hexmask.long 0x00 7.--31. 1. " SPURIOUSFIQ ,Spurious FIQ flag"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ACTIVEFIQ ,Active FIQ number"
|
|
wgroup.long 0x048++0x03
|
|
line.long 0x00 "INTCPS_CONTROL,Control Register"
|
|
bitfld.long 0x00 1. " NEWFIQAGR ,Reset FIQ output and enable new FIQ generation" "No effect,Reset/new FIQ"
|
|
bitfld.long 0x00 0. " NEWIRQAGR ,New IRQ generation" "No effect,Reset/new IRQ"
|
|
group.long 0x04C++0x07
|
|
line.long 0x00 "INTCPS_PROTECTION,Protection Register"
|
|
bitfld.long 0x00 0. " PROTECTION ,Protection mode" "Disabled,Enabled"
|
|
line.long 0x04 "INTCPS_IDLE,Idle Register"
|
|
bitfld.long 0x04 1. " TURBO ,Input synchroniser clock auto-gating" "Free-running,Auto-gated"
|
|
bitfld.long 0x04 0. " FUNCIDLE ,Functional clock auto-idle mode" "Auto-gated,Free-running"
|
|
rgroup.long 0x060++0x07
|
|
line.long 0x00 "INTCPS_IRQ_PRIORITY,IRQ Priority Register"
|
|
hexmask.long 0x00 7.--31. 1. " SPURIOUSIRQFLAG ,Spurious IRQ flag"
|
|
hexmask.long.byte 0x00 0.--6. 1. " IRQPRIORITY ,Current IRQ priority"
|
|
line.long 0x04 "INTCPS_FIQ_PRIORITY,FIQ Priority Register"
|
|
hexmask.long 0x04 7.--31. 1. " SPURIOUSFIQFLAG ,Spurious FIQ flag"
|
|
hexmask.long.byte 0x04 0.--6. 1. " FIQPRIORITY ,Current FIQ priority"
|
|
group.long 0x068++0x03
|
|
line.long 0x00 "INTCPS_THRESHOLD,Priority Threshold Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITYTHRESHOLD ,Priority threshold"
|
|
width 21.
|
|
tree "Interrupts 0-31"
|
|
rgroup.long 0x080++0x03
|
|
line.long 0x00 "INTCPS_ITR0,Raw Interrupt Input Status Register 0"
|
|
bitfld.long 0x00 31. " ITR[31] ,I2CINT3 Interrupt status before masking 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " ITR[30] ,I2CINT2 Interrupt status before masking 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " ITR[29] ,SDINT2 Interrupt status before masking 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " ITR[28] ,SDINT1 Interrupt status before masking 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 27. " ITR[27] ,TPPERRINT1 Interrupt status before masking 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " ITR[26] ,TPPERRINT0 Interrupt status before masking 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " ITR[25] ,TPPDMABS Interrupt status before masking 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ITR[24] ,TPPDMAPKT Interrupt status before masking 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ITR[23] ,TPPSTCINT1 Interrupt status before masking 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " ITR[22] ,TPPSTCINT0 Interrupt status before masking 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " ITR[21] ,TPPMBOXINT Interrupt status before masking 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " ITR[20] ,TPPSSERR Interrupt status before masking 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " ITR[19] ,USBINT1 Interrupt status before masking 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " ITR[18] ,USBINT0 Interrupt status before masking 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " ITR[17] ,USBSSINT Interrupt status before masking 17" "No interrupt,Interrupt"
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x00 16. " ITR[16] ,SATAINT Interrupt status before masking 16" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " ITR[15] ,WDTINT0 Interrupt status before masking 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " ITR[14] ,EDMAERRINT Interrupt status before masking 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " ITR[13] ,EDMAMPERR Interrupt status before masking 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " ITR[12] ,EDMACOMPINT Interrupt status before masking 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ITR[11] ,TINT8 Interrupt status before masking 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " ITR[10] ,L3APPINT Interrupt status before masking 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " ITR[9] ,L3DEBUG Interrupt status before masking 9" "No interrupt,Interrupt"
|
|
sif (cpuis("AM387*"))
|
|
bitfld.long 0x00 8. " ITR[8] ,SEC_EVENT Interrupt status before masking 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITR[7] ,NMI Interrupt status before masking 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " ITR[6] ,SSM_IRQ Interrupt status before masking 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ITR[5] ,SSM_WFI_IRQ Interrupt status before masking 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " ITR[4] ,ELM_IRQ Interrupt status before masking 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ITR[3] ,BENCH Interrupt status before masking 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ITR[2] ,COMMRX Interrupt status before masking 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " ITR[1] ,COMMTX Interrupt status before masking 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " ITR[0] ,EMUINT Interrupt status before masking 0" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 7. " ITR[7] ,NMI Interrupt status before masking 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITR[4] ,ELM_IRQ Interrupt status before masking 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " ITR[3] ,BENCH Interrupt status before masking 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ITR[2] ,COMMRX Interrupt status before masking 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " ITR[1] ,COMMTX Interrupt status before masking 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ITR[0] ,EMUINT Interrupt status before masking 0" "No interrupt,Interrupt"
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "INTCPS_MIR0_set/clr,Interrupt Mask Register 0"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x04 31. " MR31 ,I2CINT3 Interrupt mask 31" "Not masked,Masked"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x04 30. " MR30 ,I2CINT2 Interrupt mask 30" "Not masked,Masked"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x04 29. " MR29 ,SDINT2 Interrupt mask 29" "Not masked,Masked"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " MR28 ,SDINT1 Interrupt mask 28" "Not masked,Masked"
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " MR27 ,TPPERRINT1 Interrupt mask 27" "Not masked,Masked"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x04 26. " MR26 ,TPPERRINT0 Interrupt mask 26" "Not masked,Masked"
|
|
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " MR25 ,TPPDMABS Interrupt mask 25" "Not masked,Masked"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x04 24. " MR24 ,TPPDMAPKT Interrupt mask 24" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x08 23. 0x04 23. " MR23 ,TPPSTCINT1 Interrupt mask 23" "Not masked,Masked"
|
|
setclrfld.long 0x00 22. 0x08 22. 0x04 22. " MR22 ,TPPSTCINT0 Interrupt mask 22" "Not masked,Masked"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x04 21. " MR21 ,TPPMBOXINT Interrupt mask 21" "Not masked,Masked"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " MR20 ,TPPSSERR Interrupt mask 20" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " MR19 ,USBINT1 Interrupt mask 19" "Not masked,Masked"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " MR18 ,USBINT0 Interrupt mask 18" "Not masked,Masked"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " MR17 ,USBSSINT Interrupt mask 17" "Not masked,Masked"
|
|
sif (!cpuis("DRA62*"))
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " MR16 ,SATAINT Interrupt mask 16" "Not masked,Masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x08 15. 0x04 15. " MR15 ,WDTINT0 Interrupt mask 15" "Not masked,Masked"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " MR14 ,EDMAERRINT Interrupt mask 14" "Not masked,Masked"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " MR13 ,EDMAMPERR Interrupt mask 13" "Not masked,Masked"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " MR12 ,EDMACOMPINT Interrupt mask 12" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " MR11 ,TINT8 Interrupt mask 11" "Not masked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " MR10 ,L3APPINT Interrupt mask 10" "Not masked,Masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " MR9 ,L3DEBUG Interrupt mask 9" "Not masked,Masked"
|
|
sif (cpuis("AM387*"))
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " MR8 ,SEC_EVENT Interrupt mask 8" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " MR7 ,NMI Interrupt mask 7" "Not masked,Masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " MR6 ,SSM_IRQ Interrupt mask 6" "Not masked,Masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " MR5 ,SSM_WFI_IRQ Interrupt mask 5" "Not masked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " MR4 ,ELM_IRQ Interrupt mask 4" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " MR3 ,BENCH Interrupt mask 3" "Not masked,Masked"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " MR2 ,COMMRX Interrupt mask 2" "Not masked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " MR1 ,COMMTX Interrupt mask 1" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " MR0 ,EMUINT Interrupt mask 0" "Not masked,Masked"
|
|
else
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " MR7 ,NMI Interrupt mask 7" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " MR4 ,ELM_IRQ Interrupt mask 4" "Not masked,Masked"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " MR3 ,BENCH Interrupt mask 3" "Not masked,Masked"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " MR2 ,COMMRX Interrupt mask 2" "Not masked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " MR1 ,COMMTX Interrupt mask 1" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " MR0 ,EMUINT Interrupt mask 0" "Not masked,Masked"
|
|
endif
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "INTCPS_ISR0_set/clr,Software Interrupt Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ISR31 ,I2CINT3 Software interrupt 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " ISR30 ,I2CINT2 Software interrupt 30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " ISR29 ,SDINT2 Software interrupt 29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISR28 ,SDINT1 Software interrupt 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " ISR27 ,TPPERRINT1 Software interrupt 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " ISR26 ,TPPERRINT0 Software interrupt 26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " ISR25 ,TPPDMABS Software interrupt 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " ISR24 ,TPPDMAPKT Software interrupt 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " ISR23 ,TPPSTCINT1 Software interrupt 23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " ISR22 ,TPPSTCINT0 Software interrupt 22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " ISR21 ,TPPMBOXINT Software interrupt 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " ISR20 ,TPPSSERR Software interrupt 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " ISR19 ,USBINT1 Software interrupt 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " ISR18 ,USBINT0 Software interrupt 18" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " ISR17 ,USBSSINT Software interrupt 17" "No interrupt,Interrupt"
|
|
sif (!cpuis("DRA62*"))
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " ISR16 ,SATAINT Software interrupt 16" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " ISR15 ,WDTINT0 Software interrupt 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " ISR14 ,EDMAERRINT Software interrupt 14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ISR13 ,EDMAMPERR Software interrupt 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " ISR12 ,EDMACOMPINT Software interrupt 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " ISR11 ,TINT8 Software interrupt 11" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " ISR10 ,L3APPINT Software interrupt 10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " ISR9 ,L3DEBUG Software interrupt 9" "No interrupt,Interrupt"
|
|
sif (cpuis("AM387*"))
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " ISR8 ,SEC_EVENT Software interrupt 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " ISR7 ,NMI Software interrupt 7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " ISR6 ,SSM_IRQ Software interrupt 6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " ISR5 ,SSM_WFI_IRQ Software interrupt 5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " ISR4 ,ELM_IRQ Software interrupt 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " ISR3 ,BENCH Software interrupt 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " ISR2 ,COMMRX Software interrupt 2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " ISR1 ,COMMTX Software interrupt 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " ISR0 ,EMUINT Software interrupt 0" "No interrupt,Interrupt"
|
|
else
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " ISR7 ,NMI Software interrupt 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " ISR4 ,ELM_IRQ Software interrupt 4" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " ISR3 ,BENCH Software interrupt 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " ISR2 ,COMMRX Software interrupt 2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " ISR1 ,COMMTX Software interrupt 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " ISR0 ,EMUINT Software interrupt 0" "No interrupt,Interrupt"
|
|
endif
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "INTCPS_PENDING_IRQ0,IRQ Status Register 0"
|
|
bitfld.long 0x00 31. " PENDINGIRQ[31] ,I2CINT3 IRQ status after masking 31" "Low,High"
|
|
bitfld.long 0x00 30. " PENDINGIRQ[30] ,I2CINT2 IRQ status after masking 30" "Low,High"
|
|
bitfld.long 0x00 29. " PENDINGIRQ[29] ,SDINT2 IRQ status after masking 29" "Low,High"
|
|
bitfld.long 0x00 28. " PENDINGIRQ[28] ,SDINT1 IRQ status after masking 28" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 27. " PENDINGIRQ[27] ,TPPERRINT1 IRQ status after masking 27" "Low,High"
|
|
bitfld.long 0x00 26. " PENDINGIRQ[26] ,TPPERRINT0 IRQ status after masking 26" "Low,High"
|
|
bitfld.long 0x00 25. " PENDINGIRQ[25] ,TPPDMABS IRQ status after masking 25" "Low,High"
|
|
bitfld.long 0x00 24. " PENDINGIRQ[24] ,TPPDMAPKT IRQ status after masking 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGIRQ[23] ,TPPSTCINT1 IRQ status after masking 23" "Low,High"
|
|
bitfld.long 0x00 22. " PENDINGIRQ[22] ,TPPSTCINT0 IRQ status after masking 22" "Low,High"
|
|
bitfld.long 0x00 21. " PENDINGIRQ[21] ,TPPMBOXINT IRQ status after masking 21" "Low,High"
|
|
bitfld.long 0x00 20. " PENDINGIRQ[20] ,TPPSSERR IRQ status after masking 20" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " PENDINGIRQ[19] ,USBINT1 IRQ status after masking 19" "Low,High"
|
|
bitfld.long 0x00 18. " PENDINGIRQ[18] ,USBINT0 IRQ status after masking 18" "Low,High"
|
|
bitfld.long 0x00 17. " PENDINGIRQ[17] ,USBSSINT IRQ status after masking 17" "Low,High"
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x00 16. " PENDINGIRQ[16] ,SATAINT IRQ status after masking 16" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGIRQ[15] ,WDTINT0 IRQ status after masking 15" "Low,High"
|
|
bitfld.long 0x00 14. " PENDINGIRQ[14] ,EDMAERRINT IRQ status after masking 14" "Low,High"
|
|
bitfld.long 0x00 13. " PENDINGIRQ[13] ,EDMAMPERR IRQ status after masking 13" "Low,High"
|
|
bitfld.long 0x00 12. " PENDINGIRQ[12] ,EDMACOMPINT IRQ status after masking 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGIRQ[11] ,TINT8 IRQ status after masking 11" "Low,High"
|
|
bitfld.long 0x00 10. " PENDINGIRQ[10] ,L3APPINT IRQ status after masking 10" "Low,High"
|
|
bitfld.long 0x00 9. " PENDINGIRQ[9] ,L3DEBUG IRQ status after masking 9" "Low,High"
|
|
sif (cpuis("AM387*"))
|
|
bitfld.long 0x00 8. " PENDINGIRQ[8] ,SEC_EVENT IRQ status after masking 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PENDINGIRQ[7] ,NMI IRQ status after masking 7" "Low,High"
|
|
bitfld.long 0x00 6. " PENDINGIRQ[6] ,SSM_IRQ IRQ status after masking 6" "Low,High"
|
|
bitfld.long 0x00 5. " PENDINGIRQ[5] ,SSM_WFI_IRQ IRQ status after masking 5" "Low,High"
|
|
bitfld.long 0x00 4. " PENDINGIRQ[4] ,ELM_IRQ IRQ status after masking 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PENDINGIRQ[3] ,BENCH IRQ status after masking 3" "Low,High"
|
|
bitfld.long 0x00 2. " PENDINGIRQ[2] ,COMMRX IRQ status before masking 2" "Low,High"
|
|
bitfld.long 0x00 1. " PENDINGIRQ[1] ,COMMTX IRQ status before masking 1" "Low,High"
|
|
bitfld.long 0x00 0. " PENDINGIRQ[0] ,EMUINT IRQ status before masking 0" "Low,High"
|
|
else
|
|
bitfld.long 0x00 7. " PENDINGIRQ[7] ,NMI IRQ status after masking 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PENDINGIRQ[4] ,ELM IRQ status after masking 4" "Low,High"
|
|
bitfld.long 0x00 3. " PENDINGIRQ[3] ,BENCH IRQ status after masking 3" "Low,High"
|
|
bitfld.long 0x00 2. " PENDINGIRQ[2] ,COMMRX IRQ status after masking 2" "Low,High"
|
|
bitfld.long 0x00 1. " PENDINGIRQ[1] ,COMMTX IRQ status after masking 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PENDINGIRQ[0] ,EMUINT IRQ status after masking 0" "Low,High"
|
|
endif
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "INTCPS_PENDING_FIQ0,FIQ Status Register 0"
|
|
bitfld.long 0x00 31. " PENDINGFIQ[31] ,I2CINT3 FIQ status after masking 31" "Low,High"
|
|
bitfld.long 0x00 30. " PENDINGFIQ[30] ,I2CINT2 FIQ status after masking 30" "Low,High"
|
|
bitfld.long 0x00 29. " PENDINGFIQ[29] ,SDINT2 FIQ status after masking 29" "Low,High"
|
|
bitfld.long 0x00 28. " PENDINGFIQ[28] ,SDINT1 FIQ status after masking 28" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 27. " PENDINGFIQ[27] ,TPPERRINT1 FIQ status after masking 27" "Low,High"
|
|
bitfld.long 0x00 26. " PENDINGFIQ[26] ,TPPERRINT0 FIQ status after masking 26" "Low,High"
|
|
bitfld.long 0x00 25. " PENDINGFIQ[25] ,TPPDMABS FIQ status after masking 25" "Low,High"
|
|
bitfld.long 0x00 24. " PENDINGFIQ[24] ,TPPDMAPKT FIQ status after masking 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGFIQ[23] ,TPPSTCINT1 FIQ status after masking 23" "Low,High"
|
|
bitfld.long 0x00 22. " PENDINGFIQ[22] ,TPPSTCINT0 FIQ status after masking 22" "Low,High"
|
|
bitfld.long 0x00 21. " PENDINGFIQ[21] ,TPPMBOXINT FIQ status after masking 21" "Low,High"
|
|
bitfld.long 0x00 20. " PENDINGFIQ[20] ,TPPSSERR FIQ status after masking 20" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " PENDINGFIQ[19] ,USBINT1 FIQ status after masking 19" "Low,High"
|
|
bitfld.long 0x00 18. " PENDINGFIQ[18] ,USBINT0 FIQ status after masking 18" "Low,High"
|
|
bitfld.long 0x00 17. " PENDINGFIQ[17] ,USBSSINT FIQ status after masking 17" "Low,High"
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x00 16. " PENDINGFIQ[16] ,SATAINT FIQ status after masking 16" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGFIQ[15] ,WDTINT0 FIQ status after masking 15" "Low,High"
|
|
bitfld.long 0x00 14. " PENDINGFIQ[14] ,EDMAERRINT FIQ status after masking 14" "Low,High"
|
|
bitfld.long 0x00 13. " PENDINGFIQ[13] ,EDMAMPERR FIQ status after masking 13" "Low,High"
|
|
bitfld.long 0x00 12. " PENDINGFIQ[12] ,EDMACOMPINT FIQ status after masking 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGFIQ[11] ,TINT8 FIQ status after masking 11" "Low,High"
|
|
bitfld.long 0x00 10. " PENDINGFIQ[10] ,L3APPINT FIQ status after masking 10" "Low,High"
|
|
bitfld.long 0x00 9. " PENDINGFIQ[9] ,L3DEBUG FIQ status after masking 9" "Low,High"
|
|
sif (cpuis("AM387*"))
|
|
bitfld.long 0x00 8. " PENDINGIRQ[8] ,SEC_EVENT FIQ status after masking 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PENDINGIRQ[7] ,NMI FIQ status after masking 7" "Low,High"
|
|
bitfld.long 0x00 6. " PENDINGIRQ[6] ,SSM_IRQ FIQ status after masking 6" "Low,High"
|
|
bitfld.long 0x00 5. " PENDINGIRQ[5] ,SSM_WFI_IRQ FIQ status after masking 5" "Low,High"
|
|
bitfld.long 0x00 4. " PENDINGIRQ[4] ,ELM_IRQ FIQ status after masking 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PENDINGIRQ[3] ,BENCH FIQ status after masking 3" "Low,High"
|
|
bitfld.long 0x00 2. " PENDINGIRQ[2] ,COMMRX FIQ status before masking 2" "Low,High"
|
|
bitfld.long 0x00 1. " PENDINGIRQ[1] ,COMMTX FIQ status before masking 1" "Low,High"
|
|
bitfld.long 0x00 0. " PENDINGIRQ[0] ,EMUINT FIQ status before masking 0" "Low,High"
|
|
else
|
|
bitfld.long 0x00 7. " PENDINGFIQ[7] ,NMI FIQ status after masking 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PENDINGFIQ[4] ,ELM_IRQ FIQ status after masking 4" "Low,High"
|
|
bitfld.long 0x00 3. " PENDINGFIQ[3] ,BENCH FIQ status after masking 3" "Low,High"
|
|
bitfld.long 0x00 2. " PENDINGFIQ[2] ,COMMRX FIQ status after masking 2" "Low,High"
|
|
bitfld.long 0x00 1. " PENDINGFIQ[1] ,COMMTX FIQ status after masking 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PENDINGFIQ[0] ,EMUINT FIQ status after masking 0" "Low,High"
|
|
endif
|
|
tree.end
|
|
tree "Interrupts 32-63"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "INTCPS_ITR1,Raw Interrupt Input Status Register 1"
|
|
bitfld.long 0x00 31. " ITR[63] ,GPIOINT3B Interrupt status before masking 63" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " ITR[62] ,GPIOINT3A Interrupt status before masking 62" "No interrupt,Interrupt"
|
|
sif (cpuis("DRA6*"))
|
|
bitfld.long 0x00 29. " ITR[61] ,VCPINT Interrupt status before masking 61" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " ITR[60] ,MLB_INT Interrupt status before masking 60" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ITR[59] ,MLB_SYS_INT1 Interrupt status before masking 59" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " ITR[58] ,MLB_SYS_INT0 Interrupt status before masking 58" "No interrupt,Interrupt"
|
|
endif
|
|
bitfld.long 0x00 25. " ITR[57] ,DCAN1_PARITY Interrupt status before masking 57" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ITR[56] ,DCAN1_INT1 Interrupt status before masking 56" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ITR[55] ,DCAN1_INT0 Interrupt status before masking 55" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " ITR[54] ,DCAN0_PARITY Interrupt status before masking 54" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " ITR[53] ,DCAN0_INT1 Interrupt status before masking 53" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " ITR[52] ,DCAN0_INT0 Interrupt status before masking 52" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITR[51] ,PCIINT3 Interrupt status before masking 51" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " ITR[50] ,PCIINT2 Interrupt status before masking 50" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " ITR[49] ,PCIINT1 Interrupt status before masking 49" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " ITR[48] ,PCIINT0 Interrupt status before masking 48" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ITR[46] ,UARTINT5 Interrupt status before masking 46" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " ITR[45] ,UARTINT4 Interrupt status before masking 45" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " ITR[44] ,UARTINT3 Interrupt status before masking 44" "No interrupt,Interrupt"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 11. " ITR[43] ,EMACSWMISC Interrupt status before masking 43" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITR[42] ,EMACSWTXINT Interrupt status before masking 42" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " ITR[41] ,EMACSWRXINT Interrupt status before masking 41" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " ITR[40] ,EMACSWRXTHR Interrupt status before masking 40" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ITR[37] ,GFXINT Interrupt status before masking 37" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " ITR[36] ,DSSINT Interrupt status before masking 36" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " ITR[35] ,PCIeWAKEUP Interrupt status before masking 35" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 11. " ITR[43] ,3PGSWMISC0 Interrupt status before masking 43" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITR[42] ,3PGSWTXINT0 Interrupt status before masking 42" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " ITR[41] ,3PGSWRXINT0 Interrupt status before masking 41" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " ITR[40] ,3PGSWRXTHR0 Interrupt status before masking 40" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " ITR[39] ,ISS_IRQ_5 Interrupt status before masking 39" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ITR[38] ,HDMIINT Interrupt status before masking 38" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ITR[37] ,GFXINT Interrupt status before masking 37" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " ITR[36] ,DSSINT Interrupt status before masking 36" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " ITR[35] ,PCIeWAKEUP Interrupt status before masking 35" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " ITR[34] ,USBWAKEUP Interrupt status before masking 34" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " ITR[33] ,GPIOINT2B Interrupt status before masking 33" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " ITR[32] ,GPIOINT2A Interrupt status before masking 32" "No interrupt,Interrupt"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "INTCPS_MIR1_set/clr,Interrupt Mask Register 1"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x04 31. " MR63 ,GPIOINT3B Interrupt mask 63" "Not masked,Masked"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x04 30. " MR62 ,GPIOINT3A Interrupt mask 62" "Not masked,Masked"
|
|
sif (cpuis("DRA6*"))
|
|
setclrfld.long 0x00 29. 0x08 29. 0x04 29. " MR61 ,VCPINT Interrupt mask 61" "Not masked,Masked"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " MR60 ,MLB_INT Interrupt mask 60" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " MR59 ,MLB_SYS_INT1 Interrupt mask 59" "Not masked,Masked"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x04 26. " MR58 ,MLB_SYS_INT0 Interrupt mask 58" "Not masked,Masked"
|
|
endif
|
|
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " MR57 ,DCAN1_PARITY Interrupt mask 57" "Not masked,Masked"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x04 24. " MR56 ,DCAN1_INT1 Interrupt mask 56" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x08 23. 0x04 23. " MR55 ,DCAN1_INT0 Interrupt mask 55" "Not masked,Masked"
|
|
setclrfld.long 0x00 22. 0x08 22. 0x04 22. " MR54 ,DCAN0_PARITY Interrupt mask 54" "Not masked,Masked"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x04 21. " MR53 ,DCAN0_INT1 Interrupt mask 53" "Not masked,Masked"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " MR52 ,DCAN0_INT0 Interrupt mask 52" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " MR51 ,PCIINT3 Interrupt mask 51" "Not masked,Masked"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " MR50 ,PCIINT2 Interrupt mask 50" "Not masked,Masked"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " MR49 ,PCIINT1 Interrupt mask 49" "Not masked,Masked"
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " MR48 ,PCIINT0 Interrupt mask 48" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " MR46 ,UARTINT5 Interrupt mask 46" "Not masked,Masked"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " MR45 ,UARTINT4 Interrupt mask 45" "Not masked,Masked"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " MR44 ,UARTINT3 Interrupt mask 44" "Not masked,Masked"
|
|
sif (cpuis("DRA62*"))
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " MR43 ,EMACSWMISC0 Interrupt mask 43" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " MR42 ,EMACSWTXINT0 Interrupt mask 42" "Not masked,Masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " MR41 ,EMACSWRXINT0 Interrupt mask 41" "Not masked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " MR40 ,EMACSWRXTHR0 Interrupt mask 40" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " MR37 ,GFXINT Interrupt mask 37" "Not masked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " MR36 ,DSSINT Interrupt mask 36" "Not masked,Masked"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " MR35 ,PCIeWAKEUP Interrupt mask 35" "Not masked,Masked"
|
|
else
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " MR43 ,3PGSWMISC0 Interrupt mask 43" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " MR42 ,3PGSWTXINT0 Interrupt mask 42" "Not masked,Masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " MR41 ,3PGSWRXINT0 Interrupt mask 41" "Not masked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " MR40 ,3PGSWRXTHR0 Interrupt mask 40" "Not masked,Masked"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " MR39 ,ISS_IRQ_5 Interrupt mask 39" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " MR38 ,HDMIINT Interrupt mask 38" "Not masked,Masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " MR37 ,GFXINT Interrupt mask 37" "Not masked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " MR36 ,DSSINT Interrupt mask 36" "Not masked,Masked"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " MR35 ,PCIeWAKEUP Interrupt mask 35" "Not masked,Masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " MR34 ,USBWAKEUP Interrupt mask 34" "Not masked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " MR33 ,GPIOINT2B Interrupt mask 33" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " MR32 ,GPIOINT2A Interrupt mask 32" "Not masked,Masked"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "INTCPS_ISR1_set/clr,Software Interrupt Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ISR63 ,GPIOINT3B Software interrupt 63" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " ISR62 ,GPIOINT3A Software interrupt 62" "No interrupt,Interrupt"
|
|
sif (cpuis("DRA6*"))
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " ISR61 ,VCPINT Software interrupt 61" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISR60 ,MLB_INT Software interrupt 60" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " ISR59 ,MLB_SYS_INT1 Software interrupt 59" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " ISR58 ,MLB_SYS_INT0 Software interrupt 58" "No interrupt,Interrupt"
|
|
endif
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " ISR57 ,DCAN1_PARITY Software interrupt 57" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " ISR56 ,DCAN1_INT1 Software interrupt 56" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " ISR55 ,DCAN1_INT0 Software interrupt 55" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " ISR54 ,DCAN0_PARITY Software interrupt 54" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " ISR53 ,DCAN0_INT1 Software interrupt 53" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " ISR52 ,DCAN0_INT0 Software interrupt 52" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " ISR51 ,PCIINT3 Software interrupt 51" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " ISR50 ,PCIINT2 Software interrupt 50" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " ISR49 ,PCIINT1 Software interrupt 49" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " ISR48 ,PCIINT0 Software interrupt 48" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " ISR46 ,UARTINT5 Software interrupt 46" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ISR45 ,UARTINT4 Software interrupt 45" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " ISR44 ,UARTINT3 Software interrupt 44" "No interrupt,Interrupt"
|
|
sif (cpuis("DRA62*"))
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " ISR43 ,EMACSWMISC0 Software interrupt 43" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " ISR42 ,EMACSWTXINT0 Software interrupt 42" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " ISR41 ,EMACSWRXINT0 Software interrupt 41" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " ISR40 ,EMACSWRXTHR0 Software interrupt 40" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " ISR37 ,GFXINT Software interrupt 37" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " ISR36 ,DSSINT Software interrupt 36" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " ISR35 ,PCIeWAKEUP Software interrupt 35" "No interrupt,Interrupt"
|
|
else
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " ISR43 ,3PGSWMISC0 Software interrupt 43" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " ISR42 ,3PGSWTXINT0 Software interrupt 42" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " ISR41 ,3PGSWRXINT0 Software interrupt 41" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " ISR40 ,3PGSWRXTHR0 Software interrupt 40" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " ISR39 ,ISS_IRQ_5 Software interrupt 39" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " ISR38 ,HDMIINT Software interrupt 38" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " ISR37 ,GFXINT Software interrupt 37" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " ISR36 ,DSSINT Software interrupt 36" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " ISR35 ,PCIeWAKEUP Software interrupt 35" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " ISR34 ,USBWAKEUP Software interrupt 34" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " ISR33 ,GPIOINT2B Software interrupt 33" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " ISR32 ,GPIOINT2A Software interrupt 32" "No interrupt,Interrupt"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "INTCPS_PENDING_IRQ1,IRQ Status Register 1"
|
|
bitfld.long 0x00 31. " PENDINGIRQ[63] ,GPIOINT3B IRQ status after masking 63" "Low,High"
|
|
bitfld.long 0x00 30. " PENDINGIRQ[62] ,GPIOINT3A IRQ status after masking 62" "Low,High"
|
|
sif (cpuis("DRA6*"))
|
|
bitfld.long 0x00 29. " PENDINGIRQ[61] ,VCPINT IRQ status after masking 61" "Low,High"
|
|
bitfld.long 0x00 28. " PENDINGIRQ[60] ,MLB_INT IRQ status after masking 60" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGIRQ[59] ,MLB_SYS_INT1 IRQ status after masking 59" "Low,High"
|
|
bitfld.long 0x00 26. " PENDINGIRQ[58] ,MLB_SYS_INT0 IRQ status after masking 58" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 25. " PENDINGIRQ[57] ,DCAN1_PARITY IRQ status after masking 57" "Low,High"
|
|
bitfld.long 0x00 24. " PENDINGIRQ[56] ,DCAN1_INT1 IRQ status after masking 56" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGIRQ[55] ,DCAN1_INT0 IRQ status after masking 55" "Low,High"
|
|
bitfld.long 0x00 22. " PENDINGIRQ[54] ,DCAN0_PARITY IRQ status after masking 54" "Low,High"
|
|
bitfld.long 0x00 21. " PENDINGIRQ[53] ,DCAN0_INT1 status after masking 53" "Low,High"
|
|
bitfld.long 0x00 20. " PENDINGIRQ[52] ,DCAN0_INT0 IRQ status after masking 52" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PENDINGIRQ[51] ,PCIINT3 IRQ status after masking 51" "Low,High"
|
|
bitfld.long 0x00 18. " PENDINGIRQ[50] ,PCIINT2 IRQ status after masking 50" "Low,High"
|
|
bitfld.long 0x00 17. " PENDINGIRQ[49] ,PCIINT1 IRQ status after masking 49" "Low,High"
|
|
bitfld.long 0x00 16. " PENDINGIRQ[48] ,PCIINT0 IRQ status after masking 48" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PENDINGIRQ[46] ,UARTINT5 IRQ status after masking 46" "Low,High"
|
|
bitfld.long 0x00 13. " PENDINGIRQ[45] ,UARTINT4 IRQ status after masking 45" "Low,High"
|
|
bitfld.long 0x00 12. " PENDINGIRQ[44] ,UARTINT3 IRQ status after masking 44" "Low,High"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 11. " PENDINGIRQ[43] ,EMACSWMISC0 IRQ status after masking 43" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PENDINGIRQ[42] ,EMACSWTXINT0 IRQ status after masking 42" "Low,High"
|
|
bitfld.long 0x00 9. " PENDINGIRQ[41] ,EMACSWRXINT0 IRQ status after masking 41" "Low,High"
|
|
bitfld.long 0x00 8. " PENDINGIRQ[40] ,EMACSWRXTHR0 IRQ status after masking 40" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGIRQ[37] ,GFXINT IRQ status after masking 37" "Low,High"
|
|
bitfld.long 0x00 4. " PENDINGIRQ[36] ,DSSINT IRQ status after masking 36" "Low,High"
|
|
bitfld.long 0x00 3. " PENDINGIRQ[35] ,PCIeWAKEUP IRQ status after masking 35" "Low,High"
|
|
else
|
|
bitfld.long 0x00 11. " PENDINGIRQ[43] ,3PGSWMISC0 IRQ status after masking 43" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PENDINGIRQ[42] ,3PGSWTXINT0 IRQ status after masking 42" "Low,High"
|
|
bitfld.long 0x00 9. " PENDINGIRQ[41] ,3PGSWRXINT0 IRQ status after masking 41" "Low,High"
|
|
bitfld.long 0x00 8. " PENDINGIRQ[40] ,3PGSWRXTHR0 IRQ status after masking 40" "Low,High"
|
|
bitfld.long 0x00 7. " PENDINGIRQ[39] ,ISS_IRQ_5 IRQ status after masking 39" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PENDINGIRQ[38] ,HDMIINT IRQ status after masking 38" "Low,High"
|
|
bitfld.long 0x00 5. " PENDINGIRQ[37] ,GFXINT IRQ status after masking 37" "Low,High"
|
|
bitfld.long 0x00 4. " PENDINGIRQ[36] ,DSSINT IRQ status after masking 36" "Low,High"
|
|
bitfld.long 0x00 3. " PENDINGIRQ[35] ,PCIeWAKEUP IRQ status after masking 35" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " PENDINGIRQ[34] ,USBWAKEUP IRQ status after masking 34" "Low,High"
|
|
bitfld.long 0x00 1. " PENDINGIRQ[33] ,GPIOINT2B IRQ status after masking 33" "Low,High"
|
|
bitfld.long 0x00 0. " PENDINGIRQ[32] ,GPIOINT2A IRQ status after masking 32" "Low,High"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "INTCPS_PENDING_FIQ1,FIQ Status Register 1"
|
|
bitfld.long 0x00 31. " PENDINGFIQ[63] ,GPIOINT3B FIQ status after masking 63" "Low,High"
|
|
bitfld.long 0x00 30. " PENDINGFIQ[62] ,GPIOINT3A FIQ status after masking 62" "Low,High"
|
|
sif (cpuis("DRA6*"))
|
|
bitfld.long 0x00 29. " PENDINGFIQ[61] ,VCPINT FIQ status after masking 61" "Low,High"
|
|
bitfld.long 0x00 28. " PENDINGFIQ[60] ,MLB_INT FIQ status after masking 60" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGFIQ[59] ,MLB_SYS_INT1 FIQ status after masking 59" "Low,High"
|
|
bitfld.long 0x00 26. " PENDINGFIQ[58] ,MLB_SYS_INT0 FIQ status after masking 58" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 25. " PENDINGFIQ[57] ,DCAN1_PARITY FIQ status after masking 57" "Low,High"
|
|
bitfld.long 0x00 24. " PENDINGFIQ[56] ,DCAN1_INT1 FIQ status after masking 56" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGFIQ[55] ,DCAN1_INT0 FIQ status after masking 55" "Low,High"
|
|
bitfld.long 0x00 22. " PENDINGFIQ[54] ,DCAN0_PARITY FIQ status after masking 54" "Low,High"
|
|
bitfld.long 0x00 21. " PENDINGFIQ[53] ,DCAN0_INT1 FIQ status after masking 53" "Low,High"
|
|
bitfld.long 0x00 20. " PENDINGFIQ[52] ,DCAN0_INT0 FIQ status after masking 52" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PENDINGFIQ[51] ,PCIINT3 FIQ status after masking 51" "Low,High"
|
|
bitfld.long 0x00 18. " PENDINGFIQ[50] ,PCIINT2 FIQ status after masking 50" "Low,High"
|
|
bitfld.long 0x00 17. " PENDINGFIQ[49] ,PCIINT1 FIQ status after masking 49" "Low,High"
|
|
bitfld.long 0x00 16. " PENDINGFIQ[48] ,PCIINT0 FIQ status after masking 48" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PENDINGFIQ[46] ,UARTINT5 FIQ status after masking 46" "Low,High"
|
|
bitfld.long 0x00 13. " PENDINGFIQ[45] ,UARTINT4 FIQ status after masking 45" "Low,High"
|
|
bitfld.long 0x00 12. " PENDINGFIQ[44] ,UARTINT3 FIQ status after masking 44" "Low,High"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 11. " PENDINGFIQ[43] ,EMACSWMISC0 FIQ status after masking 43" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PENDINGFIQ[42] ,EMACSWTXINT0 FIQ status after masking 42" "Low,High"
|
|
bitfld.long 0x00 9. " PENDINGFIQ[41] ,EMACSWRXINT0 FIQ status after masking 41" "Low,High"
|
|
bitfld.long 0x00 8. " PENDINGFIQ[40] ,EMACSWRXTHR0 FIQ status after masking 40" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGFIQ[37] ,GFXINT FIQ status after masking 37" "Low,High"
|
|
bitfld.long 0x00 4. " PENDINGFIQ[36] ,DSSINT FIQ status after masking 36" "Low,High"
|
|
bitfld.long 0x00 3. " PENDINGFIQ[35] ,PCIeWAKEUP FIQ status after masking 35" "Low,High"
|
|
else
|
|
bitfld.long 0x00 11. " PENDINGFIQ[43] ,3PGSWMISC0 FIQ status after masking 43" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PENDINGFIQ[42] ,3PGSWTXINT0 FIQ status after masking 42" "Low,High"
|
|
bitfld.long 0x00 9. " PENDINGFIQ[41] ,3PGSWRXINT0 FIQ status after masking 41" "Low,High"
|
|
bitfld.long 0x00 8. " PENDINGFIQ[40] ,3PGSWRXTHR0 FIQ status after masking 40" "Low,High"
|
|
bitfld.long 0x00 7. " PENDINGFIQ[39] ,ISS_IRQ_5 FIQ status after masking 39" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PENDINGFIQ[38] ,HDMIINT FIQ status after masking 38" "Low,High"
|
|
bitfld.long 0x00 5. " PENDINGFIQ[37] ,GFXINT FIQ status after masking 37" "Low,High"
|
|
bitfld.long 0x00 4. " PENDINGFIQ[36] ,DSSINT FIQ status after masking 36" "Low,High"
|
|
bitfld.long 0x00 3. " PENDINGFIQ[35] ,PCIeWAKEUP FIQ status after masking 35" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " PENDINGFIQ[34] ,USBWAKEUP FIQ status after masking 34" "Low,High"
|
|
bitfld.long 0x00 1. " PENDINGFIQ[33] ,GPIOINT2B FIQ status after masking 33" "Low,High"
|
|
bitfld.long 0x00 0. " PENDINGFIQ[32] ,GPIOINT2A FIQ status after masking 32" "Low,High"
|
|
tree.end
|
|
tree "Interrupts 64-95"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "INTCPS_ITR2,Raw Interrupt Input Status Register 2"
|
|
bitfld.long 0x00 31. " ITR[95] ,TINT7 Interrupt status before masking 95" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " ITR[94] ,TINT6 Interrupt status before masking 94" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " ITR[93] ,TINT5 Interrupt status before masking 93" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " ITR[92] ,TINT4 Interrupt status before masking 92" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 26. " ITR[90] ,SMRFLX_HDVICP Interrupt status before masking 90" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 25. " ITR[89] ,SMRFLX_DSP Interrupt status before masking 89" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22. " ITR[86] ,MCBSPINT Interrupt status before masking 86" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " ITR[85] ,MCARXINT2 Interrupt status before masking 85" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " ITR[84] ,MCATXINT2 Interrupt status before masking 84" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " ITR[83] ,MCARXINT1 Interrupt status before masking 83" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 18. " ITR[82] ,MCATXINT1 Interrupt status before masking 82" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " ITR[81] ,MCARXINT0 Interrupt status before masking 81" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " ITR[80] ,MCATXINT0 Interrupt status before masking 80" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("AM387*"))
|
|
bitfld.long 0x00 15. " ITR[79] ,PLLINT Interrupt status before masking 79" "No interrupt,Interrupt"
|
|
elif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 15. " ITR[79] ,PLLRECAL Interrupt status before masking 79" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 14. " ITR[78] ,IDEINTR Interrupt status before masking 78" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 13. " ITR[77] ,MB1INT0 Interrupt status before masking 77" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 13. " ITR[77] ,MBINT Interrupt status before masking 77" "No interrupt,Interrupt"
|
|
endif
|
|
bitfld.long 0x00 12. " ITR[76] ,RTCALARMINT Interrupt status before masking 76" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " ITR[75] ,RTCINT Interrupt status before masking 75" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " ITR[74] ,UARTINT2 Interrupt status before masking 74" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ITR[73] ,UARTINT1 Interrupt status before masking 73" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " ITR[72] ,UARTINT0 Interrupt status before masking 72" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " ITR[71] ,I2CINT1 Interrupt status before masking 71" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " ITR[70] ,I2CINT0 Interrupt status before masking 70" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ITR[69] ,TINT3 Interrupt status before masking 69" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " ITR[68] ,TINT2 Interrupt status before masking 68" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " ITR[67] ,TINT1 Interrupt status before masking 67" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " ITR[65] ,SPIINT0 Interrupt status before masking 65" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ITR[64] ,SDINT0 Interrupt status before masking 64" "No interrupt,Interrupt"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "INTCPS_MIR2_set/clr,Interrupt Mask Register 2"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x04 31. " MR95 ,TINT7 Interrupt mask 95" "Not masked,Masked"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x04 30. " MR94 ,TINT6 Interrupt mask 94" "Not masked,Masked"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x04 29. " MR93 ,TINT5 Interrupt mask 93" "Not masked,Masked"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " MR92 ,TINT4 Interrupt mask 92" "Not masked,Masked"
|
|
textline " "
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
setclrfld.long 0x00 26. 0x08 26. 0x04 26. " MR90 ,SMRFLX_HDVICP Interrupt mask 89" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " MR89 ,SMRFLX_DSP Interrupt mask 90" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 22. 0x08 22. 0x04 22. " MR86 ,MCBSPINT Interrupt mask 86" "Not masked,Masked"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x04 21. " MR85 ,MCARXINT2 Interrupt mask 85" "Not masked,Masked"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " MR84 ,MCATXINT2 Interrupt mask 84" "Not masked,Masked"
|
|
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " MR83 ,MCARXINT1 Interrupt mask 83" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " MR82 ,MCATXINT1 Interrupt mask 82" "Not masked,Masked"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " MR81 ,MCARXINT0 Interrupt mask 81" "Not masked,Masked"
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " MR80 ,MCATXINT0 Interrupt mask 80" "Not masked,Masked"
|
|
textline " "
|
|
sif (cpuis("AM387*"))
|
|
setclrfld.long 0x00 15. 0x08 15. 0x04 15. " MR79 ,PLLINT Interrupt mask 79" "Not masked,Masked"
|
|
elif (cpuis("DRA62*"))
|
|
setclrfld.long 0x00 15. 0x08 15. 0x04 15. " MR79 ,PLLRECAL Interrupt mask 79" "Not masked,Masked"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " MR78 ,IDEINTR Interrupt mask 78" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("DRA62*"))
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " MR77 ,MB1INT0 Interrupt mask 77" "Not masked,Masked"
|
|
else
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " MR77 ,MBINT Interrupt mask 77" "Not masked,Masked"
|
|
endif
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " MR76 ,RTCALARMINT Interrupt mask 76" "Not masked,Masked"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " MR75 ,RTCINT Interrupt mask 75" "Not masked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " MR74 ,UARTINT2 Interrupt mask 74" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " MR73 ,UARTINT1 Interrupt mask 73" "Not masked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " MR72 ,UARTINT0 Interrupt mask 72" "Not masked,Masked"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " MR71 ,I2CINT1 Interrupt mask 71" "Not masked,Masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " MR70 ,I2CINT0 Interrupt mask 70" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " MR69 ,TINT3 Interrupt mask 69" "Not masked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " MR68 ,TINT2 Interrupt mask 68" "Not masked,Masked"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " MR67 ,TINT1 Interrupt mask 67" "Not masked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " MR65 ,SPIINT0 Interrupt mask 65" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " MR64 ,SDINT0 Interrupt mask 64" "Not masked,Masked"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "INTCPS_ISR2_set/clr,Software Interrupt Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ISR95 ,TINT7 Software interrupt 95" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " ISR94 ,TINT6 Software interrupt 94" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " ISR93 ,TINT5 Software interrupt 93" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISR92 ,TINT4 Software interrupt 92" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " ISR90 ,SMRFLX_HDVICP Software interrupt 90" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " ISR89 ,SMRFLX_DSP Software interrupt 89" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " ISR86 ,MCBSPINT Software interrupt 86" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " ISR85 ,MCARXINT2 Software interrupt 85" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " ISR84 ,MCATXINT2 Software interrupt 84" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " ISR83 ,MCARXINT1 Software interrupt 83" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " ISR82 ,MCATXINT1 Software interrupt 82" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " ISR81 ,MCARXINT0 Software interrupt 81" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " ISR80 ,MCATXINT0 Software interrupt 80" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("AM387*"))
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " ISR79 ,PLLINT Software interrupt 79" "No interrupt,Interrupt"
|
|
elif (cpuis("DRA62*"))
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " ISR79 ,PLLRECAL Software interrupt 79" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " ISR78 ,IDEINTR Software interrupt 78" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("DRA62*"))
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ISR77 ,MB1INT0 Software interrupt 77" "No interrupt,Interrupt"
|
|
else
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ISR77 ,MBINT Software interrupt 77" "No interrupt,Interrupt"
|
|
endif
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " ISR76 ,RTCALARMINT Software interrupt 76" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " ISR75 ,RTCINT Software interrupt 75" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " ISR74 ,UARTINT2 Software interrupt 74" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " ISR73 ,UARTINT1 Software interrupt 73" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " ISR72 ,UARTINT0 Software interrupt 72" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " ISR71 ,I2CINT1 Software interrupt 71" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " ISR70 ,I2CINT0 Software interrupt 70" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " ISR69 ,TINT3 Software interrupt 69" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " ISR68 ,TINT2 Software interrupt 68" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " ISR67 ,TINT1 Software interrupt 67" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " ISR65 ,SPIINT0 Software interrupt 65" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " ISR64 ,SDINT0 Software interrupt 64" "No interrupt,Interrupt"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "INTCPS_PENDING_IRQ2,IRQ Status Register 2"
|
|
bitfld.long 0x00 31. " PENDINGIRQ[95] ,TINT7 IRQ status after masking 95" "Low,High"
|
|
bitfld.long 0x00 30. " PENDINGIRQ[94] ,TINT6 IRQ status after masking 94" "Low,High"
|
|
bitfld.long 0x00 29. " PENDINGIRQ[93] ,TINT5 IRQ status after masking 93" "Low,High"
|
|
bitfld.long 0x00 28. " PENDINGIRQ[92] ,TINT4 IRQ status after masking 92" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 26. " PENDINGIRQ[90] ,SMRFLX_HDVICP IRQ status after masking 90" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 25. " PENDINGIRQ[89] ,SMRFLX_DSP IRQ status after masking 89" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22. " PENDINGIRQ[86] ,MCBSPINT IRQ status after masking 86" "Low,High"
|
|
bitfld.long 0x00 21. " PENDINGIRQ[85] ,MCARXINT2 IRQ status after masking 85" "Low,High"
|
|
bitfld.long 0x00 20. " PENDINGIRQ[84] ,MCATXINT2 IRQ status after masking 84" "Low,High"
|
|
bitfld.long 0x00 19. " PENDINGIRQ[83] ,MCARXINT1 IRQ status after masking 83" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PENDINGIRQ[82] ,MCATXINT1 IRQ status after masking 82" "Low,High"
|
|
bitfld.long 0x00 17. " PENDINGIRQ[81] ,MCARXINT0 IRQ status after masking 81" "Low,High"
|
|
bitfld.long 0x00 16. " PENDINGIRQ[80] ,MCATXINT0 IRQ status after masking 80" "Low,High"
|
|
textline " "
|
|
sif (cpuis("AM387*"))
|
|
bitfld.long 0x00 15. " PENDINGIRQ[79] ,PLLINT IRQ status after masking 79" "Low,High"
|
|
elif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 15. " PENDINGIRQ[79] ,PLLRECAL IRQ status after masking 79" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 14. " PENDINGIRQ[78] ,IDEINTR IRQ status after masking 78" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 13. " PENDINGIRQ[77] ,MB1INT0 IRQ status after masking 77" "Low,High"
|
|
else
|
|
bitfld.long 0x00 13. " PENDINGIRQ[77] ,MBINT IRQ status after masking 77" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 12. " PENDINGIRQ[76] ,RTCALARMINT IRQ status after masking 76" "Low,High"
|
|
bitfld.long 0x00 11. " PENDINGIRQ[75] ,RTCINT IRQ status after masking 75" "Low,High"
|
|
bitfld.long 0x00 10. " PENDINGIRQ[74] ,UARTINT2 IRQ status after masking 74" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PENDINGIRQ[73] ,UARTINT1 IRQ status after masking 73" "Low,High"
|
|
bitfld.long 0x00 8. " PENDINGIRQ[72] ,UARTINT0 IRQ status after masking 72" "Low,High"
|
|
bitfld.long 0x00 7. " PENDINGIRQ[71] ,I2CINT1 IRQ status after masking 71" "Low,High"
|
|
bitfld.long 0x00 6. " PENDINGIRQ[70] ,I2CINT0 IRQ status after masking 70" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGIRQ[69] ,TINT3 IRQ status after masking 69" "Low,High"
|
|
bitfld.long 0x00 4. " PENDINGIRQ[68] ,TINT2 IRQ status after masking 68" "Low,High"
|
|
bitfld.long 0x00 3. " PENDINGIRQ[67] ,TINT1 IRQ status after masking 67" "Low,High"
|
|
bitfld.long 0x00 1. " PENDINGIRQ[65] ,SPIINT0 IRQ status after masking 65" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PENDINGIRQ[64] ,SDINT0 IRQ status after masking 64" "Low,High"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "INTCPS_PENDING_FIQ2,FIQ Status Register 2"
|
|
bitfld.long 0x00 31. " PENDINGFIQ[95] ,TINT7 FIQ status after masking 95" "Low,High"
|
|
bitfld.long 0x00 30. " PENDINGFIQ[94] ,TINT6 FIQ status after masking 94" "Low,High"
|
|
bitfld.long 0x00 29. " PENDINGFIQ[93] ,TINT5 FIQ status after masking 93" "Low,High"
|
|
bitfld.long 0x00 28. " PENDINGFIQ[92] ,TINT4 FIQ status after masking 92" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 26. " PENDINGFIQ[90] ,SMRFLX_HDVICP FIQ status after masking 90" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 25. " PENDINGFIQ[89] ,SMRFLX_DSP FIQ status after masking 89" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22. " PENDINGFIQ[86] ,MCBSPINT FIQ status after masking 86" "Low,High"
|
|
bitfld.long 0x00 21. " PENDINGFIQ[85] ,MCARXINT2 FIQ status after masking 85" "Low,High"
|
|
bitfld.long 0x00 20. " PENDINGFIQ[84] ,MCATXINT2 FIQ status after masking 84" "Low,High"
|
|
bitfld.long 0x00 19. " PENDINGFIQ[83] ,MCARXINT1 FIQ status after masking 83" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PENDINGFIQ[82] ,MCATXINT1 FIQ status after masking 82" "Low,High"
|
|
bitfld.long 0x00 17. " PENDINGFIQ[81] ,MCARXINT0 FIQ status after masking 81" "Low,High"
|
|
bitfld.long 0x00 16. " PENDINGFIQ[80] ,MCATXINT0 FIQ status after masking 80" "Low,High"
|
|
textline " "
|
|
sif (cpuis("AM387*"))
|
|
bitfld.long 0x00 15. " PENDINGFIQ[79] ,PLLINT FIQ status after masking 79" "Low,High"
|
|
elif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 15. " PENDINGFIQ[79] ,PLLRECAL FIQ status after masking 79" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 14. " PENDINGFIQ[78] ,IDEINTR FIQ status after masking 78" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 13. " PENDINGFIQ[77] ,MB1INT0 FIQ status after masking 77" "Low,High"
|
|
else
|
|
bitfld.long 0x00 13. " PENDINGFIQ[77] ,MBINT FIQ status after masking 77" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 12. " PENDINGFIQ[76] ,RTCALARMINT FIQ status after masking 76" "Low,High"
|
|
bitfld.long 0x00 11. " PENDINGFIQ[75] ,RTCINT FIQ status after masking 75" "Low,High"
|
|
bitfld.long 0x00 10. " PENDINGFIQ[74] ,UARTINT2 FIQ status after masking 74" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PENDINGFIQ[73] ,UARTINT1 FIQ status after masking 73" "Low,High"
|
|
bitfld.long 0x00 8. " PENDINGFIQ[72] ,UARTINT0 FIQ status after masking 72" "Low,High"
|
|
bitfld.long 0x00 7. " PENDINGFIQ[71] ,I2CINT1 FIQ status after masking 71" "Low,High"
|
|
bitfld.long 0x00 6. " PENDINGFIQ[70] ,I2CINT0 FIQ status after masking 70" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGFIQ[69] ,TINT3 FIQ status after masking 69" "Low,High"
|
|
bitfld.long 0x00 4. " PENDINGFIQ[68] ,TINT2 FIQ status after masking 68" "Low,High"
|
|
bitfld.long 0x00 3. " PENDINGFIQ[67] ,TINT1 FIQ status after masking 67" "Low,High"
|
|
bitfld.long 0x00 1. " PENDINGFIQ[65] ,SPIINT0 FIQ status after masking 65" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PENDINGFIQ[64] ,SDINT0 FIQ status after masking 64" "Low,High"
|
|
tree.end
|
|
tree "Interrupts 96-127"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "INTCPS_ITR3,Raw Interrupt Input Status Register 3"
|
|
bitfld.long 0x00 31. " ITR[127] ,SPIINT3 Interrupt status before masking 127" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " ITR[126] ,SPIINT2 Interrupt status before masking 126" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " ITR[125] ,SPIINT1 Interrupt status before masking 125" "No interrupt,Interrupt"
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x00 28. " ITR[124] ,DMMINT Interrupt status before masking 124" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 27. " ITR[123] ,MCMMUINT Interrupt status before masking 123" "No interrupt,Interrupt"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 26. " ITR[122] ,SYSMMUINT Interrupt status before masking 122" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " ITR[121] ,SMRFLX1 Interrupt status before masking 121" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ITR[120] ,SMRFLX3 Interrupt status before masking 120" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 26. " ITR[122] ,MMUINT Interrupt status before masking 122" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " ITR[121] ,SMRFLX_CORE Interrupt status before masking 121" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " ITR[120] ,SMRFLX_ARM Interrupt status before masking 120" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 22. " ITR[118] ,GPM3SWINT Interrupt status before masking 118" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " ITR[116] ,GPM3INT Interrupt status before masking 116" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " ITR[115] ,TCERRINT3 Interrupt status before masking 115" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " ITR[114] ,TCERRINT2 Interrupt status before masking 114" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " ITR[113] ,TCERRINT1 Interrupt status before masking 113" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " ITR[112] ,TCERRINT0 Interrupt status before masking 112" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ITR[111] ,MCARXINT5 Interrupt status before masking 111" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " ITR[110] ,MCATXINT5 Interrupt status before masking 110" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " ITR[109] ,MCARXINT4 Interrupt status before masking 109" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " ITR[108] ,MCATXINT4 Interrupt status before masking 108" "No interrupt,Interrupt"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
textline " "
|
|
bitfld.long 0x00 11. " ITR[107] ,IVA0MBOXINT Interrupt status before masking 107" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITR[106] ,MCARXINT3 Interrupt status before masking 106" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " ITR[105] ,MCATXINT3 Interrupt status before masking 105" "No interrupt,Interrupt"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
textline " "
|
|
bitfld.long 0x00 8. " ITR[104] ,HDVICPCONT2SYNC Interrupt status before masking 104" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " ITR[103] ,HDVICPCONT1SYNC Interrupt status before masking 103" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 5. " ITR[101] ,DDRERR0 Interrupt status before masking 101" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 6. " ITR[102] ,DDRERR1 Interrupt status before masking 102" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ITR[101] ,DDRERR0 Interrupt status before masking 101" "No interrupt,Interrupt"
|
|
endif
|
|
bitfld.long 0x00 4. " ITR[100] ,GPMCINT Interrupt status before masking 100" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " ITR[99] ,GPIOINT1B Interrupt status before masking 99" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ITR[98] ,GPIOINT1A Interrupt status before masking 98" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " ITR[97] ,GPIOINT0B Interrupt status before masking 97" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " ITR[96] ,GPIOINT0A Interrupt status before masking 96" "No interrupt,Interrupt"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "INTCPS_MIR3_set/clr,Interrupt Mask Register 3"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x04 31. " MR127 ,SPIINT3 Interrupt mask 127" "Not masked,Masked"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x04 30. " MR126 ,SPIINT2 Interrupt mask 126" "Not masked,Masked"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x04 29. " MR125 ,SPIINT1 Interrupt mask 125" "Not masked,Masked"
|
|
sif (!cpuis("DRA62*"))
|
|
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " MR124 ,DMMINT Interrupt mask 124" "Not masked,Masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " MR123 ,MCMMUINT Interrupt mask 123" "Not masked,Masked"
|
|
sif (cpuis("DRA62*"))
|
|
setclrfld.long 0x00 26. 0x08 26. 0x04 26. " MR122 ,SYSMMUINT Interrupt mask 122" "Not masked,Masked"
|
|
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " MR121 ,SMRFLX1 Interrupt mask 121" "Not masked,Masked"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x04 24. " MR120 ,SMRFLX3 Interrupt mask 120" "Not masked,Masked"
|
|
else
|
|
setclrfld.long 0x00 26. 0x08 26. 0x04 26. " MR122 ,MMUINT Interrupt mask 122" "Not masked,Masked"
|
|
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " MR121 ,SMRFLX_CORE Interrupt mask 121" "Not masked,Masked"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x04 24. " MR120 ,SMRFLX_ARM Interrupt mask 120" "Not masked,Masked"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
setclrfld.long 0x00 22. 0x08 22. 0x04 22. " MR118 ,GPM3SWINT Interrupt mask 118" "Not masked,Masked"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " MR116 ,GPM3INT Interrupt mask 116" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " MR115 ,TCERRINT3 Interrupt mask 115" "Not masked,Masked"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " MR114 ,TCERRINT2 Interrupt mask 114" "Not masked,Masked"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " MR113 ,TCERRINT1 Interrupt mask 113" "Not masked,Masked"
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " MR112 ,TCERRINT0 Interrupt mask 112" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x08 15. 0x04 15. " MR111 ,MCARXINT5 Interrupt mask 111" "Not masked,Masked"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " MR110 ,MCATXINT5 Interrupt mask 110" "Not masked,Masked"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " MR109 ,MCARXINT4 Interrupt mask 109" "Not masked,Masked"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " MR108 ,MCATXINT4 Interrupt mask 108" "Not masked,Masked"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " MR107 ,IVA0MBOXINT Interrupt mask 107" "Not masked,Masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " MR106 ,MCARXINT3 Interrupt mask 106" "Not masked,Masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " MR105 ,MCATXINT3 Interrupt mask 105" "Not masked,Masked"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " MR104 ,HDVICPCONT2SYNC Interrupt mask 104" "Not masked,Masked"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " MR103 ,HDVICPCONT1SYNC Interrupt mask 103" "Not masked,Masked"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " MR101 ,DDRERR0 Interrupt mask 101" "Not masked,Masked"
|
|
else
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " MR102 ,DDRERR1 Interrupt mask 102" "Not masked,Masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " MR101 ,DDRERR0 Interrupt mask 101" "Not masked,Masked"
|
|
endif
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " MR100 ,GPMCINT Interrupt mask 100" "Not masked,Masked"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " MR99 ,GPIOINT1B Interrupt mask 99" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " MR98 ,GPIOINT1A Interrupt mask 98" "Not masked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " MR97 ,GPIOINT0B Interrupt mask 97" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " MR96 ,GPIOINT0A Interrupt mask 96" "Not masked,Masked"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "INTCPS_ISR3_set/clr,Software Interrupt Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ISR127 ,SPIINT3 Software interrupt 127" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " ISR126 ,SPIINT2 Software interrupt 126" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " ISR125 ,SPIINT1 Software interrupt 125" "No interrupt,Interrupt"
|
|
sif (!cpuis("DRA62*"))
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISR124 ,DMMINT Software interrupt 124" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " ISR123 ,MCMMUINT Software interrupt 123" "No interrupt,Interrupt"
|
|
sif (cpuis("DRA62*"))
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " ISR122 ,SYSMMUINT Software interrupt 122" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " ISR121 ,SMRFLX1 Software interrupt 121" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " ISR120 ,SMRFLX3 Software interrupt 120" "No interrupt,Interrupt"
|
|
else
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " ISR122 ,MMUINT Software interrupt 122" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " ISR121 ,SMRFLX_CORE Software interrupt 121" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " ISR120 ,SMRFLX_ARM Software interrupt 120" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " ISR118 ,GPM3SWINT Software interrupt 118" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " ISR116 ,GPM3INT Software interrupt 116" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " ISR115 ,TCERRINT3 Software interrupt 115" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " ISR114 ,TCERRINT2 Software interrupt 114" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " ISR113 ,TCERRINT1 Software interrupt 113" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " ISR112 ,TCERRINT0 Software interrupt 112" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " ISR111 ,MCARXINT5 Software interrupt 111" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " ISR110 ,MCATXINT5 Software interrupt 110" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ISR109 ,MCARXINT4 Software interrupt 109" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " ISR108 ,MCATXINT4 Software interrupt 108" "No interrupt,Interrupt"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " MR107 ,IVA0MBOXINT Software interrupt 107" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " ISR106 ,MCARXINT3 Software interrupt 106" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " ISR105 ,MCATXINT3 Software interrupt 105" "No interrupt,Interrupt"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " ISR104 ,HDVICPCONT2SYNC Software interrupt 104" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " ISR103 ,HDVICPCONT1SYNC Software interrupt 103" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " ISR101 ,DDRERR0 Software interrupt 101" "No interrupt,Interrupt"
|
|
else
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " ISR102 ,DDRERR1 Software interrupt 102" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " ISR101 ,DDRERR0 Software interrupt 101" "No interrupt,Interrupt"
|
|
endif
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " ISR100 ,GPMCINT Software interrupt 100" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " ISR99 ,GPIOINT1B Software interrupt 99" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " ISR98 ,GPIOINT1A Software interrupt 98" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " ISR97 ,GPIOINT0B Software interrupt 97" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " ISR96 ,GPIOINT0A Software interrupt 96" "No interrupt,Interrupt"
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "INTCPS_PENDING_IRQ3,IRQ Status Register 3"
|
|
bitfld.long 0x00 31. " PENDINGIRQ[127] ,SPIINT3 IRQ status after masking 127" "Low,High"
|
|
bitfld.long 0x00 30. " PENDINGIRQ[126] ,SPIINT2 IRQ status after masking 126" "Low,High"
|
|
bitfld.long 0x00 29. " PENDINGIRQ[125] ,SPIINT1 IRQ status after masking 125" "Low,High"
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x00 28. " PENDINGIRQ[124] ,DMMINT IRQ status after masking 124" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGIRQ[123] ,MCMMUINT IRQ status after masking 123" "Low,High"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 26. " PENDINGIRQ[122] ,SYSMMUINT IRQ status after masking 122" "Low,High"
|
|
bitfld.long 0x00 25. " PENDINGIRQ[121] ,SMRFLX1 IRQ status after masking 121" "Low,High"
|
|
bitfld.long 0x00 24. " PENDINGIRQ[120] ,SMRFLX3 IRQ status after masking 120" "Low,High"
|
|
else
|
|
bitfld.long 0x00 26. " PENDINGIRQ[122] ,MMUINT IRQ status after masking 122" "Low,High"
|
|
bitfld.long 0x00 25. " PENDINGIRQ[121] ,SMRFLX_CORE IRQ status after masking 121" "Low,High"
|
|
bitfld.long 0x00 24. " PENDINGIRQ[120] ,SMRFLX_ARM IRQ status after masking 120" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 22. " PENDINGIRQ[118] ,GPM3SWINT IRQ status after masking 118" "Low,High"
|
|
bitfld.long 0x00 20. " PENDINGIRQ[116] ,GPM3INT IRQ status after masking 116" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " PENDINGIRQ[115] ,TCERRINT3 IRQ status after masking 115" "Low,High"
|
|
bitfld.long 0x00 18. " PENDINGIRQ[114] ,TCERRINT2 IRQ status after masking 114" "Low,High"
|
|
bitfld.long 0x00 17. " PENDINGIRQ[113] ,TCERRINT1 IRQ status after masking 113" "Low,High"
|
|
bitfld.long 0x00 16. " PENDINGIRQ[112] ,TCERRINT0 IRQ status after masking 112" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGIRQ[111] ,MCARXINT5 IRQ status after masking 111" "Low,High"
|
|
bitfld.long 0x00 14. " PENDINGIRQ[110] ,MCATXINT5 IRQ status after masking 110" "Low,High"
|
|
bitfld.long 0x00 13. " PENDINGIRQ[109] ,MCARXINT4 IRQ status after masking 109" "Low,High"
|
|
bitfld.long 0x00 12. " PENDINGIRQ[108] ,MCATXINT4 IRQ status after masking 108" "Low,High"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGIRQ[107] ,IVA0MBOXINT IRQ status after masking 107" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " PENDINGIRQ[106] ,MCARXINT3 IRQ status after masking 106" "Low,High"
|
|
bitfld.long 0x00 9. " PENDINGIRQ[105] ,MCATXINT3 IRQ status after masking 105" "Low,High"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
textline " "
|
|
bitfld.long 0x00 8. " PENDINGIRQ[104] ,HDVICPCONT2SYNC IRQ status after masking 104" "Low,High"
|
|
bitfld.long 0x00 7. " PENDINGIRQ[103] ,HDVICPCONT1SYNC IRQ status after masking 103" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 5. " PENDINGIRQ[101] ,DDRERR0 IRQ status after masking 101" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " PENDINGIRQ[102] ,DDRERR1 IRQ status after masking 102" "Low,High"
|
|
bitfld.long 0x00 5. " PENDINGIRQ[101] ,DDRERR0 IRQ status after masking 101" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 4. " PENDINGIRQ[100] ,GPMCINT IRQ status after masking 100" "Low,High"
|
|
bitfld.long 0x00 3. " PENDINGIRQ[99] ,GPIOINT1B IRQ status after masking 99" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PENDINGIRQ[98] ,GPIOINT1A IRQ status after masking 98" "Low,High"
|
|
bitfld.long 0x00 1. " PENDINGIRQ[97] ,GPIOINT0B IRQ status after masking 97" "Low,High"
|
|
bitfld.long 0x00 0. " PENDINGIRQ[96] ,GPIOINT0A IRQ status after masking 96" "Low,High"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "INTCPS_PENDING_FIQ3,FIQ Status Register 3"
|
|
bitfld.long 0x00 31. " PENDINGFIQ[127] ,SPIINT3 FIQ status after masking 127" "Low,High"
|
|
bitfld.long 0x00 30. " PENDINGFIQ[126] ,SPIINT2 FIQ status after masking 126" "Low,High"
|
|
bitfld.long 0x00 29. " PENDINGFIQ[125] ,SPIINT1 FIQ status after masking 125" "Low,High"
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x00 28. " PENDINGFIQ[124] ,DMMINT FIQ status after masking 124" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGFIQ[123] ,MCMMUINT FIQ status after masking 123" "Low,High"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 26. " PENDINGFIQ[122] ,SYSMMUINT FIQ status after masking 122" "Low,High"
|
|
bitfld.long 0x00 25. " PENDINGFIQ[121] ,SMRFLX1 FIQ status after masking 121" "Low,High"
|
|
bitfld.long 0x00 24. " PENDINGFIQ[120] ,SMRFLX3 FIQ status after masking 120" "Low,High"
|
|
else
|
|
bitfld.long 0x00 26. " PENDINGFIQ[122] ,MMUINT FIQ status after masking 122" "Low,High"
|
|
bitfld.long 0x00 25. " PENDINGFIQ[121] ,SMRFLX_CORE FIQ status after masking 121" "Low,High"
|
|
bitfld.long 0x00 24. " PENDINGFIQ[120] ,SMRFLX_ARM FIQ status after masking 120" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
bitfld.long 0x00 22. " PENDINGFIQ[118] ,GPM3SWINT FIQ status after masking 118" "Low,High"
|
|
bitfld.long 0x00 20. " PENDINGFIQ[116] ,GPM3INT FIQ status after masking 116" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " PENDINGFIQ[115] ,TCERRINT3 FIQ status after masking 115" "Low,High"
|
|
bitfld.long 0x00 18. " PENDINGFIQ[114] ,TCERRINT2 FIQ status after masking 114" "Low,High"
|
|
bitfld.long 0x00 17. " PENDINGFIQ[113] ,TCERRINT1 FIQ status after masking 113" "Low,High"
|
|
bitfld.long 0x00 16. " PENDINGFIQ[112] ,TCERRINT0 FIQ status after masking 112" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGFIQ[111] ,MCARXINT5 FIQ status after masking 111" "Low,High"
|
|
bitfld.long 0x00 14. " PENDINGFIQ[110] ,MCATXINT5 FIQ status after masking 110" "Low,High"
|
|
bitfld.long 0x00 13. " PENDINGFIQ[109] ,MCARXINT4 FIQ status after masking 109" "Low,High"
|
|
bitfld.long 0x00 12. " PENDINGFIQ[108] ,MCATXINT4 FIQ status after masking 108" "Low,High"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGFIQ[107] ,IVA0MBOXINT FIQ status after masking 107" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " PENDINGFIQ[106] ,MCARXINT3 FIQ status after masking 106" "Low,High"
|
|
bitfld.long 0x00 9. " PENDINGFIQ[105] ,MCATXINT3 FIQ status after masking 105" "Low,High"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&(!cpuis("DRA62*")))
|
|
textline " "
|
|
bitfld.long 0x00 8. " PENDINGFIQ[104] ,HDVICPCONT2SYNC FIQ status after masking 104" "Low,High"
|
|
bitfld.long 0x00 7. " PENDINGFIQ[103] ,HDVICPCONT1SYNC FIQ status after masking 103" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 5. " PENDINGFIQ[101] ,DDRERR0 FIQ status after masking 101" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " PENDINGFIQ[102] ,DDRERR1 FIQ status after masking 102" "Low,High"
|
|
bitfld.long 0x00 5. " PENDINGFIQ[101] ,DDRERR0 FIQ status after masking 101" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 4. " PENDINGFIQ[100] ,GPMCINT FIQ status after masking 100" "Low,High"
|
|
bitfld.long 0x00 3. " PENDINGFIQ[99] ,GPIOINT1B FIQ status after masking 99" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PENDINGFIQ[98] ,GPIOINT1A FIQ status after masking 98" "Low,High"
|
|
bitfld.long 0x00 1. " PENDINGFIQ[97] ,GPIOINT0B FIQ status after masking 97" "Low,High"
|
|
bitfld.long 0x00 0. " PENDINGFIQ[96] ,GPIOINT0A FIQ status after masking 96" "Low,High"
|
|
tree.end
|
|
tree "Interrupts Priorities / FIQ/IRQ steering"
|
|
width 15.
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "INTCPS_ILR0,Interrupt 0 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "INTCPS_ILR1,Interrupt 1 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "INTCPS_ILR2,Interrupt 2 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "INTCPS_ILR3,Interrupt 3 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "INTCPS_ILR4,Interrupt 4 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "INTCPS_ILR5,Interrupt 5 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "INTCPS_ILR6,Interrupt 6 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x11C++0x3
|
|
line.long 0x00 "INTCPS_ILR7,Interrupt 7 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "INTCPS_ILR8,Interrupt 8 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x124++0x3
|
|
line.long 0x00 "INTCPS_ILR9,Interrupt 9 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "INTCPS_ILR10,Interrupt 10 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x12C++0x3
|
|
line.long 0x00 "INTCPS_ILR11,Interrupt 11 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x130++0x3
|
|
line.long 0x00 "INTCPS_ILR12,Interrupt 12 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "INTCPS_ILR13,Interrupt 13 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x138++0x3
|
|
line.long 0x00 "INTCPS_ILR14,Interrupt 14 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x13C++0x3
|
|
line.long 0x00 "INTCPS_ILR15,Interrupt 15 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "INTCPS_ILR16,Interrupt 16 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x144++0x3
|
|
line.long 0x00 "INTCPS_ILR17,Interrupt 17 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x148++0x3
|
|
line.long 0x00 "INTCPS_ILR18,Interrupt 18 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x14C++0x3
|
|
line.long 0x00 "INTCPS_ILR19,Interrupt 19 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x150++0x3
|
|
line.long 0x00 "INTCPS_ILR20,Interrupt 20 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x154++0x3
|
|
line.long 0x00 "INTCPS_ILR21,Interrupt 21 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x158++0x3
|
|
line.long 0x00 "INTCPS_ILR22,Interrupt 22 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x15C++0x3
|
|
line.long 0x00 "INTCPS_ILR23,Interrupt 23 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x160++0x3
|
|
line.long 0x00 "INTCPS_ILR24,Interrupt 24 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x164++0x3
|
|
line.long 0x00 "INTCPS_ILR25,Interrupt 25 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x168++0x3
|
|
line.long 0x00 "INTCPS_ILR26,Interrupt 26 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x16C++0x3
|
|
line.long 0x00 "INTCPS_ILR27,Interrupt 27 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x170++0x3
|
|
line.long 0x00 "INTCPS_ILR28,Interrupt 28 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x174++0x3
|
|
line.long 0x00 "INTCPS_ILR29,Interrupt 29 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x178++0x3
|
|
line.long 0x00 "INTCPS_ILR30,Interrupt 30 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x17C++0x3
|
|
line.long 0x00 "INTCPS_ILR31,Interrupt 31 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "INTCPS_ILR32,Interrupt 32 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "INTCPS_ILR33,Interrupt 33 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x188++0x3
|
|
line.long 0x00 "INTCPS_ILR34,Interrupt 34 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x18C++0x3
|
|
line.long 0x00 "INTCPS_ILR35,Interrupt 35 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x190++0x3
|
|
line.long 0x00 "INTCPS_ILR36,Interrupt 36 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x194++0x3
|
|
line.long 0x00 "INTCPS_ILR37,Interrupt 37 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x198++0x3
|
|
line.long 0x00 "INTCPS_ILR38,Interrupt 38 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x19C++0x3
|
|
line.long 0x00 "INTCPS_ILR39,Interrupt 39 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x00 "INTCPS_ILR40,Interrupt 40 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1A4++0x3
|
|
line.long 0x00 "INTCPS_ILR41,Interrupt 41 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1A8++0x3
|
|
line.long 0x00 "INTCPS_ILR42,Interrupt 42 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1AC++0x3
|
|
line.long 0x00 "INTCPS_ILR43,Interrupt 43 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1B0++0x3
|
|
line.long 0x00 "INTCPS_ILR44,Interrupt 44 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1B4++0x3
|
|
line.long 0x00 "INTCPS_ILR45,Interrupt 45 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1B8++0x3
|
|
line.long 0x00 "INTCPS_ILR46,Interrupt 46 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1BC++0x3
|
|
line.long 0x00 "INTCPS_ILR47,Interrupt 47 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x00 "INTCPS_ILR48,Interrupt 48 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1C4++0x3
|
|
line.long 0x00 "INTCPS_ILR49,Interrupt 49 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1C8++0x3
|
|
line.long 0x00 "INTCPS_ILR50,Interrupt 50 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1CC++0x3
|
|
line.long 0x00 "INTCPS_ILR51,Interrupt 51 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1D0++0x3
|
|
line.long 0x00 "INTCPS_ILR52,Interrupt 52 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1D4++0x3
|
|
line.long 0x00 "INTCPS_ILR53,Interrupt 53 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1D8++0x3
|
|
line.long 0x00 "INTCPS_ILR54,Interrupt 54 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1DC++0x3
|
|
line.long 0x00 "INTCPS_ILR55,Interrupt 55 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1E0++0x3
|
|
line.long 0x00 "INTCPS_ILR56,Interrupt 56 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1E4++0x3
|
|
line.long 0x00 "INTCPS_ILR57,Interrupt 57 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1E8++0x3
|
|
line.long 0x00 "INTCPS_ILR58,Interrupt 58 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1EC++0x3
|
|
line.long 0x00 "INTCPS_ILR59,Interrupt 59 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1F0++0x3
|
|
line.long 0x00 "INTCPS_ILR60,Interrupt 60 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1F4++0x3
|
|
line.long 0x00 "INTCPS_ILR61,Interrupt 61 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1F8++0x3
|
|
line.long 0x00 "INTCPS_ILR62,Interrupt 62 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x1FC++0x3
|
|
line.long 0x00 "INTCPS_ILR63,Interrupt 63 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "INTCPS_ILR64,Interrupt 64 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x204++0x3
|
|
line.long 0x00 "INTCPS_ILR65,Interrupt 65 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x208++0x3
|
|
line.long 0x00 "INTCPS_ILR66,Interrupt 66 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x20C++0x3
|
|
line.long 0x00 "INTCPS_ILR67,Interrupt 67 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x210++0x3
|
|
line.long 0x00 "INTCPS_ILR68,Interrupt 68 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x214++0x3
|
|
line.long 0x00 "INTCPS_ILR69,Interrupt 69 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x218++0x3
|
|
line.long 0x00 "INTCPS_ILR70,Interrupt 70 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x21C++0x3
|
|
line.long 0x00 "INTCPS_ILR71,Interrupt 71 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x220++0x3
|
|
line.long 0x00 "INTCPS_ILR72,Interrupt 72 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x224++0x3
|
|
line.long 0x00 "INTCPS_ILR73,Interrupt 73 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x228++0x3
|
|
line.long 0x00 "INTCPS_ILR74,Interrupt 74 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x22C++0x3
|
|
line.long 0x00 "INTCPS_ILR75,Interrupt 75 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x230++0x3
|
|
line.long 0x00 "INTCPS_ILR76,Interrupt 76 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x234++0x3
|
|
line.long 0x00 "INTCPS_ILR77,Interrupt 77 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x238++0x3
|
|
line.long 0x00 "INTCPS_ILR78,Interrupt 78 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x23C++0x3
|
|
line.long 0x00 "INTCPS_ILR79,Interrupt 79 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x240++0x3
|
|
line.long 0x00 "INTCPS_ILR80,Interrupt 80 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x244++0x3
|
|
line.long 0x00 "INTCPS_ILR81,Interrupt 81 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x248++0x3
|
|
line.long 0x00 "INTCPS_ILR82,Interrupt 82 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x24C++0x3
|
|
line.long 0x00 "INTCPS_ILR83,Interrupt 83 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x250++0x3
|
|
line.long 0x00 "INTCPS_ILR84,Interrupt 84 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x254++0x3
|
|
line.long 0x00 "INTCPS_ILR85,Interrupt 85 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x258++0x3
|
|
line.long 0x00 "INTCPS_ILR86,Interrupt 86 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x25C++0x3
|
|
line.long 0x00 "INTCPS_ILR87,Interrupt 87 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x260++0x3
|
|
line.long 0x00 "INTCPS_ILR88,Interrupt 88 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x264++0x3
|
|
line.long 0x00 "INTCPS_ILR89,Interrupt 89 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x268++0x3
|
|
line.long 0x00 "INTCPS_ILR90,Interrupt 90 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x26C++0x3
|
|
line.long 0x00 "INTCPS_ILR91,Interrupt 91 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x270++0x3
|
|
line.long 0x00 "INTCPS_ILR92,Interrupt 92 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x274++0x3
|
|
line.long 0x00 "INTCPS_ILR93,Interrupt 93 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x278++0x3
|
|
line.long 0x00 "INTCPS_ILR94,Interrupt 94 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x27C++0x3
|
|
line.long 0x00 "INTCPS_ILR95,Interrupt 95 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x280++0x3
|
|
line.long 0x00 "INTCPS_ILR96,Interrupt 96 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x284++0x3
|
|
line.long 0x00 "INTCPS_ILR97,Interrupt 97 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x288++0x3
|
|
line.long 0x00 "INTCPS_ILR98,Interrupt 98 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x28C++0x3
|
|
line.long 0x00 "INTCPS_ILR99,Interrupt 99 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x290++0x3
|
|
line.long 0x00 "INTCPS_ILR100,Interrupt 100 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x294++0x3
|
|
line.long 0x00 "INTCPS_ILR101,Interrupt 101 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x298++0x3
|
|
line.long 0x00 "INTCPS_ILR102,Interrupt 102 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x29C++0x3
|
|
line.long 0x00 "INTCPS_ILR103,Interrupt 103 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x00 "INTCPS_ILR104,Interrupt 104 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2A4++0x3
|
|
line.long 0x00 "INTCPS_ILR105,Interrupt 105 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2A8++0x3
|
|
line.long 0x00 "INTCPS_ILR106,Interrupt 106 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2AC++0x3
|
|
line.long 0x00 "INTCPS_ILR107,Interrupt 107 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2B0++0x3
|
|
line.long 0x00 "INTCPS_ILR108,Interrupt 108 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2B4++0x3
|
|
line.long 0x00 "INTCPS_ILR109,Interrupt 109 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2B8++0x3
|
|
line.long 0x00 "INTCPS_ILR110,Interrupt 110 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2BC++0x3
|
|
line.long 0x00 "INTCPS_ILR111,Interrupt 111 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2C0++0x3
|
|
line.long 0x00 "INTCPS_ILR112,Interrupt 112 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2C4++0x3
|
|
line.long 0x00 "INTCPS_ILR113,Interrupt 113 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2C8++0x3
|
|
line.long 0x00 "INTCPS_ILR114,Interrupt 114 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2CC++0x3
|
|
line.long 0x00 "INTCPS_ILR115,Interrupt 115 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2D0++0x3
|
|
line.long 0x00 "INTCPS_ILR116,Interrupt 116 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2D4++0x3
|
|
line.long 0x00 "INTCPS_ILR117,Interrupt 117 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2D8++0x3
|
|
line.long 0x00 "INTCPS_ILR118,Interrupt 118 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2DC++0x3
|
|
line.long 0x00 "INTCPS_ILR119,Interrupt 119 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2E0++0x3
|
|
line.long 0x00 "INTCPS_ILR120,Interrupt 120 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x00 "INTCPS_ILR121,Interrupt 121 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2E8++0x3
|
|
line.long 0x00 "INTCPS_ILR122,Interrupt 122 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2EC++0x3
|
|
line.long 0x00 "INTCPS_ILR123,Interrupt 123 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2F0++0x3
|
|
line.long 0x00 "INTCPS_ILR124,Interrupt 124 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2F4++0x3
|
|
line.long 0x00 "INTCPS_ILR125,Interrupt 125 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2F8++0x3
|
|
line.long 0x00 "INTCPS_ILR126,Interrupt 126 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x2FC++0x3
|
|
line.long 0x00 "INTCPS_ILR127,Interrupt 127 priority for the interrupts and the FIQ/IRQ steering"
|
|
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.open "DCAN (Dual Controller Area Network)"
|
|
tree "DCAN0"
|
|
base ad:0x481CC000
|
|
width 23.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DCAN_CTL,CAN Control Register"
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x00 25. " WUBA ,Automatic wake up on bus activity" "No wake up,Wake up"
|
|
bitfld.long 0x00 24. " PDR ,Request for local low power-down mode" "Not requested,Requested"
|
|
else
|
|
bitfld.long 0x00 26. " WUBA ,Automatic wake up on bus activity" "No wake up,Wake up"
|
|
bitfld.long 0x00 24. " PDR ,Request for local low power-down mode" "Not requested,Requested"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " DE3 ,DMA enable for IF3" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DE2 ,DMA enable for IF2" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DE1 ,DMA enable for IF1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INITDBG ,Internal init state while debug access" "Not entered,Entered"
|
|
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE0 ,DCAN0INT Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "DCAN_ES/PARITYERR_EOI,Error and Status/Parity Error EOI Register"
|
|
in
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "DCAN_ERRC,Error Counter Register"
|
|
bitfld.long 0x00 15. " RP ,Receive Error Passive" "No error,Error"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC6-0 ,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC7-0 ,Transmit Error Counter"
|
|
if (((data.long(ad:0x481CC000))&0x41)==0x41)
|
|
group.long 0x0c++0x03
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
line.long 0x00 "DCAN_BTR,Bit Timing Register"
|
|
else
|
|
line.long 0x00 "DCAN_BTBRP,Bit Timing_BRP Extension Register"
|
|
endif
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The time segment after the sample point" "0,1,2,3,4,5,6,7"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x0c++0x03
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
line.long 0x00 "DCAN_BTR,Bit Timing Register"
|
|
else
|
|
line.long 0x00 "DCAN_BTBRP,Bit Timing_BRP Extension Register"
|
|
endif
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The time segment after the sample point" "0,1,2,3,4,5,6,7"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "Reerved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "DCAN_INTR,Interrupt Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT1ID7-0 ,Interrupt 1 Identifier"
|
|
hexmask.long.word 0x00 0.--15. 1. " INT0ID15-0 ,Interrupt Identifier"
|
|
if (((data.long(ad:0x481CC000))&0x80)==0x80)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DCAN_TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Direct access"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Monitored,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "DCAN_TEST,Test Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Direct access"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Monitored,Dominant,Recessive"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Test"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,External"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Monitored,0,1"
|
|
endif
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DCAN_PERR,Parity Error Code Register"
|
|
bitfld.long 0x00 8.--10. " WN ,Word Number" "Reserved,1,2,3,4,5,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "DCAN_ABOTR,Auto Bus On Time Register"
|
|
rgroup.long 0x84--0xD3
|
|
line.long 0x00 "DCAN_TXRQX,Transmission Request X Register"
|
|
bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request X 8" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request X 7" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request X 6" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request X 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request X 4" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request X 3" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request X 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request X 1" "0,1,2,3"
|
|
line.long 0x04 "DCAN_TXRQ12,Transmission Request 1_2 Register"
|
|
bitfld.long 0x04 31. " TXRQST32 ,Transmission Request Bit 32" "Not requested,Requested"
|
|
bitfld.long 0x04 30. " TXRQST31 ,Transmission Request Bit 31" "Not requested,Requested"
|
|
bitfld.long 0x04 29. " TXRQST30 ,Transmission Request Bit 30" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 28. " TXRQST29 ,Transmission Request Bit 29" "Not requested,Requested"
|
|
bitfld.long 0x04 27. " TXRQST28 ,Transmission Request Bit 28" "Not requested,Requested"
|
|
bitfld.long 0x04 26. " TXRQST27 ,Transmission Request Bit 27" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 25. " TXRQST26 ,Transmission Request Bit 26" "Not requested,Requested"
|
|
bitfld.long 0x04 24. " TXRQST25 ,Transmission Request Bit 25" "Not requested,Requested"
|
|
bitfld.long 0x04 23. " TXRQST24 ,Transmission Request Bit 24" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 22. " TXRQST23 ,Transmission Request Bit 23" "Not requested,Requested"
|
|
bitfld.long 0x04 21. " TXRQST22 ,Transmission Request Bit 22" "Not requested,Requested"
|
|
bitfld.long 0x04 20. " TXRQST21 ,Transmission Request Bit 21" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 19. " TXRQST20 ,Transmission Request Bit 20" "Not requested,Requested"
|
|
bitfld.long 0x04 18. " TXRQST19 ,Transmission Request Bit 19" "Not requested,Requested"
|
|
bitfld.long 0x04 17. " TXRQST18 ,Transmission Request Bit 18" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 16. " TXRQST17 ,Transmission Request Bit 17" "Not requested,Requested"
|
|
bitfld.long 0x04 15. " TXRQST16 ,Transmission Request Bit 16" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " TXRQST15 ,Transmission Request Bit 15" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TXRQST14 ,Transmission Request Bit 14" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " TXRQST13 ,Transmission Request Bit 13" "Not requested,Requested"
|
|
bitfld.long 0x04 11. " TXRQST12 ,Transmission Request Bit 12" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TXRQST11 ,Transmission Request Bit 11" "Not requested,Requested"
|
|
bitfld.long 0x04 9. " TXRQST10 ,Transmission Request Bit 10" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " TXRQST9 ,Transmission Request Bit 9" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 7. " TXRQST8 ,Transmission Request Bit 8" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " TXRQST7 ,Transmission Request Bit 7" "Not requested,Requested"
|
|
bitfld.long 0x04 5. " TXRQST6 ,Transmission Request Bit 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 4. " TXRQST5 ,Transmission Request Bit 5" "Not requested,Requested"
|
|
bitfld.long 0x04 3. " TXRQST4 ,Transmission Request Bit 4" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " TXRQST3 ,Transmission Request Bit 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TXRQST2 ,Transmission Request Bit 2" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " TXRQST1 ,Transmission Request Bit 1" "Not requested,Requested"
|
|
line.long 0x08 "DCAN_TXRQ34,Transmission Request 3_4 Register"
|
|
bitfld.long 0x08 31. " TXRQST64 ,Transmission Request Bit 64" "Not requested,Requested"
|
|
bitfld.long 0x08 30. " TXRQST63 ,Transmission Request Bit 63" "Not requested,Requested"
|
|
bitfld.long 0x08 29. " TXRQST62 ,Transmission Request Bit 62" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 28. " TXRQST61 ,Transmission Request Bit 61" "Not requested,Requested"
|
|
bitfld.long 0x08 27. " TXRQST60 ,Transmission Request Bit 60" "Not requested,Requested"
|
|
bitfld.long 0x08 26. " TXRQST59 ,Transmission Request Bit 59" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 25. " TXRQST58 ,Transmission Request Bit 58" "Not requested,Requested"
|
|
bitfld.long 0x08 24. " TXRQST57 ,Transmission Request Bit 57" "Not requested,Requested"
|
|
bitfld.long 0x08 23. " TXRQST56 ,Transmission Request Bit 56" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 22. " TXRQST55 ,Transmission Request Bit 55" "Not requested,Requested"
|
|
bitfld.long 0x08 21. " TXRQST54 ,Transmission Request Bit 54" "Not requested,Requested"
|
|
bitfld.long 0x08 20. " TXRQST53 ,Transmission Request Bit 53" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 19. " TXRQST52 ,Transmission Request Bit 52" "Not requested,Requested"
|
|
bitfld.long 0x08 18. " TXRQST51 ,Transmission Request Bit 51" "Not requested,Requested"
|
|
bitfld.long 0x08 17. " TXRQST50 ,Transmission Request Bit 50" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 16. " TXRQST49 ,Transmission Request Bit 49" "Not requested,Requested"
|
|
bitfld.long 0x08 15. " TXRQST48 ,Transmission Request Bit 48" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " TXRQST47 ,Transmission Request Bit 47" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 13. " TXRQST46 ,Transmission Request Bit 46" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " TXRQST45 ,Transmission Request Bit 45" "Not requested,Requested"
|
|
bitfld.long 0x08 11. " TXRQST44 ,Transmission Request Bit 44" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 10. " TXRQST43 ,Transmission Request Bit 43" "Not requested,Requested"
|
|
bitfld.long 0x08 9. " TXRQST42 ,Transmission Request Bit 42" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " TXRQST41 ,Transmission Request Bit 41" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 7. " TXRQST40 ,Transmission Request Bit 40" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " TXRQST39 ,Transmission Request Bit 39" "Not requested,Requested"
|
|
bitfld.long 0x08 5. " TXRQST38 ,Transmission Request Bit 38" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TXRQST37 ,Transmission Request Bit 37" "Not requested,Requested"
|
|
bitfld.long 0x08 3. " TXRQST36 ,Transmission Request Bit 36" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " TXRQST35 ,Transmission Request Bit 35" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXRQST34 ,Transmission Request Bit 34" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " TXRQST33 ,Transmission Request Bit 33" "Not requested,Requested"
|
|
line.long 0x0c "DCAN_TXRQ56,Transmission Request 5_6 Register"
|
|
bitfld.long 0x0c 31. " TXRQST96 ,Transmission Request Bit 96" "Not requested,Requested"
|
|
bitfld.long 0x0c 30. " TXRQST95 ,Transmission Request Bit 95" "Not requested,Requested"
|
|
bitfld.long 0x0c 29. " TXRQST94 ,Transmission Request Bit 94" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " TXRQST93 ,Transmission Request Bit 93" "Not requested,Requested"
|
|
bitfld.long 0x0c 27. " TXRQST92 ,Transmission Request Bit 92" "Not requested,Requested"
|
|
bitfld.long 0x0c 26. " TXRQST91 ,Transmission Request Bit 91" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " TXRQST90 ,Transmission Request Bit 90" "Not requested,Requested"
|
|
bitfld.long 0x0c 24. " TXRQST89 ,Transmission Request Bit 89" "Not requested,Requested"
|
|
bitfld.long 0x0c 23. " TXRQST88 ,Transmission Request Bit 88" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " TXRQST87 ,Transmission Request Bit 87" "Not requested,Requested"
|
|
bitfld.long 0x0c 21. " TXRQST86 ,Transmission Request Bit 86" "Not requested,Requested"
|
|
bitfld.long 0x0c 20. " TXRQST85 ,Transmission Request Bit 85" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " TXRQST84 ,Transmission Request Bit 84" "Not requested,Requested"
|
|
bitfld.long 0x0c 18. " TXRQST83 ,Transmission Request Bit 83" "Not requested,Requested"
|
|
bitfld.long 0x0c 17. " TXRQST82 ,Transmission Request Bit 82" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " TXRQST81 ,Transmission Request Bit 81" "Not requested,Requested"
|
|
bitfld.long 0x0c 15. " TXRQST80 ,Transmission Request Bit 80" "Not requested,Requested"
|
|
bitfld.long 0x0c 14. " TXRQST79 ,Transmission Request Bit 79" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " TXRQST78 ,Transmission Request Bit 78" "Not requested,Requested"
|
|
bitfld.long 0x0c 12. " TXRQST77 ,Transmission Request Bit 77" "Not requested,Requested"
|
|
bitfld.long 0x0c 11. " TXRQST76 ,Transmission Request Bit 76" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " TXRQST75 ,Transmission Request Bit 75" "Not requested,Requested"
|
|
bitfld.long 0x0c 9. " TXRQST74 ,Transmission Request Bit 74" "Not requested,Requested"
|
|
bitfld.long 0x0c 8. " TXRQST73 ,Transmission Request Bit 73" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " TXRQST72 ,Transmission Request Bit 72" "Not requested,Requested"
|
|
bitfld.long 0x0c 6. " TXRQST71 ,Transmission Request Bit 71" "Not requested,Requested"
|
|
bitfld.long 0x0c 5. " TXRQST70 ,Transmission Request Bit 70" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " TXRQST69 ,Transmission Request Bit 69" "Not requested,Requested"
|
|
bitfld.long 0x0c 3. " TXRQST68 ,Transmission Request Bit 68" "Not requested,Requested"
|
|
bitfld.long 0x0c 2. " TXRQST67 ,Transmission Request Bit 67" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " TXRQST66 ,Transmission Request Bit 66" "Not requested,Requested"
|
|
bitfld.long 0x0c 0. " TXRQST65 ,Transmission Request Bit 65" "Not requested,Requested"
|
|
line.long 0x10 "DCAN_TXRQ78,Transmission Request 7_8 Register"
|
|
bitfld.long 0x10 31. " TXRQST128 ,Transmission Request Bit 128" "Not requested,Requested"
|
|
bitfld.long 0x10 30. " TXRQST127 ,Transmission Request Bit 127" "Not requested,Requested"
|
|
bitfld.long 0x10 29. " TXRQST126 ,Transmission Request Bit 126" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 28. " TXRQST125 ,Transmission Request Bit 125" "Not requested,Requested"
|
|
bitfld.long 0x10 27. " TXRQST124 ,Transmission Request Bit 124" "Not requested,Requested"
|
|
bitfld.long 0x10 26. " TXRQST123 ,Transmission Request Bit 123" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 25. " TXRQST122 ,Transmission Request Bit 122" "Not requested,Requested"
|
|
bitfld.long 0x10 24. " TXRQST121 ,Transmission Request Bit 121" "Not requested,Requested"
|
|
bitfld.long 0x10 23. " TXRQST120 ,Transmission Request Bit 120" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 22. " TXRQST119 ,Transmission Request Bit 119" "Not requested,Requested"
|
|
bitfld.long 0x10 21. " TXRQST118 ,Transmission Request Bit 118" "Not requested,Requested"
|
|
bitfld.long 0x10 20. " TXRQST117 ,Transmission Request Bit 117" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 19. " TXRQST116 ,Transmission Request Bit 116" "Not requested,Requested"
|
|
bitfld.long 0x10 18. " TXRQST115 ,Transmission Request Bit 115" "Not requested,Requested"
|
|
bitfld.long 0x10 17. " TXRQST114 ,Transmission Request Bit 114" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 16. " TXRQST113 ,Transmission Request Bit 113" "Not requested,Requested"
|
|
bitfld.long 0x10 15. " TXRQST112 ,Transmission Request Bit 112" "Not requested,Requested"
|
|
bitfld.long 0x10 14. " TXRQST111 ,Transmission Request Bit 111" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 13. " TXRQST110 ,Transmission Request Bit 110" "Not requested,Requested"
|
|
bitfld.long 0x10 12. " TXRQST109 ,Transmission Request Bit 109" "Not requested,Requested"
|
|
bitfld.long 0x10 11. " TXRQST108 ,Transmission Request Bit 108" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 10. " TXRQST107 ,Transmission Request Bit 107" "Not requested,Requested"
|
|
bitfld.long 0x10 9. " TXRQST106 ,Transmission Request Bit 106" "Not requested,Requested"
|
|
bitfld.long 0x10 8. " TXRQST105 ,Transmission Request Bit 105" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TXRQST104 ,Transmission Request Bit 104" "Not requested,Requested"
|
|
bitfld.long 0x10 6. " TXRQST103 ,Transmission Request Bit 103" "Not requested,Requested"
|
|
bitfld.long 0x10 5. " TXRQST102 ,Transmission Request Bit 102" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 4. " TXRQST101 ,Transmission Request Bit 101" "Not requested,Requested"
|
|
bitfld.long 0x10 3. " TXRQST100 ,Transmission Request Bit 100" "Not requested,Requested"
|
|
bitfld.long 0x10 2. " TXRQST99 ,Transmission Request Bit 99" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TXRQST98 ,Transmission Request Bit 98" "Not requested,Requested"
|
|
bitfld.long 0x10 0. " TXRQST97 ,Transmission Request Bit 97" "Not requested,Requested"
|
|
line.long 0x14 "DCAN_NWDAT_X,New Data X Register"
|
|
bitfld.long 0x14 14.--15. " NEWDATREG8 ,New Data X 8" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. " NEWDATREG7 ,New Data X 7" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. " NEWDATREG6 ,New Data X 6" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x14 8.--9. " NEWDATREG5 ,New Data X 5" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " NEWDATREG4 ,New Data X 4" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. " NEWDATREG3 ,New Data X 3" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x14 2.--3. " NEWDATREG2 ,New Data X 2" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. " NEWDATREG1 ,New Data X 1" "0,1,2,3"
|
|
line.long 0x18 "DCAN_NWDAT12,New Data 1_2 Register"
|
|
bitfld.long 0x18 31. " NEWDAT32 ,New Data Bit 32" "Not written,Written"
|
|
bitfld.long 0x18 30. " NEWDAT31 ,New Data Bit 31" "Not written,Written"
|
|
bitfld.long 0x18 29. " NEWDAT30 ,New Data Bit 30" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 28. " NEWDAT29 ,New Data Bit 29" "Not written,Written"
|
|
bitfld.long 0x18 27. " NEWDAT28 ,New Data Bit 28" "Not written,Written"
|
|
bitfld.long 0x18 26. " NEWDAT27 ,New Data Bit 27" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 25. " NEWDAT26 ,New Data Bit 26" "Not written,Written"
|
|
bitfld.long 0x18 24. " NEWDAT25 ,New Data Bit 25" "Not written,Written"
|
|
bitfld.long 0x18 23. " NEWDAT24 ,New Data Bit 24" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 22. " NEWDAT23 ,New Data Bit 23" "Not written,Written"
|
|
bitfld.long 0x18 21. " NEWDAT22 ,New Data Bit 22" "Not written,Written"
|
|
bitfld.long 0x18 20. " NEWDAT21 ,New Data Bit 21" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 19. " NEWDAT20 ,New Data Bit 20" "Not written,Written"
|
|
bitfld.long 0x18 18. " NEWDAT19 ,New Data Bit 19" "Not written,Written"
|
|
bitfld.long 0x18 17. " NEWDAT18 ,New Data Bit 18" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 16. " NEWDAT17 ,New Data Bit 17" "Not written,Written"
|
|
bitfld.long 0x18 15. " NEWDAT16 ,New Data Bit 16" "Not written,Written"
|
|
bitfld.long 0x18 14. " NEWDAT15 ,New Data Bit 15" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 13. " NEWDAT14 ,New Data Bit 14" "Not written,Written"
|
|
bitfld.long 0x18 12. " NEWDAT13 ,New Data Bit 13" "Not written,Written"
|
|
bitfld.long 0x18 11. " NewDat12 ,New Data Bit 12" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 10. " NEWDAT11 ,New Data Bit 11" "Not written,Written"
|
|
bitfld.long 0x18 9. " NEWDAT10 ,New Data Bit 10" "Not written,Written"
|
|
bitfld.long 0x18 8. " NEWDAT9 ,New Data Bit 9" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 7. " NEWDAT8 ,New Data Bit 8" "Not written,Written"
|
|
bitfld.long 0x18 6. " NEWDAT7 ,New Data Bit 7" "Not written,Written"
|
|
bitfld.long 0x18 5. " NEWDAT6 ,New Data Bit 6" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 4. " NEWDAT5 ,New Data Bit 5" "Not written,Written"
|
|
bitfld.long 0x18 3. " NEWDAT4 ,New Data Bit 4" "Not written,Written"
|
|
bitfld.long 0x18 2. " NEWDAT3 ,New Data Bit 3" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 1. " NEWDAT2 ,New Data Bit 2" "Not written,Written"
|
|
bitfld.long 0x18 0. " NEWDAT1 ,New Data Bit 1" "Not written,Written"
|
|
line.long 0x1c "DCAN_NWDAT34,New Data 3_4 Register"
|
|
bitfld.long 0x1c 31. " NEWDAT64 ,New Data Bit 64" "Not written,Written"
|
|
bitfld.long 0x1c 30. " NEWDAT63 ,New Data Bit 63" "Not written,Written"
|
|
bitfld.long 0x1c 29. " NEWDAT62 ,New Data Bit 62" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 28. " NEWDAT61 ,New Data Bit 61" "Not written,Written"
|
|
bitfld.long 0x1c 27. " NEWDAT60 ,New Data Bit 60" "Not written,Written"
|
|
bitfld.long 0x1c 26. " NEWDAT59 ,New Data Bit 59" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 25. " NEWDAT58 ,New Data Bit 58" "Not written,Written"
|
|
bitfld.long 0x1c 24. " NEWDAT57 ,New Data Bit 57" "Not written,Written"
|
|
bitfld.long 0x1c 23. " NEWDAT56 ,New Data Bit 56" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 22. " NEWDAT55 ,New Data Bit 55" "Not written,Written"
|
|
bitfld.long 0x1c 21. " NEWDAT54 ,New Data Bit 54" "Not written,Written"
|
|
bitfld.long 0x1c 20. " NEWDAT53 ,New Data Bit 53" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 19. " NEWDAT52 ,New Data Bit 52" "Not written,Written"
|
|
bitfld.long 0x1c 18. " NEWDAT51 ,New Data Bit 51" "Not written,Written"
|
|
bitfld.long 0x1c 17. " NEWDAT50 ,New Data Bit 50" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 16. " NEWDAT49 ,New Data Bit 49" "Not written,Written"
|
|
bitfld.long 0x1c 15. " NEWDAT48 ,New Data Bit 48" "Not written,Written"
|
|
bitfld.long 0x1c 14. " NEWDAT47 ,New Data Bit 47" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 13. " NEWDAT46 ,New Data Bit 46" "Not written,Written"
|
|
bitfld.long 0x1c 12. " NEWDAT45 ,New Data Bit 45" "Not written,Written"
|
|
bitfld.long 0x1c 11. " NEWDAT44 ,New Data Bit 44" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 10. " NEWDAT43 ,New Data Bit 43" "Not written,Written"
|
|
bitfld.long 0x1c 9. " NEWDAT42 ,New Data Bit 42" "Not written,Written"
|
|
bitfld.long 0x1c 8. " NEWDAT41 ,New Data Bit 41" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 7. " NEWDAT40 ,New Data Bit 40" "Not written,Written"
|
|
bitfld.long 0x1c 6. " NEWDAT39 ,New Data Bit 39" "Not written,Written"
|
|
bitfld.long 0x1c 5. " NEWDAT38 ,New Data Bit 38" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 4. " NEWDAT37 ,New Data Bit 37" "Not written,Written"
|
|
bitfld.long 0x1c 3. " NEWDAT36 ,New Data Bit 36" "Not written,Written"
|
|
bitfld.long 0x1c 2. " NEWDAT35 ,New Data Bit 35" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 1. " NEWDAT34 ,New Data Bit 34" "Not written,Written"
|
|
bitfld.long 0x1c 0. " NEWDAT33 ,New Data Bit 33" "Not written,Written"
|
|
line.long 0x20 "DCAN_NWDAT56,New Data 5_6 Register"
|
|
bitfld.long 0x20 31. " NEWDAT96 ,New Data Bit 96" "Not written,Written"
|
|
bitfld.long 0x20 30. " NEWDAT95 ,New Data Bit 95" "Not written,Written"
|
|
bitfld.long 0x20 29. " NEWDAT94 ,New Data Bit 94" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 28. " NEWDAT93 ,New Data Bit 93" "Not written,Written"
|
|
bitfld.long 0x20 27. " NEWDAT92 ,New Data Bit 92" "Not written,Written"
|
|
bitfld.long 0x20 26. " NEWDAT91 ,New Data Bit 91" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 25. " NEWDAT90 ,New Data Bit 90" "Not written,Written"
|
|
bitfld.long 0x20 24. " NEWDAT89 ,New Data Bit 89" "Not written,Written"
|
|
bitfld.long 0x20 23. " NEWDAT88 ,New Data Bit 88" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 22. " NEWDAT87 ,New Data Bit 87" "Not written,Written"
|
|
bitfld.long 0x20 21. " NEWDAT86 ,New Data Bit 86" "Not written,Written"
|
|
bitfld.long 0x20 20. " NEWDAT85 ,New Data Bit 85" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 19. " NEWDAT84 ,New Data Bit 84" "Not written,Written"
|
|
bitfld.long 0x20 18. " NEWDAT83 ,New Data Bit 83" "Not written,Written"
|
|
bitfld.long 0x20 17. " NEWDAT82 ,New Data Bit 82" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 16. " NEWDAT81 ,New Data Bit 81" "Not written,Written"
|
|
bitfld.long 0x20 15. " NEWDAT80 ,New Data Bit 80" "Not written,Written"
|
|
bitfld.long 0x20 14. " NEWDAT79 ,New Data Bit 79" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 13. " NEWDAT78 ,New Data Bit 78" "Not written,Written"
|
|
bitfld.long 0x20 12. " NEWDAT77 ,New Data Bit 77" "Not written,Written"
|
|
bitfld.long 0x20 11. " NEWDAT76 ,New Data Bit 76" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 10. " NEWDAT75 ,New Data Bit 75" "Not written,Written"
|
|
bitfld.long 0x20 9. " NEWDAT74 ,New Data Bit 74" "Not written,Written"
|
|
bitfld.long 0x20 8. " NEWDAT73 ,New Data Bit 73" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 7. " NEWDAT72 ,New Data Bit 72" "Not written,Written"
|
|
bitfld.long 0x20 6. " NEWDAT71 ,New Data Bit 71" "Not written,Written"
|
|
bitfld.long 0x20 5. " NEWDAT70 ,New Data Bit 70" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 4. " NEWDAT69 ,New Data Bit 69" "Not written,Written"
|
|
bitfld.long 0x20 3. " NEWDAT68 ,New Data Bit 68" "Not written,Written"
|
|
bitfld.long 0x20 2. " NEWDAT67 ,New Data Bit 67" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 1. " NEWDAT66 ,New Data Bit 66" "Not written,Written"
|
|
bitfld.long 0x20 0. " NEWDAT65 ,New Data Bit 65" "Not written,Written"
|
|
line.long 0x24 "DCAN_NWDAT78,New Data 7_8 Register"
|
|
bitfld.long 0x24 31. " NEWDAT128 ,New Data Bit 128" "Not written,Written"
|
|
bitfld.long 0x24 30. " NEWDAT127 ,New Data Bit 127" "Not written,Written"
|
|
bitfld.long 0x24 29. " NEWDAT126 ,New Data Bit 126" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 28. " NEWDAT125 ,New Data Bit 125" "Not written,Written"
|
|
bitfld.long 0x24 27. " NEWDAT124 ,New Data Bit 124" "Not written,Written"
|
|
bitfld.long 0x24 26. " NEWDAT123 ,New Data Bit 123" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 25. " NEWDAT122 ,New Data Bit 122" "Not written,Written"
|
|
bitfld.long 0x24 24. " NEWDAT121 ,New Data Bit 121" "Not written,Written"
|
|
bitfld.long 0x24 23. " NEWDAT120 ,New Data Bit 120" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 22. " NEWDAT119 ,New Data Bit 119" "Not written,Written"
|
|
bitfld.long 0x24 21. " NEWDAT118 ,New Data Bit 118" "Not written,Written"
|
|
bitfld.long 0x24 20. " NEWDAT117 ,New Data Bit 117" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 19. " NEWDAT116 ,New Data Bit 116" "Not written,Written"
|
|
bitfld.long 0x24 18. " NEWDAT115 ,New Data Bit 115" "Not written,Written"
|
|
bitfld.long 0x24 17. " NEWDAT114 ,New Data Bit 114" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 16. " NEWDAT113 ,New Data Bit 113" "Not written,Written"
|
|
bitfld.long 0x24 15. " NEWDAT112 ,New Data Bit 112" "Not written,Written"
|
|
bitfld.long 0x24 14. " NEWDAT111 ,New Data Bit 111" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 13. " NEWDAT110 ,New Data Bit 110" "Not written,Written"
|
|
bitfld.long 0x24 12. " NEWDAT109 ,New Data Bit 109" "Not written,Written"
|
|
bitfld.long 0x24 11. " NEWDAT108 ,New Data Bit 108" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 10. " NEWDAT107 ,New Data Bit 107" "Not written,Written"
|
|
bitfld.long 0x24 9. " NEWDAT106 ,New Data Bit 106" "Not written,Written"
|
|
bitfld.long 0x24 8. " NEWDAT105 ,New Data Bit 105" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 7. " NEWDAT104 ,New Data Bit 104" "Not written,Written"
|
|
bitfld.long 0x24 6. " NEWDAT103 ,New Data Bit 103" "Not written,Written"
|
|
bitfld.long 0x24 5. " NEWDAT102 ,New Data Bit 102" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 4. " NEWDAT101 ,New Data Bit 101" "Not written,Written"
|
|
bitfld.long 0x24 3. " NEWDAT100 ,New Data Bit 100" "Not written,Written"
|
|
bitfld.long 0x24 2. " NEWDAT99 ,New Data Bit 99" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 1. " NEWDAT98 ,New Data Bit 98" "Not written,Written"
|
|
bitfld.long 0x24 0. " NEWDAT97 ,New Data Bit 97" "Not written,Written"
|
|
line.long 0x28 "DCAN_INTPND_X,Interrupt Pending X Register"
|
|
bitfld.long 0x28 14.--15. " INTPNDREG8 ,Interrupt Pending X Register 8" "0,1,2,3"
|
|
bitfld.long 0x28 12.--13. " INTPNDREG7 ,Interrupt Pending X Register 7" "0,1,2,3"
|
|
bitfld.long 0x28 10.--11. " INTPNDREG6 ,Interrupt Pending X Register 6" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x28 8.--9. " INTPNDREG5 ,Interrupt Pending X Register 5" "0,1,2,3"
|
|
bitfld.long 0x28 6.--7. " INTPNDREG4 ,Interrupt Pending X Register 4" "0,1,2,3"
|
|
bitfld.long 0x28 4.--5. " INTPNDREG3 ,Interrupt Pending X Register 3" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x28 2.--3. " INTPNDREG2 ,Interrupt Pending X Register 2" "0,1,2,3"
|
|
bitfld.long 0x28 0.--1. " INTPNDREG1 ,Interrupt Pending X Register 1" "0,1,2,3"
|
|
line.long 0x2C "DCAN_INTPND12,Interrupt Pending 1_2 Register"
|
|
bitfld.long 0x2c 31. " INTPND32 ,Interrupt Pending Bit 32" "Not pending,Pending"
|
|
bitfld.long 0x2c 30. " INTPND31 ,Interrupt Pending Bit 31" "Not pending,Pending"
|
|
bitfld.long 0x2c 29. " INTPND30 ,Interrupt Pending Bit 30" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 28. " INTPND29 ,Interrupt Pending Bit 29" "Not pending,Pending"
|
|
bitfld.long 0x2c 27. " INTPND28 ,Interrupt Pending Bit 28" "Not pending,Pending"
|
|
bitfld.long 0x2c 26. " INTPND27 ,Interrupt Pending Bit 27" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 25. " INTPND26 ,Interrupt Pending Bit 26" "Not pending,Pending"
|
|
bitfld.long 0x2c 24. " INTPND25 ,Interrupt Pending Bit 25" "Not pending,Pending"
|
|
bitfld.long 0x2c 23. " INTPND24 ,Interrupt Pending Bit 24" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 22. " INTPND23 ,Interrupt Pending Bit 23" "Not pending,Pending"
|
|
bitfld.long 0x2c 21. " INTPND22 ,Interrupt Pending Bit 22" "Not pending,Pending"
|
|
bitfld.long 0x2c 20. " INTPND21 ,Interrupt Pending Bit 21" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 19. " INTPND20 ,Interrupt Pending Bit 20" "Not pending,Pending"
|
|
bitfld.long 0x2c 18. " INTPND19 ,Interrupt Pending Bit 19" "Not pending,Pending"
|
|
bitfld.long 0x2c 17. " INTPND18 ,Interrupt Pending Bit 18" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 16. " INTPND17 ,Interrupt Pending Bit 17" "Not pending,Pending"
|
|
bitfld.long 0x2c 15. " INTPND16 ,Interrupt Pending Bit 16" "Not pending,Pending"
|
|
bitfld.long 0x2c 14. " INTPND15 ,Interrupt Pending Bit 15" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 13. " INTPND14 ,Interrupt Pending Bit 14" "Not pending,Pending"
|
|
bitfld.long 0x2c 12. " INTPND13 ,Interrupt Pending Bit 13" "Not pending,Pending"
|
|
bitfld.long 0x2c 11. " INTPND12 ,Interrupt Pending Bit 12" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 10. " INTPND11 ,Interrupt Pending Bit 11" "Not pending,Pending"
|
|
bitfld.long 0x2c 9. " INTPND10 ,Interrupt Pending Bit 10" "Not pending,Pending"
|
|
bitfld.long 0x2c 8. " INTPND9 ,Interrupt Pending Bit 9" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 7. " INTPND8 ,Interrupt Pending Bit 8" "Not pending,Pending"
|
|
bitfld.long 0x2c 6. " INTPND7 ,Interrupt Pending Bit 7" "Not pending,Pending"
|
|
bitfld.long 0x2c 5. " INTPND6 ,Interrupt Pending Bit 6" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 4. " INTPND5 ,Interrupt Pending Bit 5" "Not pending,Pending"
|
|
bitfld.long 0x2c 3. " INTPND4 ,Interrupt Pending Bit 4" "Not pending,Pending"
|
|
bitfld.long 0x2c 2. " INTPND3 ,Interrupt Pending Bit 3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 1. " INTPND2 ,Interrupt Pending Bit 2" "Not pending,Pending"
|
|
bitfld.long 0x2c 0. " INTPND1 ,Interrupt Pending Bit 1" "Not pending,Pending"
|
|
line.long 0x30 "DCAN_INTPND34,Interrupt Pending 3_4 Register"
|
|
bitfld.long 0x30 31. " INTPND64 ,Interrupt Pending Bit 64" "Not pending,Pending"
|
|
bitfld.long 0x30 30. " INTPND63 ,Interrupt Pending Bit 63" "Not pending,Pending"
|
|
bitfld.long 0x30 29. " INTPND62 ,Interrupt Pending Bit 62" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 28. " INTPND61 ,Interrupt Pending Bit 61" "Not pending,Pending"
|
|
bitfld.long 0x30 27. " INTPND60 ,Interrupt Pending Bit 60" "Not pending,Pending"
|
|
bitfld.long 0x30 26. " INTPND59 ,Interrupt Pending Bit 59" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 25. " INTPND58 ,Interrupt Pending Bit 58" "Not pending,Pending"
|
|
bitfld.long 0x30 24. " INTPND57 ,Interrupt Pending Bit 57" "Not pending,Pending"
|
|
bitfld.long 0x30 23. " INTPND56 ,Interrupt Pending Bit 56" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 22. " INTPND55 ,Interrupt Pending Bit 55" "Not pending,Pending"
|
|
bitfld.long 0x30 21. " INTPND54 ,Interrupt Pending Bit 54" "Not pending,Pending"
|
|
bitfld.long 0x30 20. " INTPND53 ,Interrupt Pending Bit 53" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 19. " INTPND52 ,Interrupt Pending Bit 52" "Not pending,Pending"
|
|
bitfld.long 0x30 18. " INTPND51 ,Interrupt Pending Bit 51" "Not pending,Pending"
|
|
bitfld.long 0x30 17. " INTPND50 ,Interrupt Pending Bit 50" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 16. " INTPND49 ,Interrupt Pending Bit 49" "Not pending,Pending"
|
|
bitfld.long 0x30 15. " INTPND48 ,Interrupt Pending Bit 48" "Not pending,Pending"
|
|
bitfld.long 0x30 14. " INTPND47 ,Interrupt Pending Bit 47" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 13. " INTPND46 ,Interrupt Pending Bit 46" "Not pending,Pending"
|
|
bitfld.long 0x30 12. " INTPND45 ,Interrupt Pending Bit 45" "Not pending,Pending"
|
|
bitfld.long 0x30 11. " INTPND44 ,Interrupt Pending Bit 44" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 10. " INTPND43 ,Interrupt Pending Bit 43" "Not pending,Pending"
|
|
bitfld.long 0x30 9. " INTPND42 ,Interrupt Pending Bit 42" "Not pending,Pending"
|
|
bitfld.long 0x30 8. " INTPND41 ,Interrupt Pending Bit 41" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 7. " INTPND40 ,Interrupt Pending Bit 40" "Not pending,Pending"
|
|
bitfld.long 0x30 6. " INTPND39 ,Interrupt Pending Bit 39" "Not pending,Pending"
|
|
bitfld.long 0x30 5. " INTPND38 ,Interrupt Pending Bit 38" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 4. " INTPND37 ,Interrupt Pending Bit 37" "Not pending,Pending"
|
|
bitfld.long 0x30 3. " INTPND36 ,Interrupt Pending Bit 36" "Not pending,Pending"
|
|
bitfld.long 0x30 2. " INTPND35 ,Interrupt Pending Bit 35" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 1. " INTPND34 ,Interrupt Pending Bit 34" "Not pending,Pending"
|
|
bitfld.long 0x30 0. " INTPND33 ,Interrupt Pending Bit 33" "Not pending,Pending"
|
|
line.long 0x34 "DCAN_INTPND56,Interrupt Pending 5_6 Register"
|
|
bitfld.long 0x34 31. " INTPND96 ,Interrupt Pending Bit 96" "Not pending,Pending"
|
|
bitfld.long 0x34 30. " INTPND95 ,Interrupt Pending Bit 95" "Not pending,Pending"
|
|
bitfld.long 0x34 29. " INTPND94 ,Interrupt Pending Bit 94" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 28. " INTPND93 ,Interrupt Pending Bit 93" "Not pending,Pending"
|
|
bitfld.long 0x34 27. " INTPND92 ,Interrupt Pending Bit 92" "Not pending,Pending"
|
|
bitfld.long 0x34 26. " INTPND91 ,Interrupt Pending Bit 91" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 25. " INTPND90 ,Interrupt Pending Bit 90" "Not pending,Pending"
|
|
bitfld.long 0x34 24. " INTPND89 ,Interrupt Pending Bit 89" "Not pending,Pending"
|
|
bitfld.long 0x34 23. " INTPND88 ,Interrupt Pending Bit 88" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 22. " INTPND87 ,Interrupt Pending Bit 87" "Not pending,Pending"
|
|
bitfld.long 0x34 21. " INTPND86 ,Interrupt Pending Bit 86" "Not pending,Pending"
|
|
bitfld.long 0x34 20. " INTPND85 ,Interrupt Pending Bit 85" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 19. " INTPND84 ,Interrupt Pending Bit 84" "Not pending,Pending"
|
|
bitfld.long 0x34 18. " INTPND83 ,Interrupt Pending Bit 83" "Not pending,Pending"
|
|
bitfld.long 0x34 17. " INTPND82 ,Interrupt Pending Bit 82" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 16. " INTPND81 ,Interrupt Pending Bit 81" "Not pending,Pending"
|
|
bitfld.long 0x34 15. " INTPND80 ,Interrupt Pending Bit 80" "Not pending,Pending"
|
|
bitfld.long 0x34 14. " INTPND79 ,Interrupt Pending Bit 79" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 13. " INTPND78 ,Interrupt Pending Bit 78" "Not pending,Pending"
|
|
bitfld.long 0x34 12. " INTPND77 ,Interrupt Pending Bit 77" "Not pending,Pending"
|
|
bitfld.long 0x34 11. " INTPND76 ,Interrupt Pending Bit 76" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 10. " INTPND75 ,Interrupt Pending Bit 75" "Not pending,Pending"
|
|
bitfld.long 0x34 9. " INTPND74 ,Interrupt Pending Bit 74" "Not pending,Pending"
|
|
bitfld.long 0x34 8. " INTPND73 ,Interrupt Pending Bit 73" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 7. " INTPND72 ,Interrupt Pending Bit 72" "Not pending,Pending"
|
|
bitfld.long 0x34 6. " INTPND71 ,Interrupt Pending Bit 71" "Not pending,Pending"
|
|
bitfld.long 0x34 5. " INTPND70 ,Interrupt Pending Bit 70" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 4. " INTPND69 ,Interrupt Pending Bit 69" "Not pending,Pending"
|
|
bitfld.long 0x34 3. " INTPND68 ,Interrupt Pending Bit 68" "Not pending,Pending"
|
|
bitfld.long 0x34 2. " INTPND67 ,Interrupt Pending Bit 67" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 1. " INTPND66 ,Interrupt Pending Bit 66" "Not pending,Pending"
|
|
bitfld.long 0x34 0. " INTPND65 ,Interrupt Pending Bit 65" "Not pending,Pending"
|
|
line.long 0x38 "DCAN_INTPND78,Interrupt Pending 7_8 Register"
|
|
bitfld.long 0x38 31. " INTPND128 ,Interrupt Pending Bit 128" "Not pending,Pending"
|
|
bitfld.long 0x38 30. " INTPND127 ,Interrupt Pending Bit 127" "Not pending,Pending"
|
|
bitfld.long 0x38 29. " INTPND126 ,Interrupt Pending Bit 126" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 28. " INTPND125 ,Interrupt Pending Bit 125" "Not pending,Pending"
|
|
bitfld.long 0x38 27. " INTPND124 ,Interrupt Pending Bit 124" "Not pending,Pending"
|
|
bitfld.long 0x38 26. " INTPND123 ,Interrupt Pending Bit 123" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 25. " INTPND122 ,Interrupt Pending Bit 122" "Not pending,Pending"
|
|
bitfld.long 0x38 24. " INTPND121 ,Interrupt Pending Bit 121" "Not pending,Pending"
|
|
bitfld.long 0x38 23. " INTPND120 ,Interrupt Pending Bit 120" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 22. " INTPND119 ,Interrupt Pending Bit 119" "Not pending,Pending"
|
|
bitfld.long 0x38 21. " INTPND118 ,Interrupt Pending Bit 118" "Not pending,Pending"
|
|
bitfld.long 0x38 20. " INTPND117 ,Interrupt Pending Bit 117" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 19. " INTPND116 ,Interrupt Pending Bit 116" "Not pending,Pending"
|
|
bitfld.long 0x38 18. " INTPND115 ,Interrupt Pending Bit 115" "Not pending,Pending"
|
|
bitfld.long 0x38 17. " INTPND114 ,Interrupt Pending Bit 114" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 16. " INTPND113 ,Interrupt Pending Bit 113" "Not pending,Pending"
|
|
bitfld.long 0x38 15. " INTPND112 ,Interrupt Pending Bit 112" "Not pending,Pending"
|
|
bitfld.long 0x38 14. " INTPND111 ,Interrupt Pending Bit 111" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 13. " INTPND110 ,Interrupt Pending Bit 110" "Not pending,Pending"
|
|
bitfld.long 0x38 12. " INTPND109 ,Interrupt Pending Bit 109" "Not pending,Pending"
|
|
bitfld.long 0x38 11. " INTPND108 ,Interrupt Pending Bit 108" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 10. " INTPND107 ,Interrupt Pending Bit 107" "Not pending,Pending"
|
|
bitfld.long 0x38 9. " INTPND106 ,Interrupt Pending Bit 106" "Not pending,Pending"
|
|
bitfld.long 0x38 8. " INTPND105 ,Interrupt Pending Bit 105" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 7. " INTPND104 ,Interrupt Pending Bit 104" "Not pending,Pending"
|
|
bitfld.long 0x38 6. " INTPND103 ,Interrupt Pending Bit 103" "Not pending,Pending"
|
|
bitfld.long 0x38 5. " INTPND102 ,Interrupt Pending Bit 102" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 4. " INTPND101 ,Interrupt Pending Bit 101" "Not pending,Pending"
|
|
bitfld.long 0x38 3. " INTPND100 ,Interrupt Pending Bit 100" "Not pending,Pending"
|
|
bitfld.long 0x38 2. " INTPND99 ,Interrupt Pending Bit 99" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 1. " INTPND98 ,Interrupt Pending Bit 98" "Not pending,Pending"
|
|
bitfld.long 0x38 0. " INTPND97 ,Interrupt Pending Bit 97" "Not pending,Pending"
|
|
line.long 0x3c "DCAN_MSGVAL_X,Message Valid X Register"
|
|
bitfld.long 0x3c 14.--15. " MSGVALREG8 ,Message Valid X Register 8" "0,1,2,3"
|
|
bitfld.long 0x3c 12.--13. " MSGVALREG7 ,Message Valid X Register 7" "0,1,2,3"
|
|
bitfld.long 0x3c 10.--11. " MSGVALREG6 ,Message Valid X Register 6" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x3c 8.--9. " MSGVALREG5 ,Message Valid X Register 5" "0,1,2,3"
|
|
bitfld.long 0x3c 6.--7. " MSGVALREG4 ,Message Valid X Register 4" "0,1,2,3"
|
|
bitfld.long 0x3c 4.--5. " MSGVALREG3 ,Message Valid X Register 3" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x3c 2.--3. " MSGVALREG2 ,Message Valid X Register 2" "0,1,2,3"
|
|
bitfld.long 0x3c 0.--1. " MSGVALREG1 ,Message Valid X Register 1" "0,1,2,3"
|
|
line.long 0x40 "DCAN_MSGVAL12,Message Valid 1_2 Register"
|
|
bitfld.long 0x40 31. " MSGVAL32 ,Message Valid Bit 32" "Ignored,Not ignored"
|
|
bitfld.long 0x40 30. " MSGVAL31 ,Message Valid Bit 31" "Ignored,Not ignored"
|
|
bitfld.long 0x40 29. " MSGVAL30 ,Message Valid Bit 30" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 28. " MSGVAL29 ,Message Valid Bit 29" "Ignored,Not ignored"
|
|
bitfld.long 0x40 27. " MSGVAL28 ,Message Valid Bit 28" "Ignored,Not ignored"
|
|
bitfld.long 0x40 26. " MSGVAL27 ,Message Valid Bit 27" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 25. " MSGVAL26 ,Message Valid Bit 26" "Ignored,Not ignored"
|
|
bitfld.long 0x40 24. " MSGVAL25 ,Message Valid Bit 25" "Ignored,Not ignored"
|
|
bitfld.long 0x40 23. " MSGVAL24 ,Message Valid Bit 24" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 22. " MSGVAL23 ,Message Valid Bit 23" "Ignored,Not ignored"
|
|
bitfld.long 0x40 21. " MSGVAL22 ,Message Valid Bit 22" "Ignored,Not ignored"
|
|
bitfld.long 0x40 20. " MSGVAL21 ,Message Valid Bit 21" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 19. " MSGVAL20 ,Message Valid Bit 20" "Ignored,Not ignored"
|
|
bitfld.long 0x40 18. " MSGVAL19 ,Message Valid Bit 19" "Ignored,Not ignored"
|
|
bitfld.long 0x40 17. " MSGVAL18 ,Message Valid Bit 18" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 16. " MSGVAL17 ,Message Valid Bit 17" "Ignored,Not ignored"
|
|
bitfld.long 0x40 15. " MSGVAL16 ,Message Valid Bit 16" "Ignored,Not ignored"
|
|
bitfld.long 0x40 14. " MSGVAL15 ,Message Valid Bit 15" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 13. " MSGVAL14 ,Message Valid Bit 14" "Ignored,Not ignored"
|
|
bitfld.long 0x40 12. " MSGVAL13 ,Message Valid Bit 13" "Ignored,Not ignored"
|
|
bitfld.long 0x40 11. " MSGVAL12 ,Message Valid Bit 12" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 10. " MSGVAL11 ,Message Valid Bit 11" "Ignored,Not ignored"
|
|
bitfld.long 0x40 9. " MSGVAL10 ,Message Valid Bit 10" "Ignored,Not ignored"
|
|
bitfld.long 0x40 8. " MSGVAL9 ,Message Valid Bit 9" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 7. " MSGVAL8 ,Message Valid Bit 8" "Ignored,Not ignored"
|
|
bitfld.long 0x40 6. " MSGVAL7 ,Message Valid Bit 7" "Ignored,Not ignored"
|
|
bitfld.long 0x40 5. " MSGVAL6 ,Message Valid Bit 6" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 4. " MSGVAL5 ,Message Valid Bit 5" "Ignored,Not ignored"
|
|
bitfld.long 0x40 3. " MSGVAL4 ,Message Valid Bit 4" "Ignored,Not ignored"
|
|
bitfld.long 0x40 2. " MSGVAL3 ,Message Valid Bit 3" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 1. " MSGVAL2 ,Message Valid Bit 2" "Ignored,Not ignored"
|
|
bitfld.long 0x40 0. " MSGVAL1 ,Message Valid Bit 1" "Ignored,Not ignored"
|
|
line.long 0x44 "DCAN_MSGVAL34,Message Valid 3_4 Register"
|
|
bitfld.long 0x44 31. " MSGVAL64 ,Message Valid Bit 64" "Ignored,Not ignored"
|
|
bitfld.long 0x44 30. " MSGVAL63 ,Message Valid Bit 63" "Ignored,Not ignored"
|
|
bitfld.long 0x44 29. " MSGVAL62 ,Message Valid Bit 62" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 28. " MSGVAL61 ,Message Valid Bit 61" "Ignored,Not ignored"
|
|
bitfld.long 0x44 27. " MSGVAL60 ,Message Valid Bit 60" "Ignored,Not ignored"
|
|
bitfld.long 0x44 26. " MSGVAL59 ,Message Valid Bit 59" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 25. " MSGVAL58 ,Message Valid Bit 58" "Ignored,Not ignored"
|
|
bitfld.long 0x44 24. " MSGVAL57 ,Message Valid Bit 57" "Ignored,Not ignored"
|
|
bitfld.long 0x44 23. " MSGVAL56 ,Message Valid Bit 56" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 22. " MSGVAL55 ,Message Valid Bit 55" "Ignored,Not ignored"
|
|
bitfld.long 0x44 21. " MSGVAL54 ,Message Valid Bit 54" "Ignored,Not ignored"
|
|
bitfld.long 0x44 20. " MSGVAL53 ,Message Valid Bit 53" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 19. " MSGVAL52 ,Message Valid Bit 52" "Ignored,Not ignored"
|
|
bitfld.long 0x44 18. " MSGVAL51 ,Message Valid Bit 51" "Ignored,Not ignored"
|
|
bitfld.long 0x44 17. " MSGVAL50 ,Message Valid Bit 50" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 16. " MSGVAL49 ,Message Valid Bit 49" "Ignored,Not ignored"
|
|
bitfld.long 0x44 15. " MSGVAL48 ,Message Valid Bit 48" "Ignored,Not ignored"
|
|
bitfld.long 0x44 14. " MSGVAL47 ,Message Valid Bit 47" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 13. " MSGVAL46 ,Message Valid Bit 46" "Ignored,Not ignored"
|
|
bitfld.long 0x44 12. " MSGVAL45 ,Message Valid Bit 45" "Ignored,Not ignored"
|
|
bitfld.long 0x44 11. " MSGVAL44 ,Message Valid Bit 44" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 10. " MSGVAL43 ,Message Valid Bit 43" "Ignored,Not ignored"
|
|
bitfld.long 0x44 9. " MSGVAL42 ,Message Valid Bit 42" "Ignored,Not ignored"
|
|
bitfld.long 0x44 8. " MSGVAL41 ,Message Valid Bit 41" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 7. " MSGVAL40 ,Message Valid Bit 40" "Ignored,Not ignored"
|
|
bitfld.long 0x44 6. " MSGVAL39 ,Message Valid Bit 39" "Ignored,Not ignored"
|
|
bitfld.long 0x44 5. " MSGVAL38 ,Message Valid Bit 38" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 4. " MSGVAL37 ,Message Valid Bit 37" "Ignored,Not ignored"
|
|
bitfld.long 0x44 3. " MSGVAL36 ,Message Valid Bit 36" "Ignored,Not ignored"
|
|
bitfld.long 0x44 2. " MSGVAL35 ,Message Valid Bit 35" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 1. " MSGVAL34 ,Message Valid Bit 34" "Ignored,Not ignored"
|
|
bitfld.long 0x44 0. " MSGVAL33 ,Message Valid Bit 33" "Ignored,Not ignored"
|
|
line.long 0x48 "DCAN_MSGVAL56,Message Valid 5_6 Register"
|
|
bitfld.long 0x48 31. " MSGVAL96 ,Message Valid Bit 96" "Ignored,Not ignored"
|
|
bitfld.long 0x48 30. " MSGVAL95 ,Message Valid Bit 95" "Ignored,Not ignored"
|
|
bitfld.long 0x48 29. " MSGVAL94 ,Message Valid Bit 94" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 28. " MSGVAL93 ,Message Valid Bit 93" "Ignored,Not ignored"
|
|
bitfld.long 0x48 27. " MSGVAL92 ,Message Valid Bit 92" "Ignored,Not ignored"
|
|
bitfld.long 0x48 26. " MSGVAL91 ,Message Valid Bit 91" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 25. " MSGVAL90 ,Message Valid Bit 90" "Ignored,Not ignored"
|
|
bitfld.long 0x48 24. " MSGVAL89 ,Message Valid Bit 89" "Ignored,Not ignored"
|
|
bitfld.long 0x48 23. " MSGVAL88 ,Message Valid Bit 88" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 22. " MSGVAL87 ,Message Valid Bit 87" "Ignored,Not ignored"
|
|
bitfld.long 0x48 21. " MSGVAL86 ,Message Valid Bit 86" "Ignored,Not ignored"
|
|
bitfld.long 0x48 20. " MSGVAL85 ,Message Valid Bit 85" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 19. " MSGVAL84 ,Message Valid Bit 84" "Ignored,Not ignored"
|
|
bitfld.long 0x48 18. " MSGVAL83 ,Message Valid Bit 83" "Ignored,Not ignored"
|
|
bitfld.long 0x48 17. " MSGVAL82 ,Message Valid Bit 82" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 16. " MSGVAL81 ,Message Valid Bit 81" "Ignored,Not ignored"
|
|
bitfld.long 0x48 15. " MSGVAL80 ,Message Valid Bit 80" "Ignored,Not ignored"
|
|
bitfld.long 0x48 14. " MSGVAL79 ,Message Valid Bit 79" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 13. " MSGVAL78 ,Message Valid Bit 78" "Ignored,Not ignored"
|
|
bitfld.long 0x48 12. " MSGVAL77 ,Message Valid Bit 77" "Ignored,Not ignored"
|
|
bitfld.long 0x48 11. " MSGVAL76 ,Message Valid Bit 76" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 10. " MSGVAL75 ,Message Valid Bit 75" "Ignored,Not ignored"
|
|
bitfld.long 0x48 9. " MSGVAL74 ,Message Valid Bit 74" "Ignored,Not ignored"
|
|
bitfld.long 0x48 8. " MSGVAL73 ,Message Valid Bit 73" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 7. " MSGVAL72 ,Message Valid Bit 72" "Ignored,Not ignored"
|
|
bitfld.long 0x48 6. " MSGVAL71 ,Message Valid Bit 71" "Ignored,Not ignored"
|
|
bitfld.long 0x48 5. " MSGVAL70 ,Message Valid Bit 70" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 4. " MSGVAL69 ,Message Valid Bit 69" "Ignored,Not ignored"
|
|
bitfld.long 0x48 3. " MSGVAL68 ,Message Valid Bit 68" "Ignored,Not ignored"
|
|
bitfld.long 0x48 2. " MSGVAL67 ,Message Valid Bit 67" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 1. " MSGVAL66 ,Message Valid Bit 66" "Ignored,Not ignored"
|
|
bitfld.long 0x48 0. " MSGVAL65 ,Message Valid Bit 65" "Ignored,Not ignored"
|
|
line.long 0x4C "DCAN_MSGVAL78,Message Valid 7_8 Register"
|
|
bitfld.long 0x4C 31. " MSGVAL128 ,Message Valid Bit 128" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 30. " MSGVAL127 ,Message Valid Bit 127" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 29. " MSGVAL126 ,Message Valid Bit 126" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 28. " MSGVAL125 ,Message Valid Bit 125" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 27. " MSGVAL124 ,Message Valid Bit 124" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 26. " MSGVAL123 ,Message Valid Bit 123" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 25. " MSGVAL122 ,Message Valid Bit 122" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 24. " MSGVAL121 ,Message Valid Bit 121" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 23. " MSGVAL120 ,Message Valid Bit 120" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 22. " MSGVAL119 ,Message Valid Bit 119" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 21. " MSGVAL118 ,Message Valid Bit 118" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 20. " MSGVAL117 ,Message Valid Bit 117" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 19. " MSGVAL116 ,Message Valid Bit 116" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 18. " MSGVAL115 ,Message Valid Bit 115" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 17. " MSGVAL114 ,Message Valid Bit 114" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 16. " MSGVAL113 ,Message Valid Bit 113" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 15. " MSGVAL112 ,Message Valid Bit 112" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 14. " MSGVAL111 ,Message Valid Bit 111" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 13. " MSGVAL110 ,Message Valid Bit 110" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 12. " MSGVAL109 ,Message Valid Bit 109" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 11. " MSGVAL108 ,Message Valid Bit 108" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 10. " MSGVAL107 ,Message Valid Bit 107" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 9. " MSGVAL106 ,Message Valid Bit 106" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 8. " MSGVAL105 ,Message Valid Bit 105" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 7. " MSGVAL104 ,Message Valid Bit 104" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 6. " MSGVAL103 ,Message Valid Bit 103" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 5. " MSGVAL102 ,Message Valid Bit 102" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 4. " MSGVAL101 ,Message Valid Bit 101" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 3. " MSGVAL100 ,Message Valid Bit 100" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 2. " MSGVAL99 ,Message Valid Bit 99" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 1. " MSGVAL98 ,Message Valid Bit 98" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 0. " MSGVAL97 ,Message Valid Bit 97" "Ignored,Not ignored"
|
|
group.long 0xD8--0xE7
|
|
sif (cpuis("DRA62*"))
|
|
line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer 1_2 Register"
|
|
bitfld.long 0x00 31. " INTMUX32 ,Multiplexes IntPnd value to one of two interrupt line 32" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 30. " INTMUX31 ,Multiplexes IntPnd value to one of two interrupt line 31" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 29. " INTMUX30 ,Multiplexes IntPnd value to one of two interrupt line 30" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 28. " INTMUX29 ,Multiplexes IntPnd value to one of two interrupt line 29" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 27. " INTMUX28 ,Multiplexes IntPnd value to one of two interrupt line 28" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 26. " INTMUX27 ,Multiplexes IntPnd value to one of two interrupt line 27" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTMUX26 ,Multiplexes IntPnd value to one of two interrupt line 26" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 24. " INTMUX25 ,Multiplexes IntPnd value to one of two interrupt line 25" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 23. " INTMUX24 ,Multiplexes IntPnd value to one of two interrupt line 24" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 22. " INTMUX23 ,Multiplexes IntPnd value to one of two interrupt line 23" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 21. " INTMUX22 ,Multiplexes IntPnd value to one of two interrupt line 22" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 20. " INTMUX21 ,Multiplexes IntPnd value to one of two interrupt line 21" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTMUX20 ,Multiplexes IntPnd value to one of two interrupt line 20" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 18. " INTMUX19 ,Multiplexes IntPnd value to one of two interrupt line 19" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 17. " INTMUX18 ,Multiplexes IntPnd value to one of two interrupt line 18" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INTMUX17 ,Multiplexes IntPnd value to one of two interrupt line 17" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 15. " INTMUX16 ,Multiplexes IntPnd value to one of two interrupt line 16" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 14. " INTMUX15 ,Multiplexes IntPnd value to one of two interrupt line 15" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTMUX14 ,Multiplexes IntPnd value to one of two interrupt line 14" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 12. " INTMUX13 ,Multiplexes IntPnd value to one of two interrupt line 13" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 11. " INTMUX12 ,Multiplexes IntPnd value to one of two interrupt line 12" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INTMUX11 ,Multiplexes IntPnd value to one of two interrupt line 11" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 9. " INTMUX10 ,Multiplexes IntPnd value to one of two interrupt line 10" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 8. " INTMUX9 ,Multiplexes IntPnd value to one of two interrupt line 9" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTMUX8 ,Multiplexes IntPnd value to one of two interrupt line 8" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 6. " INTMUX7 ,Multiplexes IntPnd value to one of two interrupt line 7" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 5. " INTMUX6 ,Multiplexes IntPnd value to one of two interrupt line 6" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTMUX5 ,Multiplexes IntPnd value to one of two interrupt line 5" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 3. " INTMUX4 ,Multiplexes IntPnd value to one of two interrupt line 4" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 2. " INTMUX3 ,Multiplexes IntPnd value to one of two interrupt line 3" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTMUX2 ,Multiplexes IntPnd value to one of two interrupt line 2" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 0. " INTMUX1 ,Multiplexes IntPnd value to one of two interrupt line 1" "DCAN0INT,DCAN1INT"
|
|
line.long 0x04 "DCAN_INTMUX34,Interrupt Multiplexer 3_4 Register"
|
|
bitfld.long 0x04 31. " INTMUX64 ,Multiplexes IntPnd value to one of two interrupt line 64" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 30. " INTMUX63 ,Multiplexes IntPnd value to one of two interrupt line 63" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 29. " INTMUX62 ,Multiplexes IntPnd value to one of two interrupt line 62" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 28. " INTMUX61 ,Multiplexes IntPnd value to one of two interrupt line 61" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 27. " INTMUX60 ,Multiplexes IntPnd value to one of two interrupt line 60" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 26. " INTMUX59 ,Multiplexes IntPnd value to one of two interrupt line 59" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTMUX58 ,Multiplexes IntPnd value to one of two interrupt line 58" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 24. " INTMUX57 ,Multiplexes IntPnd value to one of two interrupt line 57" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 23. " INTMUX56 ,Multiplexes IntPnd value to one of two interrupt line 56" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 22. " INTMUX55 ,Multiplexes IntPnd value to one of two interrupt line 55" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 21. " INTMUX54 ,Multiplexes IntPnd value to one of two interrupt line 54" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 20. " INTMUX53 ,Multiplexes IntPnd value to one of two interrupt line 53" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTMUX52 ,Multiplexes IntPnd value to one of two interrupt line 52" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 18. " INTMUX51 ,Multiplexes IntPnd value to one of two interrupt line 51" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 17. " INTMUX50 ,Multiplexes IntPnd value to one of two interrupt line 50" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 16. " INTMUX49 ,Multiplexes IntPnd value to one of two interrupt line 49" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 15. " INTMUX48 ,Multiplexes IntPnd value to one of two interrupt line 48" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 14. " INTMUX47 ,Multiplexes IntPnd value to one of two interrupt line 47" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTMUX46 ,Multiplexes IntPnd value to one of two interrupt line 46" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 12. " INTMUX45 ,Multiplexes IntPnd value to one of two interrupt line 45" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 11. " INTMUX44 ,Multiplexes IntPnd value to one of two interrupt line 44" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 10. " INTMUX43 ,Multiplexes IntPnd value to one of two interrupt line 43" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 9. " INTMUX42 ,Multiplexes IntPnd value to one of two interrupt line 42" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 8. " INTMUX41 ,Multiplexes IntPnd value to one of two interrupt line 41" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTMUX40 ,Multiplexes IntPnd value to one of two interrupt line 40" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 6. " INTMUX39 ,Multiplexes IntPnd value to one of two interrupt line 39" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 5. " INTMUX38 ,Multiplexes IntPnd value to one of two interrupt line 38" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INTMUX37 ,Multiplexes IntPnd value to one of two interrupt line 37" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 3. " INTMUX36 ,Multiplexes IntPnd value to one of two interrupt line 36" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 2. " INTMUX35 ,Multiplexes IntPnd value to one of two interrupt line 35" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTMUX34 ,Multiplexes IntPnd value to one of two interrupt line 34" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 0. " INTMUX33 ,Multiplexes IntPnd value to one of two interrupt line 33" "DCAN0INT,DCAN1INT"
|
|
line.long 0x08 "DCAN_INTMUX56,Interrupt Multiplexer 5_6 Register"
|
|
bitfld.long 0x08 31. " INTMUX96 ,Multiplexes IntPnd value to one of two interrupt line 96" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 30. " INTMUX95 ,Multiplexes IntPnd value to one of two interrupt line 95" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 29. " INTMUX94 ,Multiplexes IntPnd value to one of two interrupt line 94" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 28. " INTMUX93 ,Multiplexes IntPnd value to one of two interrupt line 93" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 27. " INTMUX92 ,Multiplexes IntPnd value to one of two interrupt line 92" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 26. " INTMUX91 ,Multiplexes IntPnd value to one of two interrupt line 91" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 25. " INTMUX90 ,Multiplexes IntPnd value to one of two interrupt line 90" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 24. " INTMUX89 ,Multiplexes IntPnd value to one of two interrupt line 89" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 23. " INTMUX88 ,Multiplexes IntPnd value to one of two interrupt line 88" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 22. " INTMUX87 ,Multiplexes IntPnd value to one of two interrupt line 87" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 21. " INTMUX86 ,Multiplexes IntPnd value to one of two interrupt line 86" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 20. " INTMUX85 ,Multiplexes IntPnd value to one of two interrupt line 85" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 19. " INTMUX84 ,Multiplexes IntPnd value to one of two interrupt line 84" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 18. " INTMUX83 ,Multiplexes IntPnd value to one of two interrupt line 83" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 17. " INTMUX82 ,Multiplexes IntPnd value to one of two interrupt line 82" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 16. " INTMUX81 ,Multiplexes IntPnd value to one of two interrupt line 81" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 15. " INTMUX80 ,Multiplexes IntPnd value to one of two interrupt line 80" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 14. " INTMUX79 ,Multiplexes IntPnd value to one of two interrupt line 79" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 13. " INTMUX78 ,Multiplexes IntPnd value to one of two interrupt line 78" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 12. " INTMUX77 ,Multiplexes IntPnd value to one of two interrupt line 77" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 11. " INTMUX76 ,Multiplexes IntPnd value to one of two interrupt line 76" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 10. " INTMUX75 ,Multiplexes IntPnd value to one of two interrupt line 75" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 9. " INTMUX74 ,Multiplexes IntPnd value to one of two interrupt line 74" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 8. " INTMUX73 ,Multiplexes IntPnd value to one of two interrupt line 73" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 7. " INTMUX72 ,Multiplexes IntPnd value to one of two interrupt line 72" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 6. " INTMUX71 ,Multiplexes IntPnd value to one of two interrupt line 71" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 5. " INTMUX70 ,Multiplexes IntPnd value to one of two interrupt line 70" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 4. " INTMUX69 ,Multiplexes IntPnd value to one of two interrupt line 69" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 3. " INTMUX68 ,Multiplexes IntPnd value to one of two interrupt line 68" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 2. " INTMUX67 ,Multiplexes IntPnd value to one of two interrupt line 67" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 1. " INTMUX66 ,Multiplexes IntPnd value to one of two interrupt line 66" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 0. " INTMUX65 ,Multiplexes IntPnd value to one of two interrupt line 65" "DCAN0INT,DCAN1INT"
|
|
line.long 0x0C "DCAN_INTMUX78,Interrupt Multiplexer 7_8 Register"
|
|
bitfld.long 0x0C 31. " INTMUX128 ,Multiplexes IntPnd value to one of two interrupt line 128" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 30. " INTMUX127 ,Multiplexes IntPnd value to one of two interrupt line 127" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 29. " INTMUX126 ,Multiplexes IntPnd value to one of two interrupt line 126" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " INTMUX125 ,Multiplexes IntPnd value to one of two interrupt line 125" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 27. " INTMUX124 ,Multiplexes IntPnd value to one of two interrupt line 124" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 26. " INTMUX123 ,Multiplexes IntPnd value to one of two interrupt line 123" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " INTMUX122 ,Multiplexes IntPnd value to one of two interrupt line 122" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 24. " INTMUX121 ,Multiplexes IntPnd value to one of two interrupt line 121" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 23. " INTMUX120 ,Multiplexes IntPnd value to one of two interrupt line 120" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " INTMUX119 ,Multiplexes IntPnd value to one of two interrupt line 119" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 21. " INTMUX118 ,Multiplexes IntPnd value to one of two interrupt line 118" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 20. " INTMUX117 ,Multiplexes IntPnd value to one of two interrupt line 117" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " INTMUX116 ,Multiplexes IntPnd value to one of two interrupt line 116" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 18. " INTMUX115 ,Multiplexes IntPnd value to one of two interrupt line 115" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 17. " INTMUX114 ,Multiplexes IntPnd value to one of two interrupt line 114" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " INTMUX113 ,Multiplexes IntPnd value to one of two interrupt line 113" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 15. " INTMUX112 ,Multiplexes IntPnd value to one of two interrupt line 112" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 14. " INTMUX111 ,Multiplexes IntPnd value to one of two interrupt line 111" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " INTMUX110 ,Multiplexes IntPnd value to one of two interrupt line 110" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 12. " INTMUX109 ,Multiplexes IntPnd value to one of two interrupt line 109" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 11. " INTMUX108 ,Multiplexes IntPnd value to one of two interrupt line 108" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " INTMUX107 ,Multiplexes IntPnd value to one of two interrupt line 107" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 9. " INTMUX106 ,Multiplexes IntPnd value to one of two interrupt line 106" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 8. " INTMUX105 ,Multiplexes IntPnd value to one of two interrupt line 105" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " INTMUX104 ,Multiplexes IntPnd value to one of two interrupt line 104" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 6. " INTMUX103 ,Multiplexes IntPnd value to one of two interrupt line 103" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 5. " INTMUX102 ,Multiplexes IntPnd value to one of two interrupt line 102" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " INTMUX101 ,Multiplexes IntPnd value to one of two interrupt line 101" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 3. " INTMUX100 ,Multiplexes IntPnd value to one of two interrupt line 100" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 2. " INTMUX99 ,Multiplexes IntPnd value to one of two interrupt line 99" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " INTMUX98 ,Multiplexes IntPnd value to one of two interrupt line 98" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 0. " INTMUX97 ,Multiplexes IntPnd value to one of two interrupt line 97" "DCAN0INT,DCAN1INT"
|
|
else
|
|
line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer 1_2 Register"
|
|
bitfld.long 0x00 31. " INTPNDMUX32 ,Multiplexes IntPnd value to one of two interrupt line 32" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 30. " INTPNDMUX31 ,Multiplexes IntPnd value to one of two interrupt line 31" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 29. " INTPNDMUX30 ,Multiplexes IntPnd value to one of two interrupt line 30" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 28. " INTPNDMUX29 ,Multiplexes IntPnd value to one of two interrupt line 29" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 27. " INTPNDMUX28 ,Multiplexes IntPnd value to one of two interrupt line 28" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 26. " INTPNDMUX27 ,Multiplexes IntPnd value to one of two interrupt line 27" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTPNDMUX26 ,Multiplexes IntPnd value to one of two interrupt line 26" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 24. " INTPNDMUX25 ,Multiplexes IntPnd value to one of two interrupt line 25" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 23. " INTPNDMUX24 ,Multiplexes IntPnd value to one of two interrupt line 24" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 22. " INTPNDMUX23 ,Multiplexes IntPnd value to one of two interrupt line 23" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 21. " INTPNDMUX22 ,Multiplexes IntPnd value to one of two interrupt line 22" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 20. " INTPNDMUX21 ,Multiplexes IntPnd value to one of two interrupt line 21" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTPNDMUX20 ,Multiplexes IntPnd value to one of two interrupt line 20" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 18. " INTPNDMUX19 ,Multiplexes IntPnd value to one of two interrupt line 19" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 17. " INTPNDMUX18 ,Multiplexes IntPnd value to one of two interrupt line 18" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INTPNDMUX17 ,Multiplexes IntPnd value to one of two interrupt line 17" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 15. " INTPNDMUX16 ,Multiplexes IntPnd value to one of two interrupt line 16" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 14. " INTPNDMUX15 ,Multiplexes IntPnd value to one of two interrupt line 15" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTPNDMUX14 ,Multiplexes IntPnd value to one of two interrupt line 14" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 12. " INTPNDMUX13 ,Multiplexes IntPnd value to one of two interrupt line 13" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 11. " INTPNDMUX12 ,Multiplexes IntPnd value to one of two interrupt line 12" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INTPNDMUX11 ,Multiplexes IntPnd value to one of two interrupt line 11" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 9. " INTPNDMUX10 ,Multiplexes IntPnd value to one of two interrupt line 10" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 8. " INTPNDMUX9 ,Multiplexes IntPnd value to one of two interrupt line 9" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTPNDMUX8 ,Multiplexes IntPnd value to one of two interrupt line 8" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 6. " INTPNDMUX7 ,Multiplexes IntPnd value to one of two interrupt line 7" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 5. " INTPNDMUX6 ,Multiplexes IntPnd value to one of two interrupt line 6" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTPNDMUX5 ,Multiplexes IntPnd value to one of two interrupt line 5" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 3. " INTPNDMUX4 ,Multiplexes IntPnd value to one of two interrupt line 4" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 2. " INTPNDMUX3 ,Multiplexes IntPnd value to one of two interrupt line 3" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTPNDMUX2 ,Multiplexes IntPnd value to one of two interrupt line 2" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 0. " INTPNDMUX1 ,Multiplexes IntPnd value to one of two interrupt line 1" "DCAN0INT,DCAN1INT"
|
|
line.long 0x04 "DCAN_INTMUX34,Interrupt Multiplexer 3_4 Register"
|
|
bitfld.long 0x04 31. " INTPNDMUX64 ,Multiplexes IntPnd value to one of two interrupt line 64" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 30. " INTPNDMUX63 ,Multiplexes IntPnd value to one of two interrupt line 63" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 29. " INTPNDMUX62 ,Multiplexes IntPnd value to one of two interrupt line 62" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 28. " INTPNDMUX61 ,Multiplexes IntPnd value to one of two interrupt line 61" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 27. " INTPNDMUX60 ,Multiplexes IntPnd value to one of two interrupt line 60" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 26. " INTPNDMUX59 ,Multiplexes IntPnd value to one of two interrupt line 59" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTPNDMUX58 ,Multiplexes IntPnd value to one of two interrupt line 58" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 24. " INTPNDMUX57 ,Multiplexes IntPnd value to one of two interrupt line 57" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 23. " INTPNDMUX56 ,Multiplexes IntPnd value to one of two interrupt line 56" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 22. " INTPNDMUX55 ,Multiplexes IntPnd value to one of two interrupt line 55" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 21. " INTPNDMUX54 ,Multiplexes IntPnd value to one of two interrupt line 54" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 20. " INTPNDMUX53 ,Multiplexes IntPnd value to one of two interrupt line 53" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTPNDMUX52 ,Multiplexes IntPnd value to one of two interrupt line 52" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 18. " INTPNDMUX51 ,Multiplexes IntPnd value to one of two interrupt line 51" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 17. " INTPNDMUX50 ,Multiplexes IntPnd value to one of two interrupt line 50" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 16. " INTPNDMUX49 ,Multiplexes IntPnd value to one of two interrupt line 49" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 15. " INTPNDMUX48 ,Multiplexes IntPnd value to one of two interrupt line 48" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 14. " INTPNDMUX47 ,Multiplexes IntPnd value to one of two interrupt line 47" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTPNDMUX46 ,Multiplexes IntPnd value to one of two interrupt line 46" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 12. " INTPNDMUX45 ,Multiplexes IntPnd value to one of two interrupt line 45" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 11. " INTPNDMUX44 ,Multiplexes IntPnd value to one of two interrupt line 44" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 10. " INTPNDMUX43 ,Multiplexes IntPnd value to one of two interrupt line 43" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 9. " INTPNDMUX42 ,Multiplexes IntPnd value to one of two interrupt line 42" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 8. " INTPNDMUX41 ,Multiplexes IntPnd value to one of two interrupt line 41" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTPNDMUX40 ,Multiplexes IntPnd value to one of two interrupt line 40" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 6. " INTPNDMUX39 ,Multiplexes IntPnd value to one of two interrupt line 39" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 5. " INTPNDMUX38 ,Multiplexes IntPnd value to one of two interrupt line 38" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INTPNDMUX37 ,Multiplexes IntPnd value to one of two interrupt line 37" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 3. " INTPNDMUX36 ,Multiplexes IntPnd value to one of two interrupt line 36" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 2. " INTPNDMUX35 ,Multiplexes IntPnd value to one of two interrupt line 35" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTPNDMUX34 ,Multiplexes IntPnd value to one of two interrupt line 34" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 0. " INTPNDMUX33 ,Multiplexes IntPnd value to one of two interrupt line 33" "DCAN0INT,DCAN1INT"
|
|
line.long 0x08 "DCAN_INTMUX56,Interrupt Multiplexer 5_6 Register"
|
|
bitfld.long 0x08 31. " INTPNDMUX96 ,Multiplexes IntPnd value to one of two interrupt line 96" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 30. " INTPNDMUX95 ,Multiplexes IntPnd value to one of two interrupt line 95" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 29. " INTPNDMUX94 ,Multiplexes IntPnd value to one of two interrupt line 94" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 28. " INTPNDMUX93 ,Multiplexes IntPnd value to one of two interrupt line 93" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 27. " INTPNDMUX92 ,Multiplexes IntPnd value to one of two interrupt line 92" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 26. " INTPNDMUX91 ,Multiplexes IntPnd value to one of two interrupt line 91" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 25. " INTPNDMUX90 ,Multiplexes IntPnd value to one of two interrupt line 90" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 24. " INTPNDMUX89 ,Multiplexes IntPnd value to one of two interrupt line 89" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 23. " INTPNDMUX88 ,Multiplexes IntPnd value to one of two interrupt line 88" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 22. " INTPNDMUX87 ,Multiplexes IntPnd value to one of two interrupt line 87" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 21. " INTPNDMUX86 ,Multiplexes IntPnd value to one of two interrupt line 86" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 20. " INTPNDMUX85 ,Multiplexes IntPnd value to one of two interrupt line 85" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 19. " INTPNDMUX84 ,Multiplexes IntPnd value to one of two interrupt line 84" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 18. " INTPNDMUX83 ,Multiplexes IntPnd value to one of two interrupt line 83" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 17. " INTPNDMUX82 ,Multiplexes IntPnd value to one of two interrupt line 82" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 16. " INTPNDMUX81 ,Multiplexes IntPnd value to one of two interrupt line 81" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 15. " INTPNDMUX80 ,Multiplexes IntPnd value to one of two interrupt line 80" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 14. " INTPNDMUX79 ,Multiplexes IntPnd value to one of two interrupt line 79" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 13. " INTPNDMUX78 ,Multiplexes IntPnd value to one of two interrupt line 78" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 12. " INTPNDMUX77 ,Multiplexes IntPnd value to one of two interrupt line 77" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 11. " INTPNDMUX76 ,Multiplexes IntPnd value to one of two interrupt line 76" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 10. " INTPNDMUX75 ,Multiplexes IntPnd value to one of two interrupt line 75" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 9. " INTPNDMUX74 ,Multiplexes IntPnd value to one of two interrupt line 74" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 8. " INTPNDMUX73 ,Multiplexes IntPnd value to one of two interrupt line 73" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 7. " INTPNDMUX72 ,Multiplexes IntPnd value to one of two interrupt line 72" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 6. " INTPNDMUX71 ,Multiplexes IntPnd value to one of two interrupt line 71" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 5. " INTPNDMUX70 ,Multiplexes IntPnd value to one of two interrupt line 70" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 4. " INTPNDMUX69 ,Multiplexes IntPnd value to one of two interrupt line 69" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 3. " INTPNDMUX68 ,Multiplexes IntPnd value to one of two interrupt line 68" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 2. " INTPNDMUX67 ,Multiplexes IntPnd value to one of two interrupt line 67" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 1. " INTPNDMUX66 ,Multiplexes IntPnd value to one of two interrupt line 66" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 0. " INTPNDMUX65 ,Multiplexes IntPnd value to one of two interrupt line 65" "DCAN0INT,DCAN1INT"
|
|
line.long 0x0C "DCAN_INTMUX78,Interrupt Multiplexer 7_8 Register"
|
|
bitfld.long 0x0C 31. " INTPNDMUX128 ,Multiplexes IntPnd value to one of two interrupt line 128" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 30. " INTPNDMUX127 ,Multiplexes IntPnd value to one of two interrupt line 127" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 29. " INTPNDMUX126 ,Multiplexes IntPnd value to one of two interrupt line 126" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " INTPNDMUX125 ,Multiplexes IntPnd value to one of two interrupt line 125" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 27. " INTPNDMUX124 ,Multiplexes IntPnd value to one of two interrupt line 124" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 26. " INTPNDMUX123 ,Multiplexes IntPnd value to one of two interrupt line 123" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " INTPNDMUX122 ,Multiplexes IntPnd value to one of two interrupt line 122" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 24. " INTPNDMUX121 ,Multiplexes IntPnd value to one of two interrupt line 121" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 23. " INTPNDMUX120 ,Multiplexes IntPnd value to one of two interrupt line 120" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " INTPNDMUX119 ,Multiplexes IntPnd value to one of two interrupt line 119" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 21. " INTPNDMUX118 ,Multiplexes IntPnd value to one of two interrupt line 118" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 20. " INTPNDMUX117 ,Multiplexes IntPnd value to one of two interrupt line 117" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " INTPNDMUX116 ,Multiplexes IntPnd value to one of two interrupt line 116" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 18. " INTPNDMUX115 ,Multiplexes IntPnd value to one of two interrupt line 115" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 17. " INTPNDMUX114 ,Multiplexes IntPnd value to one of two interrupt line 114" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " INTPNDMUX113 ,Multiplexes IntPnd value to one of two interrupt line 113" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 15. " INTPNDMUX112 ,Multiplexes IntPnd value to one of two interrupt line 112" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 14. " INTPNDMUX111 ,Multiplexes IntPnd value to one of two interrupt line 111" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " INTPNDMUX110 ,Multiplexes IntPnd value to one of two interrupt line 110" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 12. " INTPNDMUX109 ,Multiplexes IntPnd value to one of two interrupt line 109" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 11. " INTPNDMUX108 ,Multiplexes IntPnd value to one of two interrupt line 108" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " INTPNDMUX107 ,Multiplexes IntPnd value to one of two interrupt line 107" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 9. " INTPNDMUX106 ,Multiplexes IntPnd value to one of two interrupt line 106" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 8. " INTPNDMUX105 ,Multiplexes IntPnd value to one of two interrupt line 105" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " INTPNDMUX104 ,Multiplexes IntPnd value to one of two interrupt line 104" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 6. " INTPNDMUX103 ,Multiplexes IntPnd value to one of two interrupt line 103" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 5. " INTPNDMUX102 ,Multiplexes IntPnd value to one of two interrupt line 102" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " INTPNDMUX101 ,Multiplexes IntPnd value to one of two interrupt line 101" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 3. " INTPNDMUX100 ,Multiplexes IntPnd value to one of two interrupt line 100" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 2. " INTPNDMUX99 ,Multiplexes IntPnd value to one of two interrupt line 99" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " INTPNDMUX98 ,Multiplexes IntPnd value to one of two interrupt line 98" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 0. " INTPNDMUX97 ,Multiplexes IntPnd value to one of two interrupt line 97" "DCAN0INT,DCAN1INT"
|
|
endif
|
|
if (((data.long(ad:0x481CC000+0x100))&0x800000)==0x800000)
|
|
group.long 0x100++0x03 "IF1 Registers"
|
|
line.long 0x00 "DCAN_IF1CMD,IF1 Command Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered"
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,?..."
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Handled,Set"
|
|
else
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Cleared,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered"
|
|
bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number"
|
|
else
|
|
group.long 0x100++0x03 "IF1 Registers"
|
|
line.long 0x00 "DCAN_IF1CMD,IF1 Command Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered"
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Unchanged,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered"
|
|
bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number"
|
|
endif
|
|
if ((((data.long(ad:0x481CC000+0x100))&0x8000)==0x8000)&&(((data.long(ad:0x481CC000+0x108))&0x40000000)==0x40000000))
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
bitfld.long 0x00 17. " ," "0,1"
|
|
bitfld.long 0x00 16. " ," "0,1"
|
|
bitfld.long 0x00 15. " ," "0,1"
|
|
bitfld.long 0x00 14. " ," "0,1"
|
|
bitfld.long 0x00 13. " ," "0,1"
|
|
bitfld.long 0x00 12. " ," "0,1"
|
|
bitfld.long 0x00 11. " ," "0,1"
|
|
bitfld.long 0x00 10. " ," "0,1"
|
|
bitfld.long 0x00 9. " ," "0,1"
|
|
bitfld.long 0x00 8. " ," "0,1"
|
|
bitfld.long 0x00 7. " ," "0,1"
|
|
bitfld.long 0x00 6. " ," "0,1"
|
|
bitfld.long 0x00 5. " ," "0,1"
|
|
bitfld.long 0x00 4. " ," "0,1"
|
|
bitfld.long 0x00 3. " ," "0,1"
|
|
bitfld.long 0x00 2. " ," "0,1"
|
|
bitfld.long 0x00 1. " ," "0,1"
|
|
bitfld.long 0x00 0. " ," "0,1"
|
|
elif ((((data.long(ad:0x481CC000+0x100))&0x8000)==0x0000)&&(((data.long(ad:0x481CC000+0x108))&0x40000000)==0x40000000))
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
bitfld.long 0x00 17. " ," "0,1"
|
|
bitfld.long 0x00 16. " ," "0,1"
|
|
bitfld.long 0x00 15. " ," "0,1"
|
|
bitfld.long 0x00 14. " ," "0,1"
|
|
bitfld.long 0x00 13. " ," "0,1"
|
|
bitfld.long 0x00 12. " ," "0,1"
|
|
bitfld.long 0x00 11. " ," "0,1"
|
|
bitfld.long 0x00 10. " ," "0,1"
|
|
bitfld.long 0x00 9. " ," "0,1"
|
|
bitfld.long 0x00 8. " ," "0,1"
|
|
bitfld.long 0x00 7. " ," "0,1"
|
|
bitfld.long 0x00 6. " ," "0,1"
|
|
bitfld.long 0x00 5. " ," "0,1"
|
|
bitfld.long 0x00 4. " ," "0,1"
|
|
bitfld.long 0x00 3. " ," "0,1"
|
|
bitfld.long 0x00 2. " ," "0,1"
|
|
bitfld.long 0x00 1. " ," "0,1"
|
|
bitfld.long 0x00 0. " ," "0,1"
|
|
elif ((((data.long(ad:0x481CC000+0x100))&0x8000)==0x8000)&&(((data.long(ad:0x481CC000+0x108))&0x40000000)==0x00))
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK10-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK10-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
endif
|
|
if ((((data.long(ad:0x481CC000+0x100))&0x8000)==0x8000)&&(((data.long(ad:0x481CC000+0x108))&0x40000000)==0x40000000))
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier"
|
|
elif ((((data.long(ad:0x481CC000+0x100))&0x8000)==0x0000)&&(((data.long(ad:0x481CC000+0x108))&0x40000000)==0x40000000))
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier"
|
|
elif ((((data.long(ad:0x481CC000+0x100))&0x8000)==0x0000)&&(((data.long(ad:0x481CC000+0x108))&0x40000000)==0x00000000))
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier"
|
|
else
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier"
|
|
endif
|
|
if (((data.long(ad:0x481CC000+0x100))&0x8000)==0x8000)
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
endif
|
|
if (((data.long(ad:0x481CC000+0x100))&0x8000)==0x8000)
|
|
rgroup.long 0x110++0x07
|
|
line.long 0x00 "DCAN_IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value"
|
|
line.long 0x04 "DCAN_IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value"
|
|
else
|
|
group.long 0x110++0x07
|
|
line.long 0x00 "DCAN_IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value"
|
|
line.long 0x04 "DCAN_IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value"
|
|
endif
|
|
if (((data.long(ad:0x481CC000+0x120))&0x800000)==0x800000)
|
|
group.long 0x120++0x03 "IF2 Registers"
|
|
line.long 0x00 "DCAN_IF2CMD,IF2 Command Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered"
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,?..."
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Handled,Set"
|
|
else
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Cleared,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered"
|
|
bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number"
|
|
else
|
|
group.long 0x120++0x03 "IF2 Registers"
|
|
line.long 0x00 "DCAN_IF2CMD,IF2 Command Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered"
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Unchanged,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered"
|
|
bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number"
|
|
endif
|
|
if ((((data.long(ad:0x481CC000+0x120))&0x8000)==0x8000)&&(((data.long(ad:0x481CC000+0x128))&0x40000000)==0x40000000))
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
bitfld.long 0x00 17. " ," "0,1"
|
|
bitfld.long 0x00 16. " ," "0,1"
|
|
bitfld.long 0x00 15. " ," "0,1"
|
|
bitfld.long 0x00 14. " ," "0,1"
|
|
bitfld.long 0x00 13. " ," "0,1"
|
|
bitfld.long 0x00 12. " ," "0,1"
|
|
bitfld.long 0x00 11. " ," "0,1"
|
|
bitfld.long 0x00 10. " ," "0,1"
|
|
bitfld.long 0x00 9. " ," "0,1"
|
|
bitfld.long 0x00 8. " ," "0,1"
|
|
bitfld.long 0x00 7. " ," "0,1"
|
|
bitfld.long 0x00 6. " ," "0,1"
|
|
bitfld.long 0x00 5. " ," "0,1"
|
|
bitfld.long 0x00 4. " ," "0,1"
|
|
bitfld.long 0x00 3. " ," "0,1"
|
|
bitfld.long 0x00 2. " ," "0,1"
|
|
bitfld.long 0x00 1. " ," "0,1"
|
|
bitfld.long 0x00 0. " ," "0,1"
|
|
elif ((((data.long(ad:0x481CC000+0x120))&0x8000)==0x0000)&&(((data.long(ad:0x481CC000+0x128))&0x40000000)==0x40000000))
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
bitfld.long 0x00 17. " ," "0,1"
|
|
bitfld.long 0x00 16. " ," "0,1"
|
|
bitfld.long 0x00 15. " ," "0,1"
|
|
bitfld.long 0x00 14. " ," "0,1"
|
|
bitfld.long 0x00 13. " ," "0,1"
|
|
bitfld.long 0x00 12. " ," "0,1"
|
|
bitfld.long 0x00 11. " ," "0,1"
|
|
bitfld.long 0x00 10. " ," "0,1"
|
|
bitfld.long 0x00 9. " ," "0,1"
|
|
bitfld.long 0x00 8. " ," "0,1"
|
|
bitfld.long 0x00 7. " ," "0,1"
|
|
bitfld.long 0x00 6. " ," "0,1"
|
|
bitfld.long 0x00 5. " ," "0,1"
|
|
bitfld.long 0x00 4. " ," "0,1"
|
|
bitfld.long 0x00 3. " ," "0,1"
|
|
bitfld.long 0x00 2. " ," "0,1"
|
|
bitfld.long 0x00 1. " ," "0,1"
|
|
bitfld.long 0x00 0. " ," "0,1"
|
|
elif ((((data.long(ad:0x481CC000+0x120))&0x8000)==0x8000)&&(((data.long(ad:0x481CC000+0x128))&0x40000000)==0x00))
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-18 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
else
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-18 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
endif
|
|
if ((((data.long(ad:0x481CC000+0x120))&0x8000)==0x8000)&&(((data.long(ad:0x481CC000+0x128))&0x40000000)==0x40000000))
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier"
|
|
elif ((((data.long(ad:0x481CC000+0x120))&0x8000)==0x0000)&&(((data.long(ad:0x481CC000+0x128))&0x40000000)==0x40000000))
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier"
|
|
elif ((((data.long(ad:0x481CC000+0x120))&0x8000)==0x0000)&&(((data.long(ad:0x481CC000+0x128))&0x40000000)==0x00000000))
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier"
|
|
else
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier"
|
|
endif
|
|
if (((data.long(ad:0x481CC000+0x120))&0x8000)==0x8000)
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
endif
|
|
if (((data.long(ad:0x481CC000+0x120))&0x8000)==0x8000)
|
|
rgroup.long 0x130++0x07
|
|
line.long 0x00 "DCAN_IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value"
|
|
line.long 0x04 "DCAN_IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value"
|
|
else
|
|
group.long 0x130++0x07
|
|
line.long 0x00 "DCAN_IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value"
|
|
line.long 0x04 "DCAN_IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value"
|
|
endif
|
|
group.long 0x140++0x03 "IF3 Registers"
|
|
line.long 0x00 "DCAN_IF3OBS,IF3 Observation Register"
|
|
bitfld.long 0x00 15. " IF3UPD ,IF3 Update Data" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B read access" "All read,Not all read"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A read access" "All read,Not all read"
|
|
bitfld.long 0x00 10. " IF3SC ,IF3 Status of control bits read access" "All read,Not all read"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration data read access" "All read,Not all read"
|
|
bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask data read access" "All read,Not all read"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATAB ,Data B read observation" "Not read,Read"
|
|
bitfld.long 0x00 3. " DATAA ,Data A read observation" "Not read,Read"
|
|
bitfld.long 0x00 2. " CTRL ,Ctrl read observation" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ARB ,Arbitration data read observation" "Not read,Read"
|
|
bitfld.long 0x00 0. " MASK ,Mask data read observation" "Not read,Read"
|
|
if (((data.long(ad:0x481CC000+0x148))&0x40000000)==0x40000000)
|
|
rgroup.long 0x144++0x3
|
|
line.long 0x00 "DCAN_IF3MSK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
bitfld.long 0x00 17. " ," "0,1"
|
|
bitfld.long 0x00 16. " ," "0,1"
|
|
bitfld.long 0x00 15. " ," "0,1"
|
|
bitfld.long 0x00 14. " ," "0,1"
|
|
bitfld.long 0x00 13. " ," "0,1"
|
|
bitfld.long 0x00 12. " ," "0,1"
|
|
bitfld.long 0x00 11. " ," "0,1"
|
|
bitfld.long 0x00 10. " ," "0,1"
|
|
bitfld.long 0x00 9. " ," "0,1"
|
|
bitfld.long 0x00 8. " ," "0,1"
|
|
bitfld.long 0x00 7. " ," "0,1"
|
|
bitfld.long 0x00 6. " ," "0,1"
|
|
bitfld.long 0x00 5. " ," "0,1"
|
|
bitfld.long 0x00 4. " ," "0,1"
|
|
bitfld.long 0x00 3. " ," "0,1"
|
|
bitfld.long 0x00 2. " ," "0,1"
|
|
bitfld.long 0x00 1. " ," "0,1"
|
|
bitfld.long 0x00 0. " ," "0,1"
|
|
else
|
|
rgroup.long 0x144++0x3
|
|
line.long 0x00 "DCAN_IF3MSK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MSK10-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 9. " ," "0,1"
|
|
bitfld.long 0x00 8. " ," "0,1"
|
|
bitfld.long 0x00 7. " ," "0,1"
|
|
bitfld.long 0x00 6. " ," "0,1"
|
|
bitfld.long 0x00 5. " ," "0,1"
|
|
bitfld.long 0x00 4. " ," "0,1"
|
|
bitfld.long 0x00 3. " ," "0,1"
|
|
bitfld.long 0x00 2. " ," "0,1"
|
|
bitfld.long 0x00 1. " ," "0,1"
|
|
bitfld.long 0x00 0. " ," "0,1"
|
|
endif
|
|
if (((data.long(ad:0x481CC000+0x148))&0x40000000)==0x40000000)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DCAN_IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier"
|
|
else
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DCAN_IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier"
|
|
endif
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "DCAN_IF3MCTL,IF3 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
rgroup.long 0x150++0x07
|
|
line.long 0x00 "DCAN_IF3DATA,IF3 Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value"
|
|
line.long 0x04 "DCAN_IF3DATB,IF3 Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value"
|
|
group.long 0x160--0x16F
|
|
line.long 0x00 "IF3UPD12,Update Enable 1_2 Register"
|
|
bitfld.long 0x00 31. " IF3UPDATEEN32 ,IF3 Update enabled 32" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IF3UPDATEEN31 ,IF3 Update enabled 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IF3UPDATEEN30 ,IF3 Update enabled 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IF3UPDATEEN29 ,IF3 Update enabled 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " IF3UPDATEEN28 ,IF3 Update enabled 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " IF3UPDATEEN27 ,IF3 Update enabled 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IF3UPDATEEN26 ,IF3 Update enabled 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " IF3UPDATEEN25 ,IF3 Update enabled 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " IF3UPDATEEN24 ,IF3 Update enabled 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IF3UPDATEEN23 ,IF3 Update enabled 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " IF3UPDATEEN22 ,IF3 Update enabled 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " IF3UPDATEEN21 ,IF3 Update enabled 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IF3UPDATEEN20 ,IF3 Update enabled 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " IF3UPDATEEN19 ,IF3 Update enabled 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " IF3UPDATEEN18 ,IF3 Update enabled 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IF3UPDATEEN17 ,IF3 Update enabled 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " IF3UPDATEEN16 ,IF3 Update enabled 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " IF3UPDATEEN15 ,IF3 Update enabled 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IF3UPDATEEN14 ,IF3 Update enabled 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IF3UPDATEEN13 ,IF3 Update enabled 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " IF3UPDATEEN12 ,IF3 Update enabled 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IF3UPDATEEN11 ,IF3 Update enabled 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " IF3UPDATEEN10 ,IF3 Update enabled 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IF3UPDATEEN9 ,IF3 Update enabled 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IF3UPDATEEN8 ,IF3 Update enabled 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IF3UPDATEEN7 ,IF3 Update enabled 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IF3UPDATEEN6 ,IF3 Update enabled 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IF3UPDATEEN5 ,IF3 Update enabled 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IF3UPDATEEN4 ,IF3 Update enabled 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IF3UPDATEEN3 ,IF3 Update enabled 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IF3UPDATEEN2 ,IF3 Update enabled 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IF3UPDATEEN1 ,IF3 Update enabled 1" "Disabled,Enabled"
|
|
line.long 0x04 "IF3UPD3_4,Update Enable 3_4 Register"
|
|
bitfld.long 0x04 31. " IF3UPDATEEN64 ,IF3 Update enabled 64" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " IF3UPDATEEN63 ,IF3 Update enabled 63" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " IF3UPDATEEN62 ,IF3 Update enabled 62" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " IF3UPDATEEN61 ,IF3 Update enabled 61" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " IF3UPDATEEN60 ,IF3 Update enabled 60" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " IF3UPDATEEN59 ,IF3 Update enabled 59" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " IF3UPDATEEN58 ,IF3 Update enabled 58" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " IF3UPDATEEN57 ,IF3 Update enabled 57" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " IF3UPDATEEN56 ,IF3 Update enabled 56" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " IF3UPDATEEN55 ,IF3 Update enabled 55" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " IF3UPDATEEN54 ,IF3 Update enabled 54" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " IF3UPDATEEN53 ,IF3 Update enabled 53" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " IF3UPDATEEN52 ,IF3 Update enabled 52" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " IF3UPDATEEN51 ,IF3 Update enabled 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " IF3UPDATEEN50 ,IF3 Update enabled 50" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " IF3UPDATEEN49 ,IF3 Update enabled 49" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " IF3UPDATEEN48 ,IF3 Update enabled 48" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " IF3UPDATEEN47 ,IF3 Update enabled 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " IF3UPDATEEN46 ,IF3 Update enabled 46" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " IF3UPDATEEN45 ,IF3 Update enabled 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " IF3UPDATEEN44 ,IF3 Update enabled 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " IF3UPDATEEN43 ,IF3 Update enabled 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " IF3UPDATEEN42 ,IF3 Update enabled 42" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " IF3UPDATEEN41 ,IF3 Update enabled 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " IF3UPDATEEN40 ,IF3 Update enabled 40" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " IF3UPDATEEN39 ,IF3 Update enabled 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " IF3UPDATEEN38 ,IF3 Update enabled 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " IF3UPDATEEN37 ,IF3 Update enabled 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IF3UPDATEEN36 ,IF3 Update enabled 36" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " IF3UPDATEEN35 ,IF3 Update enabled 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IF3UPDATEEN34 ,IF3 Update enabled 34" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " IF3UPDATEEN33 ,IF3 Update enabled 33" "Disabled,Enabled"
|
|
line.long 0x08 "IF3UPD5_6,Update Enable 5_6 Register"
|
|
bitfld.long 0x08 31. " IF3UPDATEEN96 ,IF3 Update enabled 96" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " IF3UPDATEEN95 ,IF3 Update enabled 95" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " IF3UPDATEEN94 ,IF3 Update enabled 94" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 28. " IF3UPDATEEN93 ,IF3 Update enabled 93" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " IF3UPDATEEN92 ,IF3 Update enabled 92" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " IF3UPDATEEN91 ,IF3 Update enabled 91" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IF3UPDATEEN90 ,IF3 Update enabled 90" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " IF3UPDATEEN89 ,IF3 Update enabled 89" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " IF3UPDATEEN88 ,IF3 Update enabled 88" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " IF3UPDATEEN87 ,IF3 Update enabled 87" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " IF3UPDATEEN86 ,IF3 Update enabled 86" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " IF3UPDATEEN85 ,IF3 Update enabled 85" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IF3UPDATEEN84 ,IF3 Update enabled 84" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " IF3UPDATEEN83 ,IF3 Update enabled 83" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " IF3UPDATEEN82 ,IF3 Update enabled 82" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " IF3UPDATEEN81 ,IF3 Update enabled 81" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " IF3UPDATEEN80 ,IF3 Update enabled 80" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " IF3UPDATEEN79 ,IF3 Update enabled 79" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IF3UPDATEEN78 ,IF3 Update enabled 78" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " IF3UPDATEEN77 ,IF3 Update enabled 77" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " IF3UPDATEEN76 ,IF3 Update enabled 76" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " IF3UPDATEEN75 ,IF3 Update enabled 75" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " IF3UPDATEEN74 ,IF3 Update enabled 74" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " IF3UPDATEEN73 ,IF3 Update enabled 73" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IF3UPDATEEN72 ,IF3 Update enabled 72" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " IF3UPDATEEN71 ,IF3 Update enabled 71" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " IF3UPDATEEN70 ,IF3 Update enabled 70" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " IF3UPDATEEN69 ,IF3 Update enabled 69" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " IF3UPDATEEN68 ,IF3 Update enabled 68" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " IF3UPDATEEN67 ,IF3 Update enabled 67" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IF3UPDATEEN66 ,IF3 Update enabled 66" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IF3UPDATEEN65 ,IF3 Update enabled 65" "Disabled,Enabled"
|
|
line.long 0x0C "IF3UPD7_8,Update Enable 7_8 Register"
|
|
bitfld.long 0x0C 31. " IF3UPDATEEN128 ,IF3 Update enabled 128" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " IF3UPDATEEN127 ,IF3 Update enabled 127" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " IF3UPDATEEN126 ,IF3 Update enabled 126" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " IF3UPDATEEN125 ,IF3 Update enabled 125" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " IF3UPDATEEN124 ,IF3 Update enabled 124" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " IF3UPDATEEN123 ,IF3 Update enabled 123" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " IF3UPDATEEN122 ,IF3 Update enabled 122" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " IF3UPDATEEN121 ,IF3 Update enabled 121" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " IF3UPDATEEN120 ,IF3 Update enabled 120" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " IF3UPDATEEN119 ,IF3 Update enabled 119" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " IF3UPDATEEN118 ,IF3 Update enabled 118" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " IF3UPDATEEN117 ,IF3 Update enabled 117" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " IF3UPDATEEN116 ,IF3 Update enabled 116" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " IF3UPDATEEN115 ,IF3 Update enabled 115" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " IF3UPDATEEN114 ,IF3 Update enabled 114" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " IF3UPDATEEN113 ,IF3 Update enabled 113" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " IF3UPDATEEN112 ,IF3 Update enabled 112" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " IF3UPDATEEN111 ,IF3 Update enabled 111" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " IF3UPDATEEN110 ,IF3 Update enabled 110" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " IF3UPDATEEN109 ,IF3 Update enabled 109" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " IF3UPDATEEN108 ,IF3 Update enabled 108" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " IF3UPDATEEN107 ,IF3 Update enabled 107" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " IF3UPDATEEN106 ,IF3 Update enabled 106" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " IF3UPDATEEN105 ,IF3 Update enabled 105" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " IF3UPDATEEN104 ,IF3 Update enabled 104" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " IF3UPDATEEN103 ,IF3 Update enabled 103" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " IF3UPDATEEN102 ,IF3 Update enabled 102" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " IF3UPDATEEN101 ,IF3 Update enabled 101" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " IF3UPDATEEN100 ,IF3 Update enabled 100" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " IF3UPDATEEN99 ,IF3 Update enabled 99" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " IF3UPDATEEN98 ,IF3 Update enabled 98" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " IF3UPDATEEN97 ,IF3 Update enabled 97" "Disabled,Enabled"
|
|
width 12.
|
|
if (((d.l(ad:0x481CC000))&0x1)==0x1)
|
|
// DCAN_CTL.Init == 1
|
|
group.long 0x1E0++0x07
|
|
line.long 0x00 "DCAN_TIOC,TX IO Control Register"
|
|
bitfld.long 0x00 18. " PU ,Selection of pull direction" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 17. " PD ,Pull functionality disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " OD ,Open drain mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of pin" "GPIO,CAN"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,I/O"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of pin" "Low,High"
|
|
line.long 0x04 "DCAN_RIOC,RX IO Control Register"
|
|
bitfld.long 0x04 18. " PU ,Selection of pull direction" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 17. " PD ,Pull functionality disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " OD ,Open drain mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " FUNC ,Functionality of pin" "GPIO,CAN"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,Output"
|
|
else
|
|
bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,I/O"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High"
|
|
bitfld.long 0x04 0. " IN ,Value of pin" "Low,High"
|
|
else
|
|
rgroup.long 0x1E0++0x07
|
|
line.long 0x00 "DCAN_TIOC,TX IO Control Register"
|
|
bitfld.long 0x00 18. " PU ,Selection of pull direction" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 17. " PD ,Pull functionality disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " OD ,Open drain mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of pin" "GPIO,CAN"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,I/O"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of pin" "Low,High"
|
|
line.long 0x04 "DCAN_RIOC,RX IO Control Register"
|
|
bitfld.long 0x04 18. " PU ,Selection of pull direction" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 17. " PD ,Pull functionality disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " OD ,Open drain mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " FUNC ,Functionality of pin" "GPIO,CAN"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,Output"
|
|
else
|
|
bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,I/O"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High"
|
|
bitfld.long 0x04 0. " IN ,Value of pin" "Low,High"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "DCAN1"
|
|
base ad:0x481D0000
|
|
width 23.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DCAN_CTL,CAN Control Register"
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x00 25. " WUBA ,Automatic wake up on bus activity" "No wake up,Wake up"
|
|
bitfld.long 0x00 24. " PDR ,Request for local low power-down mode" "Not requested,Requested"
|
|
else
|
|
bitfld.long 0x00 26. " WUBA ,Automatic wake up on bus activity" "No wake up,Wake up"
|
|
bitfld.long 0x00 24. " PDR ,Request for local low power-down mode" "Not requested,Requested"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " DE3 ,DMA enable for IF3" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DE2 ,DMA enable for IF2" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DE1 ,DMA enable for IF1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INITDBG ,Internal init state while debug access" "Not entered,Entered"
|
|
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE0 ,DCAN0INT Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "DCAN_ES/PARITYERR_EOI,Error and Status/Parity Error EOI Register"
|
|
in
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "DCAN_ERRC,Error Counter Register"
|
|
bitfld.long 0x00 15. " RP ,Receive Error Passive" "No error,Error"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC6-0 ,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC7-0 ,Transmit Error Counter"
|
|
if (((data.long(ad:0x481D0000))&0x41)==0x41)
|
|
group.long 0x0c++0x03
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
line.long 0x00 "DCAN_BTR,Bit Timing Register"
|
|
else
|
|
line.long 0x00 "DCAN_BTBRP,Bit Timing_BRP Extension Register"
|
|
endif
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The time segment after the sample point" "0,1,2,3,4,5,6,7"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x0c++0x03
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
line.long 0x00 "DCAN_BTR,Bit Timing Register"
|
|
else
|
|
line.long 0x00 "DCAN_BTBRP,Bit Timing_BRP Extension Register"
|
|
endif
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The time segment after the sample point" "0,1,2,3,4,5,6,7"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "Reerved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "DCAN_INTR,Interrupt Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT1ID7-0 ,Interrupt 1 Identifier"
|
|
hexmask.long.word 0x00 0.--15. 1. " INT0ID15-0 ,Interrupt Identifier"
|
|
if (((data.long(ad:0x481D0000))&0x80)==0x80)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DCAN_TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Direct access"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Monitored,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "DCAN_TEST,Test Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Direct access"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Monitored,Dominant,Recessive"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Test"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,External"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Monitored,0,1"
|
|
endif
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DCAN_PERR,Parity Error Code Register"
|
|
bitfld.long 0x00 8.--10. " WN ,Word Number" "Reserved,1,2,3,4,5,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "DCAN_ABOTR,Auto Bus On Time Register"
|
|
rgroup.long 0x84--0xD3
|
|
line.long 0x00 "DCAN_TXRQX,Transmission Request X Register"
|
|
bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request X 8" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request X 7" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request X 6" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request X 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request X 4" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request X 3" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request X 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request X 1" "0,1,2,3"
|
|
line.long 0x04 "DCAN_TXRQ12,Transmission Request 1_2 Register"
|
|
bitfld.long 0x04 31. " TXRQST32 ,Transmission Request Bit 32" "Not requested,Requested"
|
|
bitfld.long 0x04 30. " TXRQST31 ,Transmission Request Bit 31" "Not requested,Requested"
|
|
bitfld.long 0x04 29. " TXRQST30 ,Transmission Request Bit 30" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 28. " TXRQST29 ,Transmission Request Bit 29" "Not requested,Requested"
|
|
bitfld.long 0x04 27. " TXRQST28 ,Transmission Request Bit 28" "Not requested,Requested"
|
|
bitfld.long 0x04 26. " TXRQST27 ,Transmission Request Bit 27" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 25. " TXRQST26 ,Transmission Request Bit 26" "Not requested,Requested"
|
|
bitfld.long 0x04 24. " TXRQST25 ,Transmission Request Bit 25" "Not requested,Requested"
|
|
bitfld.long 0x04 23. " TXRQST24 ,Transmission Request Bit 24" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 22. " TXRQST23 ,Transmission Request Bit 23" "Not requested,Requested"
|
|
bitfld.long 0x04 21. " TXRQST22 ,Transmission Request Bit 22" "Not requested,Requested"
|
|
bitfld.long 0x04 20. " TXRQST21 ,Transmission Request Bit 21" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 19. " TXRQST20 ,Transmission Request Bit 20" "Not requested,Requested"
|
|
bitfld.long 0x04 18. " TXRQST19 ,Transmission Request Bit 19" "Not requested,Requested"
|
|
bitfld.long 0x04 17. " TXRQST18 ,Transmission Request Bit 18" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 16. " TXRQST17 ,Transmission Request Bit 17" "Not requested,Requested"
|
|
bitfld.long 0x04 15. " TXRQST16 ,Transmission Request Bit 16" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " TXRQST15 ,Transmission Request Bit 15" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TXRQST14 ,Transmission Request Bit 14" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " TXRQST13 ,Transmission Request Bit 13" "Not requested,Requested"
|
|
bitfld.long 0x04 11. " TXRQST12 ,Transmission Request Bit 12" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TXRQST11 ,Transmission Request Bit 11" "Not requested,Requested"
|
|
bitfld.long 0x04 9. " TXRQST10 ,Transmission Request Bit 10" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " TXRQST9 ,Transmission Request Bit 9" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 7. " TXRQST8 ,Transmission Request Bit 8" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " TXRQST7 ,Transmission Request Bit 7" "Not requested,Requested"
|
|
bitfld.long 0x04 5. " TXRQST6 ,Transmission Request Bit 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 4. " TXRQST5 ,Transmission Request Bit 5" "Not requested,Requested"
|
|
bitfld.long 0x04 3. " TXRQST4 ,Transmission Request Bit 4" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " TXRQST3 ,Transmission Request Bit 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TXRQST2 ,Transmission Request Bit 2" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " TXRQST1 ,Transmission Request Bit 1" "Not requested,Requested"
|
|
line.long 0x08 "DCAN_TXRQ34,Transmission Request 3_4 Register"
|
|
bitfld.long 0x08 31. " TXRQST64 ,Transmission Request Bit 64" "Not requested,Requested"
|
|
bitfld.long 0x08 30. " TXRQST63 ,Transmission Request Bit 63" "Not requested,Requested"
|
|
bitfld.long 0x08 29. " TXRQST62 ,Transmission Request Bit 62" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 28. " TXRQST61 ,Transmission Request Bit 61" "Not requested,Requested"
|
|
bitfld.long 0x08 27. " TXRQST60 ,Transmission Request Bit 60" "Not requested,Requested"
|
|
bitfld.long 0x08 26. " TXRQST59 ,Transmission Request Bit 59" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 25. " TXRQST58 ,Transmission Request Bit 58" "Not requested,Requested"
|
|
bitfld.long 0x08 24. " TXRQST57 ,Transmission Request Bit 57" "Not requested,Requested"
|
|
bitfld.long 0x08 23. " TXRQST56 ,Transmission Request Bit 56" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 22. " TXRQST55 ,Transmission Request Bit 55" "Not requested,Requested"
|
|
bitfld.long 0x08 21. " TXRQST54 ,Transmission Request Bit 54" "Not requested,Requested"
|
|
bitfld.long 0x08 20. " TXRQST53 ,Transmission Request Bit 53" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 19. " TXRQST52 ,Transmission Request Bit 52" "Not requested,Requested"
|
|
bitfld.long 0x08 18. " TXRQST51 ,Transmission Request Bit 51" "Not requested,Requested"
|
|
bitfld.long 0x08 17. " TXRQST50 ,Transmission Request Bit 50" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 16. " TXRQST49 ,Transmission Request Bit 49" "Not requested,Requested"
|
|
bitfld.long 0x08 15. " TXRQST48 ,Transmission Request Bit 48" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " TXRQST47 ,Transmission Request Bit 47" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 13. " TXRQST46 ,Transmission Request Bit 46" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " TXRQST45 ,Transmission Request Bit 45" "Not requested,Requested"
|
|
bitfld.long 0x08 11. " TXRQST44 ,Transmission Request Bit 44" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 10. " TXRQST43 ,Transmission Request Bit 43" "Not requested,Requested"
|
|
bitfld.long 0x08 9. " TXRQST42 ,Transmission Request Bit 42" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " TXRQST41 ,Transmission Request Bit 41" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 7. " TXRQST40 ,Transmission Request Bit 40" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " TXRQST39 ,Transmission Request Bit 39" "Not requested,Requested"
|
|
bitfld.long 0x08 5. " TXRQST38 ,Transmission Request Bit 38" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TXRQST37 ,Transmission Request Bit 37" "Not requested,Requested"
|
|
bitfld.long 0x08 3. " TXRQST36 ,Transmission Request Bit 36" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " TXRQST35 ,Transmission Request Bit 35" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXRQST34 ,Transmission Request Bit 34" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " TXRQST33 ,Transmission Request Bit 33" "Not requested,Requested"
|
|
line.long 0x0c "DCAN_TXRQ56,Transmission Request 5_6 Register"
|
|
bitfld.long 0x0c 31. " TXRQST96 ,Transmission Request Bit 96" "Not requested,Requested"
|
|
bitfld.long 0x0c 30. " TXRQST95 ,Transmission Request Bit 95" "Not requested,Requested"
|
|
bitfld.long 0x0c 29. " TXRQST94 ,Transmission Request Bit 94" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " TXRQST93 ,Transmission Request Bit 93" "Not requested,Requested"
|
|
bitfld.long 0x0c 27. " TXRQST92 ,Transmission Request Bit 92" "Not requested,Requested"
|
|
bitfld.long 0x0c 26. " TXRQST91 ,Transmission Request Bit 91" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " TXRQST90 ,Transmission Request Bit 90" "Not requested,Requested"
|
|
bitfld.long 0x0c 24. " TXRQST89 ,Transmission Request Bit 89" "Not requested,Requested"
|
|
bitfld.long 0x0c 23. " TXRQST88 ,Transmission Request Bit 88" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " TXRQST87 ,Transmission Request Bit 87" "Not requested,Requested"
|
|
bitfld.long 0x0c 21. " TXRQST86 ,Transmission Request Bit 86" "Not requested,Requested"
|
|
bitfld.long 0x0c 20. " TXRQST85 ,Transmission Request Bit 85" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " TXRQST84 ,Transmission Request Bit 84" "Not requested,Requested"
|
|
bitfld.long 0x0c 18. " TXRQST83 ,Transmission Request Bit 83" "Not requested,Requested"
|
|
bitfld.long 0x0c 17. " TXRQST82 ,Transmission Request Bit 82" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " TXRQST81 ,Transmission Request Bit 81" "Not requested,Requested"
|
|
bitfld.long 0x0c 15. " TXRQST80 ,Transmission Request Bit 80" "Not requested,Requested"
|
|
bitfld.long 0x0c 14. " TXRQST79 ,Transmission Request Bit 79" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " TXRQST78 ,Transmission Request Bit 78" "Not requested,Requested"
|
|
bitfld.long 0x0c 12. " TXRQST77 ,Transmission Request Bit 77" "Not requested,Requested"
|
|
bitfld.long 0x0c 11. " TXRQST76 ,Transmission Request Bit 76" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " TXRQST75 ,Transmission Request Bit 75" "Not requested,Requested"
|
|
bitfld.long 0x0c 9. " TXRQST74 ,Transmission Request Bit 74" "Not requested,Requested"
|
|
bitfld.long 0x0c 8. " TXRQST73 ,Transmission Request Bit 73" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " TXRQST72 ,Transmission Request Bit 72" "Not requested,Requested"
|
|
bitfld.long 0x0c 6. " TXRQST71 ,Transmission Request Bit 71" "Not requested,Requested"
|
|
bitfld.long 0x0c 5. " TXRQST70 ,Transmission Request Bit 70" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " TXRQST69 ,Transmission Request Bit 69" "Not requested,Requested"
|
|
bitfld.long 0x0c 3. " TXRQST68 ,Transmission Request Bit 68" "Not requested,Requested"
|
|
bitfld.long 0x0c 2. " TXRQST67 ,Transmission Request Bit 67" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " TXRQST66 ,Transmission Request Bit 66" "Not requested,Requested"
|
|
bitfld.long 0x0c 0. " TXRQST65 ,Transmission Request Bit 65" "Not requested,Requested"
|
|
line.long 0x10 "DCAN_TXRQ78,Transmission Request 7_8 Register"
|
|
bitfld.long 0x10 31. " TXRQST128 ,Transmission Request Bit 128" "Not requested,Requested"
|
|
bitfld.long 0x10 30. " TXRQST127 ,Transmission Request Bit 127" "Not requested,Requested"
|
|
bitfld.long 0x10 29. " TXRQST126 ,Transmission Request Bit 126" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 28. " TXRQST125 ,Transmission Request Bit 125" "Not requested,Requested"
|
|
bitfld.long 0x10 27. " TXRQST124 ,Transmission Request Bit 124" "Not requested,Requested"
|
|
bitfld.long 0x10 26. " TXRQST123 ,Transmission Request Bit 123" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 25. " TXRQST122 ,Transmission Request Bit 122" "Not requested,Requested"
|
|
bitfld.long 0x10 24. " TXRQST121 ,Transmission Request Bit 121" "Not requested,Requested"
|
|
bitfld.long 0x10 23. " TXRQST120 ,Transmission Request Bit 120" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 22. " TXRQST119 ,Transmission Request Bit 119" "Not requested,Requested"
|
|
bitfld.long 0x10 21. " TXRQST118 ,Transmission Request Bit 118" "Not requested,Requested"
|
|
bitfld.long 0x10 20. " TXRQST117 ,Transmission Request Bit 117" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 19. " TXRQST116 ,Transmission Request Bit 116" "Not requested,Requested"
|
|
bitfld.long 0x10 18. " TXRQST115 ,Transmission Request Bit 115" "Not requested,Requested"
|
|
bitfld.long 0x10 17. " TXRQST114 ,Transmission Request Bit 114" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 16. " TXRQST113 ,Transmission Request Bit 113" "Not requested,Requested"
|
|
bitfld.long 0x10 15. " TXRQST112 ,Transmission Request Bit 112" "Not requested,Requested"
|
|
bitfld.long 0x10 14. " TXRQST111 ,Transmission Request Bit 111" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 13. " TXRQST110 ,Transmission Request Bit 110" "Not requested,Requested"
|
|
bitfld.long 0x10 12. " TXRQST109 ,Transmission Request Bit 109" "Not requested,Requested"
|
|
bitfld.long 0x10 11. " TXRQST108 ,Transmission Request Bit 108" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 10. " TXRQST107 ,Transmission Request Bit 107" "Not requested,Requested"
|
|
bitfld.long 0x10 9. " TXRQST106 ,Transmission Request Bit 106" "Not requested,Requested"
|
|
bitfld.long 0x10 8. " TXRQST105 ,Transmission Request Bit 105" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TXRQST104 ,Transmission Request Bit 104" "Not requested,Requested"
|
|
bitfld.long 0x10 6. " TXRQST103 ,Transmission Request Bit 103" "Not requested,Requested"
|
|
bitfld.long 0x10 5. " TXRQST102 ,Transmission Request Bit 102" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 4. " TXRQST101 ,Transmission Request Bit 101" "Not requested,Requested"
|
|
bitfld.long 0x10 3. " TXRQST100 ,Transmission Request Bit 100" "Not requested,Requested"
|
|
bitfld.long 0x10 2. " TXRQST99 ,Transmission Request Bit 99" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TXRQST98 ,Transmission Request Bit 98" "Not requested,Requested"
|
|
bitfld.long 0x10 0. " TXRQST97 ,Transmission Request Bit 97" "Not requested,Requested"
|
|
line.long 0x14 "DCAN_NWDAT_X,New Data X Register"
|
|
bitfld.long 0x14 14.--15. " NEWDATREG8 ,New Data X 8" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. " NEWDATREG7 ,New Data X 7" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. " NEWDATREG6 ,New Data X 6" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x14 8.--9. " NEWDATREG5 ,New Data X 5" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " NEWDATREG4 ,New Data X 4" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. " NEWDATREG3 ,New Data X 3" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x14 2.--3. " NEWDATREG2 ,New Data X 2" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. " NEWDATREG1 ,New Data X 1" "0,1,2,3"
|
|
line.long 0x18 "DCAN_NWDAT12,New Data 1_2 Register"
|
|
bitfld.long 0x18 31. " NEWDAT32 ,New Data Bit 32" "Not written,Written"
|
|
bitfld.long 0x18 30. " NEWDAT31 ,New Data Bit 31" "Not written,Written"
|
|
bitfld.long 0x18 29. " NEWDAT30 ,New Data Bit 30" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 28. " NEWDAT29 ,New Data Bit 29" "Not written,Written"
|
|
bitfld.long 0x18 27. " NEWDAT28 ,New Data Bit 28" "Not written,Written"
|
|
bitfld.long 0x18 26. " NEWDAT27 ,New Data Bit 27" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 25. " NEWDAT26 ,New Data Bit 26" "Not written,Written"
|
|
bitfld.long 0x18 24. " NEWDAT25 ,New Data Bit 25" "Not written,Written"
|
|
bitfld.long 0x18 23. " NEWDAT24 ,New Data Bit 24" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 22. " NEWDAT23 ,New Data Bit 23" "Not written,Written"
|
|
bitfld.long 0x18 21. " NEWDAT22 ,New Data Bit 22" "Not written,Written"
|
|
bitfld.long 0x18 20. " NEWDAT21 ,New Data Bit 21" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 19. " NEWDAT20 ,New Data Bit 20" "Not written,Written"
|
|
bitfld.long 0x18 18. " NEWDAT19 ,New Data Bit 19" "Not written,Written"
|
|
bitfld.long 0x18 17. " NEWDAT18 ,New Data Bit 18" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 16. " NEWDAT17 ,New Data Bit 17" "Not written,Written"
|
|
bitfld.long 0x18 15. " NEWDAT16 ,New Data Bit 16" "Not written,Written"
|
|
bitfld.long 0x18 14. " NEWDAT15 ,New Data Bit 15" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 13. " NEWDAT14 ,New Data Bit 14" "Not written,Written"
|
|
bitfld.long 0x18 12. " NEWDAT13 ,New Data Bit 13" "Not written,Written"
|
|
bitfld.long 0x18 11. " NewDat12 ,New Data Bit 12" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 10. " NEWDAT11 ,New Data Bit 11" "Not written,Written"
|
|
bitfld.long 0x18 9. " NEWDAT10 ,New Data Bit 10" "Not written,Written"
|
|
bitfld.long 0x18 8. " NEWDAT9 ,New Data Bit 9" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 7. " NEWDAT8 ,New Data Bit 8" "Not written,Written"
|
|
bitfld.long 0x18 6. " NEWDAT7 ,New Data Bit 7" "Not written,Written"
|
|
bitfld.long 0x18 5. " NEWDAT6 ,New Data Bit 6" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 4. " NEWDAT5 ,New Data Bit 5" "Not written,Written"
|
|
bitfld.long 0x18 3. " NEWDAT4 ,New Data Bit 4" "Not written,Written"
|
|
bitfld.long 0x18 2. " NEWDAT3 ,New Data Bit 3" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x18 1. " NEWDAT2 ,New Data Bit 2" "Not written,Written"
|
|
bitfld.long 0x18 0. " NEWDAT1 ,New Data Bit 1" "Not written,Written"
|
|
line.long 0x1c "DCAN_NWDAT34,New Data 3_4 Register"
|
|
bitfld.long 0x1c 31. " NEWDAT64 ,New Data Bit 64" "Not written,Written"
|
|
bitfld.long 0x1c 30. " NEWDAT63 ,New Data Bit 63" "Not written,Written"
|
|
bitfld.long 0x1c 29. " NEWDAT62 ,New Data Bit 62" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 28. " NEWDAT61 ,New Data Bit 61" "Not written,Written"
|
|
bitfld.long 0x1c 27. " NEWDAT60 ,New Data Bit 60" "Not written,Written"
|
|
bitfld.long 0x1c 26. " NEWDAT59 ,New Data Bit 59" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 25. " NEWDAT58 ,New Data Bit 58" "Not written,Written"
|
|
bitfld.long 0x1c 24. " NEWDAT57 ,New Data Bit 57" "Not written,Written"
|
|
bitfld.long 0x1c 23. " NEWDAT56 ,New Data Bit 56" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 22. " NEWDAT55 ,New Data Bit 55" "Not written,Written"
|
|
bitfld.long 0x1c 21. " NEWDAT54 ,New Data Bit 54" "Not written,Written"
|
|
bitfld.long 0x1c 20. " NEWDAT53 ,New Data Bit 53" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 19. " NEWDAT52 ,New Data Bit 52" "Not written,Written"
|
|
bitfld.long 0x1c 18. " NEWDAT51 ,New Data Bit 51" "Not written,Written"
|
|
bitfld.long 0x1c 17. " NEWDAT50 ,New Data Bit 50" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 16. " NEWDAT49 ,New Data Bit 49" "Not written,Written"
|
|
bitfld.long 0x1c 15. " NEWDAT48 ,New Data Bit 48" "Not written,Written"
|
|
bitfld.long 0x1c 14. " NEWDAT47 ,New Data Bit 47" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 13. " NEWDAT46 ,New Data Bit 46" "Not written,Written"
|
|
bitfld.long 0x1c 12. " NEWDAT45 ,New Data Bit 45" "Not written,Written"
|
|
bitfld.long 0x1c 11. " NEWDAT44 ,New Data Bit 44" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 10. " NEWDAT43 ,New Data Bit 43" "Not written,Written"
|
|
bitfld.long 0x1c 9. " NEWDAT42 ,New Data Bit 42" "Not written,Written"
|
|
bitfld.long 0x1c 8. " NEWDAT41 ,New Data Bit 41" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 7. " NEWDAT40 ,New Data Bit 40" "Not written,Written"
|
|
bitfld.long 0x1c 6. " NEWDAT39 ,New Data Bit 39" "Not written,Written"
|
|
bitfld.long 0x1c 5. " NEWDAT38 ,New Data Bit 38" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 4. " NEWDAT37 ,New Data Bit 37" "Not written,Written"
|
|
bitfld.long 0x1c 3. " NEWDAT36 ,New Data Bit 36" "Not written,Written"
|
|
bitfld.long 0x1c 2. " NEWDAT35 ,New Data Bit 35" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x1c 1. " NEWDAT34 ,New Data Bit 34" "Not written,Written"
|
|
bitfld.long 0x1c 0. " NEWDAT33 ,New Data Bit 33" "Not written,Written"
|
|
line.long 0x20 "DCAN_NWDAT56,New Data 5_6 Register"
|
|
bitfld.long 0x20 31. " NEWDAT96 ,New Data Bit 96" "Not written,Written"
|
|
bitfld.long 0x20 30. " NEWDAT95 ,New Data Bit 95" "Not written,Written"
|
|
bitfld.long 0x20 29. " NEWDAT94 ,New Data Bit 94" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 28. " NEWDAT93 ,New Data Bit 93" "Not written,Written"
|
|
bitfld.long 0x20 27. " NEWDAT92 ,New Data Bit 92" "Not written,Written"
|
|
bitfld.long 0x20 26. " NEWDAT91 ,New Data Bit 91" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 25. " NEWDAT90 ,New Data Bit 90" "Not written,Written"
|
|
bitfld.long 0x20 24. " NEWDAT89 ,New Data Bit 89" "Not written,Written"
|
|
bitfld.long 0x20 23. " NEWDAT88 ,New Data Bit 88" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 22. " NEWDAT87 ,New Data Bit 87" "Not written,Written"
|
|
bitfld.long 0x20 21. " NEWDAT86 ,New Data Bit 86" "Not written,Written"
|
|
bitfld.long 0x20 20. " NEWDAT85 ,New Data Bit 85" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 19. " NEWDAT84 ,New Data Bit 84" "Not written,Written"
|
|
bitfld.long 0x20 18. " NEWDAT83 ,New Data Bit 83" "Not written,Written"
|
|
bitfld.long 0x20 17. " NEWDAT82 ,New Data Bit 82" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 16. " NEWDAT81 ,New Data Bit 81" "Not written,Written"
|
|
bitfld.long 0x20 15. " NEWDAT80 ,New Data Bit 80" "Not written,Written"
|
|
bitfld.long 0x20 14. " NEWDAT79 ,New Data Bit 79" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 13. " NEWDAT78 ,New Data Bit 78" "Not written,Written"
|
|
bitfld.long 0x20 12. " NEWDAT77 ,New Data Bit 77" "Not written,Written"
|
|
bitfld.long 0x20 11. " NEWDAT76 ,New Data Bit 76" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 10. " NEWDAT75 ,New Data Bit 75" "Not written,Written"
|
|
bitfld.long 0x20 9. " NEWDAT74 ,New Data Bit 74" "Not written,Written"
|
|
bitfld.long 0x20 8. " NEWDAT73 ,New Data Bit 73" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 7. " NEWDAT72 ,New Data Bit 72" "Not written,Written"
|
|
bitfld.long 0x20 6. " NEWDAT71 ,New Data Bit 71" "Not written,Written"
|
|
bitfld.long 0x20 5. " NEWDAT70 ,New Data Bit 70" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 4. " NEWDAT69 ,New Data Bit 69" "Not written,Written"
|
|
bitfld.long 0x20 3. " NEWDAT68 ,New Data Bit 68" "Not written,Written"
|
|
bitfld.long 0x20 2. " NEWDAT67 ,New Data Bit 67" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x20 1. " NEWDAT66 ,New Data Bit 66" "Not written,Written"
|
|
bitfld.long 0x20 0. " NEWDAT65 ,New Data Bit 65" "Not written,Written"
|
|
line.long 0x24 "DCAN_NWDAT78,New Data 7_8 Register"
|
|
bitfld.long 0x24 31. " NEWDAT128 ,New Data Bit 128" "Not written,Written"
|
|
bitfld.long 0x24 30. " NEWDAT127 ,New Data Bit 127" "Not written,Written"
|
|
bitfld.long 0x24 29. " NEWDAT126 ,New Data Bit 126" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 28. " NEWDAT125 ,New Data Bit 125" "Not written,Written"
|
|
bitfld.long 0x24 27. " NEWDAT124 ,New Data Bit 124" "Not written,Written"
|
|
bitfld.long 0x24 26. " NEWDAT123 ,New Data Bit 123" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 25. " NEWDAT122 ,New Data Bit 122" "Not written,Written"
|
|
bitfld.long 0x24 24. " NEWDAT121 ,New Data Bit 121" "Not written,Written"
|
|
bitfld.long 0x24 23. " NEWDAT120 ,New Data Bit 120" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 22. " NEWDAT119 ,New Data Bit 119" "Not written,Written"
|
|
bitfld.long 0x24 21. " NEWDAT118 ,New Data Bit 118" "Not written,Written"
|
|
bitfld.long 0x24 20. " NEWDAT117 ,New Data Bit 117" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 19. " NEWDAT116 ,New Data Bit 116" "Not written,Written"
|
|
bitfld.long 0x24 18. " NEWDAT115 ,New Data Bit 115" "Not written,Written"
|
|
bitfld.long 0x24 17. " NEWDAT114 ,New Data Bit 114" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 16. " NEWDAT113 ,New Data Bit 113" "Not written,Written"
|
|
bitfld.long 0x24 15. " NEWDAT112 ,New Data Bit 112" "Not written,Written"
|
|
bitfld.long 0x24 14. " NEWDAT111 ,New Data Bit 111" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 13. " NEWDAT110 ,New Data Bit 110" "Not written,Written"
|
|
bitfld.long 0x24 12. " NEWDAT109 ,New Data Bit 109" "Not written,Written"
|
|
bitfld.long 0x24 11. " NEWDAT108 ,New Data Bit 108" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 10. " NEWDAT107 ,New Data Bit 107" "Not written,Written"
|
|
bitfld.long 0x24 9. " NEWDAT106 ,New Data Bit 106" "Not written,Written"
|
|
bitfld.long 0x24 8. " NEWDAT105 ,New Data Bit 105" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 7. " NEWDAT104 ,New Data Bit 104" "Not written,Written"
|
|
bitfld.long 0x24 6. " NEWDAT103 ,New Data Bit 103" "Not written,Written"
|
|
bitfld.long 0x24 5. " NEWDAT102 ,New Data Bit 102" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 4. " NEWDAT101 ,New Data Bit 101" "Not written,Written"
|
|
bitfld.long 0x24 3. " NEWDAT100 ,New Data Bit 100" "Not written,Written"
|
|
bitfld.long 0x24 2. " NEWDAT99 ,New Data Bit 99" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x24 1. " NEWDAT98 ,New Data Bit 98" "Not written,Written"
|
|
bitfld.long 0x24 0. " NEWDAT97 ,New Data Bit 97" "Not written,Written"
|
|
line.long 0x28 "DCAN_INTPND_X,Interrupt Pending X Register"
|
|
bitfld.long 0x28 14.--15. " INTPNDREG8 ,Interrupt Pending X Register 8" "0,1,2,3"
|
|
bitfld.long 0x28 12.--13. " INTPNDREG7 ,Interrupt Pending X Register 7" "0,1,2,3"
|
|
bitfld.long 0x28 10.--11. " INTPNDREG6 ,Interrupt Pending X Register 6" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x28 8.--9. " INTPNDREG5 ,Interrupt Pending X Register 5" "0,1,2,3"
|
|
bitfld.long 0x28 6.--7. " INTPNDREG4 ,Interrupt Pending X Register 4" "0,1,2,3"
|
|
bitfld.long 0x28 4.--5. " INTPNDREG3 ,Interrupt Pending X Register 3" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x28 2.--3. " INTPNDREG2 ,Interrupt Pending X Register 2" "0,1,2,3"
|
|
bitfld.long 0x28 0.--1. " INTPNDREG1 ,Interrupt Pending X Register 1" "0,1,2,3"
|
|
line.long 0x2C "DCAN_INTPND12,Interrupt Pending 1_2 Register"
|
|
bitfld.long 0x2c 31. " INTPND32 ,Interrupt Pending Bit 32" "Not pending,Pending"
|
|
bitfld.long 0x2c 30. " INTPND31 ,Interrupt Pending Bit 31" "Not pending,Pending"
|
|
bitfld.long 0x2c 29. " INTPND30 ,Interrupt Pending Bit 30" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 28. " INTPND29 ,Interrupt Pending Bit 29" "Not pending,Pending"
|
|
bitfld.long 0x2c 27. " INTPND28 ,Interrupt Pending Bit 28" "Not pending,Pending"
|
|
bitfld.long 0x2c 26. " INTPND27 ,Interrupt Pending Bit 27" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 25. " INTPND26 ,Interrupt Pending Bit 26" "Not pending,Pending"
|
|
bitfld.long 0x2c 24. " INTPND25 ,Interrupt Pending Bit 25" "Not pending,Pending"
|
|
bitfld.long 0x2c 23. " INTPND24 ,Interrupt Pending Bit 24" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 22. " INTPND23 ,Interrupt Pending Bit 23" "Not pending,Pending"
|
|
bitfld.long 0x2c 21. " INTPND22 ,Interrupt Pending Bit 22" "Not pending,Pending"
|
|
bitfld.long 0x2c 20. " INTPND21 ,Interrupt Pending Bit 21" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 19. " INTPND20 ,Interrupt Pending Bit 20" "Not pending,Pending"
|
|
bitfld.long 0x2c 18. " INTPND19 ,Interrupt Pending Bit 19" "Not pending,Pending"
|
|
bitfld.long 0x2c 17. " INTPND18 ,Interrupt Pending Bit 18" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 16. " INTPND17 ,Interrupt Pending Bit 17" "Not pending,Pending"
|
|
bitfld.long 0x2c 15. " INTPND16 ,Interrupt Pending Bit 16" "Not pending,Pending"
|
|
bitfld.long 0x2c 14. " INTPND15 ,Interrupt Pending Bit 15" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 13. " INTPND14 ,Interrupt Pending Bit 14" "Not pending,Pending"
|
|
bitfld.long 0x2c 12. " INTPND13 ,Interrupt Pending Bit 13" "Not pending,Pending"
|
|
bitfld.long 0x2c 11. " INTPND12 ,Interrupt Pending Bit 12" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 10. " INTPND11 ,Interrupt Pending Bit 11" "Not pending,Pending"
|
|
bitfld.long 0x2c 9. " INTPND10 ,Interrupt Pending Bit 10" "Not pending,Pending"
|
|
bitfld.long 0x2c 8. " INTPND9 ,Interrupt Pending Bit 9" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 7. " INTPND8 ,Interrupt Pending Bit 8" "Not pending,Pending"
|
|
bitfld.long 0x2c 6. " INTPND7 ,Interrupt Pending Bit 7" "Not pending,Pending"
|
|
bitfld.long 0x2c 5. " INTPND6 ,Interrupt Pending Bit 6" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 4. " INTPND5 ,Interrupt Pending Bit 5" "Not pending,Pending"
|
|
bitfld.long 0x2c 3. " INTPND4 ,Interrupt Pending Bit 4" "Not pending,Pending"
|
|
bitfld.long 0x2c 2. " INTPND3 ,Interrupt Pending Bit 3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x2c 1. " INTPND2 ,Interrupt Pending Bit 2" "Not pending,Pending"
|
|
bitfld.long 0x2c 0. " INTPND1 ,Interrupt Pending Bit 1" "Not pending,Pending"
|
|
line.long 0x30 "DCAN_INTPND34,Interrupt Pending 3_4 Register"
|
|
bitfld.long 0x30 31. " INTPND64 ,Interrupt Pending Bit 64" "Not pending,Pending"
|
|
bitfld.long 0x30 30. " INTPND63 ,Interrupt Pending Bit 63" "Not pending,Pending"
|
|
bitfld.long 0x30 29. " INTPND62 ,Interrupt Pending Bit 62" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 28. " INTPND61 ,Interrupt Pending Bit 61" "Not pending,Pending"
|
|
bitfld.long 0x30 27. " INTPND60 ,Interrupt Pending Bit 60" "Not pending,Pending"
|
|
bitfld.long 0x30 26. " INTPND59 ,Interrupt Pending Bit 59" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 25. " INTPND58 ,Interrupt Pending Bit 58" "Not pending,Pending"
|
|
bitfld.long 0x30 24. " INTPND57 ,Interrupt Pending Bit 57" "Not pending,Pending"
|
|
bitfld.long 0x30 23. " INTPND56 ,Interrupt Pending Bit 56" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 22. " INTPND55 ,Interrupt Pending Bit 55" "Not pending,Pending"
|
|
bitfld.long 0x30 21. " INTPND54 ,Interrupt Pending Bit 54" "Not pending,Pending"
|
|
bitfld.long 0x30 20. " INTPND53 ,Interrupt Pending Bit 53" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 19. " INTPND52 ,Interrupt Pending Bit 52" "Not pending,Pending"
|
|
bitfld.long 0x30 18. " INTPND51 ,Interrupt Pending Bit 51" "Not pending,Pending"
|
|
bitfld.long 0x30 17. " INTPND50 ,Interrupt Pending Bit 50" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 16. " INTPND49 ,Interrupt Pending Bit 49" "Not pending,Pending"
|
|
bitfld.long 0x30 15. " INTPND48 ,Interrupt Pending Bit 48" "Not pending,Pending"
|
|
bitfld.long 0x30 14. " INTPND47 ,Interrupt Pending Bit 47" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 13. " INTPND46 ,Interrupt Pending Bit 46" "Not pending,Pending"
|
|
bitfld.long 0x30 12. " INTPND45 ,Interrupt Pending Bit 45" "Not pending,Pending"
|
|
bitfld.long 0x30 11. " INTPND44 ,Interrupt Pending Bit 44" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 10. " INTPND43 ,Interrupt Pending Bit 43" "Not pending,Pending"
|
|
bitfld.long 0x30 9. " INTPND42 ,Interrupt Pending Bit 42" "Not pending,Pending"
|
|
bitfld.long 0x30 8. " INTPND41 ,Interrupt Pending Bit 41" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 7. " INTPND40 ,Interrupt Pending Bit 40" "Not pending,Pending"
|
|
bitfld.long 0x30 6. " INTPND39 ,Interrupt Pending Bit 39" "Not pending,Pending"
|
|
bitfld.long 0x30 5. " INTPND38 ,Interrupt Pending Bit 38" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 4. " INTPND37 ,Interrupt Pending Bit 37" "Not pending,Pending"
|
|
bitfld.long 0x30 3. " INTPND36 ,Interrupt Pending Bit 36" "Not pending,Pending"
|
|
bitfld.long 0x30 2. " INTPND35 ,Interrupt Pending Bit 35" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x30 1. " INTPND34 ,Interrupt Pending Bit 34" "Not pending,Pending"
|
|
bitfld.long 0x30 0. " INTPND33 ,Interrupt Pending Bit 33" "Not pending,Pending"
|
|
line.long 0x34 "DCAN_INTPND56,Interrupt Pending 5_6 Register"
|
|
bitfld.long 0x34 31. " INTPND96 ,Interrupt Pending Bit 96" "Not pending,Pending"
|
|
bitfld.long 0x34 30. " INTPND95 ,Interrupt Pending Bit 95" "Not pending,Pending"
|
|
bitfld.long 0x34 29. " INTPND94 ,Interrupt Pending Bit 94" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 28. " INTPND93 ,Interrupt Pending Bit 93" "Not pending,Pending"
|
|
bitfld.long 0x34 27. " INTPND92 ,Interrupt Pending Bit 92" "Not pending,Pending"
|
|
bitfld.long 0x34 26. " INTPND91 ,Interrupt Pending Bit 91" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 25. " INTPND90 ,Interrupt Pending Bit 90" "Not pending,Pending"
|
|
bitfld.long 0x34 24. " INTPND89 ,Interrupt Pending Bit 89" "Not pending,Pending"
|
|
bitfld.long 0x34 23. " INTPND88 ,Interrupt Pending Bit 88" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 22. " INTPND87 ,Interrupt Pending Bit 87" "Not pending,Pending"
|
|
bitfld.long 0x34 21. " INTPND86 ,Interrupt Pending Bit 86" "Not pending,Pending"
|
|
bitfld.long 0x34 20. " INTPND85 ,Interrupt Pending Bit 85" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 19. " INTPND84 ,Interrupt Pending Bit 84" "Not pending,Pending"
|
|
bitfld.long 0x34 18. " INTPND83 ,Interrupt Pending Bit 83" "Not pending,Pending"
|
|
bitfld.long 0x34 17. " INTPND82 ,Interrupt Pending Bit 82" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 16. " INTPND81 ,Interrupt Pending Bit 81" "Not pending,Pending"
|
|
bitfld.long 0x34 15. " INTPND80 ,Interrupt Pending Bit 80" "Not pending,Pending"
|
|
bitfld.long 0x34 14. " INTPND79 ,Interrupt Pending Bit 79" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 13. " INTPND78 ,Interrupt Pending Bit 78" "Not pending,Pending"
|
|
bitfld.long 0x34 12. " INTPND77 ,Interrupt Pending Bit 77" "Not pending,Pending"
|
|
bitfld.long 0x34 11. " INTPND76 ,Interrupt Pending Bit 76" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 10. " INTPND75 ,Interrupt Pending Bit 75" "Not pending,Pending"
|
|
bitfld.long 0x34 9. " INTPND74 ,Interrupt Pending Bit 74" "Not pending,Pending"
|
|
bitfld.long 0x34 8. " INTPND73 ,Interrupt Pending Bit 73" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 7. " INTPND72 ,Interrupt Pending Bit 72" "Not pending,Pending"
|
|
bitfld.long 0x34 6. " INTPND71 ,Interrupt Pending Bit 71" "Not pending,Pending"
|
|
bitfld.long 0x34 5. " INTPND70 ,Interrupt Pending Bit 70" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 4. " INTPND69 ,Interrupt Pending Bit 69" "Not pending,Pending"
|
|
bitfld.long 0x34 3. " INTPND68 ,Interrupt Pending Bit 68" "Not pending,Pending"
|
|
bitfld.long 0x34 2. " INTPND67 ,Interrupt Pending Bit 67" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x34 1. " INTPND66 ,Interrupt Pending Bit 66" "Not pending,Pending"
|
|
bitfld.long 0x34 0. " INTPND65 ,Interrupt Pending Bit 65" "Not pending,Pending"
|
|
line.long 0x38 "DCAN_INTPND78,Interrupt Pending 7_8 Register"
|
|
bitfld.long 0x38 31. " INTPND128 ,Interrupt Pending Bit 128" "Not pending,Pending"
|
|
bitfld.long 0x38 30. " INTPND127 ,Interrupt Pending Bit 127" "Not pending,Pending"
|
|
bitfld.long 0x38 29. " INTPND126 ,Interrupt Pending Bit 126" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 28. " INTPND125 ,Interrupt Pending Bit 125" "Not pending,Pending"
|
|
bitfld.long 0x38 27. " INTPND124 ,Interrupt Pending Bit 124" "Not pending,Pending"
|
|
bitfld.long 0x38 26. " INTPND123 ,Interrupt Pending Bit 123" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 25. " INTPND122 ,Interrupt Pending Bit 122" "Not pending,Pending"
|
|
bitfld.long 0x38 24. " INTPND121 ,Interrupt Pending Bit 121" "Not pending,Pending"
|
|
bitfld.long 0x38 23. " INTPND120 ,Interrupt Pending Bit 120" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 22. " INTPND119 ,Interrupt Pending Bit 119" "Not pending,Pending"
|
|
bitfld.long 0x38 21. " INTPND118 ,Interrupt Pending Bit 118" "Not pending,Pending"
|
|
bitfld.long 0x38 20. " INTPND117 ,Interrupt Pending Bit 117" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 19. " INTPND116 ,Interrupt Pending Bit 116" "Not pending,Pending"
|
|
bitfld.long 0x38 18. " INTPND115 ,Interrupt Pending Bit 115" "Not pending,Pending"
|
|
bitfld.long 0x38 17. " INTPND114 ,Interrupt Pending Bit 114" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 16. " INTPND113 ,Interrupt Pending Bit 113" "Not pending,Pending"
|
|
bitfld.long 0x38 15. " INTPND112 ,Interrupt Pending Bit 112" "Not pending,Pending"
|
|
bitfld.long 0x38 14. " INTPND111 ,Interrupt Pending Bit 111" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 13. " INTPND110 ,Interrupt Pending Bit 110" "Not pending,Pending"
|
|
bitfld.long 0x38 12. " INTPND109 ,Interrupt Pending Bit 109" "Not pending,Pending"
|
|
bitfld.long 0x38 11. " INTPND108 ,Interrupt Pending Bit 108" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 10. " INTPND107 ,Interrupt Pending Bit 107" "Not pending,Pending"
|
|
bitfld.long 0x38 9. " INTPND106 ,Interrupt Pending Bit 106" "Not pending,Pending"
|
|
bitfld.long 0x38 8. " INTPND105 ,Interrupt Pending Bit 105" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 7. " INTPND104 ,Interrupt Pending Bit 104" "Not pending,Pending"
|
|
bitfld.long 0x38 6. " INTPND103 ,Interrupt Pending Bit 103" "Not pending,Pending"
|
|
bitfld.long 0x38 5. " INTPND102 ,Interrupt Pending Bit 102" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 4. " INTPND101 ,Interrupt Pending Bit 101" "Not pending,Pending"
|
|
bitfld.long 0x38 3. " INTPND100 ,Interrupt Pending Bit 100" "Not pending,Pending"
|
|
bitfld.long 0x38 2. " INTPND99 ,Interrupt Pending Bit 99" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x38 1. " INTPND98 ,Interrupt Pending Bit 98" "Not pending,Pending"
|
|
bitfld.long 0x38 0. " INTPND97 ,Interrupt Pending Bit 97" "Not pending,Pending"
|
|
line.long 0x3c "DCAN_MSGVAL_X,Message Valid X Register"
|
|
bitfld.long 0x3c 14.--15. " MSGVALREG8 ,Message Valid X Register 8" "0,1,2,3"
|
|
bitfld.long 0x3c 12.--13. " MSGVALREG7 ,Message Valid X Register 7" "0,1,2,3"
|
|
bitfld.long 0x3c 10.--11. " MSGVALREG6 ,Message Valid X Register 6" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x3c 8.--9. " MSGVALREG5 ,Message Valid X Register 5" "0,1,2,3"
|
|
bitfld.long 0x3c 6.--7. " MSGVALREG4 ,Message Valid X Register 4" "0,1,2,3"
|
|
bitfld.long 0x3c 4.--5. " MSGVALREG3 ,Message Valid X Register 3" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x3c 2.--3. " MSGVALREG2 ,Message Valid X Register 2" "0,1,2,3"
|
|
bitfld.long 0x3c 0.--1. " MSGVALREG1 ,Message Valid X Register 1" "0,1,2,3"
|
|
line.long 0x40 "DCAN_MSGVAL12,Message Valid 1_2 Register"
|
|
bitfld.long 0x40 31. " MSGVAL32 ,Message Valid Bit 32" "Ignored,Not ignored"
|
|
bitfld.long 0x40 30. " MSGVAL31 ,Message Valid Bit 31" "Ignored,Not ignored"
|
|
bitfld.long 0x40 29. " MSGVAL30 ,Message Valid Bit 30" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 28. " MSGVAL29 ,Message Valid Bit 29" "Ignored,Not ignored"
|
|
bitfld.long 0x40 27. " MSGVAL28 ,Message Valid Bit 28" "Ignored,Not ignored"
|
|
bitfld.long 0x40 26. " MSGVAL27 ,Message Valid Bit 27" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 25. " MSGVAL26 ,Message Valid Bit 26" "Ignored,Not ignored"
|
|
bitfld.long 0x40 24. " MSGVAL25 ,Message Valid Bit 25" "Ignored,Not ignored"
|
|
bitfld.long 0x40 23. " MSGVAL24 ,Message Valid Bit 24" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 22. " MSGVAL23 ,Message Valid Bit 23" "Ignored,Not ignored"
|
|
bitfld.long 0x40 21. " MSGVAL22 ,Message Valid Bit 22" "Ignored,Not ignored"
|
|
bitfld.long 0x40 20. " MSGVAL21 ,Message Valid Bit 21" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 19. " MSGVAL20 ,Message Valid Bit 20" "Ignored,Not ignored"
|
|
bitfld.long 0x40 18. " MSGVAL19 ,Message Valid Bit 19" "Ignored,Not ignored"
|
|
bitfld.long 0x40 17. " MSGVAL18 ,Message Valid Bit 18" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 16. " MSGVAL17 ,Message Valid Bit 17" "Ignored,Not ignored"
|
|
bitfld.long 0x40 15. " MSGVAL16 ,Message Valid Bit 16" "Ignored,Not ignored"
|
|
bitfld.long 0x40 14. " MSGVAL15 ,Message Valid Bit 15" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 13. " MSGVAL14 ,Message Valid Bit 14" "Ignored,Not ignored"
|
|
bitfld.long 0x40 12. " MSGVAL13 ,Message Valid Bit 13" "Ignored,Not ignored"
|
|
bitfld.long 0x40 11. " MSGVAL12 ,Message Valid Bit 12" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 10. " MSGVAL11 ,Message Valid Bit 11" "Ignored,Not ignored"
|
|
bitfld.long 0x40 9. " MSGVAL10 ,Message Valid Bit 10" "Ignored,Not ignored"
|
|
bitfld.long 0x40 8. " MSGVAL9 ,Message Valid Bit 9" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 7. " MSGVAL8 ,Message Valid Bit 8" "Ignored,Not ignored"
|
|
bitfld.long 0x40 6. " MSGVAL7 ,Message Valid Bit 7" "Ignored,Not ignored"
|
|
bitfld.long 0x40 5. " MSGVAL6 ,Message Valid Bit 6" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 4. " MSGVAL5 ,Message Valid Bit 5" "Ignored,Not ignored"
|
|
bitfld.long 0x40 3. " MSGVAL4 ,Message Valid Bit 4" "Ignored,Not ignored"
|
|
bitfld.long 0x40 2. " MSGVAL3 ,Message Valid Bit 3" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x40 1. " MSGVAL2 ,Message Valid Bit 2" "Ignored,Not ignored"
|
|
bitfld.long 0x40 0. " MSGVAL1 ,Message Valid Bit 1" "Ignored,Not ignored"
|
|
line.long 0x44 "DCAN_MSGVAL34,Message Valid 3_4 Register"
|
|
bitfld.long 0x44 31. " MSGVAL64 ,Message Valid Bit 64" "Ignored,Not ignored"
|
|
bitfld.long 0x44 30. " MSGVAL63 ,Message Valid Bit 63" "Ignored,Not ignored"
|
|
bitfld.long 0x44 29. " MSGVAL62 ,Message Valid Bit 62" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 28. " MSGVAL61 ,Message Valid Bit 61" "Ignored,Not ignored"
|
|
bitfld.long 0x44 27. " MSGVAL60 ,Message Valid Bit 60" "Ignored,Not ignored"
|
|
bitfld.long 0x44 26. " MSGVAL59 ,Message Valid Bit 59" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 25. " MSGVAL58 ,Message Valid Bit 58" "Ignored,Not ignored"
|
|
bitfld.long 0x44 24. " MSGVAL57 ,Message Valid Bit 57" "Ignored,Not ignored"
|
|
bitfld.long 0x44 23. " MSGVAL56 ,Message Valid Bit 56" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 22. " MSGVAL55 ,Message Valid Bit 55" "Ignored,Not ignored"
|
|
bitfld.long 0x44 21. " MSGVAL54 ,Message Valid Bit 54" "Ignored,Not ignored"
|
|
bitfld.long 0x44 20. " MSGVAL53 ,Message Valid Bit 53" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 19. " MSGVAL52 ,Message Valid Bit 52" "Ignored,Not ignored"
|
|
bitfld.long 0x44 18. " MSGVAL51 ,Message Valid Bit 51" "Ignored,Not ignored"
|
|
bitfld.long 0x44 17. " MSGVAL50 ,Message Valid Bit 50" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 16. " MSGVAL49 ,Message Valid Bit 49" "Ignored,Not ignored"
|
|
bitfld.long 0x44 15. " MSGVAL48 ,Message Valid Bit 48" "Ignored,Not ignored"
|
|
bitfld.long 0x44 14. " MSGVAL47 ,Message Valid Bit 47" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 13. " MSGVAL46 ,Message Valid Bit 46" "Ignored,Not ignored"
|
|
bitfld.long 0x44 12. " MSGVAL45 ,Message Valid Bit 45" "Ignored,Not ignored"
|
|
bitfld.long 0x44 11. " MSGVAL44 ,Message Valid Bit 44" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 10. " MSGVAL43 ,Message Valid Bit 43" "Ignored,Not ignored"
|
|
bitfld.long 0x44 9. " MSGVAL42 ,Message Valid Bit 42" "Ignored,Not ignored"
|
|
bitfld.long 0x44 8. " MSGVAL41 ,Message Valid Bit 41" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 7. " MSGVAL40 ,Message Valid Bit 40" "Ignored,Not ignored"
|
|
bitfld.long 0x44 6. " MSGVAL39 ,Message Valid Bit 39" "Ignored,Not ignored"
|
|
bitfld.long 0x44 5. " MSGVAL38 ,Message Valid Bit 38" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 4. " MSGVAL37 ,Message Valid Bit 37" "Ignored,Not ignored"
|
|
bitfld.long 0x44 3. " MSGVAL36 ,Message Valid Bit 36" "Ignored,Not ignored"
|
|
bitfld.long 0x44 2. " MSGVAL35 ,Message Valid Bit 35" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x44 1. " MSGVAL34 ,Message Valid Bit 34" "Ignored,Not ignored"
|
|
bitfld.long 0x44 0. " MSGVAL33 ,Message Valid Bit 33" "Ignored,Not ignored"
|
|
line.long 0x48 "DCAN_MSGVAL56,Message Valid 5_6 Register"
|
|
bitfld.long 0x48 31. " MSGVAL96 ,Message Valid Bit 96" "Ignored,Not ignored"
|
|
bitfld.long 0x48 30. " MSGVAL95 ,Message Valid Bit 95" "Ignored,Not ignored"
|
|
bitfld.long 0x48 29. " MSGVAL94 ,Message Valid Bit 94" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 28. " MSGVAL93 ,Message Valid Bit 93" "Ignored,Not ignored"
|
|
bitfld.long 0x48 27. " MSGVAL92 ,Message Valid Bit 92" "Ignored,Not ignored"
|
|
bitfld.long 0x48 26. " MSGVAL91 ,Message Valid Bit 91" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 25. " MSGVAL90 ,Message Valid Bit 90" "Ignored,Not ignored"
|
|
bitfld.long 0x48 24. " MSGVAL89 ,Message Valid Bit 89" "Ignored,Not ignored"
|
|
bitfld.long 0x48 23. " MSGVAL88 ,Message Valid Bit 88" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 22. " MSGVAL87 ,Message Valid Bit 87" "Ignored,Not ignored"
|
|
bitfld.long 0x48 21. " MSGVAL86 ,Message Valid Bit 86" "Ignored,Not ignored"
|
|
bitfld.long 0x48 20. " MSGVAL85 ,Message Valid Bit 85" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 19. " MSGVAL84 ,Message Valid Bit 84" "Ignored,Not ignored"
|
|
bitfld.long 0x48 18. " MSGVAL83 ,Message Valid Bit 83" "Ignored,Not ignored"
|
|
bitfld.long 0x48 17. " MSGVAL82 ,Message Valid Bit 82" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 16. " MSGVAL81 ,Message Valid Bit 81" "Ignored,Not ignored"
|
|
bitfld.long 0x48 15. " MSGVAL80 ,Message Valid Bit 80" "Ignored,Not ignored"
|
|
bitfld.long 0x48 14. " MSGVAL79 ,Message Valid Bit 79" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 13. " MSGVAL78 ,Message Valid Bit 78" "Ignored,Not ignored"
|
|
bitfld.long 0x48 12. " MSGVAL77 ,Message Valid Bit 77" "Ignored,Not ignored"
|
|
bitfld.long 0x48 11. " MSGVAL76 ,Message Valid Bit 76" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 10. " MSGVAL75 ,Message Valid Bit 75" "Ignored,Not ignored"
|
|
bitfld.long 0x48 9. " MSGVAL74 ,Message Valid Bit 74" "Ignored,Not ignored"
|
|
bitfld.long 0x48 8. " MSGVAL73 ,Message Valid Bit 73" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 7. " MSGVAL72 ,Message Valid Bit 72" "Ignored,Not ignored"
|
|
bitfld.long 0x48 6. " MSGVAL71 ,Message Valid Bit 71" "Ignored,Not ignored"
|
|
bitfld.long 0x48 5. " MSGVAL70 ,Message Valid Bit 70" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 4. " MSGVAL69 ,Message Valid Bit 69" "Ignored,Not ignored"
|
|
bitfld.long 0x48 3. " MSGVAL68 ,Message Valid Bit 68" "Ignored,Not ignored"
|
|
bitfld.long 0x48 2. " MSGVAL67 ,Message Valid Bit 67" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x48 1. " MSGVAL66 ,Message Valid Bit 66" "Ignored,Not ignored"
|
|
bitfld.long 0x48 0. " MSGVAL65 ,Message Valid Bit 65" "Ignored,Not ignored"
|
|
line.long 0x4C "DCAN_MSGVAL78,Message Valid 7_8 Register"
|
|
bitfld.long 0x4C 31. " MSGVAL128 ,Message Valid Bit 128" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 30. " MSGVAL127 ,Message Valid Bit 127" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 29. " MSGVAL126 ,Message Valid Bit 126" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 28. " MSGVAL125 ,Message Valid Bit 125" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 27. " MSGVAL124 ,Message Valid Bit 124" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 26. " MSGVAL123 ,Message Valid Bit 123" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 25. " MSGVAL122 ,Message Valid Bit 122" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 24. " MSGVAL121 ,Message Valid Bit 121" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 23. " MSGVAL120 ,Message Valid Bit 120" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 22. " MSGVAL119 ,Message Valid Bit 119" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 21. " MSGVAL118 ,Message Valid Bit 118" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 20. " MSGVAL117 ,Message Valid Bit 117" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 19. " MSGVAL116 ,Message Valid Bit 116" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 18. " MSGVAL115 ,Message Valid Bit 115" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 17. " MSGVAL114 ,Message Valid Bit 114" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 16. " MSGVAL113 ,Message Valid Bit 113" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 15. " MSGVAL112 ,Message Valid Bit 112" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 14. " MSGVAL111 ,Message Valid Bit 111" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 13. " MSGVAL110 ,Message Valid Bit 110" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 12. " MSGVAL109 ,Message Valid Bit 109" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 11. " MSGVAL108 ,Message Valid Bit 108" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 10. " MSGVAL107 ,Message Valid Bit 107" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 9. " MSGVAL106 ,Message Valid Bit 106" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 8. " MSGVAL105 ,Message Valid Bit 105" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 7. " MSGVAL104 ,Message Valid Bit 104" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 6. " MSGVAL103 ,Message Valid Bit 103" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 5. " MSGVAL102 ,Message Valid Bit 102" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 4. " MSGVAL101 ,Message Valid Bit 101" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 3. " MSGVAL100 ,Message Valid Bit 100" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 2. " MSGVAL99 ,Message Valid Bit 99" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x4C 1. " MSGVAL98 ,Message Valid Bit 98" "Ignored,Not ignored"
|
|
bitfld.long 0x4C 0. " MSGVAL97 ,Message Valid Bit 97" "Ignored,Not ignored"
|
|
group.long 0xD8--0xE7
|
|
sif (cpuis("DRA62*"))
|
|
line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer 1_2 Register"
|
|
bitfld.long 0x00 31. " INTMUX32 ,Multiplexes IntPnd value to one of two interrupt line 32" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 30. " INTMUX31 ,Multiplexes IntPnd value to one of two interrupt line 31" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 29. " INTMUX30 ,Multiplexes IntPnd value to one of two interrupt line 30" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 28. " INTMUX29 ,Multiplexes IntPnd value to one of two interrupt line 29" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 27. " INTMUX28 ,Multiplexes IntPnd value to one of two interrupt line 28" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 26. " INTMUX27 ,Multiplexes IntPnd value to one of two interrupt line 27" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTMUX26 ,Multiplexes IntPnd value to one of two interrupt line 26" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 24. " INTMUX25 ,Multiplexes IntPnd value to one of two interrupt line 25" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 23. " INTMUX24 ,Multiplexes IntPnd value to one of two interrupt line 24" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 22. " INTMUX23 ,Multiplexes IntPnd value to one of two interrupt line 23" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 21. " INTMUX22 ,Multiplexes IntPnd value to one of two interrupt line 22" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 20. " INTMUX21 ,Multiplexes IntPnd value to one of two interrupt line 21" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTMUX20 ,Multiplexes IntPnd value to one of two interrupt line 20" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 18. " INTMUX19 ,Multiplexes IntPnd value to one of two interrupt line 19" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 17. " INTMUX18 ,Multiplexes IntPnd value to one of two interrupt line 18" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INTMUX17 ,Multiplexes IntPnd value to one of two interrupt line 17" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 15. " INTMUX16 ,Multiplexes IntPnd value to one of two interrupt line 16" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 14. " INTMUX15 ,Multiplexes IntPnd value to one of two interrupt line 15" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTMUX14 ,Multiplexes IntPnd value to one of two interrupt line 14" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 12. " INTMUX13 ,Multiplexes IntPnd value to one of two interrupt line 13" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 11. " INTMUX12 ,Multiplexes IntPnd value to one of two interrupt line 12" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INTMUX11 ,Multiplexes IntPnd value to one of two interrupt line 11" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 9. " INTMUX10 ,Multiplexes IntPnd value to one of two interrupt line 10" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 8. " INTMUX9 ,Multiplexes IntPnd value to one of two interrupt line 9" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTMUX8 ,Multiplexes IntPnd value to one of two interrupt line 8" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 6. " INTMUX7 ,Multiplexes IntPnd value to one of two interrupt line 7" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 5. " INTMUX6 ,Multiplexes IntPnd value to one of two interrupt line 6" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTMUX5 ,Multiplexes IntPnd value to one of two interrupt line 5" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 3. " INTMUX4 ,Multiplexes IntPnd value to one of two interrupt line 4" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 2. " INTMUX3 ,Multiplexes IntPnd value to one of two interrupt line 3" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTMUX2 ,Multiplexes IntPnd value to one of two interrupt line 2" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 0. " INTMUX1 ,Multiplexes IntPnd value to one of two interrupt line 1" "DCAN0INT,DCAN1INT"
|
|
line.long 0x04 "DCAN_INTMUX34,Interrupt Multiplexer 3_4 Register"
|
|
bitfld.long 0x04 31. " INTMUX64 ,Multiplexes IntPnd value to one of two interrupt line 64" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 30. " INTMUX63 ,Multiplexes IntPnd value to one of two interrupt line 63" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 29. " INTMUX62 ,Multiplexes IntPnd value to one of two interrupt line 62" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 28. " INTMUX61 ,Multiplexes IntPnd value to one of two interrupt line 61" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 27. " INTMUX60 ,Multiplexes IntPnd value to one of two interrupt line 60" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 26. " INTMUX59 ,Multiplexes IntPnd value to one of two interrupt line 59" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTMUX58 ,Multiplexes IntPnd value to one of two interrupt line 58" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 24. " INTMUX57 ,Multiplexes IntPnd value to one of two interrupt line 57" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 23. " INTMUX56 ,Multiplexes IntPnd value to one of two interrupt line 56" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 22. " INTMUX55 ,Multiplexes IntPnd value to one of two interrupt line 55" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 21. " INTMUX54 ,Multiplexes IntPnd value to one of two interrupt line 54" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 20. " INTMUX53 ,Multiplexes IntPnd value to one of two interrupt line 53" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTMUX52 ,Multiplexes IntPnd value to one of two interrupt line 52" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 18. " INTMUX51 ,Multiplexes IntPnd value to one of two interrupt line 51" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 17. " INTMUX50 ,Multiplexes IntPnd value to one of two interrupt line 50" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 16. " INTMUX49 ,Multiplexes IntPnd value to one of two interrupt line 49" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 15. " INTMUX48 ,Multiplexes IntPnd value to one of two interrupt line 48" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 14. " INTMUX47 ,Multiplexes IntPnd value to one of two interrupt line 47" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTMUX46 ,Multiplexes IntPnd value to one of two interrupt line 46" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 12. " INTMUX45 ,Multiplexes IntPnd value to one of two interrupt line 45" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 11. " INTMUX44 ,Multiplexes IntPnd value to one of two interrupt line 44" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 10. " INTMUX43 ,Multiplexes IntPnd value to one of two interrupt line 43" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 9. " INTMUX42 ,Multiplexes IntPnd value to one of two interrupt line 42" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 8. " INTMUX41 ,Multiplexes IntPnd value to one of two interrupt line 41" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTMUX40 ,Multiplexes IntPnd value to one of two interrupt line 40" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 6. " INTMUX39 ,Multiplexes IntPnd value to one of two interrupt line 39" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 5. " INTMUX38 ,Multiplexes IntPnd value to one of two interrupt line 38" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INTMUX37 ,Multiplexes IntPnd value to one of two interrupt line 37" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 3. " INTMUX36 ,Multiplexes IntPnd value to one of two interrupt line 36" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 2. " INTMUX35 ,Multiplexes IntPnd value to one of two interrupt line 35" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTMUX34 ,Multiplexes IntPnd value to one of two interrupt line 34" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 0. " INTMUX33 ,Multiplexes IntPnd value to one of two interrupt line 33" "DCAN0INT,DCAN1INT"
|
|
line.long 0x08 "DCAN_INTMUX56,Interrupt Multiplexer 5_6 Register"
|
|
bitfld.long 0x08 31. " INTMUX96 ,Multiplexes IntPnd value to one of two interrupt line 96" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 30. " INTMUX95 ,Multiplexes IntPnd value to one of two interrupt line 95" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 29. " INTMUX94 ,Multiplexes IntPnd value to one of two interrupt line 94" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 28. " INTMUX93 ,Multiplexes IntPnd value to one of two interrupt line 93" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 27. " INTMUX92 ,Multiplexes IntPnd value to one of two interrupt line 92" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 26. " INTMUX91 ,Multiplexes IntPnd value to one of two interrupt line 91" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 25. " INTMUX90 ,Multiplexes IntPnd value to one of two interrupt line 90" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 24. " INTMUX89 ,Multiplexes IntPnd value to one of two interrupt line 89" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 23. " INTMUX88 ,Multiplexes IntPnd value to one of two interrupt line 88" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 22. " INTMUX87 ,Multiplexes IntPnd value to one of two interrupt line 87" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 21. " INTMUX86 ,Multiplexes IntPnd value to one of two interrupt line 86" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 20. " INTMUX85 ,Multiplexes IntPnd value to one of two interrupt line 85" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 19. " INTMUX84 ,Multiplexes IntPnd value to one of two interrupt line 84" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 18. " INTMUX83 ,Multiplexes IntPnd value to one of two interrupt line 83" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 17. " INTMUX82 ,Multiplexes IntPnd value to one of two interrupt line 82" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 16. " INTMUX81 ,Multiplexes IntPnd value to one of two interrupt line 81" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 15. " INTMUX80 ,Multiplexes IntPnd value to one of two interrupt line 80" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 14. " INTMUX79 ,Multiplexes IntPnd value to one of two interrupt line 79" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 13. " INTMUX78 ,Multiplexes IntPnd value to one of two interrupt line 78" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 12. " INTMUX77 ,Multiplexes IntPnd value to one of two interrupt line 77" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 11. " INTMUX76 ,Multiplexes IntPnd value to one of two interrupt line 76" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 10. " INTMUX75 ,Multiplexes IntPnd value to one of two interrupt line 75" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 9. " INTMUX74 ,Multiplexes IntPnd value to one of two interrupt line 74" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 8. " INTMUX73 ,Multiplexes IntPnd value to one of two interrupt line 73" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 7. " INTMUX72 ,Multiplexes IntPnd value to one of two interrupt line 72" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 6. " INTMUX71 ,Multiplexes IntPnd value to one of two interrupt line 71" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 5. " INTMUX70 ,Multiplexes IntPnd value to one of two interrupt line 70" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 4. " INTMUX69 ,Multiplexes IntPnd value to one of two interrupt line 69" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 3. " INTMUX68 ,Multiplexes IntPnd value to one of two interrupt line 68" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 2. " INTMUX67 ,Multiplexes IntPnd value to one of two interrupt line 67" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 1. " INTMUX66 ,Multiplexes IntPnd value to one of two interrupt line 66" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 0. " INTMUX65 ,Multiplexes IntPnd value to one of two interrupt line 65" "DCAN0INT,DCAN1INT"
|
|
line.long 0x0C "DCAN_INTMUX78,Interrupt Multiplexer 7_8 Register"
|
|
bitfld.long 0x0C 31. " INTMUX128 ,Multiplexes IntPnd value to one of two interrupt line 128" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 30. " INTMUX127 ,Multiplexes IntPnd value to one of two interrupt line 127" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 29. " INTMUX126 ,Multiplexes IntPnd value to one of two interrupt line 126" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " INTMUX125 ,Multiplexes IntPnd value to one of two interrupt line 125" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 27. " INTMUX124 ,Multiplexes IntPnd value to one of two interrupt line 124" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 26. " INTMUX123 ,Multiplexes IntPnd value to one of two interrupt line 123" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " INTMUX122 ,Multiplexes IntPnd value to one of two interrupt line 122" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 24. " INTMUX121 ,Multiplexes IntPnd value to one of two interrupt line 121" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 23. " INTMUX120 ,Multiplexes IntPnd value to one of two interrupt line 120" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " INTMUX119 ,Multiplexes IntPnd value to one of two interrupt line 119" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 21. " INTMUX118 ,Multiplexes IntPnd value to one of two interrupt line 118" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 20. " INTMUX117 ,Multiplexes IntPnd value to one of two interrupt line 117" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " INTMUX116 ,Multiplexes IntPnd value to one of two interrupt line 116" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 18. " INTMUX115 ,Multiplexes IntPnd value to one of two interrupt line 115" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 17. " INTMUX114 ,Multiplexes IntPnd value to one of two interrupt line 114" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " INTMUX113 ,Multiplexes IntPnd value to one of two interrupt line 113" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 15. " INTMUX112 ,Multiplexes IntPnd value to one of two interrupt line 112" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 14. " INTMUX111 ,Multiplexes IntPnd value to one of two interrupt line 111" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " INTMUX110 ,Multiplexes IntPnd value to one of two interrupt line 110" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 12. " INTMUX109 ,Multiplexes IntPnd value to one of two interrupt line 109" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 11. " INTMUX108 ,Multiplexes IntPnd value to one of two interrupt line 108" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " INTMUX107 ,Multiplexes IntPnd value to one of two interrupt line 107" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 9. " INTMUX106 ,Multiplexes IntPnd value to one of two interrupt line 106" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 8. " INTMUX105 ,Multiplexes IntPnd value to one of two interrupt line 105" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " INTMUX104 ,Multiplexes IntPnd value to one of two interrupt line 104" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 6. " INTMUX103 ,Multiplexes IntPnd value to one of two interrupt line 103" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 5. " INTMUX102 ,Multiplexes IntPnd value to one of two interrupt line 102" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " INTMUX101 ,Multiplexes IntPnd value to one of two interrupt line 101" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 3. " INTMUX100 ,Multiplexes IntPnd value to one of two interrupt line 100" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 2. " INTMUX99 ,Multiplexes IntPnd value to one of two interrupt line 99" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " INTMUX98 ,Multiplexes IntPnd value to one of two interrupt line 98" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 0. " INTMUX97 ,Multiplexes IntPnd value to one of two interrupt line 97" "DCAN0INT,DCAN1INT"
|
|
else
|
|
line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer 1_2 Register"
|
|
bitfld.long 0x00 31. " INTPNDMUX32 ,Multiplexes IntPnd value to one of two interrupt line 32" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 30. " INTPNDMUX31 ,Multiplexes IntPnd value to one of two interrupt line 31" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 29. " INTPNDMUX30 ,Multiplexes IntPnd value to one of two interrupt line 30" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 28. " INTPNDMUX29 ,Multiplexes IntPnd value to one of two interrupt line 29" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 27. " INTPNDMUX28 ,Multiplexes IntPnd value to one of two interrupt line 28" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 26. " INTPNDMUX27 ,Multiplexes IntPnd value to one of two interrupt line 27" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTPNDMUX26 ,Multiplexes IntPnd value to one of two interrupt line 26" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 24. " INTPNDMUX25 ,Multiplexes IntPnd value to one of two interrupt line 25" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 23. " INTPNDMUX24 ,Multiplexes IntPnd value to one of two interrupt line 24" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 22. " INTPNDMUX23 ,Multiplexes IntPnd value to one of two interrupt line 23" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 21. " INTPNDMUX22 ,Multiplexes IntPnd value to one of two interrupt line 22" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 20. " INTPNDMUX21 ,Multiplexes IntPnd value to one of two interrupt line 21" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTPNDMUX20 ,Multiplexes IntPnd value to one of two interrupt line 20" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 18. " INTPNDMUX19 ,Multiplexes IntPnd value to one of two interrupt line 19" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 17. " INTPNDMUX18 ,Multiplexes IntPnd value to one of two interrupt line 18" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INTPNDMUX17 ,Multiplexes IntPnd value to one of two interrupt line 17" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 15. " INTPNDMUX16 ,Multiplexes IntPnd value to one of two interrupt line 16" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 14. " INTPNDMUX15 ,Multiplexes IntPnd value to one of two interrupt line 15" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTPNDMUX14 ,Multiplexes IntPnd value to one of two interrupt line 14" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 12. " INTPNDMUX13 ,Multiplexes IntPnd value to one of two interrupt line 13" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 11. " INTPNDMUX12 ,Multiplexes IntPnd value to one of two interrupt line 12" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INTPNDMUX11 ,Multiplexes IntPnd value to one of two interrupt line 11" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 9. " INTPNDMUX10 ,Multiplexes IntPnd value to one of two interrupt line 10" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 8. " INTPNDMUX9 ,Multiplexes IntPnd value to one of two interrupt line 9" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTPNDMUX8 ,Multiplexes IntPnd value to one of two interrupt line 8" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 6. " INTPNDMUX7 ,Multiplexes IntPnd value to one of two interrupt line 7" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 5. " INTPNDMUX6 ,Multiplexes IntPnd value to one of two interrupt line 6" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTPNDMUX5 ,Multiplexes IntPnd value to one of two interrupt line 5" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 3. " INTPNDMUX4 ,Multiplexes IntPnd value to one of two interrupt line 4" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 2. " INTPNDMUX3 ,Multiplexes IntPnd value to one of two interrupt line 3" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTPNDMUX2 ,Multiplexes IntPnd value to one of two interrupt line 2" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 0. " INTPNDMUX1 ,Multiplexes IntPnd value to one of two interrupt line 1" "DCAN0INT,DCAN1INT"
|
|
line.long 0x04 "DCAN_INTMUX34,Interrupt Multiplexer 3_4 Register"
|
|
bitfld.long 0x04 31. " INTPNDMUX64 ,Multiplexes IntPnd value to one of two interrupt line 64" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 30. " INTPNDMUX63 ,Multiplexes IntPnd value to one of two interrupt line 63" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 29. " INTPNDMUX62 ,Multiplexes IntPnd value to one of two interrupt line 62" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 28. " INTPNDMUX61 ,Multiplexes IntPnd value to one of two interrupt line 61" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 27. " INTPNDMUX60 ,Multiplexes IntPnd value to one of two interrupt line 60" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 26. " INTPNDMUX59 ,Multiplexes IntPnd value to one of two interrupt line 59" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTPNDMUX58 ,Multiplexes IntPnd value to one of two interrupt line 58" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 24. " INTPNDMUX57 ,Multiplexes IntPnd value to one of two interrupt line 57" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 23. " INTPNDMUX56 ,Multiplexes IntPnd value to one of two interrupt line 56" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 22. " INTPNDMUX55 ,Multiplexes IntPnd value to one of two interrupt line 55" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 21. " INTPNDMUX54 ,Multiplexes IntPnd value to one of two interrupt line 54" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 20. " INTPNDMUX53 ,Multiplexes IntPnd value to one of two interrupt line 53" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTPNDMUX52 ,Multiplexes IntPnd value to one of two interrupt line 52" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 18. " INTPNDMUX51 ,Multiplexes IntPnd value to one of two interrupt line 51" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 17. " INTPNDMUX50 ,Multiplexes IntPnd value to one of two interrupt line 50" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 16. " INTPNDMUX49 ,Multiplexes IntPnd value to one of two interrupt line 49" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 15. " INTPNDMUX48 ,Multiplexes IntPnd value to one of two interrupt line 48" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 14. " INTPNDMUX47 ,Multiplexes IntPnd value to one of two interrupt line 47" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTPNDMUX46 ,Multiplexes IntPnd value to one of two interrupt line 46" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 12. " INTPNDMUX45 ,Multiplexes IntPnd value to one of two interrupt line 45" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 11. " INTPNDMUX44 ,Multiplexes IntPnd value to one of two interrupt line 44" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 10. " INTPNDMUX43 ,Multiplexes IntPnd value to one of two interrupt line 43" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 9. " INTPNDMUX42 ,Multiplexes IntPnd value to one of two interrupt line 42" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 8. " INTPNDMUX41 ,Multiplexes IntPnd value to one of two interrupt line 41" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTPNDMUX40 ,Multiplexes IntPnd value to one of two interrupt line 40" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 6. " INTPNDMUX39 ,Multiplexes IntPnd value to one of two interrupt line 39" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 5. " INTPNDMUX38 ,Multiplexes IntPnd value to one of two interrupt line 38" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INTPNDMUX37 ,Multiplexes IntPnd value to one of two interrupt line 37" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 3. " INTPNDMUX36 ,Multiplexes IntPnd value to one of two interrupt line 36" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 2. " INTPNDMUX35 ,Multiplexes IntPnd value to one of two interrupt line 35" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTPNDMUX34 ,Multiplexes IntPnd value to one of two interrupt line 34" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 0. " INTPNDMUX33 ,Multiplexes IntPnd value to one of two interrupt line 33" "DCAN0INT,DCAN1INT"
|
|
line.long 0x08 "DCAN_INTMUX56,Interrupt Multiplexer 5_6 Register"
|
|
bitfld.long 0x08 31. " INTPNDMUX96 ,Multiplexes IntPnd value to one of two interrupt line 96" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 30. " INTPNDMUX95 ,Multiplexes IntPnd value to one of two interrupt line 95" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 29. " INTPNDMUX94 ,Multiplexes IntPnd value to one of two interrupt line 94" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 28. " INTPNDMUX93 ,Multiplexes IntPnd value to one of two interrupt line 93" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 27. " INTPNDMUX92 ,Multiplexes IntPnd value to one of two interrupt line 92" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 26. " INTPNDMUX91 ,Multiplexes IntPnd value to one of two interrupt line 91" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 25. " INTPNDMUX90 ,Multiplexes IntPnd value to one of two interrupt line 90" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 24. " INTPNDMUX89 ,Multiplexes IntPnd value to one of two interrupt line 89" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 23. " INTPNDMUX88 ,Multiplexes IntPnd value to one of two interrupt line 88" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 22. " INTPNDMUX87 ,Multiplexes IntPnd value to one of two interrupt line 87" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 21. " INTPNDMUX86 ,Multiplexes IntPnd value to one of two interrupt line 86" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 20. " INTPNDMUX85 ,Multiplexes IntPnd value to one of two interrupt line 85" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 19. " INTPNDMUX84 ,Multiplexes IntPnd value to one of two interrupt line 84" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 18. " INTPNDMUX83 ,Multiplexes IntPnd value to one of two interrupt line 83" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 17. " INTPNDMUX82 ,Multiplexes IntPnd value to one of two interrupt line 82" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 16. " INTPNDMUX81 ,Multiplexes IntPnd value to one of two interrupt line 81" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 15. " INTPNDMUX80 ,Multiplexes IntPnd value to one of two interrupt line 80" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 14. " INTPNDMUX79 ,Multiplexes IntPnd value to one of two interrupt line 79" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 13. " INTPNDMUX78 ,Multiplexes IntPnd value to one of two interrupt line 78" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 12. " INTPNDMUX77 ,Multiplexes IntPnd value to one of two interrupt line 77" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 11. " INTPNDMUX76 ,Multiplexes IntPnd value to one of two interrupt line 76" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 10. " INTPNDMUX75 ,Multiplexes IntPnd value to one of two interrupt line 75" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 9. " INTPNDMUX74 ,Multiplexes IntPnd value to one of two interrupt line 74" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 8. " INTPNDMUX73 ,Multiplexes IntPnd value to one of two interrupt line 73" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 7. " INTPNDMUX72 ,Multiplexes IntPnd value to one of two interrupt line 72" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 6. " INTPNDMUX71 ,Multiplexes IntPnd value to one of two interrupt line 71" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 5. " INTPNDMUX70 ,Multiplexes IntPnd value to one of two interrupt line 70" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 4. " INTPNDMUX69 ,Multiplexes IntPnd value to one of two interrupt line 69" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 3. " INTPNDMUX68 ,Multiplexes IntPnd value to one of two interrupt line 68" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 2. " INTPNDMUX67 ,Multiplexes IntPnd value to one of two interrupt line 67" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x08 1. " INTPNDMUX66 ,Multiplexes IntPnd value to one of two interrupt line 66" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 0. " INTPNDMUX65 ,Multiplexes IntPnd value to one of two interrupt line 65" "DCAN0INT,DCAN1INT"
|
|
line.long 0x0C "DCAN_INTMUX78,Interrupt Multiplexer 7_8 Register"
|
|
bitfld.long 0x0C 31. " INTPNDMUX128 ,Multiplexes IntPnd value to one of two interrupt line 128" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 30. " INTPNDMUX127 ,Multiplexes IntPnd value to one of two interrupt line 127" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 29. " INTPNDMUX126 ,Multiplexes IntPnd value to one of two interrupt line 126" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " INTPNDMUX125 ,Multiplexes IntPnd value to one of two interrupt line 125" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 27. " INTPNDMUX124 ,Multiplexes IntPnd value to one of two interrupt line 124" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 26. " INTPNDMUX123 ,Multiplexes IntPnd value to one of two interrupt line 123" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " INTPNDMUX122 ,Multiplexes IntPnd value to one of two interrupt line 122" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 24. " INTPNDMUX121 ,Multiplexes IntPnd value to one of two interrupt line 121" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 23. " INTPNDMUX120 ,Multiplexes IntPnd value to one of two interrupt line 120" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " INTPNDMUX119 ,Multiplexes IntPnd value to one of two interrupt line 119" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 21. " INTPNDMUX118 ,Multiplexes IntPnd value to one of two interrupt line 118" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 20. " INTPNDMUX117 ,Multiplexes IntPnd value to one of two interrupt line 117" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " INTPNDMUX116 ,Multiplexes IntPnd value to one of two interrupt line 116" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 18. " INTPNDMUX115 ,Multiplexes IntPnd value to one of two interrupt line 115" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 17. " INTPNDMUX114 ,Multiplexes IntPnd value to one of two interrupt line 114" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " INTPNDMUX113 ,Multiplexes IntPnd value to one of two interrupt line 113" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 15. " INTPNDMUX112 ,Multiplexes IntPnd value to one of two interrupt line 112" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 14. " INTPNDMUX111 ,Multiplexes IntPnd value to one of two interrupt line 111" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " INTPNDMUX110 ,Multiplexes IntPnd value to one of two interrupt line 110" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 12. " INTPNDMUX109 ,Multiplexes IntPnd value to one of two interrupt line 109" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 11. " INTPNDMUX108 ,Multiplexes IntPnd value to one of two interrupt line 108" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " INTPNDMUX107 ,Multiplexes IntPnd value to one of two interrupt line 107" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 9. " INTPNDMUX106 ,Multiplexes IntPnd value to one of two interrupt line 106" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 8. " INTPNDMUX105 ,Multiplexes IntPnd value to one of two interrupt line 105" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " INTPNDMUX104 ,Multiplexes IntPnd value to one of two interrupt line 104" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 6. " INTPNDMUX103 ,Multiplexes IntPnd value to one of two interrupt line 103" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 5. " INTPNDMUX102 ,Multiplexes IntPnd value to one of two interrupt line 102" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " INTPNDMUX101 ,Multiplexes IntPnd value to one of two interrupt line 101" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 3. " INTPNDMUX100 ,Multiplexes IntPnd value to one of two interrupt line 100" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 2. " INTPNDMUX99 ,Multiplexes IntPnd value to one of two interrupt line 99" "DCAN0INT,DCAN1INT"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " INTPNDMUX98 ,Multiplexes IntPnd value to one of two interrupt line 98" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 0. " INTPNDMUX97 ,Multiplexes IntPnd value to one of two interrupt line 97" "DCAN0INT,DCAN1INT"
|
|
endif
|
|
if (((data.long(ad:0x481D0000+0x100))&0x800000)==0x800000)
|
|
group.long 0x100++0x03 "IF1 Registers"
|
|
line.long 0x00 "DCAN_IF1CMD,IF1 Command Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered"
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,?..."
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Handled,Set"
|
|
else
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Cleared,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered"
|
|
bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number"
|
|
else
|
|
group.long 0x100++0x03 "IF1 Registers"
|
|
line.long 0x00 "DCAN_IF1CMD,IF1 Command Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered"
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Unchanged,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered"
|
|
bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number"
|
|
endif
|
|
if ((((data.long(ad:0x481D0000+0x100))&0x8000)==0x8000)&&(((data.long(ad:0x481D0000+0x108))&0x40000000)==0x40000000))
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
bitfld.long 0x00 17. " ," "0,1"
|
|
bitfld.long 0x00 16. " ," "0,1"
|
|
bitfld.long 0x00 15. " ," "0,1"
|
|
bitfld.long 0x00 14. " ," "0,1"
|
|
bitfld.long 0x00 13. " ," "0,1"
|
|
bitfld.long 0x00 12. " ," "0,1"
|
|
bitfld.long 0x00 11. " ," "0,1"
|
|
bitfld.long 0x00 10. " ," "0,1"
|
|
bitfld.long 0x00 9. " ," "0,1"
|
|
bitfld.long 0x00 8. " ," "0,1"
|
|
bitfld.long 0x00 7. " ," "0,1"
|
|
bitfld.long 0x00 6. " ," "0,1"
|
|
bitfld.long 0x00 5. " ," "0,1"
|
|
bitfld.long 0x00 4. " ," "0,1"
|
|
bitfld.long 0x00 3. " ," "0,1"
|
|
bitfld.long 0x00 2. " ," "0,1"
|
|
bitfld.long 0x00 1. " ," "0,1"
|
|
bitfld.long 0x00 0. " ," "0,1"
|
|
elif ((((data.long(ad:0x481D0000+0x100))&0x8000)==0x0000)&&(((data.long(ad:0x481D0000+0x108))&0x40000000)==0x40000000))
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
bitfld.long 0x00 17. " ," "0,1"
|
|
bitfld.long 0x00 16. " ," "0,1"
|
|
bitfld.long 0x00 15. " ," "0,1"
|
|
bitfld.long 0x00 14. " ," "0,1"
|
|
bitfld.long 0x00 13. " ," "0,1"
|
|
bitfld.long 0x00 12. " ," "0,1"
|
|
bitfld.long 0x00 11. " ," "0,1"
|
|
bitfld.long 0x00 10. " ," "0,1"
|
|
bitfld.long 0x00 9. " ," "0,1"
|
|
bitfld.long 0x00 8. " ," "0,1"
|
|
bitfld.long 0x00 7. " ," "0,1"
|
|
bitfld.long 0x00 6. " ," "0,1"
|
|
bitfld.long 0x00 5. " ," "0,1"
|
|
bitfld.long 0x00 4. " ," "0,1"
|
|
bitfld.long 0x00 3. " ," "0,1"
|
|
bitfld.long 0x00 2. " ," "0,1"
|
|
bitfld.long 0x00 1. " ," "0,1"
|
|
bitfld.long 0x00 0. " ," "0,1"
|
|
elif ((((data.long(ad:0x481D0000+0x100))&0x8000)==0x8000)&&(((data.long(ad:0x481D0000+0x108))&0x40000000)==0x00))
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK10-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK10-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
endif
|
|
if ((((data.long(ad:0x481D0000+0x100))&0x8000)==0x8000)&&(((data.long(ad:0x481D0000+0x108))&0x40000000)==0x40000000))
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier"
|
|
elif ((((data.long(ad:0x481D0000+0x100))&0x8000)==0x0000)&&(((data.long(ad:0x481D0000+0x108))&0x40000000)==0x40000000))
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier"
|
|
elif ((((data.long(ad:0x481D0000+0x100))&0x8000)==0x0000)&&(((data.long(ad:0x481D0000+0x108))&0x40000000)==0x00000000))
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier"
|
|
else
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier"
|
|
endif
|
|
if (((data.long(ad:0x481D0000+0x100))&0x8000)==0x8000)
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
endif
|
|
if (((data.long(ad:0x481D0000+0x100))&0x8000)==0x8000)
|
|
rgroup.long 0x110++0x07
|
|
line.long 0x00 "DCAN_IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value"
|
|
line.long 0x04 "DCAN_IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value"
|
|
else
|
|
group.long 0x110++0x07
|
|
line.long 0x00 "DCAN_IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value"
|
|
line.long 0x04 "DCAN_IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value"
|
|
endif
|
|
if (((data.long(ad:0x481D0000+0x120))&0x800000)==0x800000)
|
|
group.long 0x120++0x03 "IF2 Registers"
|
|
line.long 0x00 "DCAN_IF2CMD,IF2 Command Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered"
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,?..."
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Handled,Set"
|
|
else
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Cleared,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered"
|
|
bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number"
|
|
else
|
|
group.long 0x120++0x03 "IF2 Registers"
|
|
line.long 0x00 "DCAN_IF2CMD,IF2 Command Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered"
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Unchanged,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered"
|
|
bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number"
|
|
endif
|
|
if ((((data.long(ad:0x481D0000+0x120))&0x8000)==0x8000)&&(((data.long(ad:0x481D0000+0x128))&0x40000000)==0x40000000))
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
bitfld.long 0x00 17. " ," "0,1"
|
|
bitfld.long 0x00 16. " ," "0,1"
|
|
bitfld.long 0x00 15. " ," "0,1"
|
|
bitfld.long 0x00 14. " ," "0,1"
|
|
bitfld.long 0x00 13. " ," "0,1"
|
|
bitfld.long 0x00 12. " ," "0,1"
|
|
bitfld.long 0x00 11. " ," "0,1"
|
|
bitfld.long 0x00 10. " ," "0,1"
|
|
bitfld.long 0x00 9. " ," "0,1"
|
|
bitfld.long 0x00 8. " ," "0,1"
|
|
bitfld.long 0x00 7. " ," "0,1"
|
|
bitfld.long 0x00 6. " ," "0,1"
|
|
bitfld.long 0x00 5. " ," "0,1"
|
|
bitfld.long 0x00 4. " ," "0,1"
|
|
bitfld.long 0x00 3. " ," "0,1"
|
|
bitfld.long 0x00 2. " ," "0,1"
|
|
bitfld.long 0x00 1. " ," "0,1"
|
|
bitfld.long 0x00 0. " ," "0,1"
|
|
elif ((((data.long(ad:0x481D0000+0x120))&0x8000)==0x0000)&&(((data.long(ad:0x481D0000+0x128))&0x40000000)==0x40000000))
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
bitfld.long 0x00 17. " ," "0,1"
|
|
bitfld.long 0x00 16. " ," "0,1"
|
|
bitfld.long 0x00 15. " ," "0,1"
|
|
bitfld.long 0x00 14. " ," "0,1"
|
|
bitfld.long 0x00 13. " ," "0,1"
|
|
bitfld.long 0x00 12. " ," "0,1"
|
|
bitfld.long 0x00 11. " ," "0,1"
|
|
bitfld.long 0x00 10. " ," "0,1"
|
|
bitfld.long 0x00 9. " ," "0,1"
|
|
bitfld.long 0x00 8. " ," "0,1"
|
|
bitfld.long 0x00 7. " ," "0,1"
|
|
bitfld.long 0x00 6. " ," "0,1"
|
|
bitfld.long 0x00 5. " ," "0,1"
|
|
bitfld.long 0x00 4. " ," "0,1"
|
|
bitfld.long 0x00 3. " ," "0,1"
|
|
bitfld.long 0x00 2. " ," "0,1"
|
|
bitfld.long 0x00 1. " ," "0,1"
|
|
bitfld.long 0x00 0. " ," "0,1"
|
|
elif ((((data.long(ad:0x481D0000+0x120))&0x8000)==0x8000)&&(((data.long(ad:0x481D0000+0x128))&0x40000000)==0x00))
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-18 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
else
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-18 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
endif
|
|
if ((((data.long(ad:0x481D0000+0x120))&0x8000)==0x8000)&&(((data.long(ad:0x481D0000+0x128))&0x40000000)==0x40000000))
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier"
|
|
elif ((((data.long(ad:0x481D0000+0x120))&0x8000)==0x0000)&&(((data.long(ad:0x481D0000+0x128))&0x40000000)==0x40000000))
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier"
|
|
elif ((((data.long(ad:0x481D0000+0x120))&0x8000)==0x0000)&&(((data.long(ad:0x481D0000+0x128))&0x40000000)==0x00000000))
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier"
|
|
else
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier"
|
|
endif
|
|
if (((data.long(ad:0x481D0000+0x120))&0x8000)==0x8000)
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
endif
|
|
if (((data.long(ad:0x481D0000+0x120))&0x8000)==0x8000)
|
|
rgroup.long 0x130++0x07
|
|
line.long 0x00 "DCAN_IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value"
|
|
line.long 0x04 "DCAN_IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value"
|
|
else
|
|
group.long 0x130++0x07
|
|
line.long 0x00 "DCAN_IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value"
|
|
line.long 0x04 "DCAN_IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value"
|
|
endif
|
|
group.long 0x140++0x03 "IF3 Registers"
|
|
line.long 0x00 "DCAN_IF3OBS,IF3 Observation Register"
|
|
bitfld.long 0x00 15. " IF3UPD ,IF3 Update Data" "Not updated,Updated"
|
|
bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B read access" "All read,Not all read"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A read access" "All read,Not all read"
|
|
bitfld.long 0x00 10. " IF3SC ,IF3 Status of control bits read access" "All read,Not all read"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration data read access" "All read,Not all read"
|
|
bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask data read access" "All read,Not all read"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATAB ,Data B read observation" "Not read,Read"
|
|
bitfld.long 0x00 3. " DATAA ,Data A read observation" "Not read,Read"
|
|
bitfld.long 0x00 2. " CTRL ,Ctrl read observation" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ARB ,Arbitration data read observation" "Not read,Read"
|
|
bitfld.long 0x00 0. " MASK ,Mask data read observation" "Not read,Read"
|
|
if (((data.long(ad:0x481D0000+0x148))&0x40000000)==0x40000000)
|
|
rgroup.long 0x144++0x3
|
|
line.long 0x00 "DCAN_IF3MSK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 27. " ," "0,1"
|
|
bitfld.long 0x00 26. " ," "0,1"
|
|
bitfld.long 0x00 25. " ," "0,1"
|
|
bitfld.long 0x00 24. " ," "0,1"
|
|
bitfld.long 0x00 23. " ," "0,1"
|
|
bitfld.long 0x00 22. " ," "0,1"
|
|
bitfld.long 0x00 21. " ," "0,1"
|
|
bitfld.long 0x00 20. " ," "0,1"
|
|
bitfld.long 0x00 19. " ," "0,1"
|
|
bitfld.long 0x00 18. " ," "0,1"
|
|
bitfld.long 0x00 17. " ," "0,1"
|
|
bitfld.long 0x00 16. " ," "0,1"
|
|
bitfld.long 0x00 15. " ," "0,1"
|
|
bitfld.long 0x00 14. " ," "0,1"
|
|
bitfld.long 0x00 13. " ," "0,1"
|
|
bitfld.long 0x00 12. " ," "0,1"
|
|
bitfld.long 0x00 11. " ," "0,1"
|
|
bitfld.long 0x00 10. " ," "0,1"
|
|
bitfld.long 0x00 9. " ," "0,1"
|
|
bitfld.long 0x00 8. " ," "0,1"
|
|
bitfld.long 0x00 7. " ," "0,1"
|
|
bitfld.long 0x00 6. " ," "0,1"
|
|
bitfld.long 0x00 5. " ," "0,1"
|
|
bitfld.long 0x00 4. " ," "0,1"
|
|
bitfld.long 0x00 3. " ," "0,1"
|
|
bitfld.long 0x00 2. " ," "0,1"
|
|
bitfld.long 0x00 1. " ," "0,1"
|
|
bitfld.long 0x00 0. " ," "0,1"
|
|
else
|
|
rgroup.long 0x144++0x3
|
|
line.long 0x00 "DCAN_IF3MSK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MSK10-0 ,Identifier Mask" "0,1"
|
|
bitfld.long 0x00 9. " ," "0,1"
|
|
bitfld.long 0x00 8. " ," "0,1"
|
|
bitfld.long 0x00 7. " ," "0,1"
|
|
bitfld.long 0x00 6. " ," "0,1"
|
|
bitfld.long 0x00 5. " ," "0,1"
|
|
bitfld.long 0x00 4. " ," "0,1"
|
|
bitfld.long 0x00 3. " ," "0,1"
|
|
bitfld.long 0x00 2. " ," "0,1"
|
|
bitfld.long 0x00 1. " ," "0,1"
|
|
bitfld.long 0x00 0. " ," "0,1"
|
|
endif
|
|
if (((data.long(ad:0x481D0000+0x148))&0x40000000)==0x40000000)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DCAN_IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier"
|
|
else
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DCAN_IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier"
|
|
endif
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "DCAN_IF3MCTL,IF3 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
rgroup.long 0x150++0x07
|
|
line.long 0x00 "DCAN_IF3DATA,IF3 Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value"
|
|
line.long 0x04 "DCAN_IF3DATB,IF3 Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value"
|
|
group.long 0x160--0x16F
|
|
line.long 0x00 "IF3UPD12,Update Enable 1_2 Register"
|
|
bitfld.long 0x00 31. " IF3UPDATEEN32 ,IF3 Update enabled 32" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IF3UPDATEEN31 ,IF3 Update enabled 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IF3UPDATEEN30 ,IF3 Update enabled 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IF3UPDATEEN29 ,IF3 Update enabled 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " IF3UPDATEEN28 ,IF3 Update enabled 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " IF3UPDATEEN27 ,IF3 Update enabled 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IF3UPDATEEN26 ,IF3 Update enabled 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " IF3UPDATEEN25 ,IF3 Update enabled 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " IF3UPDATEEN24 ,IF3 Update enabled 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IF3UPDATEEN23 ,IF3 Update enabled 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " IF3UPDATEEN22 ,IF3 Update enabled 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " IF3UPDATEEN21 ,IF3 Update enabled 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IF3UPDATEEN20 ,IF3 Update enabled 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " IF3UPDATEEN19 ,IF3 Update enabled 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " IF3UPDATEEN18 ,IF3 Update enabled 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IF3UPDATEEN17 ,IF3 Update enabled 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " IF3UPDATEEN16 ,IF3 Update enabled 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " IF3UPDATEEN15 ,IF3 Update enabled 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IF3UPDATEEN14 ,IF3 Update enabled 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IF3UPDATEEN13 ,IF3 Update enabled 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " IF3UPDATEEN12 ,IF3 Update enabled 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IF3UPDATEEN11 ,IF3 Update enabled 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " IF3UPDATEEN10 ,IF3 Update enabled 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IF3UPDATEEN9 ,IF3 Update enabled 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IF3UPDATEEN8 ,IF3 Update enabled 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IF3UPDATEEN7 ,IF3 Update enabled 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IF3UPDATEEN6 ,IF3 Update enabled 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IF3UPDATEEN5 ,IF3 Update enabled 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IF3UPDATEEN4 ,IF3 Update enabled 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IF3UPDATEEN3 ,IF3 Update enabled 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IF3UPDATEEN2 ,IF3 Update enabled 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IF3UPDATEEN1 ,IF3 Update enabled 1" "Disabled,Enabled"
|
|
line.long 0x04 "IF3UPD3_4,Update Enable 3_4 Register"
|
|
bitfld.long 0x04 31. " IF3UPDATEEN64 ,IF3 Update enabled 64" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " IF3UPDATEEN63 ,IF3 Update enabled 63" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " IF3UPDATEEN62 ,IF3 Update enabled 62" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " IF3UPDATEEN61 ,IF3 Update enabled 61" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " IF3UPDATEEN60 ,IF3 Update enabled 60" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " IF3UPDATEEN59 ,IF3 Update enabled 59" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " IF3UPDATEEN58 ,IF3 Update enabled 58" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " IF3UPDATEEN57 ,IF3 Update enabled 57" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " IF3UPDATEEN56 ,IF3 Update enabled 56" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " IF3UPDATEEN55 ,IF3 Update enabled 55" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " IF3UPDATEEN54 ,IF3 Update enabled 54" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " IF3UPDATEEN53 ,IF3 Update enabled 53" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " IF3UPDATEEN52 ,IF3 Update enabled 52" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " IF3UPDATEEN51 ,IF3 Update enabled 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " IF3UPDATEEN50 ,IF3 Update enabled 50" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " IF3UPDATEEN49 ,IF3 Update enabled 49" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " IF3UPDATEEN48 ,IF3 Update enabled 48" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " IF3UPDATEEN47 ,IF3 Update enabled 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " IF3UPDATEEN46 ,IF3 Update enabled 46" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " IF3UPDATEEN45 ,IF3 Update enabled 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " IF3UPDATEEN44 ,IF3 Update enabled 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " IF3UPDATEEN43 ,IF3 Update enabled 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " IF3UPDATEEN42 ,IF3 Update enabled 42" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " IF3UPDATEEN41 ,IF3 Update enabled 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " IF3UPDATEEN40 ,IF3 Update enabled 40" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " IF3UPDATEEN39 ,IF3 Update enabled 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " IF3UPDATEEN38 ,IF3 Update enabled 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " IF3UPDATEEN37 ,IF3 Update enabled 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IF3UPDATEEN36 ,IF3 Update enabled 36" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " IF3UPDATEEN35 ,IF3 Update enabled 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IF3UPDATEEN34 ,IF3 Update enabled 34" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " IF3UPDATEEN33 ,IF3 Update enabled 33" "Disabled,Enabled"
|
|
line.long 0x08 "IF3UPD5_6,Update Enable 5_6 Register"
|
|
bitfld.long 0x08 31. " IF3UPDATEEN96 ,IF3 Update enabled 96" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " IF3UPDATEEN95 ,IF3 Update enabled 95" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " IF3UPDATEEN94 ,IF3 Update enabled 94" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 28. " IF3UPDATEEN93 ,IF3 Update enabled 93" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " IF3UPDATEEN92 ,IF3 Update enabled 92" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " IF3UPDATEEN91 ,IF3 Update enabled 91" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IF3UPDATEEN90 ,IF3 Update enabled 90" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " IF3UPDATEEN89 ,IF3 Update enabled 89" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " IF3UPDATEEN88 ,IF3 Update enabled 88" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " IF3UPDATEEN87 ,IF3 Update enabled 87" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " IF3UPDATEEN86 ,IF3 Update enabled 86" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " IF3UPDATEEN85 ,IF3 Update enabled 85" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IF3UPDATEEN84 ,IF3 Update enabled 84" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " IF3UPDATEEN83 ,IF3 Update enabled 83" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " IF3UPDATEEN82 ,IF3 Update enabled 82" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " IF3UPDATEEN81 ,IF3 Update enabled 81" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " IF3UPDATEEN80 ,IF3 Update enabled 80" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " IF3UPDATEEN79 ,IF3 Update enabled 79" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IF3UPDATEEN78 ,IF3 Update enabled 78" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " IF3UPDATEEN77 ,IF3 Update enabled 77" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " IF3UPDATEEN76 ,IF3 Update enabled 76" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " IF3UPDATEEN75 ,IF3 Update enabled 75" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " IF3UPDATEEN74 ,IF3 Update enabled 74" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " IF3UPDATEEN73 ,IF3 Update enabled 73" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IF3UPDATEEN72 ,IF3 Update enabled 72" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " IF3UPDATEEN71 ,IF3 Update enabled 71" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " IF3UPDATEEN70 ,IF3 Update enabled 70" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " IF3UPDATEEN69 ,IF3 Update enabled 69" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " IF3UPDATEEN68 ,IF3 Update enabled 68" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " IF3UPDATEEN67 ,IF3 Update enabled 67" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IF3UPDATEEN66 ,IF3 Update enabled 66" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IF3UPDATEEN65 ,IF3 Update enabled 65" "Disabled,Enabled"
|
|
line.long 0x0C "IF3UPD7_8,Update Enable 7_8 Register"
|
|
bitfld.long 0x0C 31. " IF3UPDATEEN128 ,IF3 Update enabled 128" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " IF3UPDATEEN127 ,IF3 Update enabled 127" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " IF3UPDATEEN126 ,IF3 Update enabled 126" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " IF3UPDATEEN125 ,IF3 Update enabled 125" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " IF3UPDATEEN124 ,IF3 Update enabled 124" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " IF3UPDATEEN123 ,IF3 Update enabled 123" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " IF3UPDATEEN122 ,IF3 Update enabled 122" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " IF3UPDATEEN121 ,IF3 Update enabled 121" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " IF3UPDATEEN120 ,IF3 Update enabled 120" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " IF3UPDATEEN119 ,IF3 Update enabled 119" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " IF3UPDATEEN118 ,IF3 Update enabled 118" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " IF3UPDATEEN117 ,IF3 Update enabled 117" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " IF3UPDATEEN116 ,IF3 Update enabled 116" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " IF3UPDATEEN115 ,IF3 Update enabled 115" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " IF3UPDATEEN114 ,IF3 Update enabled 114" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " IF3UPDATEEN113 ,IF3 Update enabled 113" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " IF3UPDATEEN112 ,IF3 Update enabled 112" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " IF3UPDATEEN111 ,IF3 Update enabled 111" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " IF3UPDATEEN110 ,IF3 Update enabled 110" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " IF3UPDATEEN109 ,IF3 Update enabled 109" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " IF3UPDATEEN108 ,IF3 Update enabled 108" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " IF3UPDATEEN107 ,IF3 Update enabled 107" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " IF3UPDATEEN106 ,IF3 Update enabled 106" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " IF3UPDATEEN105 ,IF3 Update enabled 105" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " IF3UPDATEEN104 ,IF3 Update enabled 104" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " IF3UPDATEEN103 ,IF3 Update enabled 103" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " IF3UPDATEEN102 ,IF3 Update enabled 102" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " IF3UPDATEEN101 ,IF3 Update enabled 101" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " IF3UPDATEEN100 ,IF3 Update enabled 100" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " IF3UPDATEEN99 ,IF3 Update enabled 99" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " IF3UPDATEEN98 ,IF3 Update enabled 98" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " IF3UPDATEEN97 ,IF3 Update enabled 97" "Disabled,Enabled"
|
|
width 12.
|
|
if (((d.l(ad:0x481D0000))&0x1)==0x1)
|
|
// DCAN_CTL.Init == 1
|
|
group.long 0x1E0++0x07
|
|
line.long 0x00 "DCAN_TIOC,TX IO Control Register"
|
|
bitfld.long 0x00 18. " PU ,Selection of pull direction" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 17. " PD ,Pull functionality disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " OD ,Open drain mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of pin" "GPIO,CAN"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,I/O"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of pin" "Low,High"
|
|
line.long 0x04 "DCAN_RIOC,RX IO Control Register"
|
|
bitfld.long 0x04 18. " PU ,Selection of pull direction" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 17. " PD ,Pull functionality disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " OD ,Open drain mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " FUNC ,Functionality of pin" "GPIO,CAN"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,Output"
|
|
else
|
|
bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,I/O"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High"
|
|
bitfld.long 0x04 0. " IN ,Value of pin" "Low,High"
|
|
else
|
|
rgroup.long 0x1E0++0x07
|
|
line.long 0x00 "DCAN_TIOC,TX IO Control Register"
|
|
bitfld.long 0x00 18. " PU ,Selection of pull direction" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 17. " PD ,Pull functionality disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " OD ,Open drain mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of pin" "GPIO,CAN"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,I/O"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of pin" "Low,High"
|
|
line.long 0x04 "DCAN_RIOC,RX IO Control Register"
|
|
bitfld.long 0x04 18. " PU ,Selection of pull direction" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 17. " PD ,Pull functionality disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " OD ,Open drain mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " FUNC ,Functionality of pin" "GPIO,CAN"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,Output"
|
|
else
|
|
bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,I/O"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High"
|
|
bitfld.long 0x04 0. " IN ,Value of pin" "Low,High"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "EDMA (Enhanced Direct-Memory-Access)"
|
|
tree "EDMA TPCC (EDMA Channel Controller Control Registers)"
|
|
base ad:0x49000000
|
|
tree "Global Registers"
|
|
width 10.
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "PID,Peripheral ID Register"
|
|
line.long 0x04 "CCCFG,EDMA3CC Configuration Register"
|
|
sif ((cpuis("AM387*"))||(cpuis("DRA62*")))
|
|
bitfld.long 0x04 25. " MP_EXIST ,Memory Protection Existence" "Reserved,Included"
|
|
bitfld.long 0x04 24. " CHMAP_EXIST ,Channel Mapping Existence" "Reserved,Included"
|
|
textline " "
|
|
bitfld.long 0x04 20.--21. " NUM_REGN ,Number of Shadow Regions" "Reserved,Reserved,Reserved,8 regions"
|
|
bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of Queues / Number of TCs" "Reserved,Reserved,Reserved,4 EDMA3TCs/Event,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " NUM_PAENTRY ,Number of PaRAM Sets" "Reserved,Reserved,Reserved,Reserved,Reserved,512,?..."
|
|
elif (cpuis("AM335*"))
|
|
bitfld.long 0x04 25. " MP_EXIST ,Memory Protection Existence" "Reserved,Included"
|
|
bitfld.long 0x04 24. " CHMAP_EXIST ,Channel Mapping Existence" "Reserved,Included"
|
|
textline " "
|
|
bitfld.long 0x04 20.--21. " NUM_REGN ,Number of Shadow Regions" "Reserved,Reserved,4 regions,?..."
|
|
bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of Queues / Number of TCs" "Reserved,Reserved,3 EDMA3TCs/Event,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " NUM_PAENTRY ,Number of PaRAM Sets" "Reserved,Reserved,Reserved,Reserved,256,?..."
|
|
else
|
|
bitfld.long 0x04 25. " MP_EXIST ,Memory Protection Existence" "Not exist,?..."
|
|
bitfld.long 0x04 24. " CHMAP_EXIST ,Channel Mapping Existence" "Not exist,?..."
|
|
textline " "
|
|
bitfld.long 0x04 20.--21. " NUM_REGN ,Number of Shadow Regions" "Reserved,2 regions,?..."
|
|
bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of Queues / Number of TCs" "Reserved,Reserved,2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " NUM_PAENTRY ,Number of PaRAM Sets" "Reserved,Reserved,Reserved,128 sets,?..."
|
|
endif
|
|
bitfld.long 0x04 8.--10. " NUM_INTCH ,Number of Interrupt Channels" "Reserved,Reserved,Reserved,Reserved,64 channels,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " NUM_QDMACH ,Number of QDMA Channels" "Reserved,Reserved,Reserved,Reserved,8 channels,?..."
|
|
bitfld.long 0x04 0.--2. " NUM_DMACH ,Number of DMA Channels" "Reserved,Reserved,Reserved,Reserved,Reserved,64 channels,?..."
|
|
tree "DMA Channels Mapping Registers"
|
|
group.long 0x100++0xFF
|
|
line.long 0x0 "DCHMAP0,DMA Channel Map 0 Register"
|
|
hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 0"
|
|
line.long 0x4 "DCHMAP1,DMA Channel Map 1 Register"
|
|
hexmask.long.word 0x4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 1"
|
|
line.long 0x8 "DCHMAP2,DMA Channel Map 2 Register"
|
|
hexmask.long.word 0x8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 2"
|
|
line.long 0xC "DCHMAP3,DMA Channel Map 3 Register"
|
|
hexmask.long.word 0xC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 3"
|
|
line.long 0x10 "DCHMAP4,DMA Channel Map 4 Register"
|
|
hexmask.long.word 0x10 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 4"
|
|
line.long 0x14 "DCHMAP5,DMA Channel Map 5 Register"
|
|
hexmask.long.word 0x14 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 5"
|
|
line.long 0x18 "DCHMAP6,DMA Channel Map 6 Register"
|
|
hexmask.long.word 0x18 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 6"
|
|
line.long 0x1C "DCHMAP7,DMA Channel Map 7 Register"
|
|
hexmask.long.word 0x1C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 7"
|
|
line.long 0x20 "DCHMAP8,DMA Channel Map 8 Register"
|
|
hexmask.long.word 0x20 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 8"
|
|
line.long 0x24 "DCHMAP9,DMA Channel Map 9 Register"
|
|
hexmask.long.word 0x24 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 9"
|
|
line.long 0x28 "DCHMAP10,DMA Channel Map 10 Register"
|
|
hexmask.long.word 0x28 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 10"
|
|
line.long 0x2C "DCHMAP11,DMA Channel Map 11 Register"
|
|
hexmask.long.word 0x2C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 11"
|
|
line.long 0x30 "DCHMAP12,DMA Channel Map 12 Register"
|
|
hexmask.long.word 0x30 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 12"
|
|
line.long 0x34 "DCHMAP13,DMA Channel Map 13 Register"
|
|
hexmask.long.word 0x34 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 13"
|
|
line.long 0x38 "DCHMAP14,DMA Channel Map 14 Register"
|
|
hexmask.long.word 0x38 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 14"
|
|
line.long 0x3C "DCHMAP15,DMA Channel Map 15 Register"
|
|
hexmask.long.word 0x3C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 15"
|
|
line.long 0x40 "DCHMAP16,DMA Channel Map 16 Register"
|
|
hexmask.long.word 0x40 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 16"
|
|
line.long 0x44 "DCHMAP17,DMA Channel Map 17 Register"
|
|
hexmask.long.word 0x44 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 17"
|
|
line.long 0x48 "DCHMAP18,DMA Channel Map 18 Register"
|
|
hexmask.long.word 0x48 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 18"
|
|
line.long 0x4C "DCHMAP19,DMA Channel Map 19 Register"
|
|
hexmask.long.word 0x4C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 19"
|
|
line.long 0x50 "DCHMAP20,DMA Channel Map 20 Register"
|
|
hexmask.long.word 0x50 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 20"
|
|
line.long 0x54 "DCHMAP21,DMA Channel Map 21 Register"
|
|
hexmask.long.word 0x54 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 21"
|
|
line.long 0x58 "DCHMAP22,DMA Channel Map 22 Register"
|
|
hexmask.long.word 0x58 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 22"
|
|
line.long 0x5C "DCHMAP23,DMA Channel Map 23 Register"
|
|
hexmask.long.word 0x5C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 23"
|
|
line.long 0x60 "DCHMAP24,DMA Channel Map 24 Register"
|
|
hexmask.long.word 0x60 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 24"
|
|
line.long 0x64 "DCHMAP25,DMA Channel Map 25 Register"
|
|
hexmask.long.word 0x64 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 25"
|
|
line.long 0x68 "DCHMAP26,DMA Channel Map 26 Register"
|
|
hexmask.long.word 0x68 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 26"
|
|
line.long 0x6C "DCHMAP27,DMA Channel Map 27 Register"
|
|
hexmask.long.word 0x6C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 27"
|
|
line.long 0x70 "DCHMAP28,DMA Channel Map 28 Register"
|
|
hexmask.long.word 0x70 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 28"
|
|
line.long 0x74 "DCHMAP29,DMA Channel Map 29 Register"
|
|
hexmask.long.word 0x74 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 29"
|
|
line.long 0x78 "DCHMAP30,DMA Channel Map 30 Register"
|
|
hexmask.long.word 0x78 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 30"
|
|
line.long 0x7C "DCHMAP31,DMA Channel Map 31 Register"
|
|
hexmask.long.word 0x7C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 31"
|
|
line.long 0x80 "DCHMAP32,DMA Channel Map 32 Register"
|
|
hexmask.long.word 0x80 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 32"
|
|
line.long 0x84 "DCHMAP33,DMA Channel Map 33 Register"
|
|
hexmask.long.word 0x84 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 33"
|
|
line.long 0x88 "DCHMAP34,DMA Channel Map 34 Register"
|
|
hexmask.long.word 0x88 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 34"
|
|
line.long 0x8C "DCHMAP35,DMA Channel Map 35 Register"
|
|
hexmask.long.word 0x8C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 35"
|
|
line.long 0x90 "DCHMAP36,DMA Channel Map 36 Register"
|
|
hexmask.long.word 0x90 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 36"
|
|
line.long 0x94 "DCHMAP37,DMA Channel Map 37 Register"
|
|
hexmask.long.word 0x94 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 37"
|
|
line.long 0x98 "DCHMAP38,DMA Channel Map 38 Register"
|
|
hexmask.long.word 0x98 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 38"
|
|
line.long 0x9C "DCHMAP39,DMA Channel Map 39 Register"
|
|
hexmask.long.word 0x9C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 39"
|
|
line.long 0xA0 "DCHMAP40,DMA Channel Map 40 Register"
|
|
hexmask.long.word 0xA0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 40"
|
|
line.long 0xA4 "DCHMAP41,DMA Channel Map 41 Register"
|
|
hexmask.long.word 0xA4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 41"
|
|
line.long 0xA8 "DCHMAP42,DMA Channel Map 42 Register"
|
|
hexmask.long.word 0xA8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 42"
|
|
line.long 0xAC "DCHMAP43,DMA Channel Map 43 Register"
|
|
hexmask.long.word 0xAC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 43"
|
|
line.long 0xB0 "DCHMAP44,DMA Channel Map 44 Register"
|
|
hexmask.long.word 0xB0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 44"
|
|
line.long 0xB4 "DCHMAP45,DMA Channel Map 45 Register"
|
|
hexmask.long.word 0xB4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 45"
|
|
line.long 0xB8 "DCHMAP46,DMA Channel Map 46 Register"
|
|
hexmask.long.word 0xB8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 46"
|
|
line.long 0xBC "DCHMAP47,DMA Channel Map 47 Register"
|
|
hexmask.long.word 0xBC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 47"
|
|
line.long 0xC0 "DCHMAP48,DMA Channel Map 48 Register"
|
|
hexmask.long.word 0xC0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 48"
|
|
line.long 0xC4 "DCHMAP49,DMA Channel Map 49 Register"
|
|
hexmask.long.word 0xC4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 49"
|
|
line.long 0xC8 "DCHMAP50,DMA Channel Map 50 Register"
|
|
hexmask.long.word 0xC8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 50"
|
|
line.long 0xCC "DCHMAP51,DMA Channel Map 51 Register"
|
|
hexmask.long.word 0xCC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 51"
|
|
line.long 0xD0 "DCHMAP52,DMA Channel Map 52 Register"
|
|
hexmask.long.word 0xD0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 52"
|
|
line.long 0xD4 "DCHMAP53,DMA Channel Map 53 Register"
|
|
hexmask.long.word 0xD4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 53"
|
|
line.long 0xD8 "DCHMAP54,DMA Channel Map 54 Register"
|
|
hexmask.long.word 0xD8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 54"
|
|
line.long 0xDC "DCHMAP55,DMA Channel Map 55 Register"
|
|
hexmask.long.word 0xDC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 55"
|
|
line.long 0xE0 "DCHMAP56,DMA Channel Map 56 Register"
|
|
hexmask.long.word 0xE0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 56"
|
|
line.long 0xE4 "DCHMAP57,DMA Channel Map 57 Register"
|
|
hexmask.long.word 0xE4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 57"
|
|
line.long 0xE8 "DCHMAP58,DMA Channel Map 58 Register"
|
|
hexmask.long.word 0xE8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 58"
|
|
line.long 0xEC "DCHMAP59,DMA Channel Map 59 Register"
|
|
hexmask.long.word 0xEC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 59"
|
|
line.long 0xF0 "DCHMAP60,DMA Channel Map 60 Register"
|
|
hexmask.long.word 0xF0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 60"
|
|
line.long 0xF4 "DCHMAP61,DMA Channel Map 61 Register"
|
|
hexmask.long.word 0xF4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 61"
|
|
line.long 0xF8 "DCHMAP62,DMA Channel Map 62 Register"
|
|
hexmask.long.word 0xF8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 62"
|
|
line.long 0xFC "DCHMAP63,DMA Channel Map 63 Register"
|
|
hexmask.long.word 0xFC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 63"
|
|
tree.end
|
|
tree "QDMA Channels Mapping Registers"
|
|
group.long 0x200++0x1f
|
|
line.long 0x0 "QCHMAP0,QDMA Channel Map 0 Register"
|
|
hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 0"
|
|
hexmask.long.byte 0x0 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY"
|
|
line.long 0x4 "QCHMAP1,QDMA Channel Map 1 Register"
|
|
hexmask.long.word 0x4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 1"
|
|
hexmask.long.byte 0x4 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY"
|
|
line.long 0x8 "QCHMAP2,QDMA Channel Map 2 Register"
|
|
hexmask.long.word 0x8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 2"
|
|
hexmask.long.byte 0x8 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY"
|
|
line.long 0xC "QCHMAP3,QDMA Channel Map 3 Register"
|
|
hexmask.long.word 0xC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 3"
|
|
hexmask.long.byte 0xC 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY"
|
|
line.long 0x10 "QCHMAP4,QDMA Channel Map 4 Register"
|
|
hexmask.long.word 0x10 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 4"
|
|
hexmask.long.byte 0x10 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY"
|
|
line.long 0x14 "QCHMAP5,QDMA Channel Map 5 Register"
|
|
hexmask.long.word 0x14 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 5"
|
|
hexmask.long.byte 0x14 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY"
|
|
line.long 0x18 "QCHMAP6,QDMA Channel Map 6 Register"
|
|
hexmask.long.word 0x18 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 6"
|
|
hexmask.long.byte 0x18 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY"
|
|
line.long 0x1C "QCHMAP7,QDMA Channel Map 7 Register"
|
|
hexmask.long.word 0x1C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 7"
|
|
hexmask.long.byte 0x1C 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY"
|
|
tree.end
|
|
width 10.
|
|
tree "DMA Queue Registers"
|
|
group.long 0x240++0x1f
|
|
line.long 0x00 "DMAQNUM0,DMA Queue Number Register 0"
|
|
bitfld.long 0x00 28.--30. " E7 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x00 24.--26. " E6 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x00 20.--22. " E5 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x00 16.--18. " E4 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " E3 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x00 8.--10. " E2 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x00 4.--6. " E1 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x00 0.--2. " E0 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
line.long 0x04 "DMAQNUM1,DMA Queue Number Register 1"
|
|
bitfld.long 0x04 28.--30. " E15 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x04 24.--26. " E14 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x04 20.--22. " E13 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x04 16.--18. " E12 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " E11 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x04 8.--10. " E10 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x04 4.--6. " E9 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x04 0.--2. " E8 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
line.long 0x08 "DMAQNUM2,DMA Queue Number Register 2"
|
|
bitfld.long 0x08 28.--30. " E23 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x08 24.--26. " E22 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x08 20.--22. " E21 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x08 16.--18. " E20 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " E19 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x08 8.--10. " E18 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x08 4.--6. " E17 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x08 0.--2. " E16 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
line.long 0x0c "DMAQNUM3,DMA Queue Number Register 3"
|
|
bitfld.long 0x0c 28.--30. " E31 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x0c 24.--26. " E30 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x0c 20.--22. " E29 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x0c 16.--18. " E28 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 12.--14. " E27 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x0c 8.--10. " E26 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x0c 4.--6. " E25 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x0c 0.--2. " E24 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
line.long 0x10 "DMAQNUM4,DMA Queue Number Register 4"
|
|
bitfld.long 0x10 28.--30. " E39 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x10 24.--26. " E38 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x10 20.--22. " E37 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x10 16.--18. " E36 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
textline " "
|
|
bitfld.long 0x10 12.--14. " E35 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x10 8.--10. " E34 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x10 4.--6. " E33 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x10 0.--2. " E32 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
line.long 0x14 "DMAQNUM5,DMA Queue Number Register 5"
|
|
bitfld.long 0x14 28.--30. " E47 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x14 24.--26. " E46 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x14 20.--22. " E45 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x14 16.--18. " E44 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
textline " "
|
|
bitfld.long 0x14 12.--14. " E43 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x14 8.--10. " E42 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x14 4.--6. " E41 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x14 0.--2. " E40 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
line.long 0x18 "DMAQNUM6,DMA Queue Number Register 6"
|
|
bitfld.long 0x18 28.--30. " E55 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x18 24.--26. " E54 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x18 20.--22. " E53 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x18 16.--18. " E52 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
textline " "
|
|
bitfld.long 0x18 12.--14. " E51 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x18 8.--10. " E50 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x18 4.--6. " E49 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x18 0.--2. " E48 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
line.long 0x1c "DMAQNUM7,DMA Queue Number Register 7"
|
|
bitfld.long 0x1c 28.--30. " E63 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x1c 24.--26. " E62 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x1c 20.--22. " E61 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x1c 16.--18. " E60 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
textline " "
|
|
bitfld.long 0x1c 12.--14. " E59 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x1c 8.--10. " E58 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x1c 4.--6. " E57 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x1c 0.--2. " E56 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
group.long 0x260++0x3
|
|
line.long 0x00 "QDMAQNUM,QDMA Channel Queue Number Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 28.--30. " E4 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x00 24.--26. " E6 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x00 20.--22. " E5 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x00 16.--18. " E4 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
endif
|
|
bitfld.long 0x00 12.--14. " E3 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x00 8.--10. " E2 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x00 4.--6. " E1 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
bitfld.long 0x00 0.--2. " E0 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..."
|
|
group.long 0x284++0x3
|
|
line.long 0x00 "QUEPRI,Queue Priority Register"
|
|
bitfld.long 0x00 12.--14. " PRIQ3 ,Priority Level for Queue 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRIQ2 ,Priority Level for Queue 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRIQ1 ,Priority Level for Queue 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRIQ0 ,Priority Level for Queue 0" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree.end
|
|
tree "Error Registers"
|
|
width 10.
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x00 "EMR,Event Missed Register"
|
|
bitfld.long 0x00 31. " E31 ,Channel 31 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 30. " E30 ,Channel 30 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 29. " E29 ,Channel 29 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 28. " E28 ,Channel 28 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,Channel 27 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 26. " E26 ,Channel 26 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 25. " E25 ,Channel 25 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 24. " E24 ,Channel 24 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,Channel 23 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 22. " E22 ,Channel 22 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 21. " E21 ,Channel 21 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 20. " E20 ,Channel 20 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Channel 19 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 18. " E18 ,Channel 18 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 17. " E17 ,Channel 17 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 16. " E16 ,Channel 16 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,Channel 15 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 14. " E14 ,Channel 14 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 13. " E13 ,Channel 13 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 12. " E12 ,Channel 12 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,Channel 11 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 10. " E10 ,Channel 10 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 9. " E9 ,Channel 9 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 8. " E8 ,Channel 8 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Channel 7 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 6. " E6 ,Channel 6 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 5. " E5 ,Channel 5 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 4. " E4 ,Channel 4 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Channel 3 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 2. " E2 ,Channel 2 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 1. " E1 ,Channel 1 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 0. " E0 ,Channel 0 event missed" "Not missed,Missed"
|
|
line.long 0x04 "EMRH,Event Missed Register High"
|
|
bitfld.long 0x04 31. " E63 ,Channel 63 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 30. " E62 ,Channel 62 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 29. " E61 ,Channel 61 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 28. " E60 ,Channel 60 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 27. " E59 ,Channel 59 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 26. " E58 ,Channel 58 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 25. " E57 ,Channel 57 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 24. " E56 ,Channel 56 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 23. " E55 ,Channel 55 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 22. " E54 ,Channel 54 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 21. " E53 ,Channel 53 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 20. " E52 ,Channel 52 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Channel 51 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 18. " E50 ,Channel 50 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 17. " E49 ,Channel 49 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 16. " E48 ,Channel 48 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 15. " E47 ,Channel 47 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 14. " E46 ,Channel 46 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 13. " E45 ,Channel 45 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 12. " E44 ,Channel 44 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 11. " E43 ,Channel 43 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 10. " E42 ,Channel 42 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 9. " E41 ,Channel 41 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 8. " E40 ,Channel 40 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Channel 39 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 6. " E38 ,Channel 38 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 5. " E37 ,Channel 37 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 4. " E36 ,Channel 36 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 3. " E35 ,Channel 35 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 2. " E34 ,Channel 34 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 1. " E33 ,Channel 33 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 0. " E32 ,Channel 32 event missed" "Not missed,Missed"
|
|
wgroup.long 0x308++0x7
|
|
line.long 0x00 "EMCR,Event Missed Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event missed 31 clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event missed 30 clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event missed 29 clear" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event missed 28 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,Event missed 27 clear" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event missed 26 clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " E25 ,Event missed 25 clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Event missed 24 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,Event missed 23 clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event missed 22 clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event missed 21 clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event missed 20 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Event missed 19 clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event missed 18 clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Event missed 17 clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event missed 16 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,Event missed 15 clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event missed 14 clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " E13 ,Event missed 13 clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event missed 12 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,Event missed 11 clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " E10 ,Event missed 10 clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event missed 9 clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event missed 8 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Event missed 7 clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event missed 6 clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event missed 5 clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event missed 4 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Event missed 3 clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event missed 2 clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event missed 1 clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event missed 0 clear" "No effect,Clear"
|
|
line.long 0x04 "EMCRH,Event Missed Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event missed 63 clear" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event missed 62 clear" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event missed 61 clear" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event missed 60 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " E59 ,Event missed 59 clear" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event missed 58 clear" "No effect,Clear"
|
|
bitfld.long 0x04 25. " E57 ,Event missed 57 clear" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Event missed 56 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " E55 ,Event missed 55 clear" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event missed 54 clear" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event missed 53 clear" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event missed 52 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Event missed 51 clear" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event missed 50 clear" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Event missed 49 clear" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event missed 48 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " E47 ,Event missed 47 clear" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event missed 46 clear" "No effect,Clear"
|
|
bitfld.long 0x04 13. " E45 ,Event missed 45 clear" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event missed 44 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " E43 ,Event missed 43 clear" "No effect,Clear"
|
|
bitfld.long 0x04 10. " E42 ,Event missed 42 clear" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event missed 41 clear" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event missed 40 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Event missed 39 clear" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event missed 38 clear" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event missed 37 clear" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event missed 36 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " E35 ,Event missed 35 clear" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event missed 34 clear" "No effect,Clear"
|
|
bitfld.long 0x04 1. " E33 ,Event missed 33 clear" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event missed 32 clear" "No effect,Clear"
|
|
rgroup.long 0x310++0x3
|
|
line.long 0x00 "QEMR,QDMA Event Missed Register"
|
|
bitfld.long 0x00 7. " E7 ,Channel 7 QDMA event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 6. " E6 ,Channel 6 QDMA event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 5. " E5 ,Channel 5 QDMA event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 4. " E4 ,Channel 4 QDMA event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Channel 3 QDMA event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 2. " E2 ,Channel 2 QDMA event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 1. " E1 ,Channel 1 QDMA event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 0. " E0 ,Channel 0 QDMA event missed" "Not missed,Missed"
|
|
wgroup.long 0x314++0x3
|
|
line.long 0x00 "QEMCR,QDMA Event Missed Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event missed 7 clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event missed 6 clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event missed 5 clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event missed 4 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event missed 3 clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event missed 2 clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event missed 1 clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event missed 0 clear" "No effect,Clear"
|
|
rgroup.long 0x318++0x3
|
|
line.long 0x00 "CCERR,EDMA3CC Error Register"
|
|
bitfld.long 0x00 16. " TCCERR ,Transfer completion code error" "Not reached,Reached"
|
|
textline " "
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Queue threshold error for queue 3" "Not exceeded,Exceeded"
|
|
textline " "
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error for queue 2" "Not exceeded,Exceeded"
|
|
textline " "
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error for queue 1" "Not exceeded,Exceeded"
|
|
textline " "
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error for queue 0" "Not exceeded,Exceeded"
|
|
wgroup.long 0x31c++0x3
|
|
line.long 0x00 "CCERRCLR,EDMA3CC Error Clear Register"
|
|
bitfld.long 0x00 16. " TCCERR ,Transfer completion code error clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Queue threshold error clear for queue 3" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error clear for queue 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error clear for queue 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error clear for queue 0" "No effect,Clear"
|
|
wgroup.long 0x320++0x3
|
|
line.long 0x00 "EEVAL,Error Evaluation Register"
|
|
bitfld.long 0x00 0. " EVAL ,Error interrupt evaluate" "No effect,Evaluate"
|
|
tree.end
|
|
tree "Region Access Enable Registers"
|
|
width 8.
|
|
group.long 0x340++0x7
|
|
line.long 0x00 "DRAE0,DMA Region Access Enable Register for Region 0"
|
|
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 0" "Not allowed,Allowed"
|
|
line.long 0x04 "DRAEH0,DMA Region Access Enabled Register High for Region 0"
|
|
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 0" "Not allowed,Allowed"
|
|
group.long 0x348++0x7
|
|
line.long 0x00 "DRAE1,DMA Region Access Enable Register for Region 1"
|
|
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 1" "Not allowed,Allowed"
|
|
line.long 0x04 "DRAEH1,DMA Region Access Enabled Register High for Region 1"
|
|
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 1" "Not allowed,Allowed"
|
|
group.long 0x350++0x7
|
|
line.long 0x00 "DRAE2,DMA Region Access Enable Register for Region 2"
|
|
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 2" "Not allowed,Allowed"
|
|
line.long 0x04 "DRAEH2,DMA Region Access Enabled Register High for Region 2"
|
|
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 2" "Not allowed,Allowed"
|
|
group.long 0x358++0x7
|
|
line.long 0x00 "DRAE3,DMA Region Access Enable Register for Region 3"
|
|
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 3" "Not allowed,Allowed"
|
|
line.long 0x04 "DRAEH3,DMA Region Access Enabled Register High for Region 3"
|
|
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 3" "Not allowed,Allowed"
|
|
group.long 0x360++0x7
|
|
line.long 0x00 "DRAE4,DMA Region Access Enable Register for Region 4"
|
|
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 4" "Not allowed,Allowed"
|
|
line.long 0x04 "DRAEH4,DMA Region Access Enabled Register High for Region 4"
|
|
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 4" "Not allowed,Allowed"
|
|
group.long 0x368++0x7
|
|
line.long 0x00 "DRAE5,DMA Region Access Enable Register for Region 5"
|
|
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 5" "Not allowed,Allowed"
|
|
line.long 0x04 "DRAEH5,DMA Region Access Enabled Register High for Region 5"
|
|
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 5" "Not allowed,Allowed"
|
|
group.long 0x370++0x7
|
|
line.long 0x00 "DRAE6,DMA Region Access Enable Register for Region 6"
|
|
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 6" "Not allowed,Allowed"
|
|
line.long 0x04 "DRAEH6,DMA Region Access Enabled Register High for Region 6"
|
|
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 6" "Not allowed,Allowed"
|
|
group.long 0x378++0x7
|
|
line.long 0x00 "DRAE7,DMA Region Access Enable Register for Region 7"
|
|
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 7" "Not allowed,Allowed"
|
|
line.long 0x04 "DRAEH7,DMA Region Access Enabled Register High for Region 7"
|
|
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 7" "Not allowed,Allowed"
|
|
group.long 0x380++0x3
|
|
line.long 0x00 "QRAE0,QDMA Region Access Enable Register for Region 0"
|
|
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 0" "Not allowed,Allowed"
|
|
group.long 0x384++0x3
|
|
line.long 0x00 "QRAE1,QDMA Region Access Enable Register for Region 1"
|
|
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 1" "Not allowed,Allowed"
|
|
group.long 0x388++0x3
|
|
line.long 0x00 "QRAE2,QDMA Region Access Enable Register for Region 2"
|
|
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 2" "Not allowed,Allowed"
|
|
group.long 0x38C++0x3
|
|
line.long 0x00 "QRAE3,QDMA Region Access Enable Register for Region 3"
|
|
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 3" "Not allowed,Allowed"
|
|
group.long 0x390++0x3
|
|
line.long 0x00 "QRAE4,QDMA Region Access Enable Register for Region 4"
|
|
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 4" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 4" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 4" "Not allowed,Allowed"
|
|
group.long 0x394++0x3
|
|
line.long 0x00 "QRAE5,QDMA Region Access Enable Register for Region 5"
|
|
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 5" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 5" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 5" "Not allowed,Allowed"
|
|
group.long 0x398++0x3
|
|
line.long 0x00 "QRAE6,QDMA Region Access Enable Register for Region 6"
|
|
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 6" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 6" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 6" "Not allowed,Allowed"
|
|
group.long 0x39C++0x3
|
|
line.long 0x00 "QRAE7,QDMA Region Access Enable Register for Region 7"
|
|
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 7" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 7" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 7" "Not allowed,Allowed"
|
|
tree.end
|
|
tree "Status/Debug Visibility Registers"
|
|
width 9.
|
|
rgroup.long 0x400++0x3f "Event Queue 0 Registers"
|
|
line.long 0x0 "Q0E0 ,Event Queue Entry 0 Register"
|
|
bitfld.long 0x0 6.--7. " ETYPE ,Event trigger type for entry 0 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x0 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x4 "Q0E1 ,Event Queue Entry 1 Register"
|
|
bitfld.long 0x4 6.--7. " ETYPE ,Event trigger type for entry 1 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x4 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x8 "Q0E2 ,Event Queue Entry 2 Register"
|
|
bitfld.long 0x8 6.--7. " ETYPE ,Event trigger type for entry 2 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x8 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0xC "Q0E3 ,Event Queue Entry 3 Register"
|
|
bitfld.long 0xC 6.--7. " ETYPE ,Event trigger type for entry 3 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0xC 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x10 "Q0E4 ,Event Queue Entry 4 Register"
|
|
bitfld.long 0x10 6.--7. " ETYPE ,Event trigger type for entry 4 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x10 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x14 "Q0E5 ,Event Queue Entry 5 Register"
|
|
bitfld.long 0x14 6.--7. " ETYPE ,Event trigger type for entry 5 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x14 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x18 "Q0E6 ,Event Queue Entry 6 Register"
|
|
bitfld.long 0x18 6.--7. " ETYPE ,Event trigger type for entry 6 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x18 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x1C "Q0E7 ,Event Queue Entry 7 Register"
|
|
bitfld.long 0x1C 6.--7. " ETYPE ,Event trigger type for entry 7 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x1C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x20 "Q0E8 ,Event Queue Entry 8 Register"
|
|
bitfld.long 0x20 6.--7. " ETYPE ,Event trigger type for entry 8 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x20 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x24 "Q0E9 ,Event Queue Entry 9 Register"
|
|
bitfld.long 0x24 6.--7. " ETYPE ,Event trigger type for entry 9 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x24 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x28 "Q0E10,Event Queue Entry 10 Register"
|
|
bitfld.long 0x28 6.--7. " ETYPE ,Event trigger type for entry 10 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x28 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x2C "Q0E11,Event Queue Entry 11 Register"
|
|
bitfld.long 0x2C 6.--7. " ETYPE ,Event trigger type for entry 11 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x2C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x30 "Q0E12,Event Queue Entry 12 Register"
|
|
bitfld.long 0x30 6.--7. " ETYPE ,Event trigger type for entry 12 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x30 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x34 "Q0E13,Event Queue Entry 13 Register"
|
|
bitfld.long 0x34 6.--7. " ETYPE ,Event trigger type for entry 13 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x34 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x38 "Q0E14,Event Queue Entry 14 Register"
|
|
bitfld.long 0x38 6.--7. " ETYPE ,Event trigger type for entry 14 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x38 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x3C "Q0E15,Event Queue Entry 15 Register"
|
|
bitfld.long 0x3C 6.--7. " ETYPE ,Event trigger type for entry 15 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x3C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
rgroup.long 0x440++0x3f "Event Queue 1 Registers"
|
|
line.long 0x0 "Q1E0 ,Event Queue Entry 0 Register"
|
|
bitfld.long 0x0 6.--7. " ETYPE ,Event trigger type for entry 0 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x0 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x4 "Q1E1 ,Event Queue Entry 1 Register"
|
|
bitfld.long 0x4 6.--7. " ETYPE ,Event trigger type for entry 1 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x4 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x8 "Q1E2 ,Event Queue Entry 2 Register"
|
|
bitfld.long 0x8 6.--7. " ETYPE ,Event trigger type for entry 2 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x8 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0xC "Q1E3 ,Event Queue Entry 3 Register"
|
|
bitfld.long 0xC 6.--7. " ETYPE ,Event trigger type for entry 3 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0xC 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x10 "Q1E4 ,Event Queue Entry 4 Register"
|
|
bitfld.long 0x10 6.--7. " ETYPE ,Event trigger type for entry 4 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x10 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x14 "Q1E5 ,Event Queue Entry 5 Register"
|
|
bitfld.long 0x14 6.--7. " ETYPE ,Event trigger type for entry 5 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x14 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x18 "Q1E6 ,Event Queue Entry 6 Register"
|
|
bitfld.long 0x18 6.--7. " ETYPE ,Event trigger type for entry 6 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x18 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
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|
line.long 0x1C "Q1E7 ,Event Queue Entry 7 Register"
|
|
bitfld.long 0x1C 6.--7. " ETYPE ,Event trigger type for entry 7 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
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|
bitfld.long 0x1C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
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|
line.long 0x20 "Q1E8 ,Event Queue Entry 8 Register"
|
|
bitfld.long 0x20 6.--7. " ETYPE ,Event trigger type for entry 8 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
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|
bitfld.long 0x20 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
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|
line.long 0x24 "Q1E9 ,Event Queue Entry 9 Register"
|
|
bitfld.long 0x24 6.--7. " ETYPE ,Event trigger type for entry 9 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
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|
bitfld.long 0x24 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
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|
line.long 0x28 "Q1E10,Event Queue Entry 10 Register"
|
|
bitfld.long 0x28 6.--7. " ETYPE ,Event trigger type for entry 10 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
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|
bitfld.long 0x28 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
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|
line.long 0x2C "Q1E11,Event Queue Entry 11 Register"
|
|
bitfld.long 0x2C 6.--7. " ETYPE ,Event trigger type for entry 11 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
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|
bitfld.long 0x2C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
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|
line.long 0x30 "Q1E12,Event Queue Entry 12 Register"
|
|
bitfld.long 0x30 6.--7. " ETYPE ,Event trigger type for entry 12 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
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|
bitfld.long 0x30 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x34 "Q1E13,Event Queue Entry 13 Register"
|
|
bitfld.long 0x34 6.--7. " ETYPE ,Event trigger type for entry 13 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x34 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x38 "Q1E14,Event Queue Entry 14 Register"
|
|
bitfld.long 0x38 6.--7. " ETYPE ,Event trigger type for entry 14 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x38 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x3C "Q1E15,Event Queue Entry 15 Register"
|
|
bitfld.long 0x3C 6.--7. " ETYPE ,Event trigger type for entry 15 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x3C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
rgroup.long 0x480++0x3f "Event Queue 2 Registers"
|
|
line.long 0x0 "Q2E0 ,Event Queue Entry 0 Register"
|
|
bitfld.long 0x0 6.--7. " ETYPE ,Event trigger type for entry 0 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
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|
bitfld.long 0x0 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x4 "Q2E1 ,Event Queue Entry 1 Register"
|
|
bitfld.long 0x4 6.--7. " ETYPE ,Event trigger type for entry 1 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x4 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x8 "Q2E2 ,Event Queue Entry 2 Register"
|
|
bitfld.long 0x8 6.--7. " ETYPE ,Event trigger type for entry 2 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
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|
bitfld.long 0x8 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0xC "Q2E3 ,Event Queue Entry 3 Register"
|
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bitfld.long 0xC 6.--7. " ETYPE ,Event trigger type for entry 3 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
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|
bitfld.long 0xC 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x10 "Q2E4 ,Event Queue Entry 4 Register"
|
|
bitfld.long 0x10 6.--7. " ETYPE ,Event trigger type for entry 4 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
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|
bitfld.long 0x10 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x14 "Q2E5 ,Event Queue Entry 5 Register"
|
|
bitfld.long 0x14 6.--7. " ETYPE ,Event trigger type for entry 5 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x14 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x18 "Q2E6 ,Event Queue Entry 6 Register"
|
|
bitfld.long 0x18 6.--7. " ETYPE ,Event trigger type for entry 6 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x18 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x1C "Q2E7 ,Event Queue Entry 7 Register"
|
|
bitfld.long 0x1C 6.--7. " ETYPE ,Event trigger type for entry 7 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x1C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x20 "Q2E8 ,Event Queue Entry 8 Register"
|
|
bitfld.long 0x20 6.--7. " ETYPE ,Event trigger type for entry 8 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x20 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x24 "Q2E9 ,Event Queue Entry 9 Register"
|
|
bitfld.long 0x24 6.--7. " ETYPE ,Event trigger type for entry 9 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x24 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x28 "Q2E10,Event Queue Entry 10 Register"
|
|
bitfld.long 0x28 6.--7. " ETYPE ,Event trigger type for entry 10 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x28 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x2C "Q2E11,Event Queue Entry 11 Register"
|
|
bitfld.long 0x2C 6.--7. " ETYPE ,Event trigger type for entry 11 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x2C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x30 "Q2E12,Event Queue Entry 12 Register"
|
|
bitfld.long 0x30 6.--7. " ETYPE ,Event trigger type for entry 12 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x30 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x34 "Q2E13,Event Queue Entry 13 Register"
|
|
bitfld.long 0x34 6.--7. " ETYPE ,Event trigger type for entry 13 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x34 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x38 "Q2E14,Event Queue Entry 14 Register"
|
|
bitfld.long 0x38 6.--7. " ETYPE ,Event trigger type for entry 14 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x38 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x3C "Q2E15,Event Queue Entry 15 Register"
|
|
bitfld.long 0x3C 6.--7. " ETYPE ,Event trigger type for entry 15 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x3C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
rgroup.long 0x4C0++0x3f "Event Queue 3 Registers"
|
|
line.long 0x0 "Q3E0 ,Event Queue Entry 0 Register"
|
|
bitfld.long 0x0 6.--7. " ETYPE ,Event trigger type for entry 0 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x0 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x4 "Q3E1 ,Event Queue Entry 1 Register"
|
|
bitfld.long 0x4 6.--7. " ETYPE ,Event trigger type for entry 1 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x4 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x8 "Q3E2 ,Event Queue Entry 2 Register"
|
|
bitfld.long 0x8 6.--7. " ETYPE ,Event trigger type for entry 2 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x8 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0xC "Q3E3 ,Event Queue Entry 3 Register"
|
|
bitfld.long 0xC 6.--7. " ETYPE ,Event trigger type for entry 3 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0xC 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x10 "Q3E4 ,Event Queue Entry 4 Register"
|
|
bitfld.long 0x10 6.--7. " ETYPE ,Event trigger type for entry 4 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x10 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x14 "Q3E5 ,Event Queue Entry 5 Register"
|
|
bitfld.long 0x14 6.--7. " ETYPE ,Event trigger type for entry 5 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x14 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x18 "Q3E6 ,Event Queue Entry 6 Register"
|
|
bitfld.long 0x18 6.--7. " ETYPE ,Event trigger type for entry 6 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x18 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x1C "Q3E7 ,Event Queue Entry 7 Register"
|
|
bitfld.long 0x1C 6.--7. " ETYPE ,Event trigger type for entry 7 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x1C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x20 "Q3E8 ,Event Queue Entry 8 Register"
|
|
bitfld.long 0x20 6.--7. " ETYPE ,Event trigger type for entry 8 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x20 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x24 "Q3E9 ,Event Queue Entry 9 Register"
|
|
bitfld.long 0x24 6.--7. " ETYPE ,Event trigger type for entry 9 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x24 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x28 "Q3E10,Event Queue Entry 10 Register"
|
|
bitfld.long 0x28 6.--7. " ETYPE ,Event trigger type for entry 10 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x28 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x2C "Q3E11,Event Queue Entry 11 Register"
|
|
bitfld.long 0x2C 6.--7. " ETYPE ,Event trigger type for entry 11 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x2C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x30 "Q3E12,Event Queue Entry 12 Register"
|
|
bitfld.long 0x30 6.--7. " ETYPE ,Event trigger type for entry 12 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x30 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x34 "Q3E13,Event Queue Entry 13 Register"
|
|
bitfld.long 0x34 6.--7. " ETYPE ,Event trigger type for entry 13 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x34 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x38 "Q3E14,Event Queue Entry 14 Register"
|
|
bitfld.long 0x38 6.--7. " ETYPE ,Event trigger type for entry 14 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x38 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
line.long 0x3C "Q3E15,Event Queue Entry 15 Register"
|
|
bitfld.long 0x3C 6.--7. " ETYPE ,Event trigger type for entry 15 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
bitfld.long 0x3C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
width 9.
|
|
rgroup.long 0x600++0xB "Queue Status Registers"
|
|
line.long 0x0 "QSTAT0,Queue 0 Status Register"
|
|
bitfld.long 0x0 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
|
|
bitfld.long 0x0 16.--20. " WM ,Watermark" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..."
|
|
bitfld.long 0x0 8.--12. " NUMVAL ,Number of valid entrier in queue 0" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..."
|
|
bitfld.long 0x0 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "QSTAT1,Queue 1 Status Register"
|
|
bitfld.long 0x4 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
|
|
bitfld.long 0x4 16.--20. " WM ,Watermark" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..."
|
|
bitfld.long 0x4 8.--12. " NUMVAL ,Number of valid entrier in queue 1" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..."
|
|
bitfld.long 0x4 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "QSTAT2,Queue 2 Status Register"
|
|
bitfld.long 0x8 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
|
|
bitfld.long 0x8 16.--20. " WM ,Watermark" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..."
|
|
bitfld.long 0x8 8.--12. " NUMVAL ,Number of valid entrier in queue 2" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..."
|
|
bitfld.long 0x8 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpuis("DRA62*"))
|
|
rgroup.long 0x60C++0x3
|
|
line.long 0x00 "QSTAT3,Queue 3 Status Register"
|
|
bitfld.long 0x00 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 16.--20. " WM ,Watermark" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..."
|
|
bitfld.long 0x00 8.--12. " NUMVAL ,Number of valid entrier in queue $2" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..."
|
|
bitfld.long 0x00 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 9.
|
|
group.long 0x620++0x3
|
|
line.long 0x00 "QWMTHRA,Queue Watermark Threshold A Register"
|
|
bitfld.long 0x00 24.--28. " Q3 ,Queue threshold for queue 3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Disabled,?..."
|
|
bitfld.long 0x00 16.--20. " Q2 ,Queue threshold for queue 2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Disabled,?..."
|
|
bitfld.long 0x00 8.--12. " Q1 ,Queue threshold for queue 1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Disabled,?..."
|
|
bitfld.long 0x00 0.--4. " Q0 ,Queue threshold for queue 0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Disabled,?..."
|
|
rgroup.long 0x640++0x3
|
|
line.long 0x00 "CCSTAT,EDMA3CC Status Register"
|
|
bitfld.long 0x00 19. " QUEACTV3 ,Queue 3 active" "Not active,Active"
|
|
bitfld.long 0x00 18. " QUEACTV2 ,Queue 2 active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 17. " QUEACTV1 ,Queue 1 active" "Not active,Active"
|
|
bitfld.long 0x00 16. " QUEACTV0 ,Queue 0 active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " COMPACTV ,Completion request active" "No requests,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4. " ACTV ,Channel controller active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TRACTV ,Transfer request active" "Not active,Active"
|
|
bitfld.long 0x00 1. " QEVTACTV ,QDMA event active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EVTACTV ,DMA event active" "Not active,Active"
|
|
tree.end
|
|
tree "Memory Protection Address Space"
|
|
width 7.
|
|
rgroup.long 0x800++0x7
|
|
line.long 0x00 "MPFAR,Memory Protection Fault Address Register"
|
|
line.long 0x04 "MPFSR,Memory Protection Fault Status Register"
|
|
hexmask.long.byte 0x04 9.--12. 1. " FID ,Faulted identification"
|
|
bitfld.long 0x04 5. " SRE ,Supervisor read error" "No error,Error"
|
|
bitfld.long 0x04 4. " SWE ,Supervisor write error" "No error,Error"
|
|
bitfld.long 0x04 3. " SXE ,Supervisor execute error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 2. " URE ,User read error" "No error,Error"
|
|
bitfld.long 0x04 1. " UWE ,User write error" "No error,Error"
|
|
bitfld.long 0x04 0. " UXE ,User execute error" "No error,Error"
|
|
wgroup.long 0x808++0x3
|
|
line.long 0x00 "MPFCR,Memory Protection Fault Command Register"
|
|
bitfld.long 0x00 0. " MPFCLR ,Fault clear register" "No effect,Clear"
|
|
sif (!cpuis("AM335*"))
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "MPPAG,Memory Protection Page Attribute Register Global"
|
|
bitfld.long 0x00 15. " AID5 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x00 14. " AID4 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x00 13. " AID3 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x00 12. " AID2 ,Allowed ID" "Not allowed,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AID1 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x00 10. " AID0 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x00 9. " EXT ,External allowed ID" "Not allowed,Permited"
|
|
bitfld.long 0x00 5. " SR ,Supervisor read permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " UR ,User read permission" "Not allowed,Allowed"
|
|
bitfld.long 0x00 1. " UW ,User write permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UX ,User execute permission" "Not allowed,Allowed"
|
|
endif
|
|
group.long 0x810++0x1f
|
|
line.long 0x0 "MPPA0,Memory Protection Page Attribute Register 0"
|
|
bitfld.long 0x0 15. " AID5 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x0 14. " AID4 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x0 13. " AID3 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x0 12. " AID2 ,Allowed ID" "Not allowed,Permitted"
|
|
textline " "
|
|
bitfld.long 0x0 11. " AID1 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x0 10. " AID0 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x0 9. " EXT ,External allowed ID" "Not allowed,Permited"
|
|
bitfld.long 0x0 5. " SR ,Supervisor read permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x0 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
|
|
bitfld.long 0x0 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
|
|
bitfld.long 0x0 2. " UR ,User read permission" "Not allowed,Allowed"
|
|
bitfld.long 0x0 1. " UW ,User write permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x0 0. " UX ,User execute permission" "Not allowed,Allowed"
|
|
line.long 0x4 "MPPA1,Memory Protection Page Attribute Register 1"
|
|
bitfld.long 0x4 15. " AID5 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x4 14. " AID4 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x4 13. " AID3 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x4 12. " AID2 ,Allowed ID" "Not allowed,Permitted"
|
|
textline " "
|
|
bitfld.long 0x4 11. " AID1 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x4 10. " AID0 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x4 9. " EXT ,External allowed ID" "Not allowed,Permited"
|
|
bitfld.long 0x4 5. " SR ,Supervisor read permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x4 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
|
|
bitfld.long 0x4 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
|
|
bitfld.long 0x4 2. " UR ,User read permission" "Not allowed,Allowed"
|
|
bitfld.long 0x4 1. " UW ,User write permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " UX ,User execute permission" "Not allowed,Allowed"
|
|
line.long 0x8 "MPPA2,Memory Protection Page Attribute Register 2"
|
|
bitfld.long 0x8 15. " AID5 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x8 14. " AID4 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x8 13. " AID3 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x8 12. " AID2 ,Allowed ID" "Not allowed,Permitted"
|
|
textline " "
|
|
bitfld.long 0x8 11. " AID1 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x8 10. " AID0 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x8 9. " EXT ,External allowed ID" "Not allowed,Permited"
|
|
bitfld.long 0x8 5. " SR ,Supervisor read permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x8 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
|
|
bitfld.long 0x8 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
|
|
bitfld.long 0x8 2. " UR ,User read permission" "Not allowed,Allowed"
|
|
bitfld.long 0x8 1. " UW ,User write permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " UX ,User execute permission" "Not allowed,Allowed"
|
|
line.long 0xC "MPPA3,Memory Protection Page Attribute Register 3"
|
|
bitfld.long 0xC 15. " AID5 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0xC 14. " AID4 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0xC 13. " AID3 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0xC 12. " AID2 ,Allowed ID" "Not allowed,Permitted"
|
|
textline " "
|
|
bitfld.long 0xC 11. " AID1 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0xC 10. " AID0 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0xC 9. " EXT ,External allowed ID" "Not allowed,Permited"
|
|
bitfld.long 0xC 5. " SR ,Supervisor read permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0xC 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
|
|
bitfld.long 0xC 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
|
|
bitfld.long 0xC 2. " UR ,User read permission" "Not allowed,Allowed"
|
|
bitfld.long 0xC 1. " UW ,User write permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " UX ,User execute permission" "Not allowed,Allowed"
|
|
line.long 0x10 "MPPA4,Memory Protection Page Attribute Register 4"
|
|
bitfld.long 0x10 15. " AID5 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x10 14. " AID4 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x10 13. " AID3 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x10 12. " AID2 ,Allowed ID" "Not allowed,Permitted"
|
|
textline " "
|
|
bitfld.long 0x10 11. " AID1 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x10 10. " AID0 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x10 9. " EXT ,External allowed ID" "Not allowed,Permited"
|
|
bitfld.long 0x10 5. " SR ,Supervisor read permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x10 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
|
|
bitfld.long 0x10 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
|
|
bitfld.long 0x10 2. " UR ,User read permission" "Not allowed,Allowed"
|
|
bitfld.long 0x10 1. " UW ,User write permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x10 0. " UX ,User execute permission" "Not allowed,Allowed"
|
|
line.long 0x14 "MPPA5,Memory Protection Page Attribute Register 5"
|
|
bitfld.long 0x14 15. " AID5 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x14 14. " AID4 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x14 13. " AID3 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x14 12. " AID2 ,Allowed ID" "Not allowed,Permitted"
|
|
textline " "
|
|
bitfld.long 0x14 11. " AID1 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x14 10. " AID0 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x14 9. " EXT ,External allowed ID" "Not allowed,Permited"
|
|
bitfld.long 0x14 5. " SR ,Supervisor read permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x14 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
|
|
bitfld.long 0x14 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
|
|
bitfld.long 0x14 2. " UR ,User read permission" "Not allowed,Allowed"
|
|
bitfld.long 0x14 1. " UW ,User write permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x14 0. " UX ,User execute permission" "Not allowed,Allowed"
|
|
line.long 0x18 "MPPA6,Memory Protection Page Attribute Register 6"
|
|
bitfld.long 0x18 15. " AID5 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x18 14. " AID4 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x18 13. " AID3 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x18 12. " AID2 ,Allowed ID" "Not allowed,Permitted"
|
|
textline " "
|
|
bitfld.long 0x18 11. " AID1 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x18 10. " AID0 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x18 9. " EXT ,External allowed ID" "Not allowed,Permited"
|
|
bitfld.long 0x18 5. " SR ,Supervisor read permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x18 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
|
|
bitfld.long 0x18 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
|
|
bitfld.long 0x18 2. " UR ,User read permission" "Not allowed,Allowed"
|
|
bitfld.long 0x18 1. " UW ,User write permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x18 0. " UX ,User execute permission" "Not allowed,Allowed"
|
|
line.long 0x1C "MPPA7,Memory Protection Page Attribute Register 7"
|
|
bitfld.long 0x1C 15. " AID5 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x1C 14. " AID4 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x1C 13. " AID3 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x1C 12. " AID2 ,Allowed ID" "Not allowed,Permitted"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " AID1 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x1C 10. " AID0 ,Allowed ID" "Not allowed,Permitted"
|
|
bitfld.long 0x1C 9. " EXT ,External allowed ID" "Not allowed,Permited"
|
|
bitfld.long 0x1C 5. " SR ,Supervisor read permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
|
|
bitfld.long 0x1C 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
|
|
bitfld.long 0x1C 2. " UR ,User read permission" "Not allowed,Allowed"
|
|
bitfld.long 0x1C 1. " UW ,User write permission" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " UX ,User execute permission" "Not allowed,Allowed"
|
|
tree.end
|
|
tree "DMA Channel Registers"
|
|
width 7.
|
|
group.long 0x1000++0x7
|
|
line.long 0x00 "ER,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted"
|
|
line.long 0x04 "ERH,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted"
|
|
rgroup.long 0x1018++0x7
|
|
line.long 0x00 "CER,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized"
|
|
bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized"
|
|
bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized"
|
|
bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized"
|
|
bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized"
|
|
bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized"
|
|
bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized"
|
|
bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized"
|
|
bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized"
|
|
bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized"
|
|
bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized"
|
|
bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized"
|
|
bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized"
|
|
bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized"
|
|
bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized"
|
|
bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized"
|
|
bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized"
|
|
bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized"
|
|
line.long 0x04 "CERH,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized"
|
|
bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized"
|
|
bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized"
|
|
bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized"
|
|
bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized"
|
|
bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized"
|
|
bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized"
|
|
bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized"
|
|
bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized"
|
|
bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized"
|
|
bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized"
|
|
bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized"
|
|
bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized"
|
|
bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized"
|
|
bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized"
|
|
bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized"
|
|
bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized"
|
|
bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized"
|
|
bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized"
|
|
bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized"
|
|
bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized"
|
|
bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized"
|
|
group.long 0x1020++0x7
|
|
line.long 0x00 "EER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled"
|
|
rgroup.long 0x1038++0x7
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored"
|
|
line.long 0x04 "SERH,Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored"
|
|
wgroup.long 0x1040++0x7
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear"
|
|
line.long 0x04 "SECRH,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear"
|
|
tree.end
|
|
tree "Interrupt Registers"
|
|
width 7.
|
|
group.long 0x1050++0x7
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "IERH,Interrupt Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " I63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " I62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " I61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " I60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " I59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " I58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " I57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " I56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " I55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " I54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " I53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " I52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " I51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " I50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " I49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " I48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " I47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " I46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " I45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " I44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " I43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " I42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " I41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " I40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " I39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " I38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " I37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " I36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " I35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " I34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " I33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " I32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled"
|
|
rgroup.long 0x1068++0x7
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected"
|
|
line.long 0x04 "IPRH,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected"
|
|
wgroup.long 0x1070++0x7
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear"
|
|
line.long 0x04 "ICRH,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
|
|
bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulsed"
|
|
tree.end
|
|
tree "QDMA Registers"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
|
|
group.long 0x1084++0x3
|
|
line.long 0x00 "QEER,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored"
|
|
wgroup.long 0x1094++0x3
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear"
|
|
tree.end
|
|
sif (!cpuis("AM335*"))
|
|
tree "Shadow Region 0 Channel Registers"
|
|
tree "DMA Channel Registers"
|
|
width 7.
|
|
group.long (0x2000+0x0)++0x7
|
|
line.long 0x00 "ER,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted"
|
|
line.long 0x04 "ERH,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted"
|
|
rgroup.long (0x2018+0x0)++0x7
|
|
line.long 0x00 "ECR,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized"
|
|
bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized"
|
|
bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized"
|
|
bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized"
|
|
bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized"
|
|
bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized"
|
|
bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized"
|
|
bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized"
|
|
bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized"
|
|
bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized"
|
|
bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized"
|
|
bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized"
|
|
bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized"
|
|
bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized"
|
|
bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized"
|
|
bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized"
|
|
bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized"
|
|
bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized"
|
|
line.long 0x04 "ECRH,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized"
|
|
bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized"
|
|
bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized"
|
|
bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized"
|
|
bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized"
|
|
bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized"
|
|
bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized"
|
|
bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized"
|
|
bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized"
|
|
bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized"
|
|
bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized"
|
|
bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized"
|
|
bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized"
|
|
bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized"
|
|
bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized"
|
|
bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized"
|
|
bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized"
|
|
bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized"
|
|
bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized"
|
|
bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized"
|
|
bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized"
|
|
bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized"
|
|
group.long (0x2020+0x0)++0x7
|
|
line.long 0x00 "EER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled"
|
|
rgroup.long (0x2038+0x0)++0x7
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored"
|
|
line.long 0x04 "SERH,Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored"
|
|
wgroup.long (0x2040+0x0)++0x7
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear"
|
|
line.long 0x04 "SECRH,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear"
|
|
tree.end
|
|
tree "Interrupt Registers"
|
|
width 7.
|
|
group.long (0x2050+0x0)++0x7
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "IERH,Interrupt Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled"
|
|
rgroup.long (0x2068+0x0)++0x7
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected"
|
|
line.long 0x04 "IPRH,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected"
|
|
wgroup.long (0x2070+0x0)++0x7
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear"
|
|
line.long 0x04 "ICRH,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear"
|
|
wgroup.long (0x2078+0x0)++0x3
|
|
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
|
|
bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse"
|
|
tree.end
|
|
tree "QDMA Registers"
|
|
rgroup.long (0x2080+0x0)++0x3
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
|
|
group.long (0x2084+0x0)++0x3
|
|
line.long 0x00 "QEER,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x2090+0x0)++0x3
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored"
|
|
wgroup.long (0x2094+0x0)++0x3
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear"
|
|
tree.end
|
|
tree.end
|
|
tree "Shadow Region 1 Channel Registers"
|
|
tree "DMA Channel Registers"
|
|
width 7.
|
|
group.long (0x2000+0x200)++0x7
|
|
line.long 0x00 "ER,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted"
|
|
line.long 0x04 "ERH,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted"
|
|
rgroup.long (0x2018+0x200)++0x7
|
|
line.long 0x00 "ECR,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized"
|
|
bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized"
|
|
bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized"
|
|
bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized"
|
|
bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized"
|
|
bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized"
|
|
bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized"
|
|
bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized"
|
|
bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized"
|
|
bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized"
|
|
bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized"
|
|
bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized"
|
|
bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized"
|
|
bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized"
|
|
bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized"
|
|
bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized"
|
|
bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized"
|
|
bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized"
|
|
line.long 0x04 "ECRH,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized"
|
|
bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized"
|
|
bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized"
|
|
bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized"
|
|
bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized"
|
|
bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized"
|
|
bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized"
|
|
bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized"
|
|
bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized"
|
|
bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized"
|
|
bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized"
|
|
bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized"
|
|
bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized"
|
|
bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized"
|
|
bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized"
|
|
bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized"
|
|
bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized"
|
|
bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized"
|
|
bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized"
|
|
bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized"
|
|
bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized"
|
|
bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized"
|
|
group.long (0x2020+0x200)++0x7
|
|
line.long 0x00 "EER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled"
|
|
rgroup.long (0x2038+0x200)++0x7
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored"
|
|
line.long 0x04 "SERH,Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored"
|
|
wgroup.long (0x2040+0x200)++0x7
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear"
|
|
line.long 0x04 "SECRH,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear"
|
|
tree.end
|
|
tree "Interrupt Registers"
|
|
width 7.
|
|
group.long (0x2050+0x200)++0x7
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "IERH,Interrupt Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled"
|
|
rgroup.long (0x2068+0x200)++0x7
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected"
|
|
line.long 0x04 "IPRH,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected"
|
|
wgroup.long (0x2070+0x200)++0x7
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear"
|
|
line.long 0x04 "ICRH,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear"
|
|
wgroup.long (0x2078+0x200)++0x3
|
|
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
|
|
bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse"
|
|
tree.end
|
|
tree "QDMA Registers"
|
|
rgroup.long (0x2080+0x200)++0x3
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
|
|
group.long (0x2084+0x200)++0x3
|
|
line.long 0x00 "QEER,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x2090+0x200)++0x3
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored"
|
|
wgroup.long (0x2094+0x200)++0x3
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear"
|
|
tree.end
|
|
tree.end
|
|
tree "Shadow Region 2 Channel Registers"
|
|
tree "DMA Channel Registers"
|
|
width 7.
|
|
group.long (0x2000+0x400)++0x7
|
|
line.long 0x00 "ER,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted"
|
|
line.long 0x04 "ERH,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted"
|
|
rgroup.long (0x2018+0x400)++0x7
|
|
line.long 0x00 "ECR,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized"
|
|
bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized"
|
|
bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized"
|
|
bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized"
|
|
bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized"
|
|
bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized"
|
|
bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized"
|
|
bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized"
|
|
bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized"
|
|
bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized"
|
|
bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized"
|
|
bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized"
|
|
bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized"
|
|
bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized"
|
|
bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized"
|
|
bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized"
|
|
bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized"
|
|
bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized"
|
|
line.long 0x04 "ECRH,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized"
|
|
bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized"
|
|
bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized"
|
|
bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized"
|
|
bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized"
|
|
bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized"
|
|
bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized"
|
|
bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized"
|
|
bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized"
|
|
bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized"
|
|
bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized"
|
|
bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized"
|
|
bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized"
|
|
bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized"
|
|
bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized"
|
|
bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized"
|
|
bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized"
|
|
bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized"
|
|
bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized"
|
|
bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized"
|
|
bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized"
|
|
bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized"
|
|
group.long (0x2020+0x400)++0x7
|
|
line.long 0x00 "EER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled"
|
|
rgroup.long (0x2038+0x400)++0x7
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored"
|
|
line.long 0x04 "SERH,Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored"
|
|
wgroup.long (0x2040+0x400)++0x7
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear"
|
|
line.long 0x04 "SECRH,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear"
|
|
tree.end
|
|
tree "Interrupt Registers"
|
|
width 7.
|
|
group.long (0x2050+0x400)++0x7
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "IERH,Interrupt Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled"
|
|
rgroup.long (0x2068+0x400)++0x7
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected"
|
|
line.long 0x04 "IPRH,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected"
|
|
wgroup.long (0x2070+0x400)++0x7
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear"
|
|
line.long 0x04 "ICRH,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear"
|
|
wgroup.long (0x2078+0x400)++0x3
|
|
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
|
|
bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse"
|
|
tree.end
|
|
tree "QDMA Registers"
|
|
rgroup.long (0x2080+0x400)++0x3
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
|
|
group.long (0x2084+0x400)++0x3
|
|
line.long 0x00 "QEER,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x2090+0x400)++0x3
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored"
|
|
wgroup.long (0x2094+0x400)++0x3
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear"
|
|
tree.end
|
|
tree.end
|
|
tree "Shadow Region 3 Channel Registers"
|
|
tree "DMA Channel Registers"
|
|
width 7.
|
|
group.long (0x2000+0x600)++0x7
|
|
line.long 0x00 "ER,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted"
|
|
line.long 0x04 "ERH,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted"
|
|
rgroup.long (0x2018+0x600)++0x7
|
|
line.long 0x00 "ECR,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized"
|
|
bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized"
|
|
bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized"
|
|
bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized"
|
|
bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized"
|
|
bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized"
|
|
bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized"
|
|
bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized"
|
|
bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized"
|
|
bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized"
|
|
bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized"
|
|
bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized"
|
|
bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized"
|
|
bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized"
|
|
bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized"
|
|
bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized"
|
|
bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized"
|
|
bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized"
|
|
line.long 0x04 "ECRH,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized"
|
|
bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized"
|
|
bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized"
|
|
bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized"
|
|
bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized"
|
|
bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized"
|
|
bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized"
|
|
bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized"
|
|
bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized"
|
|
bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized"
|
|
bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized"
|
|
bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized"
|
|
bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized"
|
|
bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized"
|
|
bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized"
|
|
bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized"
|
|
bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized"
|
|
bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized"
|
|
bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized"
|
|
bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized"
|
|
bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized"
|
|
bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized"
|
|
group.long (0x2020+0x600)++0x7
|
|
line.long 0x00 "EER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled"
|
|
rgroup.long (0x2038+0x600)++0x7
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored"
|
|
line.long 0x04 "SERH,Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored"
|
|
wgroup.long (0x2040+0x600)++0x7
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear"
|
|
line.long 0x04 "SECRH,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear"
|
|
tree.end
|
|
tree "Interrupt Registers"
|
|
width 7.
|
|
group.long (0x2050+0x600)++0x7
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "IERH,Interrupt Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled"
|
|
rgroup.long (0x2068+0x600)++0x7
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected"
|
|
line.long 0x04 "IPRH,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected"
|
|
wgroup.long (0x2070+0x600)++0x7
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear"
|
|
line.long 0x04 "ICRH,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear"
|
|
wgroup.long (0x2078+0x600)++0x3
|
|
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
|
|
bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse"
|
|
tree.end
|
|
tree "QDMA Registers"
|
|
rgroup.long (0x2080+0x600)++0x3
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
|
|
group.long (0x2084+0x600)++0x3
|
|
line.long 0x00 "QEER,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x2090+0x600)++0x3
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored"
|
|
wgroup.long (0x2094+0x600)++0x3
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear"
|
|
tree.end
|
|
tree.end
|
|
tree "Shadow Region 4 Channel Registers"
|
|
tree "DMA Channel Registers"
|
|
width 7.
|
|
group.long (0x2000+0x800)++0x7
|
|
line.long 0x00 "ER,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted"
|
|
line.long 0x04 "ERH,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted"
|
|
rgroup.long (0x2018+0x800)++0x7
|
|
line.long 0x00 "ECR,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized"
|
|
bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized"
|
|
bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized"
|
|
bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized"
|
|
bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized"
|
|
bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized"
|
|
bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized"
|
|
bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized"
|
|
bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized"
|
|
bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized"
|
|
bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized"
|
|
bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized"
|
|
bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized"
|
|
bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized"
|
|
bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized"
|
|
bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized"
|
|
bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized"
|
|
bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized"
|
|
line.long 0x04 "ECRH,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized"
|
|
bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized"
|
|
bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized"
|
|
bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized"
|
|
bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized"
|
|
bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized"
|
|
bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized"
|
|
bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized"
|
|
bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized"
|
|
bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized"
|
|
bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized"
|
|
bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized"
|
|
bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized"
|
|
bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized"
|
|
bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized"
|
|
bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized"
|
|
bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized"
|
|
bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized"
|
|
bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized"
|
|
bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized"
|
|
bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized"
|
|
bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized"
|
|
group.long (0x2020+0x800)++0x7
|
|
line.long 0x00 "EER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled"
|
|
rgroup.long (0x2038+0x800)++0x7
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored"
|
|
line.long 0x04 "SERH,Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored"
|
|
wgroup.long (0x2040+0x800)++0x7
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear"
|
|
line.long 0x04 "SECRH,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear"
|
|
tree.end
|
|
tree "Interrupt Registers"
|
|
width 7.
|
|
group.long (0x2050+0x800)++0x7
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "IERH,Interrupt Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled"
|
|
rgroup.long (0x2068+0x800)++0x7
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected"
|
|
line.long 0x04 "IPRH,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected"
|
|
wgroup.long (0x2070+0x800)++0x7
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear"
|
|
line.long 0x04 "ICRH,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear"
|
|
wgroup.long (0x2078+0x800)++0x3
|
|
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
|
|
bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse"
|
|
tree.end
|
|
tree "QDMA Registers"
|
|
rgroup.long (0x2080+0x800)++0x3
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
|
|
group.long (0x2084+0x800)++0x3
|
|
line.long 0x00 "QEER,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x2090+0x800)++0x3
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored"
|
|
wgroup.long (0x2094+0x800)++0x3
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear"
|
|
tree.end
|
|
tree.end
|
|
tree "Shadow Region 5 Channel Registers"
|
|
tree "DMA Channel Registers"
|
|
width 7.
|
|
group.long (0x2000+0xA00)++0x7
|
|
line.long 0x00 "ER,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted"
|
|
line.long 0x04 "ERH,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted"
|
|
rgroup.long (0x2018+0xA00)++0x7
|
|
line.long 0x00 "ECR,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized"
|
|
bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized"
|
|
bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized"
|
|
bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized"
|
|
bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized"
|
|
bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized"
|
|
bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized"
|
|
bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized"
|
|
bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized"
|
|
bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized"
|
|
bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized"
|
|
bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized"
|
|
bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized"
|
|
bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized"
|
|
bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized"
|
|
bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized"
|
|
bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized"
|
|
bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized"
|
|
line.long 0x04 "ECRH,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized"
|
|
bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized"
|
|
bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized"
|
|
bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized"
|
|
bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized"
|
|
bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized"
|
|
bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized"
|
|
bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized"
|
|
bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized"
|
|
bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized"
|
|
bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized"
|
|
bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized"
|
|
bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized"
|
|
bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized"
|
|
bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized"
|
|
bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized"
|
|
bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized"
|
|
bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized"
|
|
bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized"
|
|
bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized"
|
|
bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized"
|
|
bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized"
|
|
group.long (0x2020+0xA00)++0x7
|
|
line.long 0x00 "EER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled"
|
|
rgroup.long (0x2038+0xA00)++0x7
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored"
|
|
line.long 0x04 "SERH,Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored"
|
|
wgroup.long (0x2040+0xA00)++0x7
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear"
|
|
line.long 0x04 "SECRH,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear"
|
|
tree.end
|
|
tree "Interrupt Registers"
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width 7.
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group.long (0x2050+0xA00)++0x7
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line.long 0x00 "IER,Interrupt Enable Register"
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setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled"
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setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled"
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setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled"
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setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled"
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setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled"
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setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled"
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line.long 0x04 "IERH,Interrupt Enable Register High"
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setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled"
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setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled"
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setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled"
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setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled"
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setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled"
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setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled"
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setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled"
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setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled"
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setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled"
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setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled"
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setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled"
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setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled"
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setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled"
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setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled"
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setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled"
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setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled"
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setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled"
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rgroup.long (0x2068+0xA00)++0x7
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line.long 0x00 "IPR,Interrupt Pending Register"
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bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected"
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bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected"
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bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected"
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bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected"
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bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected"
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bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected"
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bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected"
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bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected"
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bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected"
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bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected"
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bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected"
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bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected"
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bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected"
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bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected"
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bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected"
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bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected"
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bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected"
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line.long 0x04 "IPRH,Interrupt Pending Register High"
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bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected"
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bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected"
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bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected"
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bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected"
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bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected"
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bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected"
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bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected"
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bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected"
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bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected"
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bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected"
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bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected"
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bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected"
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bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected"
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bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected"
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bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected"
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bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected"
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textline " "
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bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected"
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bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected"
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wgroup.long (0x2070+0xA00)++0x7
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line.long 0x00 "ICR,Interrupt Clear Register"
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bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear"
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bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear"
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textline " "
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bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear"
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bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear"
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textline " "
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bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear"
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bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear"
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textline " "
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bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear"
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bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear"
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textline " "
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bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear"
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bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear"
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textline " "
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bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear"
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bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear"
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textline " "
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bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear"
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bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear"
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textline " "
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bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear"
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bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear"
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textline " "
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bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear"
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bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear"
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textline " "
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bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear"
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bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear"
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textline " "
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bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear"
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bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear"
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textline " "
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bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear"
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bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear"
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textline " "
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bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear"
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bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear"
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textline " "
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bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear"
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bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear"
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textline " "
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bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear"
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bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear"
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textline " "
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bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear"
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bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear"
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line.long 0x04 "ICRH,Interrupt Clear Register High"
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bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear"
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bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear"
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textline " "
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bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear"
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bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear"
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textline " "
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bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear"
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bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear"
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textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear"
|
|
wgroup.long (0x2078+0xA00)++0x3
|
|
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
|
|
bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse"
|
|
tree.end
|
|
tree "QDMA Registers"
|
|
rgroup.long (0x2080+0xA00)++0x3
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
|
|
group.long (0x2084+0xA00)++0x3
|
|
line.long 0x00 "QEER,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x2090+0xA00)++0x3
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored"
|
|
wgroup.long (0x2094+0xA00)++0x3
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear"
|
|
tree.end
|
|
tree.end
|
|
tree "Shadow Region 6 Channel Registers"
|
|
tree "DMA Channel Registers"
|
|
width 7.
|
|
group.long (0x2000+0xC00)++0x7
|
|
line.long 0x00 "ER,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted"
|
|
line.long 0x04 "ERH,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted"
|
|
rgroup.long (0x2018+0xC00)++0x7
|
|
line.long 0x00 "ECR,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized"
|
|
bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized"
|
|
bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized"
|
|
bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized"
|
|
bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized"
|
|
bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized"
|
|
bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized"
|
|
bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized"
|
|
bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized"
|
|
bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized"
|
|
bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized"
|
|
bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized"
|
|
bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized"
|
|
bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized"
|
|
bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized"
|
|
bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized"
|
|
bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized"
|
|
bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized"
|
|
line.long 0x04 "ECRH,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized"
|
|
bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized"
|
|
bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized"
|
|
bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized"
|
|
bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized"
|
|
bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized"
|
|
bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized"
|
|
bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized"
|
|
bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized"
|
|
bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized"
|
|
bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized"
|
|
bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized"
|
|
bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized"
|
|
bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized"
|
|
bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized"
|
|
bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized"
|
|
bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized"
|
|
bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized"
|
|
bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized"
|
|
bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized"
|
|
bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized"
|
|
bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized"
|
|
group.long (0x2020+0xC00)++0x7
|
|
line.long 0x00 "EER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled"
|
|
rgroup.long (0x2038+0xC00)++0x7
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored"
|
|
line.long 0x04 "SERH,Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored"
|
|
wgroup.long (0x2040+0xC00)++0x7
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear"
|
|
line.long 0x04 "SECRH,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear"
|
|
tree.end
|
|
tree "Interrupt Registers"
|
|
width 7.
|
|
group.long (0x2050+0xC00)++0x7
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "IERH,Interrupt Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled"
|
|
rgroup.long (0x2068+0xC00)++0x7
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected"
|
|
line.long 0x04 "IPRH,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected"
|
|
wgroup.long (0x2070+0xC00)++0x7
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear"
|
|
line.long 0x04 "ICRH,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear"
|
|
wgroup.long (0x2078+0xC00)++0x3
|
|
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
|
|
bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse"
|
|
tree.end
|
|
tree "QDMA Registers"
|
|
rgroup.long (0x2080+0xC00)++0x3
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
|
|
group.long (0x2084+0xC00)++0x3
|
|
line.long 0x00 "QEER,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x2090+0xC00)++0x3
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored"
|
|
wgroup.long (0x2094+0xC00)++0x3
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear"
|
|
tree.end
|
|
tree.end
|
|
tree "Shadow Channel Registers for MP Space 7"
|
|
tree "DMA Channel Registers"
|
|
width 7.
|
|
group.long (0x2000+0xE00)++0x7
|
|
line.long 0x00 "ER,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted"
|
|
line.long 0x04 "ERH,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted"
|
|
rgroup.long (0x2018+0xE00)++0x7
|
|
line.long 0x00 "ECR,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized"
|
|
bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized"
|
|
bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized"
|
|
bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized"
|
|
bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized"
|
|
bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized"
|
|
bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized"
|
|
bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized"
|
|
bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized"
|
|
bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized"
|
|
bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized"
|
|
bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized"
|
|
bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized"
|
|
bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized"
|
|
bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized"
|
|
bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized"
|
|
bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized"
|
|
bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized"
|
|
line.long 0x04 "ECRH,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized"
|
|
bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized"
|
|
bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized"
|
|
bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized"
|
|
bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized"
|
|
bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized"
|
|
bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized"
|
|
bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized"
|
|
bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized"
|
|
bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized"
|
|
bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized"
|
|
bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized"
|
|
bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized"
|
|
bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized"
|
|
bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized"
|
|
bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized"
|
|
bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized"
|
|
bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized"
|
|
bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized"
|
|
bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized"
|
|
bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized"
|
|
bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized"
|
|
group.long (0x2020+0xE00)++0x7
|
|
line.long 0x00 "EER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled"
|
|
rgroup.long (0x2038+0xE00)++0x7
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored"
|
|
line.long 0x04 "SERH,Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored"
|
|
wgroup.long (0x2040+0xE00)++0x7
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear"
|
|
line.long 0x04 "SECRH,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear"
|
|
bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear"
|
|
tree.end
|
|
tree "Interrupt Registers"
|
|
width 7.
|
|
group.long (0x2050+0xE00)++0x7
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "IERH,Interrupt Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled"
|
|
rgroup.long (0x2068+0xE00)++0x7
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected"
|
|
line.long 0x04 "IPRH,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected"
|
|
wgroup.long (0x2070+0xE00)++0x7
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear"
|
|
line.long 0x04 "ICRH,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear"
|
|
bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear"
|
|
wgroup.long (0x2078+0xE00)++0x3
|
|
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
|
|
bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse"
|
|
tree.end
|
|
tree "QDMA Registers"
|
|
rgroup.long (0x2080+0xE00)++0x3
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
|
|
group.long (0x2084+0xE00)++0x3
|
|
line.long 0x00 "QEER,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x2090+0xE00)++0x3
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored"
|
|
wgroup.long (0x2094+0xE00)++0x3
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
tree "EDMA TPTC0 (EDMA Transfer Controller Control Registers)"
|
|
base ad:0x49800000
|
|
width 8.
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "PID,Peripheral Identifier"
|
|
line.long 0x04 "TCCFG,EDMA3TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" "Reserved,Reserved,4 entry,?..."
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parameterization" "Reserved,Reserved,128-bit,?..."
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size" "Reserved,Reserved,Reserved,Reserved,Reserved,1024 byte,?..."
|
|
rgroup.long 0x100++0x3
|
|
line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register"
|
|
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,?..."
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
tree "Error Registers"
|
|
width 9.
|
|
sif (cpuis("DRA62*"))
|
|
rgroup.long 0x120++0x3
|
|
line.long 0x00 "ERRSTAT,Error Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,MMR address error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " TRERR ,Transfer request error event" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " BUSERR ,Bus error event" "Not detected,Detected"
|
|
group.long 0x124++0x3
|
|
line.long 0x00 "ERREN,Error Enable Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,Interrupt enable for MMR address error" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TRERR ,Interrupt enable for Transfer request error event" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BUSERR ,Interrupt enable for Bus error event" "Disabled,Enabled"
|
|
wgroup.long 0x128++0x3
|
|
line.long 0x00 "ERRCLR,Error Clear Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,Interrupt clear for MMR address error" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TRERR ,Interrupt clear for Transfer request error event" "No effect,Clear"
|
|
bitfld.long 0x00 0. " BUSERR ,Interrupt clear for Bus error event" "No effect,Clear"
|
|
else
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "ERRSTAT,Error Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "Not detected,Detected"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,Transfer request error event" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 0. " BUSERR ,Bus error event" "Not detected,Detected"
|
|
endif
|
|
rgroup.long 0x12c++0x3
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error"
|
|
wgroup.long 0x130++0x3
|
|
line.long 0x00 "ERRCMD,Error Interrupt Command Register"
|
|
bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Pulsed"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate - number of cycles between read commands" "0 cycles,4 cycles,8 cycles,16 cycles,32 cycles,?..."
|
|
tree.end
|
|
tree "EDMA3TC Channel Registers"
|
|
width 11.
|
|
group.long 0x240++0x3 "Source Active Registers"
|
|
line.long 0x00 "SAOPT,Source Active Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "SASRC,Source Active Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
hgroup.long 0x24c++0x03
|
|
hide.long 0x00 "SADST,Source Active Destination Address Register"
|
|
rgroup.long 0x250++0x0f
|
|
line.long 0x00 "SABIDX,Source Active Source B-Dimension Index Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x04 "SAMPPRXY,Source Active Memory Protection Proxy Register"
|
|
bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRIVID ,Privilege ID"
|
|
line.long 0x08 "SACNTRLD,Source Active Count Reload Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-count reload value"
|
|
line.long 0x0c "SASRCBREF,Source Active Source Address B-Reference Register"
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register"
|
|
rgroup.long 0x280++0x03 "Destination FIFO Registers"
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-count reload value"
|
|
hgroup.long 0x284++0x03
|
|
hide.long 0x00 "DFSRCBREF,Destination FIFO Source Address B-Reference Register"
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "DFDSTBREF,Destination FIFO Destination Address B-Reference Register"
|
|
group.long 0x300++0x3
|
|
line.long 0x00 "DFOPT0,Destination FIFO Options Register 0"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x300+0x4)++0x3
|
|
hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register 0"
|
|
rgroup.long (0x300+0x8)++0xF
|
|
line.long 0x00 "DFCNT0,Destination FIFO Count Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST0,Destination FIFO Destination Address Register 0"
|
|
line.long 0x08 "DFBIDX0,Destination FIFO B-Dimension Index Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register 0"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
group.long 0x340++0x3
|
|
line.long 0x00 "DFOPT1,Destination FIFO Options Register 1"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x340+0x4)++0x3
|
|
hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register 1"
|
|
rgroup.long (0x340+0x8)++0xF
|
|
line.long 0x00 "DFCNT1,Destination FIFO Count Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST1,Destination FIFO Destination Address Register 1"
|
|
line.long 0x08 "DFBIDX1,Destination FIFO B-Dimension Index Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register 1"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
group.long 0x380++0x3
|
|
line.long 0x00 "DFOPT2,Destination FIFO Options Register 2"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x380+0x4)++0x3
|
|
hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register 2"
|
|
rgroup.long (0x380+0x8)++0xF
|
|
line.long 0x00 "DFCNT2,Destination FIFO Count Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST2,Destination FIFO Destination Address Register 2"
|
|
line.long 0x08 "DFBIDX2,Destination FIFO B-Dimension Index Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register 2"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
group.long 0x3C0++0x3
|
|
line.long 0x00 "DFOPT3,Destination FIFO Options Register 3"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x3C0+0x4)++0x3
|
|
hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register 3"
|
|
rgroup.long (0x3C0+0x8)++0xF
|
|
line.long 0x00 "DFCNT3,Destination FIFO Count Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST3,Destination FIFO Destination Address Register 3"
|
|
line.long 0x08 "DFBIDX3,Destination FIFO B-Dimension Index Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register 3"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
tree.end
|
|
tree.end
|
|
tree "EDMA TPTC1 (EDMA Transfer Controller Control Registers)"
|
|
base ad:0x49900000
|
|
width 8.
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "PID,Peripheral Identifier"
|
|
line.long 0x04 "TCCFG,EDMA3TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" "Reserved,Reserved,4 entry,?..."
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parameterization" "Reserved,Reserved,128-bit,?..."
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size" "Reserved,Reserved,Reserved,Reserved,Reserved,1024 byte,?..."
|
|
rgroup.long 0x100++0x3
|
|
line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register"
|
|
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,?..."
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
tree "Error Registers"
|
|
width 9.
|
|
sif (cpuis("DRA62*"))
|
|
rgroup.long 0x120++0x3
|
|
line.long 0x00 "ERRSTAT,Error Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,MMR address error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " TRERR ,Transfer request error event" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " BUSERR ,Bus error event" "Not detected,Detected"
|
|
group.long 0x124++0x3
|
|
line.long 0x00 "ERREN,Error Enable Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,Interrupt enable for MMR address error" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TRERR ,Interrupt enable for Transfer request error event" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BUSERR ,Interrupt enable for Bus error event" "Disabled,Enabled"
|
|
wgroup.long 0x128++0x3
|
|
line.long 0x00 "ERRCLR,Error Clear Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,Interrupt clear for MMR address error" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TRERR ,Interrupt clear for Transfer request error event" "No effect,Clear"
|
|
bitfld.long 0x00 0. " BUSERR ,Interrupt clear for Bus error event" "No effect,Clear"
|
|
else
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "ERRSTAT,Error Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "Not detected,Detected"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,Transfer request error event" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 0. " BUSERR ,Bus error event" "Not detected,Detected"
|
|
endif
|
|
rgroup.long 0x12c++0x3
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error"
|
|
wgroup.long 0x130++0x3
|
|
line.long 0x00 "ERRCMD,Error Interrupt Command Register"
|
|
bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Pulsed"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate - number of cycles between read commands" "0 cycles,4 cycles,8 cycles,16 cycles,32 cycles,?..."
|
|
tree.end
|
|
tree "EDMA3TC Channel Registers"
|
|
width 11.
|
|
group.long 0x240++0x3 "Source Active Registers"
|
|
line.long 0x00 "SAOPT,Source Active Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "SASRC,Source Active Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
hgroup.long 0x24c++0x03
|
|
hide.long 0x00 "SADST,Source Active Destination Address Register"
|
|
rgroup.long 0x250++0x0f
|
|
line.long 0x00 "SABIDX,Source Active Source B-Dimension Index Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x04 "SAMPPRXY,Source Active Memory Protection Proxy Register"
|
|
bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRIVID ,Privilege ID"
|
|
line.long 0x08 "SACNTRLD,Source Active Count Reload Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-count reload value"
|
|
line.long 0x0c "SASRCBREF,Source Active Source Address B-Reference Register"
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register"
|
|
rgroup.long 0x280++0x03 "Destination FIFO Registers"
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-count reload value"
|
|
hgroup.long 0x284++0x03
|
|
hide.long 0x00 "DFSRCBREF,Destination FIFO Source Address B-Reference Register"
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "DFDSTBREF,Destination FIFO Destination Address B-Reference Register"
|
|
group.long 0x300++0x3
|
|
line.long 0x00 "DFOPT0,Destination FIFO Options Register 0"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x300+0x4)++0x3
|
|
hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register 0"
|
|
rgroup.long (0x300+0x8)++0xF
|
|
line.long 0x00 "DFCNT0,Destination FIFO Count Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST0,Destination FIFO Destination Address Register 0"
|
|
line.long 0x08 "DFBIDX0,Destination FIFO B-Dimension Index Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register 0"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
group.long 0x340++0x3
|
|
line.long 0x00 "DFOPT1,Destination FIFO Options Register 1"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x340+0x4)++0x3
|
|
hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register 1"
|
|
rgroup.long (0x340+0x8)++0xF
|
|
line.long 0x00 "DFCNT1,Destination FIFO Count Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST1,Destination FIFO Destination Address Register 1"
|
|
line.long 0x08 "DFBIDX1,Destination FIFO B-Dimension Index Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register 1"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
group.long 0x380++0x3
|
|
line.long 0x00 "DFOPT2,Destination FIFO Options Register 2"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x380+0x4)++0x3
|
|
hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register 2"
|
|
rgroup.long (0x380+0x8)++0xF
|
|
line.long 0x00 "DFCNT2,Destination FIFO Count Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST2,Destination FIFO Destination Address Register 2"
|
|
line.long 0x08 "DFBIDX2,Destination FIFO B-Dimension Index Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register 2"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
group.long 0x3C0++0x3
|
|
line.long 0x00 "DFOPT3,Destination FIFO Options Register 3"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x3C0+0x4)++0x3
|
|
hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register 3"
|
|
rgroup.long (0x3C0+0x8)++0xF
|
|
line.long 0x00 "DFCNT3,Destination FIFO Count Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST3,Destination FIFO Destination Address Register 3"
|
|
line.long 0x08 "DFBIDX3,Destination FIFO B-Dimension Index Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register 3"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
tree.end
|
|
tree.end
|
|
tree "EDMA TPTC2 (EDMA Transfer Controller Control Registers)"
|
|
base ad:0x49A00000
|
|
width 8.
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "PID,Peripheral Identifier"
|
|
line.long 0x04 "TCCFG,EDMA3TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" "Reserved,Reserved,4 entry,?..."
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parameterization" "Reserved,Reserved,128-bit,?..."
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size" "Reserved,Reserved,Reserved,Reserved,Reserved,1024 byte,?..."
|
|
rgroup.long 0x100++0x3
|
|
line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register"
|
|
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,?..."
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
tree "Error Registers"
|
|
width 9.
|
|
sif (cpuis("DRA62*"))
|
|
rgroup.long 0x120++0x3
|
|
line.long 0x00 "ERRSTAT,Error Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,MMR address error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " TRERR ,Transfer request error event" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " BUSERR ,Bus error event" "Not detected,Detected"
|
|
group.long 0x124++0x3
|
|
line.long 0x00 "ERREN,Error Enable Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,Interrupt enable for MMR address error" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TRERR ,Interrupt enable for Transfer request error event" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BUSERR ,Interrupt enable for Bus error event" "Disabled,Enabled"
|
|
wgroup.long 0x128++0x3
|
|
line.long 0x00 "ERRCLR,Error Clear Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,Interrupt clear for MMR address error" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TRERR ,Interrupt clear for Transfer request error event" "No effect,Clear"
|
|
bitfld.long 0x00 0. " BUSERR ,Interrupt clear for Bus error event" "No effect,Clear"
|
|
else
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "ERRSTAT,Error Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "Not detected,Detected"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,Transfer request error event" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 0. " BUSERR ,Bus error event" "Not detected,Detected"
|
|
endif
|
|
rgroup.long 0x12c++0x3
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error"
|
|
wgroup.long 0x130++0x3
|
|
line.long 0x00 "ERRCMD,Error Interrupt Command Register"
|
|
bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Pulsed"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate - number of cycles between read commands" "0 cycles,4 cycles,8 cycles,16 cycles,32 cycles,?..."
|
|
tree.end
|
|
tree "EDMA3TC Channel Registers"
|
|
width 11.
|
|
group.long 0x240++0x3 "Source Active Registers"
|
|
line.long 0x00 "SAOPT,Source Active Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "SASRC,Source Active Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
hgroup.long 0x24c++0x03
|
|
hide.long 0x00 "SADST,Source Active Destination Address Register"
|
|
rgroup.long 0x250++0x0f
|
|
line.long 0x00 "SABIDX,Source Active Source B-Dimension Index Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x04 "SAMPPRXY,Source Active Memory Protection Proxy Register"
|
|
bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRIVID ,Privilege ID"
|
|
line.long 0x08 "SACNTRLD,Source Active Count Reload Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-count reload value"
|
|
line.long 0x0c "SASRCBREF,Source Active Source Address B-Reference Register"
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register"
|
|
rgroup.long 0x280++0x03 "Destination FIFO Registers"
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-count reload value"
|
|
hgroup.long 0x284++0x03
|
|
hide.long 0x00 "DFSRCBREF,Destination FIFO Source Address B-Reference Register"
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "DFDSTBREF,Destination FIFO Destination Address B-Reference Register"
|
|
group.long 0x300++0x3
|
|
line.long 0x00 "DFOPT0,Destination FIFO Options Register 0"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x300+0x4)++0x3
|
|
hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register 0"
|
|
rgroup.long (0x300+0x8)++0xF
|
|
line.long 0x00 "DFCNT0,Destination FIFO Count Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST0,Destination FIFO Destination Address Register 0"
|
|
line.long 0x08 "DFBIDX0,Destination FIFO B-Dimension Index Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register 0"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
group.long 0x340++0x3
|
|
line.long 0x00 "DFOPT1,Destination FIFO Options Register 1"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x340+0x4)++0x3
|
|
hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register 1"
|
|
rgroup.long (0x340+0x8)++0xF
|
|
line.long 0x00 "DFCNT1,Destination FIFO Count Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST1,Destination FIFO Destination Address Register 1"
|
|
line.long 0x08 "DFBIDX1,Destination FIFO B-Dimension Index Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register 1"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
group.long 0x380++0x3
|
|
line.long 0x00 "DFOPT2,Destination FIFO Options Register 2"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x380+0x4)++0x3
|
|
hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register 2"
|
|
rgroup.long (0x380+0x8)++0xF
|
|
line.long 0x00 "DFCNT2,Destination FIFO Count Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST2,Destination FIFO Destination Address Register 2"
|
|
line.long 0x08 "DFBIDX2,Destination FIFO B-Dimension Index Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register 2"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
group.long 0x3C0++0x3
|
|
line.long 0x00 "DFOPT3,Destination FIFO Options Register 3"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x3C0+0x4)++0x3
|
|
hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register 3"
|
|
rgroup.long (0x3C0+0x8)++0xF
|
|
line.long 0x00 "DFCNT3,Destination FIFO Count Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST3,Destination FIFO Destination Address Register 3"
|
|
line.long 0x08 "DFBIDX3,Destination FIFO B-Dimension Index Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register 3"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
tree.end
|
|
tree.end
|
|
tree "EDMA TPTC3 (EDMA Transfer Controller Control Registers)"
|
|
base ad:0x49B00000
|
|
width 8.
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "PID,Peripheral Identifier"
|
|
line.long 0x04 "TCCFG,EDMA3TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" "Reserved,Reserved,4 entry,?..."
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parameterization" "Reserved,Reserved,128-bit,?..."
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size" "Reserved,Reserved,Reserved,Reserved,Reserved,1024 byte,?..."
|
|
rgroup.long 0x100++0x3
|
|
line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register"
|
|
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,?..."
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
tree "Error Registers"
|
|
width 9.
|
|
sif (cpuis("DRA62*"))
|
|
rgroup.long 0x120++0x3
|
|
line.long 0x00 "ERRSTAT,Error Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,MMR address error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " TRERR ,Transfer request error event" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " BUSERR ,Bus error event" "Not detected,Detected"
|
|
group.long 0x124++0x3
|
|
line.long 0x00 "ERREN,Error Enable Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,Interrupt enable for MMR address error" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TRERR ,Interrupt enable for Transfer request error event" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BUSERR ,Interrupt enable for Bus error event" "Disabled,Enabled"
|
|
wgroup.long 0x128++0x3
|
|
line.long 0x00 "ERRCLR,Error Clear Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,Interrupt clear for MMR address error" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TRERR ,Interrupt clear for Transfer request error event" "No effect,Clear"
|
|
bitfld.long 0x00 0. " BUSERR ,Interrupt clear for Bus error event" "No effect,Clear"
|
|
else
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "ERRSTAT,Error Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "Not detected,Detected"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,Transfer request error event" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 0. " BUSERR ,Bus error event" "Not detected,Detected"
|
|
endif
|
|
rgroup.long 0x12c++0x3
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error"
|
|
wgroup.long 0x130++0x3
|
|
line.long 0x00 "ERRCMD,Error Interrupt Command Register"
|
|
bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Pulsed"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate - number of cycles between read commands" "0 cycles,4 cycles,8 cycles,16 cycles,32 cycles,?..."
|
|
tree.end
|
|
tree "EDMA3TC Channel Registers"
|
|
width 11.
|
|
group.long 0x240++0x3 "Source Active Registers"
|
|
line.long 0x00 "SAOPT,Source Active Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "SASRC,Source Active Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
hgroup.long 0x24c++0x03
|
|
hide.long 0x00 "SADST,Source Active Destination Address Register"
|
|
rgroup.long 0x250++0x0f
|
|
line.long 0x00 "SABIDX,Source Active Source B-Dimension Index Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x04 "SAMPPRXY,Source Active Memory Protection Proxy Register"
|
|
bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRIVID ,Privilege ID"
|
|
line.long 0x08 "SACNTRLD,Source Active Count Reload Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-count reload value"
|
|
line.long 0x0c "SASRCBREF,Source Active Source Address B-Reference Register"
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register"
|
|
rgroup.long 0x280++0x03 "Destination FIFO Registers"
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-count reload value"
|
|
hgroup.long 0x284++0x03
|
|
hide.long 0x00 "DFSRCBREF,Destination FIFO Source Address B-Reference Register"
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "DFDSTBREF,Destination FIFO Destination Address B-Reference Register"
|
|
group.long 0x300++0x3
|
|
line.long 0x00 "DFOPT0,Destination FIFO Options Register 0"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x300+0x4)++0x3
|
|
hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register 0"
|
|
rgroup.long (0x300+0x8)++0xF
|
|
line.long 0x00 "DFCNT0,Destination FIFO Count Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST0,Destination FIFO Destination Address Register 0"
|
|
line.long 0x08 "DFBIDX0,Destination FIFO B-Dimension Index Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register 0"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
group.long 0x340++0x3
|
|
line.long 0x00 "DFOPT1,Destination FIFO Options Register 1"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x340+0x4)++0x3
|
|
hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register 1"
|
|
rgroup.long (0x340+0x8)++0xF
|
|
line.long 0x00 "DFCNT1,Destination FIFO Count Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST1,Destination FIFO Destination Address Register 1"
|
|
line.long 0x08 "DFBIDX1,Destination FIFO B-Dimension Index Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register 1"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
group.long 0x380++0x3
|
|
line.long 0x00 "DFOPT2,Destination FIFO Options Register 2"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x380+0x4)++0x3
|
|
hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register 2"
|
|
rgroup.long (0x380+0x8)++0xF
|
|
line.long 0x00 "DFCNT2,Destination FIFO Count Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST2,Destination FIFO Destination Address Register 2"
|
|
line.long 0x08 "DFBIDX2,Destination FIFO B-Dimension Index Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register 2"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
group.long 0x3C0++0x3
|
|
line.long 0x00 "DFOPT3,Destination FIFO Options Register 3"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
hgroup.long (0x3C0+0x4)++0x3
|
|
hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register 3"
|
|
rgroup.long (0x3C0+0x8)++0xF
|
|
line.long 0x00 "DFCNT3,Destination FIFO Count Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x04 "DFDST3,Destination FIFO Destination Address Register 3"
|
|
line.long 0x08 "DFBIDX3,Destination FIFO B-Dimension Index Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
|
|
line.long 0x0c "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register 3"
|
|
bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "SPINLOCK (Spinlock Registers)"
|
|
base ad:0x480ca000
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "SPINLOCK_REV,IP Revision Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SPINLOCK_SYSCFG,System Configuration Register"
|
|
rbitfld.long 0x00 8. " CLOCKACTIVITY ,Clock activity during IDLE mode" "Not required,Required"
|
|
rbitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
rbitfld.long 0x00 2. " ENWAKEUP ,Asynchronous wakeup generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No action,Reset"
|
|
rbitfld.long 0x00 0. " AUTOGATING ,Internal interface clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "SPINLOCK_SYSSTAT,System Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " NUMLOCKS ,Number of lock registers implemented"
|
|
bitfld.long 0x00 15. " IU7 ,In-Use flag 7" "Low,High"
|
|
bitfld.long 0x00 14. " IU6 ,In-Use flag 6" "Low,High"
|
|
bitfld.long 0x00 13. " IU5 ,In-Use flag 5" "Low,High"
|
|
bitfld.long 0x00 12. " IU4 ,In-Use flag 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IU3 ,In-Use flag 3" "Low,High"
|
|
bitfld.long 0x00 10. " IU2 ,In-Use flag 2" "Low,High"
|
|
bitfld.long 0x00 9. " IU1 ,In-Use flag 1" "Low,High"
|
|
bitfld.long 0x00 8. " IU0 ,In-Use flag 0" "Low,High"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset done status" "In progress,Completed"
|
|
width 22.
|
|
tree "Lock Registers"
|
|
group.long (0x800+0x0)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_0,Lock Register 0"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x4)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_1,Lock Register 1"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x8)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_2,Lock Register 2"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xC)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_3,Lock Register 3"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x10)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_4,Lock Register 4"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x14)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_5,Lock Register 5"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x18)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_6,Lock Register 6"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_7,Lock Register 7"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x20)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_8,Lock Register 8"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x24)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_9,Lock Register 9"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x28)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_10,Lock Register 10"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x2C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_11,Lock Register 11"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x30)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_12,Lock Register 12"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x34)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_13,Lock Register 13"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x38)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_14,Lock Register 14"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x3C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_15,Lock Register 15"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x40)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_16,Lock Register 16"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x44)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_17,Lock Register 17"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x48)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_18,Lock Register 18"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x4C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_19,Lock Register 19"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x50)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_20,Lock Register 20"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x54)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_21,Lock Register 21"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x58)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_22,Lock Register 22"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x5C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_23,Lock Register 23"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x60)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_24,Lock Register 24"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x64)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_25,Lock Register 25"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x68)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_26,Lock Register 26"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x6C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_27,Lock Register 27"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x70)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_28,Lock Register 28"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x74)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_29,Lock Register 29"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x78)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_30,Lock Register 30"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x7C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_31,Lock Register 31"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x80)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_32,Lock Register 32"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x84)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_33,Lock Register 33"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x88)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_34,Lock Register 34"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x8C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_35,Lock Register 35"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x90)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_36,Lock Register 36"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x94)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_37,Lock Register 37"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x98)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_38,Lock Register 38"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x9C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_39,Lock Register 39"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xA0)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_40,Lock Register 40"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xA4)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_41,Lock Register 41"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xA8)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_42,Lock Register 42"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xAC)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_43,Lock Register 43"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xB0)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_44,Lock Register 44"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xB4)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_45,Lock Register 45"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xB8)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_46,Lock Register 46"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xBC)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_47,Lock Register 47"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xC0)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_48,Lock Register 48"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xC4)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_49,Lock Register 49"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xC8)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_50,Lock Register 50"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xCC)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_51,Lock Register 51"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xD0)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_52,Lock Register 52"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xD4)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_53,Lock Register 53"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xD8)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_54,Lock Register 54"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xDC)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_55,Lock Register 55"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xE0)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_56,Lock Register 56"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xE4)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_57,Lock Register 57"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xE8)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_58,Lock Register 58"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xEC)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_59,Lock Register 59"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xF0)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_60,Lock Register 60"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xF4)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_61,Lock Register 61"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xF8)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_62,Lock Register 62"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0xFC)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_63,Lock Register 63"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x100)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_64,Lock Register 64"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x104)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_65,Lock Register 65"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x108)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_66,Lock Register 66"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x10C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_67,Lock Register 67"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x110)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_68,Lock Register 68"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x114)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_69,Lock Register 69"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x118)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_70,Lock Register 70"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x11C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_71,Lock Register 71"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x120)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_72,Lock Register 72"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x124)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_73,Lock Register 73"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x128)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_74,Lock Register 74"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x12C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_75,Lock Register 75"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x130)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_76,Lock Register 76"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x134)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_77,Lock Register 77"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x138)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_78,Lock Register 78"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x13C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_79,Lock Register 79"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x140)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_80,Lock Register 80"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x144)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_81,Lock Register 81"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x148)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_82,Lock Register 82"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x14C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_83,Lock Register 83"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x150)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_84,Lock Register 84"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x154)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_85,Lock Register 85"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x158)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_86,Lock Register 86"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x15C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_87,Lock Register 87"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x160)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_88,Lock Register 88"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x164)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_89,Lock Register 89"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x168)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_90,Lock Register 90"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x16C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_91,Lock Register 91"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x170)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_92,Lock Register 92"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x174)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_93,Lock Register 93"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x178)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_94,Lock Register 94"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x17C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_95,Lock Register 95"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x180)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_96,Lock Register 96"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x184)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_97,Lock Register 97"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x188)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_98,Lock Register 98"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x18C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_99,Lock Register 99"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x190)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_100,Lock Register 100"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x194)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_101,Lock Register 101"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x198)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_102,Lock Register 102"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x19C)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_103,Lock Register 103"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1A0)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_104,Lock Register 104"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1A4)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_105,Lock Register 105"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1A8)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_106,Lock Register 106"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1AC)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_107,Lock Register 107"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1B0)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_108,Lock Register 108"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1B4)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_109,Lock Register 109"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1B8)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_110,Lock Register 110"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1BC)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_111,Lock Register 111"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1C0)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_112,Lock Register 112"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1C4)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_113,Lock Register 113"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1C8)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_114,Lock Register 114"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1CC)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_115,Lock Register 115"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1D0)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_116,Lock Register 116"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1D4)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_117,Lock Register 117"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1D8)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_118,Lock Register 118"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1DC)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_119,Lock Register 119"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1E0)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_120,Lock Register 120"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1E4)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_121,Lock Register 121"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1E8)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_122,Lock Register 122"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1EC)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_123,Lock Register 123"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1F0)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_124,Lock Register 124"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1F4)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_125,Lock Register 125"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1F8)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_126,Lock Register 126"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
group.long (0x800+0x1FC)++0x3
|
|
line.long 0x00 "SPINLOCK_LOCK_REG_127,Lock Register 127"
|
|
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
sif ((cpu()=="AM3874")||(cpu()=="C6A8148")||(cpu()=="DM8148")||(cpuis("DRA6*")&&!cpuis("DRA623*")))
|
|
tree "SGX530 (2D/3D Graphics Accelerator)"
|
|
base ad:0x5600fe00
|
|
width 21.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "OCP_REVISION,OCP Revision Register"
|
|
line.long 0x04 "OCP_HWINFO,Hardware implementation information"
|
|
bitfld.long 0x04 2. " MEM_BUS_WIDTH ,Memory bus width (bits)" "64,128"
|
|
bitfld.long 0x04 0.--1. " SYS_BUS_WIDTH ,System bus width (bits)" "32,64,128,?..."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "OCP_SYSCONFIG,System Configuration register"
|
|
bitfld.long 0x00 4.--5. " STANDBY_MODE ,Clock standby mode" "Force Standby,No Standby,Smart Standby,Smart Standby"
|
|
bitfld.long 0x00 2.--3. " IDLE_MODE ,Clock Idle mode" "Force Idle,No idle,Smart Idle,Smart Idle"
|
|
group.long 0x24++0x0b
|
|
line.long 0x00 "OCP_IRQSTATUS_RAW_0,Raw IRQ 0 Status"
|
|
bitfld.long 0x00 0. " INIT_MINTERRUPT_RAW ,Interrupt 0 - master port raw event" "No interrupt,Interrupt"
|
|
line.long 0x04 "OCP_IRQSTATUS_RAW_1,Raw IRQ1 Status"
|
|
bitfld.long 0x04 0. " TARGET_SINTERRUPT_RAW ,Interrupt 1 - slave port raw event" "No interrupt,Interrupt"
|
|
line.long 0x08 "OCP_IRQSTATUS_RAW_2,Raw IRQ2 Status"
|
|
bitfld.long 0x08 0. " THALIA_IRQ_RAW ,Interrupt 2 - Thalia port raw event" "No interrupt,Interrupt"
|
|
sif (cpuis("DRA62*"))
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "OCP_IRQSTATUS_0,Interrupt 0 Status event"
|
|
eventfld.long 0x00 0. " INIT_MINTERRUPT_STATUS ,Interrupt 0 - master port status event" "No interrupt,Interrupt"
|
|
line.long 0x04 "OCP_IRQSTATUS_1,Interrupt 1 Status event"
|
|
eventfld.long 0x04 0. " TARGET_SINTERRUPT_STATUS ,Interrupt 1 - slave port status event" "No interrupt,Interrupt"
|
|
line.long 0x08 "OCP_IRQSTATUS_2,Interrupt 2 Status event"
|
|
eventfld.long 0x08 0. " THALIA_IRQ_STATUS ,Interrupt 2 - Thalia (core) status event" "No interrupt,Interrupt"
|
|
group.long 0x3C++0x0B
|
|
line.long 0x00 "OCP_IRQENABLE_0,Interrupt 0 Enable"
|
|
setclrfld.long 0x00 0. 0x00 0. 0xC 0. " INIT_MINTERRUPT_ENABLE_set/clr ,Interrupt 0 - master port enable" "Disabled,Enabled"
|
|
line.long 0x04 "OCP_IRQENABLE_1,Interrupt 1 Enable"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x10 0. " TARGET_SINTERRUPT_ENABLE_set/clr ,Interrupt 1 - slave port enable" "Disabled,Enabled"
|
|
line.long 0x08 "OCP_IRQENABLE_2,Interrupt 2 Enable"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x14 0. " THALIA_IRQ_ENABLE_set/clr ,Interrupt 2 - Thalia (core) enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "OCP_IRQSTATUS_0,Interrupt 0 Status event"
|
|
setclrfld.long 0x00 0. 0x0c 0. 0x18 0. " INIT_MINTERRUPT_STATUS_set/clr ,Interrupt 0 - master port status event" "No interrupt,Interrupt"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "OCP_IRQSTATUS_1,Interrupt 1 Status event"
|
|
setclrfld.long 0x00 0. 0x0c 0. 0x18 0. " TARGET_SINTERRUPT_STATUS_set/clr ,Interrupt 1 - slave port status event" "No interrupt,Interrupt"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "OCP_IRQSTATUS_2,Interrupt 2 Status event"
|
|
setclrfld.long 0x00 0. 0x0c 0. 0x18 0. " THALIA_IRQ_STATUS_set/clr ,Interrupt 2 - Thalia (core) status event" "No interrupt,Interrupt"
|
|
endif
|
|
group.long 0x100++0x0f
|
|
line.long 0x00 "OCP_PAGE_CONFIG,Configure memory pages"
|
|
sif (cpuis("DRA62*")||cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
|
|
bitfld.long 0x00 3.--4. " OCP_PAGE_SIZE ,Defines the page size on OCP memory interface" "4 KB,2 KB,1 KB,520 B"
|
|
else
|
|
bitfld.long 0x00 3.--4. " OCP_PAGE_SIZE ,Defines the page size on OCP memory interface" "4 KB,2 KB,1 KB,512 B"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " MEM_PAGE_CHECK_EN ,Enable page boundary checking" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
|
|
bitfld.long 0x00 0.--1. " MEM_PAGE_SIZE ,Defines the page size on internal memory interface" "4 KB,2 KB,1 KB,520 B"
|
|
else
|
|
bitfld.long 0x00 0.--1. " MEM_PAGE_SIZE ,Defines the page size on internal memory interface" "4 KB,2 KB,1 KB,512 B"
|
|
endif
|
|
line.long 0x04 "OCP_INTERRUPT_EVENT,Interrupt events"
|
|
bitfld.long 0x04 10. " TARGET_INVALID_OCP_CMD ,Invalid command from OCP" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " TARGET_CMD_FIFO_FULL ,Command FIFO full" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TARGET_RESP_FIFO_FULL ,Response FIFO full" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INIT_MEM_REQ_FIFO_OVERRUN ,Memory request FIFO overrun" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INIT_READ_TAG_FIFO_OVERRUN ,Read tag FIFO overrun" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INIT_PAGE_CROSS_ERROR ,Memory page had been crossed during a burst" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " INIT_RESP_ERROR ,Receiving error response" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INIT_RESP_UNUSED_TAG ,Receiving response on an unused tag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " INIT_RESP_UNEXPECTED ,Receiving response when not expected" "No interrupt,Interrupt"
|
|
line.long 0x08 "OCP_DEBUG_CONFIG,Configuration of debug modes"
|
|
bitfld.long 0x08 31. " THALIA_INT_BYPASS ,Bypass OCP IPG interrupt logic" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SELECT_INIT_IDLE ,Select Init Idle" "Whole SGX,OCP initiator"
|
|
textline " "
|
|
bitfld.long 0x08 4. " FORCE_PASS_DATA ,Forces the initiator to pass data independent of disconnect protocol" "Normal,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " FORCE_INIT_IDLE ,Forces the OCP master port to Idle" "Normal,Port always Idle,Target port never Idle,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " FORCE_TARGET_IDLE ,Forces the OCP target port to Idle" "Normal,Port always Idle,Target port never Idle,Normal"
|
|
line.long 0x0c "OCP_DEBUG_STATUS,Status of debug"
|
|
bitfld.long 0x0C 31. " CMD_DEBUG_STATE ,Target command state machine" "Idle,Accepted"
|
|
textline " "
|
|
bitfld.long 0x0C 30. " CMD_RESP_DEBUG_STATE ,Target response state machine" "Send,Wait"
|
|
textline " "
|
|
rbitfld.long 0x0C 29. " TARGET_IDLE ,Target idle" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x0C 28. " RESP_FIFO_FULL ,Target response FIFO full" "Not full,Full"
|
|
textline " "
|
|
rbitfld.long 0x0C 27. " CMD_FIFO_FULL ,Target command FIFO full" "Not full,Full"
|
|
textline " "
|
|
rbitfld.long 0x0C 26. " RESP_ERROR ,Respond to OCP with error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 21.--25. " WHICH_TARGET_REGISTER ,Indicates which OCP target registers to read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x0C 18.--20. " TARGET_CMD_OUT ,Command received from OCP" "WRSYS,RDSYS,WR_ERROR,RD_ERROR,CHK_WRADDR_PAGE,CHK_RDADDR_PAGE,TARGET_REG_WRITE,TARGET_REG_READ"
|
|
textline " "
|
|
rbitfld.long 0x0C 17. " INIT_MSTANDBY ,Status of init_MStandby signal" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x0C 16. " INIT_MWAIT ,Status of init_MWait signal" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x0C 14.--15. " INIT_MDISCREQ ,Disconnect status of the OCP interface" "FUNCT,SLEEP TRANS,Reserved,IDLE"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " INIT_MDISCACK ,Memory request FIFO full" "Not full,Full"
|
|
textline " "
|
|
rbitfld.long 0x0C 12. " INIT_SCONNECT2 ,Defines whether to wait in M_WAIT state for MConnect FSM" "Skip,Wait"
|
|
textline " "
|
|
rbitfld.long 0x0C 11. " INIT_SCONNECT1 ,Defines the busy-ness state of the slave" "Drained,Loaded"
|
|
textline " "
|
|
rbitfld.long 0x0C 10. " INIT_SCONNECT0 ,Disconnect from slave" "Disconnected,Connected"
|
|
textline " "
|
|
rbitfld.long 0x0C 8.--9. " INIT_MCONNECT ,Initiator MConnect state" "M_OFF,M_WAIT,M_DISC,M_CON"
|
|
textline " "
|
|
rbitfld.long 0x0C 6.--7. " TARGET_SIDLEACK ,Acknowledge the SIdleAck state machine" "FUNCT,SLEEP TRANS,Reserved,IDLE"
|
|
textline " "
|
|
rbitfld.long 0x0C 4.--5. " TARGET_SDISCACK ,Acknowledge the SDiscAck state machine" "FUNCT,TRANS,Reserved,IDLE"
|
|
textline " "
|
|
rbitfld.long 0x0C 3. " TARGET_SIDLEREQ ,Request the target to go idle" "Not idle/go active,Go idle"
|
|
textline " "
|
|
rbitfld.long 0x0C 2. " TARGET_SCONNECT ,Target SConnect state" "Disconnected,Connected"
|
|
textline " "
|
|
rbitfld.long 0x0C 0.--1. " TARGET_MCONNECT ,Target MConnect state" "M_OFF,M_WAIT,M_DISC,M_CON"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpuis("DRA62*"))
|
|
tree.open "MAILBOX (Mailbox Registers)"
|
|
tree "MAILBOX1"
|
|
base ad:0x480c8000
|
|
width 23.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "MAILBOX_REVISION,Mailbox IP Revision Code"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MAILBOX_SYSCONFIG,Mailbox System Configuration Register"
|
|
sif (cpu()=="AM3874")||(cpu()=="AM3872")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
|
|
bitfld.long 0x00 2.--3. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
else
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
endif
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
sif (cpu()!="AM3874")&&(cpu()!="AM3872")&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MAILBOX_SYSSTATUS,Mailbox Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "On-going,Completed"
|
|
endif
|
|
group.long 0x40++0x2f
|
|
line.long 0x0 "MAILBOX_MESSAGE_0,Mailbox Message 0 Register"
|
|
line.long 0x4 "MAILBOX_MESSAGE_1,Mailbox Message 1 Register"
|
|
line.long 0x8 "MAILBOX_MESSAGE_2,Mailbox Message 2 Register"
|
|
line.long 0xC "MAILBOX_MESSAGE_3,Mailbox Message 3 Register"
|
|
line.long 0x10 "MAILBOX_MESSAGE_4,Mailbox Message 4 Register"
|
|
line.long 0x14 "MAILBOX_MESSAGE_5,Mailbox Message 5 Register"
|
|
line.long 0x18 "MAILBOX_MESSAGE_6,Mailbox Message 6 Register"
|
|
line.long 0x1C "MAILBOX_MESSAGE_7,Mailbox Message 7 Register"
|
|
line.long 0x20 "MAILBOX_MESSAGE_8,Mailbox Message 8 Register"
|
|
line.long 0x24 "MAILBOX_MESSAGE_9,Mailbox Message 9 Register"
|
|
line.long 0x28 "MAILBOX_MESSAGE_10,Mailbox Message 10 Register"
|
|
line.long 0x2C "MAILBOX_MESSAGE_11,Mailbox Message 11 Register"
|
|
rgroup.long 0x80++0x2f
|
|
line.long 0x0 "MAILBOX_FIFOSTATUS_0 ,Mailbox FIFO Status 0 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x0 1.--31. 1. " MESSAGEVALUEMB0 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 0. " FIFOFULLMB0 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x4 "MAILBOX_FIFOSTATUS_1 ,Mailbox FIFO Status 1 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x4 1.--31. 1. " MESSAGEVALUEMB1 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 0. " FIFOFULLMB1 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x8 "MAILBOX_FIFOSTATUS_2 ,Mailbox FIFO Status 2 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x8 1.--31. 1. " MESSAGEVALUEMB2 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 0. " FIFOFULLMB2 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0xC "MAILBOX_FIFOSTATUS_3 ,Mailbox FIFO Status 3 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0xC 1.--31. 1. " MESSAGEVALUEMB3 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 0. " FIFOFULLMB3 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x10 "MAILBOX_FIFOSTATUS_4 ,Mailbox FIFO Status 4 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x10 1.--31. 1. " MESSAGEVALUEMB4 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " FIFOFULLMB4 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x14 "MAILBOX_FIFOSTATUS_5 ,Mailbox FIFO Status 5 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x14 1.--31. 1. " MESSAGEVALUEMB5 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 0. " FIFOFULLMB5 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x18 "MAILBOX_FIFOSTATUS_6 ,Mailbox FIFO Status 6 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x18 1.--31. 1. " MESSAGEVALUEMB6 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 0. " FIFOFULLMB6 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x1C "MAILBOX_FIFOSTATUS_7 ,Mailbox FIFO Status 7 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x1C 1.--31. 1. " MESSAGEVALUEMB7 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 0. " FIFOFULLMB7 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x20 "MAILBOX_FIFOSTATUS_8 ,Mailbox FIFO Status 8 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x20 1.--31. 1. " MESSAGEVALUEMB8 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 0. " FIFOFULLMB8 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x24 "MAILBOX_FIFOSTATUS_9 ,Mailbox FIFO Status 9 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x24 1.--31. 1. " MESSAGEVALUEMB9 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 0. " FIFOFULLMB9 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x28 "MAILBOX_FIFOSTATUS_10,Mailbox FIFO Status 10 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x28 1.--31. 1. " MESSAGEVALUEMB10 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 0. " FIFOFULLMB10 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x2C "MAILBOX_FIFOSTATUS_11,Mailbox FIFO Status 11 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x2C 1.--31. 1. " MESSAGEVALUEMB11 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 0. " FIFOFULLMB11 ,Full flag for Mailbox" "Not full,Full"
|
|
rgroup.long 0xC0++0x2f
|
|
line.long 0x0 "MAILBOX_MSGSTATUS_0 ,Mailbox Message Status 0 Register"
|
|
bitfld.long 0x0 0.--2. " NBOFMSGMBM0 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x4 "MAILBOX_MSGSTATUS_1 ,Mailbox Message Status 1 Register"
|
|
bitfld.long 0x4 0.--2. " NBOFMSGMBM1 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x8 "MAILBOX_MSGSTATUS_2 ,Mailbox Message Status 2 Register"
|
|
bitfld.long 0x8 0.--2. " NBOFMSGMBM2 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0xC "MAILBOX_MSGSTATUS_3 ,Mailbox Message Status 3 Register"
|
|
bitfld.long 0xC 0.--2. " NBOFMSGMBM3 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x10 "MAILBOX_MSGSTATUS_4 ,Mailbox Message Status 4 Register"
|
|
bitfld.long 0x10 0.--2. " NBOFMSGMBM4 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x14 "MAILBOX_MSGSTATUS_5 ,Mailbox Message Status 5 Register"
|
|
bitfld.long 0x14 0.--2. " NBOFMSGMBM5 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x18 "MAILBOX_MSGSTATUS_6 ,Mailbox Message Status 6 Register"
|
|
bitfld.long 0x18 0.--2. " NBOFMSGMBM6 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x1C "MAILBOX_MSGSTATUS_7 ,Mailbox Message Status 7 Register"
|
|
bitfld.long 0x1C 0.--2. " NBOFMSGMBM7 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x20 "MAILBOX_MSGSTATUS_8 ,Mailbox Message Status 8 Register"
|
|
bitfld.long 0x20 0.--2. " NBOFMSGMBM8 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x24 "MAILBOX_MSGSTATUS_9 ,Mailbox Message Status 9 Register"
|
|
bitfld.long 0x24 0.--2. " NBOFMSGMBM9 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x28 "MAILBOX_MSGSTATUS_10,Mailbox Message Status 10 Register"
|
|
bitfld.long 0x28 0.--2. " NBOFMSGMBM10 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x2C "MAILBOX_MSGSTATUS_11,Mailbox Message Status 11 Register"
|
|
bitfld.long 0x2C 0.--2. " NBOFMSGMBM11 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
width 25.
|
|
tree "User 0 Mailbox Interrupts"
|
|
group.long (0x100+0x0)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_0,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU0MB11 ,NotFull Raw Status bit for User 0 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU0MB11 ,NewMessage Raw Status bit for User 0 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU0MB10 ,NotFull Raw Status bit for User 0 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU0MB10 ,NewMessage Raw Status bit for User 0 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU0MB9 ,NotFull Raw Status bit for User 0 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU0MB9 ,NewMessage Raw Status bit for User 0 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU0MB8 ,NotFull Raw Status bit for User 0 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU0MB8 ,NewMessage Raw Status bit for User 0 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU0MB7 ,NotFull Raw Status bit for User 0 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU0MB7 ,NewMessage Raw Status bit for User 0 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU0MB6 ,NotFull Raw Status bit for User 0 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU0MB6 ,NewMessage Raw Status bit for User 0 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU0MB5 ,NotFull Raw Status bit for User 0 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU0MB5 ,NewMessage Raw Status bit for User 0 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU0MB4 ,NotFull Raw Status bit for User 0 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU0MB4 ,NewMessage Raw Status bit for User 0 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU0MB3 ,NotFull Raw Status bit for User 0 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU0MB3 ,NewMessage Raw Status bit for User 0 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU0MB2 ,NotFull Raw Status bit for User 0 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU0MB2 ,NewMessage Raw Status bit for User 0 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU0MB1 ,NotFull Raw Status bit for User 0 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU0MB1 ,NewMessage Raw Status bit for User 0 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU0MB0 ,NotFull Raw Status bit for User 0 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU0MB0 ,NewMessage Raw Status bit for User 0 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_0,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU0MB11 ,NotFull Clear Status bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU0MB11 ,NewMessage Clear Status bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU0MB10 ,NotFull Clear Status bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU0MB10 ,NewMessage Clear Status bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU0MB9 ,NotFull Clear Status bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU0MB9 ,NewMessage Clear Status bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU0MB8 ,NotFull Clear Status bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU0MB8 ,NewMessage Clear Status bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU0MB7 ,NotFull Clear Status bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU0MB7 ,NewMessage Clear Status bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU0MB6 ,NotFull Clear Status bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU0MB6 ,NewMessage Clear Status bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU0MB5 ,NotFull Clear Status bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU0MB5 ,NewMessage Clear Status bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU0MB4 ,NotFull Clear Status bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU0MB4 ,NewMessage Clear Status bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU0MB3 ,NotFull Clear Status bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU0MB3 ,NewMessage Clear Status bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU0MB2 ,NotFull Clear Status bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU0MB2 ,NewMessage Clear Status bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU0MB1 ,NotFull Clear Status bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU0MB1 ,NewMessage Clear Status bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU0MB0 ,NotFull Clear Status bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU0MB0 ,NewMessage Clear Status bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_0,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU0MB11 ,NotFull Enable Set bit for User 0 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU0MB11 ,NewMessage Enable Set bit for User 0 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU0MB10 ,NotFull Enable Set bit for User 0 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU0MB10 ,NewMessage Enable Set bit for User 0 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU0MB9 ,NotFull Enable Set bit for User 0 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU0MB9 ,NewMessage Enable Set bit for User 0 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU0MB8 ,NotFull Enable Set bit for User 0 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU0MB8 ,NewMessage Enable Set bit for User 0 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU0MB7 ,NotFull Enable Set bit for User 0 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU0MB7 ,NewMessage Enable Set bit for User 0 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU0MB6 ,NotFull Enable Set bit for User 0 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU0MB6 ,NewMessage Enable Set bit for User 0 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU0MB5 ,NotFull Enable Set bit for User 0 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU0MB5 ,NewMessage Enable Set bit for User 0 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU0MB4 ,NotFull Enable Set bit for User 0 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU0MB4 ,NewMessage Enable Set bit for User 0 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU0MB3 ,NotFull Enable Set bit for User 0 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU0MB3 ,NewMessage Enable Set bit for User 0 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU0MB2 ,NotFull Enable Set bit for User 0 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU0MB2 ,NewMessage Enable Set bit for User 0 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU0MB1 ,NotFull Enable Set bit for User 0 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU0MB1 ,NewMessage Enable Set bit for User 0 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU0MB0 ,NotFull Enable Set bit for User 0 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU0MB0 ,NewMessage Enable Set bit for User 0 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_0,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU0MB11 ,NotFull Enable Clear bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU0MB11 ,NewMessage Enable Clear bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU0MB10 ,NotFull Enable Clear bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU0MB10 ,NewMessage Enable Clear bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU0MB9 ,NotFull Enable Clear bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU0MB9 ,NewMessage Enable Clear bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU0MB8 ,NotFull Enable Clear bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU0MB8 ,NewMessage Enable Clear bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU0MB7 ,NotFull Enable Clear bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU0MB7 ,NewMessage Enable Clear bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU0MB6 ,NotFull Enable Clear bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU0MB6 ,NewMessage Enable Clear bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU0MB5 ,NotFull Enable Clear bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU0MB5 ,NewMessage Enable Clear bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU0MB4 ,NotFull Enable Clear bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU0MB4 ,NewMessage Enable Clear bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU0MB3 ,NotFull Enable Clear bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU0MB3 ,NewMessage Enable Clear bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU0MB2 ,NotFull Enable Clear bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU0MB2 ,NewMessage Enable Clear bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU0MB1 ,NotFull Enable Clear bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU0MB1 ,NewMessage Enable Clear bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU0MB0 ,NotFull Enable Clear bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU0MB0 ,NewMessage Enable Clear bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
tree "User 1 Mailbox Interrupts"
|
|
group.long (0x100+0x10)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_1,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU1MB11 ,NotFull Raw Status bit for User 1 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU1MB11 ,NewMessage Raw Status bit for User 1 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU1MB10 ,NotFull Raw Status bit for User 1 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU1MB10 ,NewMessage Raw Status bit for User 1 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU1MB9 ,NotFull Raw Status bit for User 1 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU1MB9 ,NewMessage Raw Status bit for User 1 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU1MB8 ,NotFull Raw Status bit for User 1 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU1MB8 ,NewMessage Raw Status bit for User 1 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU1MB7 ,NotFull Raw Status bit for User 1 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU1MB7 ,NewMessage Raw Status bit for User 1 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU1MB6 ,NotFull Raw Status bit for User 1 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU1MB6 ,NewMessage Raw Status bit for User 1 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU1MB5 ,NotFull Raw Status bit for User 1 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU1MB5 ,NewMessage Raw Status bit for User 1 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU1MB4 ,NotFull Raw Status bit for User 1 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU1MB4 ,NewMessage Raw Status bit for User 1 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU1MB3 ,NotFull Raw Status bit for User 1 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU1MB3 ,NewMessage Raw Status bit for User 1 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU1MB2 ,NotFull Raw Status bit for User 1 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU1MB2 ,NewMessage Raw Status bit for User 1 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU1MB1 ,NotFull Raw Status bit for User 1 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU1MB1 ,NewMessage Raw Status bit for User 1 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU1MB0 ,NotFull Raw Status bit for User 1 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU1MB0 ,NewMessage Raw Status bit for User 1 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_1,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU1MB11 ,NotFull Clear Status bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU1MB11 ,NewMessage Clear Status bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU1MB10 ,NotFull Clear Status bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU1MB10 ,NewMessage Clear Status bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU1MB9 ,NotFull Clear Status bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU1MB9 ,NewMessage Clear Status bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU1MB8 ,NotFull Clear Status bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU1MB8 ,NewMessage Clear Status bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU1MB7 ,NotFull Clear Status bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU1MB7 ,NewMessage Clear Status bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU1MB6 ,NotFull Clear Status bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU1MB6 ,NewMessage Clear Status bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU1MB5 ,NotFull Clear Status bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU1MB5 ,NewMessage Clear Status bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU1MB4 ,NotFull Clear Status bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU1MB4 ,NewMessage Clear Status bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU1MB3 ,NotFull Clear Status bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU1MB3 ,NewMessage Clear Status bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU1MB2 ,NotFull Clear Status bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU1MB2 ,NewMessage Clear Status bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU1MB1 ,NotFull Clear Status bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU1MB1 ,NewMessage Clear Status bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU1MB0 ,NotFull Clear Status bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU1MB0 ,NewMessage Clear Status bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_1,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU1MB11 ,NotFull Enable Set bit for User 1 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU1MB11 ,NewMessage Enable Set bit for User 1 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU1MB10 ,NotFull Enable Set bit for User 1 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU1MB10 ,NewMessage Enable Set bit for User 1 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU1MB9 ,NotFull Enable Set bit for User 1 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU1MB9 ,NewMessage Enable Set bit for User 1 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU1MB8 ,NotFull Enable Set bit for User 1 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU1MB8 ,NewMessage Enable Set bit for User 1 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU1MB7 ,NotFull Enable Set bit for User 1 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU1MB7 ,NewMessage Enable Set bit for User 1 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU1MB6 ,NotFull Enable Set bit for User 1 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU1MB6 ,NewMessage Enable Set bit for User 1 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU1MB5 ,NotFull Enable Set bit for User 1 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU1MB5 ,NewMessage Enable Set bit for User 1 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU1MB4 ,NotFull Enable Set bit for User 1 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU1MB4 ,NewMessage Enable Set bit for User 1 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU1MB3 ,NotFull Enable Set bit for User 1 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU1MB3 ,NewMessage Enable Set bit for User 1 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU1MB2 ,NotFull Enable Set bit for User 1 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU1MB2 ,NewMessage Enable Set bit for User 1 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU1MB1 ,NotFull Enable Set bit for User 1 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU1MB1 ,NewMessage Enable Set bit for User 1 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU1MB0 ,NotFull Enable Set bit for User 1 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU1MB0 ,NewMessage Enable Set bit for User 1 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_1,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU1MB11 ,NotFull Enable Clear bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU1MB11 ,NewMessage Enable Clear bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU1MB10 ,NotFull Enable Clear bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU1MB10 ,NewMessage Enable Clear bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU1MB9 ,NotFull Enable Clear bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU1MB9 ,NewMessage Enable Clear bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU1MB8 ,NotFull Enable Clear bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU1MB8 ,NewMessage Enable Clear bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU1MB7 ,NotFull Enable Clear bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU1MB7 ,NewMessage Enable Clear bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU1MB6 ,NotFull Enable Clear bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU1MB6 ,NewMessage Enable Clear bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU1MB5 ,NotFull Enable Clear bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU1MB5 ,NewMessage Enable Clear bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU1MB4 ,NotFull Enable Clear bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU1MB4 ,NewMessage Enable Clear bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU1MB3 ,NotFull Enable Clear bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU1MB3 ,NewMessage Enable Clear bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU1MB2 ,NotFull Enable Clear bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU1MB2 ,NewMessage Enable Clear bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU1MB1 ,NotFull Enable Clear bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU1MB1 ,NewMessage Enable Clear bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU1MB0 ,NotFull Enable Clear bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU1MB0 ,NewMessage Enable Clear bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
tree "User 2 Mailbox Interrupts"
|
|
group.long (0x100+0x20)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_2,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU2MB11 ,NotFull Raw Status bit for User 2 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU2MB11 ,NewMessage Raw Status bit for User 2 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU2MB10 ,NotFull Raw Status bit for User 2 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU2MB10 ,NewMessage Raw Status bit for User 2 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU2MB9 ,NotFull Raw Status bit for User 2 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU2MB9 ,NewMessage Raw Status bit for User 2 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU2MB8 ,NotFull Raw Status bit for User 2 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU2MB8 ,NewMessage Raw Status bit for User 2 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU2MB7 ,NotFull Raw Status bit for User 2 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU2MB7 ,NewMessage Raw Status bit for User 2 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU2MB6 ,NotFull Raw Status bit for User 2 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU2MB6 ,NewMessage Raw Status bit for User 2 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU2MB5 ,NotFull Raw Status bit for User 2 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU2MB5 ,NewMessage Raw Status bit for User 2 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU2MB4 ,NotFull Raw Status bit for User 2 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU2MB4 ,NewMessage Raw Status bit for User 2 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU2MB3 ,NotFull Raw Status bit for User 2 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU2MB3 ,NewMessage Raw Status bit for User 2 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU2MB2 ,NotFull Raw Status bit for User 2 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU2MB2 ,NewMessage Raw Status bit for User 2 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU2MB1 ,NotFull Raw Status bit for User 2 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU2MB1 ,NewMessage Raw Status bit for User 2 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU2MB0 ,NotFull Raw Status bit for User 2 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU2MB0 ,NewMessage Raw Status bit for User 2 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_2,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU2MB11 ,NotFull Clear Status bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU2MB11 ,NewMessage Clear Status bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU2MB10 ,NotFull Clear Status bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU2MB10 ,NewMessage Clear Status bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU2MB9 ,NotFull Clear Status bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU2MB9 ,NewMessage Clear Status bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU2MB8 ,NotFull Clear Status bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU2MB8 ,NewMessage Clear Status bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU2MB7 ,NotFull Clear Status bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU2MB7 ,NewMessage Clear Status bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU2MB6 ,NotFull Clear Status bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU2MB6 ,NewMessage Clear Status bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU2MB5 ,NotFull Clear Status bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU2MB5 ,NewMessage Clear Status bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU2MB4 ,NotFull Clear Status bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU2MB4 ,NewMessage Clear Status bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU2MB3 ,NotFull Clear Status bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU2MB3 ,NewMessage Clear Status bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU2MB2 ,NotFull Clear Status bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU2MB2 ,NewMessage Clear Status bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU2MB1 ,NotFull Clear Status bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU2MB1 ,NewMessage Clear Status bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU2MB0 ,NotFull Clear Status bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU2MB0 ,NewMessage Clear Status bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_2,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU2MB11 ,NotFull Enable Set bit for User 2 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU2MB11 ,NewMessage Enable Set bit for User 2 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU2MB10 ,NotFull Enable Set bit for User 2 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU2MB10 ,NewMessage Enable Set bit for User 2 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU2MB9 ,NotFull Enable Set bit for User 2 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU2MB9 ,NewMessage Enable Set bit for User 2 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU2MB8 ,NotFull Enable Set bit for User 2 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU2MB8 ,NewMessage Enable Set bit for User 2 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU2MB7 ,NotFull Enable Set bit for User 2 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU2MB7 ,NewMessage Enable Set bit for User 2 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU2MB6 ,NotFull Enable Set bit for User 2 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU2MB6 ,NewMessage Enable Set bit for User 2 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU2MB5 ,NotFull Enable Set bit for User 2 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU2MB5 ,NewMessage Enable Set bit for User 2 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU2MB4 ,NotFull Enable Set bit for User 2 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU2MB4 ,NewMessage Enable Set bit for User 2 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU2MB3 ,NotFull Enable Set bit for User 2 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU2MB3 ,NewMessage Enable Set bit for User 2 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU2MB2 ,NotFull Enable Set bit for User 2 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU2MB2 ,NewMessage Enable Set bit for User 2 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU2MB1 ,NotFull Enable Set bit for User 2 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU2MB1 ,NewMessage Enable Set bit for User 2 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU2MB0 ,NotFull Enable Set bit for User 2 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU2MB0 ,NewMessage Enable Set bit for User 2 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_2,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU2MB11 ,NotFull Enable Clear bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU2MB11 ,NewMessage Enable Clear bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU2MB10 ,NotFull Enable Clear bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU2MB10 ,NewMessage Enable Clear bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU2MB9 ,NotFull Enable Clear bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU2MB9 ,NewMessage Enable Clear bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU2MB8 ,NotFull Enable Clear bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU2MB8 ,NewMessage Enable Clear bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU2MB7 ,NotFull Enable Clear bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU2MB7 ,NewMessage Enable Clear bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU2MB6 ,NotFull Enable Clear bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU2MB6 ,NewMessage Enable Clear bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU2MB5 ,NotFull Enable Clear bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU2MB5 ,NewMessage Enable Clear bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU2MB4 ,NotFull Enable Clear bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU2MB4 ,NewMessage Enable Clear bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU2MB3 ,NotFull Enable Clear bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU2MB3 ,NewMessage Enable Clear bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU2MB2 ,NotFull Enable Clear bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU2MB2 ,NewMessage Enable Clear bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU2MB1 ,NotFull Enable Clear bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU2MB1 ,NewMessage Enable Clear bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU2MB0 ,NotFull Enable Clear bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU2MB0 ,NewMessage Enable Clear bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
tree "User 3 Mailbox Interrupts"
|
|
group.long (0x100+0x30)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_3,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU3MB11 ,NotFull Raw Status bit for User 3 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU3MB11 ,NewMessage Raw Status bit for User 3 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU3MB10 ,NotFull Raw Status bit for User 3 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU3MB10 ,NewMessage Raw Status bit for User 3 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU3MB9 ,NotFull Raw Status bit for User 3 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU3MB9 ,NewMessage Raw Status bit for User 3 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU3MB8 ,NotFull Raw Status bit for User 3 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU3MB8 ,NewMessage Raw Status bit for User 3 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU3MB7 ,NotFull Raw Status bit for User 3 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU3MB7 ,NewMessage Raw Status bit for User 3 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU3MB6 ,NotFull Raw Status bit for User 3 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU3MB6 ,NewMessage Raw Status bit for User 3 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU3MB5 ,NotFull Raw Status bit for User 3 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU3MB5 ,NewMessage Raw Status bit for User 3 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU3MB4 ,NotFull Raw Status bit for User 3 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU3MB4 ,NewMessage Raw Status bit for User 3 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU3MB3 ,NotFull Raw Status bit for User 3 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU3MB3 ,NewMessage Raw Status bit for User 3 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU3MB2 ,NotFull Raw Status bit for User 3 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU3MB2 ,NewMessage Raw Status bit for User 3 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU3MB1 ,NotFull Raw Status bit for User 3 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU3MB1 ,NewMessage Raw Status bit for User 3 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU3MB0 ,NotFull Raw Status bit for User 3 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU3MB0 ,NewMessage Raw Status bit for User 3 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_3,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU3MB11 ,NotFull Clear Status bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU3MB11 ,NewMessage Clear Status bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU3MB10 ,NotFull Clear Status bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU3MB10 ,NewMessage Clear Status bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU3MB9 ,NotFull Clear Status bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU3MB9 ,NewMessage Clear Status bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU3MB8 ,NotFull Clear Status bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU3MB8 ,NewMessage Clear Status bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU3MB7 ,NotFull Clear Status bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU3MB7 ,NewMessage Clear Status bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU3MB6 ,NotFull Clear Status bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU3MB6 ,NewMessage Clear Status bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU3MB5 ,NotFull Clear Status bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU3MB5 ,NewMessage Clear Status bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU3MB4 ,NotFull Clear Status bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU3MB4 ,NewMessage Clear Status bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU3MB3 ,NotFull Clear Status bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU3MB3 ,NewMessage Clear Status bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU3MB2 ,NotFull Clear Status bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU3MB2 ,NewMessage Clear Status bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU3MB1 ,NotFull Clear Status bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU3MB1 ,NewMessage Clear Status bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU3MB0 ,NotFull Clear Status bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU3MB0 ,NewMessage Clear Status bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_3,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU3MB11 ,NotFull Enable Set bit for User 3 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU3MB11 ,NewMessage Enable Set bit for User 3 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU3MB10 ,NotFull Enable Set bit for User 3 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU3MB10 ,NewMessage Enable Set bit for User 3 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU3MB9 ,NotFull Enable Set bit for User 3 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU3MB9 ,NewMessage Enable Set bit for User 3 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU3MB8 ,NotFull Enable Set bit for User 3 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU3MB8 ,NewMessage Enable Set bit for User 3 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU3MB7 ,NotFull Enable Set bit for User 3 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU3MB7 ,NewMessage Enable Set bit for User 3 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU3MB6 ,NotFull Enable Set bit for User 3 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU3MB6 ,NewMessage Enable Set bit for User 3 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU3MB5 ,NotFull Enable Set bit for User 3 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU3MB5 ,NewMessage Enable Set bit for User 3 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU3MB4 ,NotFull Enable Set bit for User 3 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU3MB4 ,NewMessage Enable Set bit for User 3 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU3MB3 ,NotFull Enable Set bit for User 3 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU3MB3 ,NewMessage Enable Set bit for User 3 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU3MB2 ,NotFull Enable Set bit for User 3 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU3MB2 ,NewMessage Enable Set bit for User 3 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU3MB1 ,NotFull Enable Set bit for User 3 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU3MB1 ,NewMessage Enable Set bit for User 3 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU3MB0 ,NotFull Enable Set bit for User 3 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU3MB0 ,NewMessage Enable Set bit for User 3 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_3,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU3MB11 ,NotFull Enable Clear bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU3MB11 ,NewMessage Enable Clear bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU3MB10 ,NotFull Enable Clear bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU3MB10 ,NewMessage Enable Clear bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU3MB9 ,NotFull Enable Clear bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU3MB9 ,NewMessage Enable Clear bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU3MB8 ,NotFull Enable Clear bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU3MB8 ,NewMessage Enable Clear bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU3MB7 ,NotFull Enable Clear bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU3MB7 ,NewMessage Enable Clear bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU3MB6 ,NotFull Enable Clear bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU3MB6 ,NewMessage Enable Clear bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU3MB5 ,NotFull Enable Clear bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU3MB5 ,NewMessage Enable Clear bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU3MB4 ,NotFull Enable Clear bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU3MB4 ,NewMessage Enable Clear bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU3MB3 ,NotFull Enable Clear bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU3MB3 ,NewMessage Enable Clear bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU3MB2 ,NotFull Enable Clear bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU3MB2 ,NewMessage Enable Clear bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU3MB1 ,NotFull Enable Clear bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU3MB1 ,NewMessage Enable Clear bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU3MB0 ,NotFull Enable Clear bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU3MB0 ,NewMessage Enable Clear bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "MAILBOX2"
|
|
base ad:0x48459000
|
|
width 23.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "MAILBOX_REVISION,Mailbox IP Revision Code"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MAILBOX_SYSCONFIG,Mailbox System Configuration Register"
|
|
sif (cpu()=="AM3874")||(cpu()=="AM3872")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
|
|
bitfld.long 0x00 2.--3. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
else
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
endif
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
sif (cpu()!="AM3874")&&(cpu()!="AM3872")&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MAILBOX_SYSSTATUS,Mailbox Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "On-going,Completed"
|
|
endif
|
|
group.long 0x40++0x2f
|
|
line.long 0x0 "MAILBOX_MESSAGE_0,Mailbox Message 0 Register"
|
|
line.long 0x4 "MAILBOX_MESSAGE_1,Mailbox Message 1 Register"
|
|
line.long 0x8 "MAILBOX_MESSAGE_2,Mailbox Message 2 Register"
|
|
line.long 0xC "MAILBOX_MESSAGE_3,Mailbox Message 3 Register"
|
|
line.long 0x10 "MAILBOX_MESSAGE_4,Mailbox Message 4 Register"
|
|
line.long 0x14 "MAILBOX_MESSAGE_5,Mailbox Message 5 Register"
|
|
line.long 0x18 "MAILBOX_MESSAGE_6,Mailbox Message 6 Register"
|
|
line.long 0x1C "MAILBOX_MESSAGE_7,Mailbox Message 7 Register"
|
|
line.long 0x20 "MAILBOX_MESSAGE_8,Mailbox Message 8 Register"
|
|
line.long 0x24 "MAILBOX_MESSAGE_9,Mailbox Message 9 Register"
|
|
line.long 0x28 "MAILBOX_MESSAGE_10,Mailbox Message 10 Register"
|
|
line.long 0x2C "MAILBOX_MESSAGE_11,Mailbox Message 11 Register"
|
|
rgroup.long 0x80++0x2f
|
|
line.long 0x0 "MAILBOX_FIFOSTATUS_0 ,Mailbox FIFO Status 0 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x0 1.--31. 1. " MESSAGEVALUEMB0 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 0. " FIFOFULLMB0 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x4 "MAILBOX_FIFOSTATUS_1 ,Mailbox FIFO Status 1 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x4 1.--31. 1. " MESSAGEVALUEMB1 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 0. " FIFOFULLMB1 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x8 "MAILBOX_FIFOSTATUS_2 ,Mailbox FIFO Status 2 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x8 1.--31. 1. " MESSAGEVALUEMB2 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 0. " FIFOFULLMB2 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0xC "MAILBOX_FIFOSTATUS_3 ,Mailbox FIFO Status 3 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0xC 1.--31. 1. " MESSAGEVALUEMB3 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 0. " FIFOFULLMB3 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x10 "MAILBOX_FIFOSTATUS_4 ,Mailbox FIFO Status 4 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x10 1.--31. 1. " MESSAGEVALUEMB4 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " FIFOFULLMB4 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x14 "MAILBOX_FIFOSTATUS_5 ,Mailbox FIFO Status 5 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x14 1.--31. 1. " MESSAGEVALUEMB5 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 0. " FIFOFULLMB5 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x18 "MAILBOX_FIFOSTATUS_6 ,Mailbox FIFO Status 6 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x18 1.--31. 1. " MESSAGEVALUEMB6 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 0. " FIFOFULLMB6 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x1C "MAILBOX_FIFOSTATUS_7 ,Mailbox FIFO Status 7 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x1C 1.--31. 1. " MESSAGEVALUEMB7 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 0. " FIFOFULLMB7 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x20 "MAILBOX_FIFOSTATUS_8 ,Mailbox FIFO Status 8 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x20 1.--31. 1. " MESSAGEVALUEMB8 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 0. " FIFOFULLMB8 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x24 "MAILBOX_FIFOSTATUS_9 ,Mailbox FIFO Status 9 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x24 1.--31. 1. " MESSAGEVALUEMB9 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 0. " FIFOFULLMB9 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x28 "MAILBOX_FIFOSTATUS_10,Mailbox FIFO Status 10 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x28 1.--31. 1. " MESSAGEVALUEMB10 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 0. " FIFOFULLMB10 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x2C "MAILBOX_FIFOSTATUS_11,Mailbox FIFO Status 11 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x2C 1.--31. 1. " MESSAGEVALUEMB11 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 0. " FIFOFULLMB11 ,Full flag for Mailbox" "Not full,Full"
|
|
rgroup.long 0xC0++0x2f
|
|
line.long 0x0 "MAILBOX_MSGSTATUS_0 ,Mailbox Message Status 0 Register"
|
|
bitfld.long 0x0 0.--2. " NBOFMSGMBM0 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x4 "MAILBOX_MSGSTATUS_1 ,Mailbox Message Status 1 Register"
|
|
bitfld.long 0x4 0.--2. " NBOFMSGMBM1 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x8 "MAILBOX_MSGSTATUS_2 ,Mailbox Message Status 2 Register"
|
|
bitfld.long 0x8 0.--2. " NBOFMSGMBM2 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0xC "MAILBOX_MSGSTATUS_3 ,Mailbox Message Status 3 Register"
|
|
bitfld.long 0xC 0.--2. " NBOFMSGMBM3 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x10 "MAILBOX_MSGSTATUS_4 ,Mailbox Message Status 4 Register"
|
|
bitfld.long 0x10 0.--2. " NBOFMSGMBM4 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x14 "MAILBOX_MSGSTATUS_5 ,Mailbox Message Status 5 Register"
|
|
bitfld.long 0x14 0.--2. " NBOFMSGMBM5 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x18 "MAILBOX_MSGSTATUS_6 ,Mailbox Message Status 6 Register"
|
|
bitfld.long 0x18 0.--2. " NBOFMSGMBM6 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x1C "MAILBOX_MSGSTATUS_7 ,Mailbox Message Status 7 Register"
|
|
bitfld.long 0x1C 0.--2. " NBOFMSGMBM7 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x20 "MAILBOX_MSGSTATUS_8 ,Mailbox Message Status 8 Register"
|
|
bitfld.long 0x20 0.--2. " NBOFMSGMBM8 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x24 "MAILBOX_MSGSTATUS_9 ,Mailbox Message Status 9 Register"
|
|
bitfld.long 0x24 0.--2. " NBOFMSGMBM9 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x28 "MAILBOX_MSGSTATUS_10,Mailbox Message Status 10 Register"
|
|
bitfld.long 0x28 0.--2. " NBOFMSGMBM10 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x2C "MAILBOX_MSGSTATUS_11,Mailbox Message Status 11 Register"
|
|
bitfld.long 0x2C 0.--2. " NBOFMSGMBM11 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
width 25.
|
|
tree "User 0 Mailbox Interrupts"
|
|
group.long (0x100+0x0)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_0,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU0MB11 ,NotFull Raw Status bit for User 0 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU0MB11 ,NewMessage Raw Status bit for User 0 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU0MB10 ,NotFull Raw Status bit for User 0 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU0MB10 ,NewMessage Raw Status bit for User 0 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU0MB9 ,NotFull Raw Status bit for User 0 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU0MB9 ,NewMessage Raw Status bit for User 0 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU0MB8 ,NotFull Raw Status bit for User 0 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU0MB8 ,NewMessage Raw Status bit for User 0 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU0MB7 ,NotFull Raw Status bit for User 0 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU0MB7 ,NewMessage Raw Status bit for User 0 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU0MB6 ,NotFull Raw Status bit for User 0 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU0MB6 ,NewMessage Raw Status bit for User 0 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU0MB5 ,NotFull Raw Status bit for User 0 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU0MB5 ,NewMessage Raw Status bit for User 0 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU0MB4 ,NotFull Raw Status bit for User 0 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU0MB4 ,NewMessage Raw Status bit for User 0 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU0MB3 ,NotFull Raw Status bit for User 0 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU0MB3 ,NewMessage Raw Status bit for User 0 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU0MB2 ,NotFull Raw Status bit for User 0 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU0MB2 ,NewMessage Raw Status bit for User 0 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU0MB1 ,NotFull Raw Status bit for User 0 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU0MB1 ,NewMessage Raw Status bit for User 0 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU0MB0 ,NotFull Raw Status bit for User 0 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU0MB0 ,NewMessage Raw Status bit for User 0 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_0,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU0MB11 ,NotFull Clear Status bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU0MB11 ,NewMessage Clear Status bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU0MB10 ,NotFull Clear Status bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU0MB10 ,NewMessage Clear Status bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU0MB9 ,NotFull Clear Status bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU0MB9 ,NewMessage Clear Status bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU0MB8 ,NotFull Clear Status bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU0MB8 ,NewMessage Clear Status bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU0MB7 ,NotFull Clear Status bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU0MB7 ,NewMessage Clear Status bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU0MB6 ,NotFull Clear Status bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU0MB6 ,NewMessage Clear Status bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU0MB5 ,NotFull Clear Status bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU0MB5 ,NewMessage Clear Status bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU0MB4 ,NotFull Clear Status bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU0MB4 ,NewMessage Clear Status bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU0MB3 ,NotFull Clear Status bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU0MB3 ,NewMessage Clear Status bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU0MB2 ,NotFull Clear Status bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU0MB2 ,NewMessage Clear Status bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU0MB1 ,NotFull Clear Status bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU0MB1 ,NewMessage Clear Status bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU0MB0 ,NotFull Clear Status bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU0MB0 ,NewMessage Clear Status bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_0,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU0MB11 ,NotFull Enable Set bit for User 0 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU0MB11 ,NewMessage Enable Set bit for User 0 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU0MB10 ,NotFull Enable Set bit for User 0 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU0MB10 ,NewMessage Enable Set bit for User 0 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU0MB9 ,NotFull Enable Set bit for User 0 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU0MB9 ,NewMessage Enable Set bit for User 0 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU0MB8 ,NotFull Enable Set bit for User 0 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU0MB8 ,NewMessage Enable Set bit for User 0 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU0MB7 ,NotFull Enable Set bit for User 0 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU0MB7 ,NewMessage Enable Set bit for User 0 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU0MB6 ,NotFull Enable Set bit for User 0 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU0MB6 ,NewMessage Enable Set bit for User 0 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU0MB5 ,NotFull Enable Set bit for User 0 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU0MB5 ,NewMessage Enable Set bit for User 0 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU0MB4 ,NotFull Enable Set bit for User 0 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU0MB4 ,NewMessage Enable Set bit for User 0 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU0MB3 ,NotFull Enable Set bit for User 0 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU0MB3 ,NewMessage Enable Set bit for User 0 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU0MB2 ,NotFull Enable Set bit for User 0 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU0MB2 ,NewMessage Enable Set bit for User 0 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU0MB1 ,NotFull Enable Set bit for User 0 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU0MB1 ,NewMessage Enable Set bit for User 0 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU0MB0 ,NotFull Enable Set bit for User 0 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU0MB0 ,NewMessage Enable Set bit for User 0 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_0,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU0MB11 ,NotFull Enable Clear bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU0MB11 ,NewMessage Enable Clear bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU0MB10 ,NotFull Enable Clear bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU0MB10 ,NewMessage Enable Clear bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU0MB9 ,NotFull Enable Clear bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU0MB9 ,NewMessage Enable Clear bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU0MB8 ,NotFull Enable Clear bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU0MB8 ,NewMessage Enable Clear bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU0MB7 ,NotFull Enable Clear bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU0MB7 ,NewMessage Enable Clear bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU0MB6 ,NotFull Enable Clear bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU0MB6 ,NewMessage Enable Clear bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU0MB5 ,NotFull Enable Clear bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU0MB5 ,NewMessage Enable Clear bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU0MB4 ,NotFull Enable Clear bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU0MB4 ,NewMessage Enable Clear bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU0MB3 ,NotFull Enable Clear bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU0MB3 ,NewMessage Enable Clear bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU0MB2 ,NotFull Enable Clear bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU0MB2 ,NewMessage Enable Clear bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU0MB1 ,NotFull Enable Clear bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU0MB1 ,NewMessage Enable Clear bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU0MB0 ,NotFull Enable Clear bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU0MB0 ,NewMessage Enable Clear bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
tree "User 1 Mailbox Interrupts"
|
|
group.long (0x100+0x10)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_1,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU1MB11 ,NotFull Raw Status bit for User 1 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU1MB11 ,NewMessage Raw Status bit for User 1 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU1MB10 ,NotFull Raw Status bit for User 1 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU1MB10 ,NewMessage Raw Status bit for User 1 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU1MB9 ,NotFull Raw Status bit for User 1 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU1MB9 ,NewMessage Raw Status bit for User 1 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU1MB8 ,NotFull Raw Status bit for User 1 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU1MB8 ,NewMessage Raw Status bit for User 1 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU1MB7 ,NotFull Raw Status bit for User 1 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU1MB7 ,NewMessage Raw Status bit for User 1 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU1MB6 ,NotFull Raw Status bit for User 1 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU1MB6 ,NewMessage Raw Status bit for User 1 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU1MB5 ,NotFull Raw Status bit for User 1 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU1MB5 ,NewMessage Raw Status bit for User 1 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU1MB4 ,NotFull Raw Status bit for User 1 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU1MB4 ,NewMessage Raw Status bit for User 1 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU1MB3 ,NotFull Raw Status bit for User 1 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU1MB3 ,NewMessage Raw Status bit for User 1 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU1MB2 ,NotFull Raw Status bit for User 1 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU1MB2 ,NewMessage Raw Status bit for User 1 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU1MB1 ,NotFull Raw Status bit for User 1 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU1MB1 ,NewMessage Raw Status bit for User 1 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU1MB0 ,NotFull Raw Status bit for User 1 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU1MB0 ,NewMessage Raw Status bit for User 1 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_1,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU1MB11 ,NotFull Clear Status bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU1MB11 ,NewMessage Clear Status bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU1MB10 ,NotFull Clear Status bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU1MB10 ,NewMessage Clear Status bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU1MB9 ,NotFull Clear Status bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU1MB9 ,NewMessage Clear Status bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU1MB8 ,NotFull Clear Status bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU1MB8 ,NewMessage Clear Status bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU1MB7 ,NotFull Clear Status bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU1MB7 ,NewMessage Clear Status bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU1MB6 ,NotFull Clear Status bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU1MB6 ,NewMessage Clear Status bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU1MB5 ,NotFull Clear Status bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU1MB5 ,NewMessage Clear Status bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU1MB4 ,NotFull Clear Status bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU1MB4 ,NewMessage Clear Status bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU1MB3 ,NotFull Clear Status bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU1MB3 ,NewMessage Clear Status bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU1MB2 ,NotFull Clear Status bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU1MB2 ,NewMessage Clear Status bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU1MB1 ,NotFull Clear Status bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU1MB1 ,NewMessage Clear Status bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU1MB0 ,NotFull Clear Status bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU1MB0 ,NewMessage Clear Status bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_1,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU1MB11 ,NotFull Enable Set bit for User 1 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU1MB11 ,NewMessage Enable Set bit for User 1 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU1MB10 ,NotFull Enable Set bit for User 1 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU1MB10 ,NewMessage Enable Set bit for User 1 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU1MB9 ,NotFull Enable Set bit for User 1 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU1MB9 ,NewMessage Enable Set bit for User 1 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU1MB8 ,NotFull Enable Set bit for User 1 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU1MB8 ,NewMessage Enable Set bit for User 1 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU1MB7 ,NotFull Enable Set bit for User 1 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU1MB7 ,NewMessage Enable Set bit for User 1 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU1MB6 ,NotFull Enable Set bit for User 1 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU1MB6 ,NewMessage Enable Set bit for User 1 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU1MB5 ,NotFull Enable Set bit for User 1 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU1MB5 ,NewMessage Enable Set bit for User 1 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU1MB4 ,NotFull Enable Set bit for User 1 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU1MB4 ,NewMessage Enable Set bit for User 1 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU1MB3 ,NotFull Enable Set bit for User 1 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU1MB3 ,NewMessage Enable Set bit for User 1 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU1MB2 ,NotFull Enable Set bit for User 1 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU1MB2 ,NewMessage Enable Set bit for User 1 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU1MB1 ,NotFull Enable Set bit for User 1 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU1MB1 ,NewMessage Enable Set bit for User 1 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU1MB0 ,NotFull Enable Set bit for User 1 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU1MB0 ,NewMessage Enable Set bit for User 1 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_1,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU1MB11 ,NotFull Enable Clear bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU1MB11 ,NewMessage Enable Clear bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU1MB10 ,NotFull Enable Clear bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU1MB10 ,NewMessage Enable Clear bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU1MB9 ,NotFull Enable Clear bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU1MB9 ,NewMessage Enable Clear bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU1MB8 ,NotFull Enable Clear bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU1MB8 ,NewMessage Enable Clear bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU1MB7 ,NotFull Enable Clear bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU1MB7 ,NewMessage Enable Clear bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU1MB6 ,NotFull Enable Clear bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU1MB6 ,NewMessage Enable Clear bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU1MB5 ,NotFull Enable Clear bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU1MB5 ,NewMessage Enable Clear bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU1MB4 ,NotFull Enable Clear bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU1MB4 ,NewMessage Enable Clear bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU1MB3 ,NotFull Enable Clear bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU1MB3 ,NewMessage Enable Clear bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU1MB2 ,NotFull Enable Clear bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU1MB2 ,NewMessage Enable Clear bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU1MB1 ,NotFull Enable Clear bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU1MB1 ,NewMessage Enable Clear bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU1MB0 ,NotFull Enable Clear bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU1MB0 ,NewMessage Enable Clear bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
tree "User 2 Mailbox Interrupts"
|
|
group.long (0x100+0x20)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_2,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU2MB11 ,NotFull Raw Status bit for User 2 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU2MB11 ,NewMessage Raw Status bit for User 2 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU2MB10 ,NotFull Raw Status bit for User 2 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU2MB10 ,NewMessage Raw Status bit for User 2 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU2MB9 ,NotFull Raw Status bit for User 2 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU2MB9 ,NewMessage Raw Status bit for User 2 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU2MB8 ,NotFull Raw Status bit for User 2 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU2MB8 ,NewMessage Raw Status bit for User 2 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU2MB7 ,NotFull Raw Status bit for User 2 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU2MB7 ,NewMessage Raw Status bit for User 2 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU2MB6 ,NotFull Raw Status bit for User 2 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU2MB6 ,NewMessage Raw Status bit for User 2 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU2MB5 ,NotFull Raw Status bit for User 2 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU2MB5 ,NewMessage Raw Status bit for User 2 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU2MB4 ,NotFull Raw Status bit for User 2 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU2MB4 ,NewMessage Raw Status bit for User 2 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU2MB3 ,NotFull Raw Status bit for User 2 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU2MB3 ,NewMessage Raw Status bit for User 2 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU2MB2 ,NotFull Raw Status bit for User 2 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU2MB2 ,NewMessage Raw Status bit for User 2 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU2MB1 ,NotFull Raw Status bit for User 2 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU2MB1 ,NewMessage Raw Status bit for User 2 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU2MB0 ,NotFull Raw Status bit for User 2 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU2MB0 ,NewMessage Raw Status bit for User 2 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_2,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU2MB11 ,NotFull Clear Status bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU2MB11 ,NewMessage Clear Status bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU2MB10 ,NotFull Clear Status bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU2MB10 ,NewMessage Clear Status bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU2MB9 ,NotFull Clear Status bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU2MB9 ,NewMessage Clear Status bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU2MB8 ,NotFull Clear Status bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU2MB8 ,NewMessage Clear Status bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU2MB7 ,NotFull Clear Status bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU2MB7 ,NewMessage Clear Status bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU2MB6 ,NotFull Clear Status bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU2MB6 ,NewMessage Clear Status bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU2MB5 ,NotFull Clear Status bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU2MB5 ,NewMessage Clear Status bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU2MB4 ,NotFull Clear Status bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU2MB4 ,NewMessage Clear Status bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU2MB3 ,NotFull Clear Status bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU2MB3 ,NewMessage Clear Status bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU2MB2 ,NotFull Clear Status bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU2MB2 ,NewMessage Clear Status bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU2MB1 ,NotFull Clear Status bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU2MB1 ,NewMessage Clear Status bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU2MB0 ,NotFull Clear Status bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU2MB0 ,NewMessage Clear Status bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_2,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU2MB11 ,NotFull Enable Set bit for User 2 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU2MB11 ,NewMessage Enable Set bit for User 2 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU2MB10 ,NotFull Enable Set bit for User 2 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU2MB10 ,NewMessage Enable Set bit for User 2 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU2MB9 ,NotFull Enable Set bit for User 2 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU2MB9 ,NewMessage Enable Set bit for User 2 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU2MB8 ,NotFull Enable Set bit for User 2 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU2MB8 ,NewMessage Enable Set bit for User 2 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU2MB7 ,NotFull Enable Set bit for User 2 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU2MB7 ,NewMessage Enable Set bit for User 2 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU2MB6 ,NotFull Enable Set bit for User 2 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU2MB6 ,NewMessage Enable Set bit for User 2 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU2MB5 ,NotFull Enable Set bit for User 2 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU2MB5 ,NewMessage Enable Set bit for User 2 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU2MB4 ,NotFull Enable Set bit for User 2 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU2MB4 ,NewMessage Enable Set bit for User 2 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU2MB3 ,NotFull Enable Set bit for User 2 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU2MB3 ,NewMessage Enable Set bit for User 2 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU2MB2 ,NotFull Enable Set bit for User 2 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU2MB2 ,NewMessage Enable Set bit for User 2 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU2MB1 ,NotFull Enable Set bit for User 2 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU2MB1 ,NewMessage Enable Set bit for User 2 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU2MB0 ,NotFull Enable Set bit for User 2 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU2MB0 ,NewMessage Enable Set bit for User 2 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_2,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU2MB11 ,NotFull Enable Clear bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU2MB11 ,NewMessage Enable Clear bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU2MB10 ,NotFull Enable Clear bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU2MB10 ,NewMessage Enable Clear bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU2MB9 ,NotFull Enable Clear bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU2MB9 ,NewMessage Enable Clear bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU2MB8 ,NotFull Enable Clear bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU2MB8 ,NewMessage Enable Clear bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU2MB7 ,NotFull Enable Clear bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU2MB7 ,NewMessage Enable Clear bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU2MB6 ,NotFull Enable Clear bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU2MB6 ,NewMessage Enable Clear bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU2MB5 ,NotFull Enable Clear bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU2MB5 ,NewMessage Enable Clear bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU2MB4 ,NotFull Enable Clear bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU2MB4 ,NewMessage Enable Clear bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU2MB3 ,NotFull Enable Clear bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU2MB3 ,NewMessage Enable Clear bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU2MB2 ,NotFull Enable Clear bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU2MB2 ,NewMessage Enable Clear bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU2MB1 ,NotFull Enable Clear bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU2MB1 ,NewMessage Enable Clear bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU2MB0 ,NotFull Enable Clear bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU2MB0 ,NewMessage Enable Clear bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
tree "User 3 Mailbox Interrupts"
|
|
group.long (0x100+0x30)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_3,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU3MB11 ,NotFull Raw Status bit for User 3 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU3MB11 ,NewMessage Raw Status bit for User 3 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU3MB10 ,NotFull Raw Status bit for User 3 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU3MB10 ,NewMessage Raw Status bit for User 3 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU3MB9 ,NotFull Raw Status bit for User 3 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU3MB9 ,NewMessage Raw Status bit for User 3 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU3MB8 ,NotFull Raw Status bit for User 3 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU3MB8 ,NewMessage Raw Status bit for User 3 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU3MB7 ,NotFull Raw Status bit for User 3 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU3MB7 ,NewMessage Raw Status bit for User 3 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU3MB6 ,NotFull Raw Status bit for User 3 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU3MB6 ,NewMessage Raw Status bit for User 3 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU3MB5 ,NotFull Raw Status bit for User 3 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU3MB5 ,NewMessage Raw Status bit for User 3 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU3MB4 ,NotFull Raw Status bit for User 3 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU3MB4 ,NewMessage Raw Status bit for User 3 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU3MB3 ,NotFull Raw Status bit for User 3 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU3MB3 ,NewMessage Raw Status bit for User 3 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU3MB2 ,NotFull Raw Status bit for User 3 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU3MB2 ,NewMessage Raw Status bit for User 3 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU3MB1 ,NotFull Raw Status bit for User 3 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU3MB1 ,NewMessage Raw Status bit for User 3 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU3MB0 ,NotFull Raw Status bit for User 3 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU3MB0 ,NewMessage Raw Status bit for User 3 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_3,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU3MB11 ,NotFull Clear Status bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU3MB11 ,NewMessage Clear Status bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU3MB10 ,NotFull Clear Status bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU3MB10 ,NewMessage Clear Status bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU3MB9 ,NotFull Clear Status bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU3MB9 ,NewMessage Clear Status bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU3MB8 ,NotFull Clear Status bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU3MB8 ,NewMessage Clear Status bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU3MB7 ,NotFull Clear Status bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU3MB7 ,NewMessage Clear Status bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU3MB6 ,NotFull Clear Status bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU3MB6 ,NewMessage Clear Status bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU3MB5 ,NotFull Clear Status bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU3MB5 ,NewMessage Clear Status bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU3MB4 ,NotFull Clear Status bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU3MB4 ,NewMessage Clear Status bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU3MB3 ,NotFull Clear Status bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU3MB3 ,NewMessage Clear Status bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU3MB2 ,NotFull Clear Status bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU3MB2 ,NewMessage Clear Status bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU3MB1 ,NotFull Clear Status bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU3MB1 ,NewMessage Clear Status bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU3MB0 ,NotFull Clear Status bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU3MB0 ,NewMessage Clear Status bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_3,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU3MB11 ,NotFull Enable Set bit for User 3 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU3MB11 ,NewMessage Enable Set bit for User 3 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU3MB10 ,NotFull Enable Set bit for User 3 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU3MB10 ,NewMessage Enable Set bit for User 3 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU3MB9 ,NotFull Enable Set bit for User 3 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU3MB9 ,NewMessage Enable Set bit for User 3 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU3MB8 ,NotFull Enable Set bit for User 3 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU3MB8 ,NewMessage Enable Set bit for User 3 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU3MB7 ,NotFull Enable Set bit for User 3 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU3MB7 ,NewMessage Enable Set bit for User 3 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU3MB6 ,NotFull Enable Set bit for User 3 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU3MB6 ,NewMessage Enable Set bit for User 3 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU3MB5 ,NotFull Enable Set bit for User 3 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU3MB5 ,NewMessage Enable Set bit for User 3 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU3MB4 ,NotFull Enable Set bit for User 3 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU3MB4 ,NewMessage Enable Set bit for User 3 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU3MB3 ,NotFull Enable Set bit for User 3 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU3MB3 ,NewMessage Enable Set bit for User 3 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU3MB2 ,NotFull Enable Set bit for User 3 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU3MB2 ,NewMessage Enable Set bit for User 3 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU3MB1 ,NotFull Enable Set bit for User 3 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU3MB1 ,NewMessage Enable Set bit for User 3 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU3MB0 ,NotFull Enable Set bit for User 3 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU3MB0 ,NewMessage Enable Set bit for User 3 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_3,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU3MB11 ,NotFull Enable Clear bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU3MB11 ,NewMessage Enable Clear bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU3MB10 ,NotFull Enable Clear bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU3MB10 ,NewMessage Enable Clear bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU3MB9 ,NotFull Enable Clear bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU3MB9 ,NewMessage Enable Clear bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU3MB8 ,NotFull Enable Clear bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU3MB8 ,NewMessage Enable Clear bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU3MB7 ,NotFull Enable Clear bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU3MB7 ,NewMessage Enable Clear bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU3MB6 ,NotFull Enable Clear bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU3MB6 ,NewMessage Enable Clear bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU3MB5 ,NotFull Enable Clear bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU3MB5 ,NewMessage Enable Clear bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU3MB4 ,NotFull Enable Clear bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU3MB4 ,NewMessage Enable Clear bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU3MB3 ,NotFull Enable Clear bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU3MB3 ,NewMessage Enable Clear bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU3MB2 ,NotFull Enable Clear bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU3MB2 ,NewMessage Enable Clear bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU3MB1 ,NotFull Enable Clear bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU3MB1 ,NewMessage Enable Clear bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU3MB0 ,NotFull Enable Clear bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU3MB0 ,NewMessage Enable Clear bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "MAILBOX3"
|
|
base ad:0x4845B000
|
|
width 23.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "MAILBOX_REVISION,Mailbox IP Revision Code"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MAILBOX_SYSCONFIG,Mailbox System Configuration Register"
|
|
sif (cpu()=="AM3874")||(cpu()=="AM3872")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
|
|
bitfld.long 0x00 2.--3. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
else
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
endif
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
sif (cpu()!="AM3874")&&(cpu()!="AM3872")&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MAILBOX_SYSSTATUS,Mailbox Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "On-going,Completed"
|
|
endif
|
|
group.long 0x40++0x2f
|
|
line.long 0x0 "MAILBOX_MESSAGE_0,Mailbox Message 0 Register"
|
|
line.long 0x4 "MAILBOX_MESSAGE_1,Mailbox Message 1 Register"
|
|
line.long 0x8 "MAILBOX_MESSAGE_2,Mailbox Message 2 Register"
|
|
line.long 0xC "MAILBOX_MESSAGE_3,Mailbox Message 3 Register"
|
|
line.long 0x10 "MAILBOX_MESSAGE_4,Mailbox Message 4 Register"
|
|
line.long 0x14 "MAILBOX_MESSAGE_5,Mailbox Message 5 Register"
|
|
line.long 0x18 "MAILBOX_MESSAGE_6,Mailbox Message 6 Register"
|
|
line.long 0x1C "MAILBOX_MESSAGE_7,Mailbox Message 7 Register"
|
|
line.long 0x20 "MAILBOX_MESSAGE_8,Mailbox Message 8 Register"
|
|
line.long 0x24 "MAILBOX_MESSAGE_9,Mailbox Message 9 Register"
|
|
line.long 0x28 "MAILBOX_MESSAGE_10,Mailbox Message 10 Register"
|
|
line.long 0x2C "MAILBOX_MESSAGE_11,Mailbox Message 11 Register"
|
|
rgroup.long 0x80++0x2f
|
|
line.long 0x0 "MAILBOX_FIFOSTATUS_0 ,Mailbox FIFO Status 0 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x0 1.--31. 1. " MESSAGEVALUEMB0 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 0. " FIFOFULLMB0 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x4 "MAILBOX_FIFOSTATUS_1 ,Mailbox FIFO Status 1 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x4 1.--31. 1. " MESSAGEVALUEMB1 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 0. " FIFOFULLMB1 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x8 "MAILBOX_FIFOSTATUS_2 ,Mailbox FIFO Status 2 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x8 1.--31. 1. " MESSAGEVALUEMB2 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 0. " FIFOFULLMB2 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0xC "MAILBOX_FIFOSTATUS_3 ,Mailbox FIFO Status 3 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0xC 1.--31. 1. " MESSAGEVALUEMB3 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 0. " FIFOFULLMB3 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x10 "MAILBOX_FIFOSTATUS_4 ,Mailbox FIFO Status 4 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x10 1.--31. 1. " MESSAGEVALUEMB4 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " FIFOFULLMB4 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x14 "MAILBOX_FIFOSTATUS_5 ,Mailbox FIFO Status 5 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x14 1.--31. 1. " MESSAGEVALUEMB5 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 0. " FIFOFULLMB5 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x18 "MAILBOX_FIFOSTATUS_6 ,Mailbox FIFO Status 6 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x18 1.--31. 1. " MESSAGEVALUEMB6 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 0. " FIFOFULLMB6 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x1C "MAILBOX_FIFOSTATUS_7 ,Mailbox FIFO Status 7 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x1C 1.--31. 1. " MESSAGEVALUEMB7 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 0. " FIFOFULLMB7 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x20 "MAILBOX_FIFOSTATUS_8 ,Mailbox FIFO Status 8 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x20 1.--31. 1. " MESSAGEVALUEMB8 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 0. " FIFOFULLMB8 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x24 "MAILBOX_FIFOSTATUS_9 ,Mailbox FIFO Status 9 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x24 1.--31. 1. " MESSAGEVALUEMB9 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 0. " FIFOFULLMB9 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x28 "MAILBOX_FIFOSTATUS_10,Mailbox FIFO Status 10 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x28 1.--31. 1. " MESSAGEVALUEMB10 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 0. " FIFOFULLMB10 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x2C "MAILBOX_FIFOSTATUS_11,Mailbox FIFO Status 11 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x2C 1.--31. 1. " MESSAGEVALUEMB11 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 0. " FIFOFULLMB11 ,Full flag for Mailbox" "Not full,Full"
|
|
rgroup.long 0xC0++0x2f
|
|
line.long 0x0 "MAILBOX_MSGSTATUS_0 ,Mailbox Message Status 0 Register"
|
|
bitfld.long 0x0 0.--2. " NBOFMSGMBM0 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x4 "MAILBOX_MSGSTATUS_1 ,Mailbox Message Status 1 Register"
|
|
bitfld.long 0x4 0.--2. " NBOFMSGMBM1 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x8 "MAILBOX_MSGSTATUS_2 ,Mailbox Message Status 2 Register"
|
|
bitfld.long 0x8 0.--2. " NBOFMSGMBM2 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0xC "MAILBOX_MSGSTATUS_3 ,Mailbox Message Status 3 Register"
|
|
bitfld.long 0xC 0.--2. " NBOFMSGMBM3 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x10 "MAILBOX_MSGSTATUS_4 ,Mailbox Message Status 4 Register"
|
|
bitfld.long 0x10 0.--2. " NBOFMSGMBM4 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x14 "MAILBOX_MSGSTATUS_5 ,Mailbox Message Status 5 Register"
|
|
bitfld.long 0x14 0.--2. " NBOFMSGMBM5 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x18 "MAILBOX_MSGSTATUS_6 ,Mailbox Message Status 6 Register"
|
|
bitfld.long 0x18 0.--2. " NBOFMSGMBM6 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x1C "MAILBOX_MSGSTATUS_7 ,Mailbox Message Status 7 Register"
|
|
bitfld.long 0x1C 0.--2. " NBOFMSGMBM7 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x20 "MAILBOX_MSGSTATUS_8 ,Mailbox Message Status 8 Register"
|
|
bitfld.long 0x20 0.--2. " NBOFMSGMBM8 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x24 "MAILBOX_MSGSTATUS_9 ,Mailbox Message Status 9 Register"
|
|
bitfld.long 0x24 0.--2. " NBOFMSGMBM9 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x28 "MAILBOX_MSGSTATUS_10,Mailbox Message Status 10 Register"
|
|
bitfld.long 0x28 0.--2. " NBOFMSGMBM10 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x2C "MAILBOX_MSGSTATUS_11,Mailbox Message Status 11 Register"
|
|
bitfld.long 0x2C 0.--2. " NBOFMSGMBM11 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
width 25.
|
|
tree "User 0 Mailbox Interrupts"
|
|
group.long (0x100+0x0)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_0,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU0MB11 ,NotFull Raw Status bit for User 0 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU0MB11 ,NewMessage Raw Status bit for User 0 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU0MB10 ,NotFull Raw Status bit for User 0 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU0MB10 ,NewMessage Raw Status bit for User 0 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU0MB9 ,NotFull Raw Status bit for User 0 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU0MB9 ,NewMessage Raw Status bit for User 0 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU0MB8 ,NotFull Raw Status bit for User 0 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU0MB8 ,NewMessage Raw Status bit for User 0 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU0MB7 ,NotFull Raw Status bit for User 0 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU0MB7 ,NewMessage Raw Status bit for User 0 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU0MB6 ,NotFull Raw Status bit for User 0 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU0MB6 ,NewMessage Raw Status bit for User 0 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU0MB5 ,NotFull Raw Status bit for User 0 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU0MB5 ,NewMessage Raw Status bit for User 0 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU0MB4 ,NotFull Raw Status bit for User 0 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU0MB4 ,NewMessage Raw Status bit for User 0 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU0MB3 ,NotFull Raw Status bit for User 0 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU0MB3 ,NewMessage Raw Status bit for User 0 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU0MB2 ,NotFull Raw Status bit for User 0 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU0MB2 ,NewMessage Raw Status bit for User 0 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU0MB1 ,NotFull Raw Status bit for User 0 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU0MB1 ,NewMessage Raw Status bit for User 0 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU0MB0 ,NotFull Raw Status bit for User 0 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU0MB0 ,NewMessage Raw Status bit for User 0 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_0,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU0MB11 ,NotFull Clear Status bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU0MB11 ,NewMessage Clear Status bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU0MB10 ,NotFull Clear Status bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU0MB10 ,NewMessage Clear Status bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU0MB9 ,NotFull Clear Status bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU0MB9 ,NewMessage Clear Status bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU0MB8 ,NotFull Clear Status bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU0MB8 ,NewMessage Clear Status bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU0MB7 ,NotFull Clear Status bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU0MB7 ,NewMessage Clear Status bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU0MB6 ,NotFull Clear Status bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU0MB6 ,NewMessage Clear Status bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU0MB5 ,NotFull Clear Status bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU0MB5 ,NewMessage Clear Status bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU0MB4 ,NotFull Clear Status bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU0MB4 ,NewMessage Clear Status bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU0MB3 ,NotFull Clear Status bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU0MB3 ,NewMessage Clear Status bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU0MB2 ,NotFull Clear Status bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU0MB2 ,NewMessage Clear Status bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU0MB1 ,NotFull Clear Status bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU0MB1 ,NewMessage Clear Status bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU0MB0 ,NotFull Clear Status bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU0MB0 ,NewMessage Clear Status bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_0,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU0MB11 ,NotFull Enable Set bit for User 0 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU0MB11 ,NewMessage Enable Set bit for User 0 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU0MB10 ,NotFull Enable Set bit for User 0 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU0MB10 ,NewMessage Enable Set bit for User 0 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU0MB9 ,NotFull Enable Set bit for User 0 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU0MB9 ,NewMessage Enable Set bit for User 0 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU0MB8 ,NotFull Enable Set bit for User 0 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU0MB8 ,NewMessage Enable Set bit for User 0 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU0MB7 ,NotFull Enable Set bit for User 0 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU0MB7 ,NewMessage Enable Set bit for User 0 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU0MB6 ,NotFull Enable Set bit for User 0 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU0MB6 ,NewMessage Enable Set bit for User 0 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU0MB5 ,NotFull Enable Set bit for User 0 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU0MB5 ,NewMessage Enable Set bit for User 0 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU0MB4 ,NotFull Enable Set bit for User 0 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU0MB4 ,NewMessage Enable Set bit for User 0 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU0MB3 ,NotFull Enable Set bit for User 0 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU0MB3 ,NewMessage Enable Set bit for User 0 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU0MB2 ,NotFull Enable Set bit for User 0 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU0MB2 ,NewMessage Enable Set bit for User 0 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU0MB1 ,NotFull Enable Set bit for User 0 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU0MB1 ,NewMessage Enable Set bit for User 0 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU0MB0 ,NotFull Enable Set bit for User 0 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU0MB0 ,NewMessage Enable Set bit for User 0 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_0,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU0MB11 ,NotFull Enable Clear bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU0MB11 ,NewMessage Enable Clear bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU0MB10 ,NotFull Enable Clear bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU0MB10 ,NewMessage Enable Clear bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU0MB9 ,NotFull Enable Clear bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU0MB9 ,NewMessage Enable Clear bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU0MB8 ,NotFull Enable Clear bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU0MB8 ,NewMessage Enable Clear bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU0MB7 ,NotFull Enable Clear bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU0MB7 ,NewMessage Enable Clear bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU0MB6 ,NotFull Enable Clear bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU0MB6 ,NewMessage Enable Clear bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU0MB5 ,NotFull Enable Clear bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU0MB5 ,NewMessage Enable Clear bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU0MB4 ,NotFull Enable Clear bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU0MB4 ,NewMessage Enable Clear bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU0MB3 ,NotFull Enable Clear bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU0MB3 ,NewMessage Enable Clear bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU0MB2 ,NotFull Enable Clear bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU0MB2 ,NewMessage Enable Clear bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU0MB1 ,NotFull Enable Clear bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU0MB1 ,NewMessage Enable Clear bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU0MB0 ,NotFull Enable Clear bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU0MB0 ,NewMessage Enable Clear bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
tree "User 1 Mailbox Interrupts"
|
|
group.long (0x100+0x10)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_1,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU1MB11 ,NotFull Raw Status bit for User 1 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU1MB11 ,NewMessage Raw Status bit for User 1 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU1MB10 ,NotFull Raw Status bit for User 1 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU1MB10 ,NewMessage Raw Status bit for User 1 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU1MB9 ,NotFull Raw Status bit for User 1 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU1MB9 ,NewMessage Raw Status bit for User 1 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU1MB8 ,NotFull Raw Status bit for User 1 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU1MB8 ,NewMessage Raw Status bit for User 1 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU1MB7 ,NotFull Raw Status bit for User 1 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU1MB7 ,NewMessage Raw Status bit for User 1 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU1MB6 ,NotFull Raw Status bit for User 1 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU1MB6 ,NewMessage Raw Status bit for User 1 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU1MB5 ,NotFull Raw Status bit for User 1 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU1MB5 ,NewMessage Raw Status bit for User 1 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU1MB4 ,NotFull Raw Status bit for User 1 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU1MB4 ,NewMessage Raw Status bit for User 1 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU1MB3 ,NotFull Raw Status bit for User 1 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU1MB3 ,NewMessage Raw Status bit for User 1 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU1MB2 ,NotFull Raw Status bit for User 1 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU1MB2 ,NewMessage Raw Status bit for User 1 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU1MB1 ,NotFull Raw Status bit for User 1 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU1MB1 ,NewMessage Raw Status bit for User 1 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU1MB0 ,NotFull Raw Status bit for User 1 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU1MB0 ,NewMessage Raw Status bit for User 1 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_1,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU1MB11 ,NotFull Clear Status bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU1MB11 ,NewMessage Clear Status bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU1MB10 ,NotFull Clear Status bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU1MB10 ,NewMessage Clear Status bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU1MB9 ,NotFull Clear Status bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU1MB9 ,NewMessage Clear Status bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU1MB8 ,NotFull Clear Status bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU1MB8 ,NewMessage Clear Status bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU1MB7 ,NotFull Clear Status bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU1MB7 ,NewMessage Clear Status bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU1MB6 ,NotFull Clear Status bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU1MB6 ,NewMessage Clear Status bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU1MB5 ,NotFull Clear Status bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU1MB5 ,NewMessage Clear Status bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU1MB4 ,NotFull Clear Status bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU1MB4 ,NewMessage Clear Status bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU1MB3 ,NotFull Clear Status bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU1MB3 ,NewMessage Clear Status bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU1MB2 ,NotFull Clear Status bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU1MB2 ,NewMessage Clear Status bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU1MB1 ,NotFull Clear Status bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU1MB1 ,NewMessage Clear Status bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU1MB0 ,NotFull Clear Status bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU1MB0 ,NewMessage Clear Status bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_1,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU1MB11 ,NotFull Enable Set bit for User 1 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU1MB11 ,NewMessage Enable Set bit for User 1 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU1MB10 ,NotFull Enable Set bit for User 1 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU1MB10 ,NewMessage Enable Set bit for User 1 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU1MB9 ,NotFull Enable Set bit for User 1 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU1MB9 ,NewMessage Enable Set bit for User 1 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU1MB8 ,NotFull Enable Set bit for User 1 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU1MB8 ,NewMessage Enable Set bit for User 1 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU1MB7 ,NotFull Enable Set bit for User 1 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU1MB7 ,NewMessage Enable Set bit for User 1 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU1MB6 ,NotFull Enable Set bit for User 1 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU1MB6 ,NewMessage Enable Set bit for User 1 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU1MB5 ,NotFull Enable Set bit for User 1 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU1MB5 ,NewMessage Enable Set bit for User 1 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU1MB4 ,NotFull Enable Set bit for User 1 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU1MB4 ,NewMessage Enable Set bit for User 1 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU1MB3 ,NotFull Enable Set bit for User 1 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU1MB3 ,NewMessage Enable Set bit for User 1 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU1MB2 ,NotFull Enable Set bit for User 1 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU1MB2 ,NewMessage Enable Set bit for User 1 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU1MB1 ,NotFull Enable Set bit for User 1 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU1MB1 ,NewMessage Enable Set bit for User 1 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU1MB0 ,NotFull Enable Set bit for User 1 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU1MB0 ,NewMessage Enable Set bit for User 1 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_1,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU1MB11 ,NotFull Enable Clear bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU1MB11 ,NewMessage Enable Clear bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU1MB10 ,NotFull Enable Clear bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU1MB10 ,NewMessage Enable Clear bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU1MB9 ,NotFull Enable Clear bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU1MB9 ,NewMessage Enable Clear bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU1MB8 ,NotFull Enable Clear bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU1MB8 ,NewMessage Enable Clear bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU1MB7 ,NotFull Enable Clear bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU1MB7 ,NewMessage Enable Clear bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU1MB6 ,NotFull Enable Clear bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU1MB6 ,NewMessage Enable Clear bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU1MB5 ,NotFull Enable Clear bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU1MB5 ,NewMessage Enable Clear bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU1MB4 ,NotFull Enable Clear bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU1MB4 ,NewMessage Enable Clear bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU1MB3 ,NotFull Enable Clear bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU1MB3 ,NewMessage Enable Clear bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU1MB2 ,NotFull Enable Clear bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU1MB2 ,NewMessage Enable Clear bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU1MB1 ,NotFull Enable Clear bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU1MB1 ,NewMessage Enable Clear bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU1MB0 ,NotFull Enable Clear bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU1MB0 ,NewMessage Enable Clear bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
tree "User 2 Mailbox Interrupts"
|
|
group.long (0x100+0x20)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_2,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU2MB11 ,NotFull Raw Status bit for User 2 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU2MB11 ,NewMessage Raw Status bit for User 2 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU2MB10 ,NotFull Raw Status bit for User 2 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU2MB10 ,NewMessage Raw Status bit for User 2 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU2MB9 ,NotFull Raw Status bit for User 2 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU2MB9 ,NewMessage Raw Status bit for User 2 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU2MB8 ,NotFull Raw Status bit for User 2 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU2MB8 ,NewMessage Raw Status bit for User 2 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU2MB7 ,NotFull Raw Status bit for User 2 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU2MB7 ,NewMessage Raw Status bit for User 2 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU2MB6 ,NotFull Raw Status bit for User 2 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU2MB6 ,NewMessage Raw Status bit for User 2 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU2MB5 ,NotFull Raw Status bit for User 2 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU2MB5 ,NewMessage Raw Status bit for User 2 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU2MB4 ,NotFull Raw Status bit for User 2 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU2MB4 ,NewMessage Raw Status bit for User 2 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU2MB3 ,NotFull Raw Status bit for User 2 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU2MB3 ,NewMessage Raw Status bit for User 2 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU2MB2 ,NotFull Raw Status bit for User 2 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU2MB2 ,NewMessage Raw Status bit for User 2 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU2MB1 ,NotFull Raw Status bit for User 2 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU2MB1 ,NewMessage Raw Status bit for User 2 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU2MB0 ,NotFull Raw Status bit for User 2 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU2MB0 ,NewMessage Raw Status bit for User 2 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_2,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU2MB11 ,NotFull Clear Status bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU2MB11 ,NewMessage Clear Status bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU2MB10 ,NotFull Clear Status bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU2MB10 ,NewMessage Clear Status bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU2MB9 ,NotFull Clear Status bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU2MB9 ,NewMessage Clear Status bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU2MB8 ,NotFull Clear Status bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU2MB8 ,NewMessage Clear Status bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU2MB7 ,NotFull Clear Status bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU2MB7 ,NewMessage Clear Status bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU2MB6 ,NotFull Clear Status bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU2MB6 ,NewMessage Clear Status bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU2MB5 ,NotFull Clear Status bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU2MB5 ,NewMessage Clear Status bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU2MB4 ,NotFull Clear Status bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU2MB4 ,NewMessage Clear Status bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU2MB3 ,NotFull Clear Status bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU2MB3 ,NewMessage Clear Status bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU2MB2 ,NotFull Clear Status bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU2MB2 ,NewMessage Clear Status bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU2MB1 ,NotFull Clear Status bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU2MB1 ,NewMessage Clear Status bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU2MB0 ,NotFull Clear Status bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU2MB0 ,NewMessage Clear Status bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_2,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU2MB11 ,NotFull Enable Set bit for User 2 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU2MB11 ,NewMessage Enable Set bit for User 2 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU2MB10 ,NotFull Enable Set bit for User 2 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU2MB10 ,NewMessage Enable Set bit for User 2 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU2MB9 ,NotFull Enable Set bit for User 2 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU2MB9 ,NewMessage Enable Set bit for User 2 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU2MB8 ,NotFull Enable Set bit for User 2 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU2MB8 ,NewMessage Enable Set bit for User 2 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU2MB7 ,NotFull Enable Set bit for User 2 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU2MB7 ,NewMessage Enable Set bit for User 2 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU2MB6 ,NotFull Enable Set bit for User 2 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU2MB6 ,NewMessage Enable Set bit for User 2 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU2MB5 ,NotFull Enable Set bit for User 2 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU2MB5 ,NewMessage Enable Set bit for User 2 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU2MB4 ,NotFull Enable Set bit for User 2 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU2MB4 ,NewMessage Enable Set bit for User 2 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU2MB3 ,NotFull Enable Set bit for User 2 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU2MB3 ,NewMessage Enable Set bit for User 2 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU2MB2 ,NotFull Enable Set bit for User 2 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU2MB2 ,NewMessage Enable Set bit for User 2 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU2MB1 ,NotFull Enable Set bit for User 2 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU2MB1 ,NewMessage Enable Set bit for User 2 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU2MB0 ,NotFull Enable Set bit for User 2 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU2MB0 ,NewMessage Enable Set bit for User 2 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_2,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU2MB11 ,NotFull Enable Clear bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU2MB11 ,NewMessage Enable Clear bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU2MB10 ,NotFull Enable Clear bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU2MB10 ,NewMessage Enable Clear bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU2MB9 ,NotFull Enable Clear bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU2MB9 ,NewMessage Enable Clear bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU2MB8 ,NotFull Enable Clear bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU2MB8 ,NewMessage Enable Clear bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU2MB7 ,NotFull Enable Clear bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU2MB7 ,NewMessage Enable Clear bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU2MB6 ,NotFull Enable Clear bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU2MB6 ,NewMessage Enable Clear bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU2MB5 ,NotFull Enable Clear bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU2MB5 ,NewMessage Enable Clear bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU2MB4 ,NotFull Enable Clear bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU2MB4 ,NewMessage Enable Clear bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU2MB3 ,NotFull Enable Clear bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU2MB3 ,NewMessage Enable Clear bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU2MB2 ,NotFull Enable Clear bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU2MB2 ,NewMessage Enable Clear bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU2MB1 ,NotFull Enable Clear bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU2MB1 ,NewMessage Enable Clear bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU2MB0 ,NotFull Enable Clear bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU2MB0 ,NewMessage Enable Clear bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
tree "User 3 Mailbox Interrupts"
|
|
group.long (0x100+0x30)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_3,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU3MB11 ,NotFull Raw Status bit for User 3 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU3MB11 ,NewMessage Raw Status bit for User 3 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU3MB10 ,NotFull Raw Status bit for User 3 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU3MB10 ,NewMessage Raw Status bit for User 3 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU3MB9 ,NotFull Raw Status bit for User 3 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU3MB9 ,NewMessage Raw Status bit for User 3 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU3MB8 ,NotFull Raw Status bit for User 3 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU3MB8 ,NewMessage Raw Status bit for User 3 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU3MB7 ,NotFull Raw Status bit for User 3 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU3MB7 ,NewMessage Raw Status bit for User 3 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU3MB6 ,NotFull Raw Status bit for User 3 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU3MB6 ,NewMessage Raw Status bit for User 3 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU3MB5 ,NotFull Raw Status bit for User 3 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU3MB5 ,NewMessage Raw Status bit for User 3 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU3MB4 ,NotFull Raw Status bit for User 3 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU3MB4 ,NewMessage Raw Status bit for User 3 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU3MB3 ,NotFull Raw Status bit for User 3 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU3MB3 ,NewMessage Raw Status bit for User 3 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU3MB2 ,NotFull Raw Status bit for User 3 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU3MB2 ,NewMessage Raw Status bit for User 3 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU3MB1 ,NotFull Raw Status bit for User 3 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU3MB1 ,NewMessage Raw Status bit for User 3 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU3MB0 ,NotFull Raw Status bit for User 3 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU3MB0 ,NewMessage Raw Status bit for User 3 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_3,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU3MB11 ,NotFull Clear Status bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU3MB11 ,NewMessage Clear Status bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU3MB10 ,NotFull Clear Status bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU3MB10 ,NewMessage Clear Status bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU3MB9 ,NotFull Clear Status bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU3MB9 ,NewMessage Clear Status bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU3MB8 ,NotFull Clear Status bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU3MB8 ,NewMessage Clear Status bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU3MB7 ,NotFull Clear Status bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU3MB7 ,NewMessage Clear Status bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU3MB6 ,NotFull Clear Status bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU3MB6 ,NewMessage Clear Status bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU3MB5 ,NotFull Clear Status bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU3MB5 ,NewMessage Clear Status bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU3MB4 ,NotFull Clear Status bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU3MB4 ,NewMessage Clear Status bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU3MB3 ,NotFull Clear Status bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU3MB3 ,NewMessage Clear Status bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU3MB2 ,NotFull Clear Status bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU3MB2 ,NewMessage Clear Status bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU3MB1 ,NotFull Clear Status bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU3MB1 ,NewMessage Clear Status bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU3MB0 ,NotFull Clear Status bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU3MB0 ,NewMessage Clear Status bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_3,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU3MB11 ,NotFull Enable Set bit for User 3 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU3MB11 ,NewMessage Enable Set bit for User 3 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU3MB10 ,NotFull Enable Set bit for User 3 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU3MB10 ,NewMessage Enable Set bit for User 3 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU3MB9 ,NotFull Enable Set bit for User 3 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU3MB9 ,NewMessage Enable Set bit for User 3 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU3MB8 ,NotFull Enable Set bit for User 3 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU3MB8 ,NewMessage Enable Set bit for User 3 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU3MB7 ,NotFull Enable Set bit for User 3 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU3MB7 ,NewMessage Enable Set bit for User 3 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU3MB6 ,NotFull Enable Set bit for User 3 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU3MB6 ,NewMessage Enable Set bit for User 3 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU3MB5 ,NotFull Enable Set bit for User 3 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU3MB5 ,NewMessage Enable Set bit for User 3 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU3MB4 ,NotFull Enable Set bit for User 3 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU3MB4 ,NewMessage Enable Set bit for User 3 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU3MB3 ,NotFull Enable Set bit for User 3 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU3MB3 ,NewMessage Enable Set bit for User 3 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU3MB2 ,NotFull Enable Set bit for User 3 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU3MB2 ,NewMessage Enable Set bit for User 3 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU3MB1 ,NotFull Enable Set bit for User 3 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU3MB1 ,NewMessage Enable Set bit for User 3 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU3MB0 ,NotFull Enable Set bit for User 3 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU3MB0 ,NewMessage Enable Set bit for User 3 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_3,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU3MB11 ,NotFull Enable Clear bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU3MB11 ,NewMessage Enable Clear bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU3MB10 ,NotFull Enable Clear bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU3MB10 ,NewMessage Enable Clear bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU3MB9 ,NotFull Enable Clear bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU3MB9 ,NewMessage Enable Clear bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU3MB8 ,NotFull Enable Clear bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU3MB8 ,NewMessage Enable Clear bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU3MB7 ,NotFull Enable Clear bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU3MB7 ,NewMessage Enable Clear bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU3MB6 ,NotFull Enable Clear bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU3MB6 ,NewMessage Enable Clear bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU3MB5 ,NotFull Enable Clear bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU3MB5 ,NewMessage Enable Clear bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU3MB4 ,NotFull Enable Clear bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU3MB4 ,NewMessage Enable Clear bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU3MB3 ,NotFull Enable Clear bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU3MB3 ,NewMessage Enable Clear bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU3MB2 ,NotFull Enable Clear bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU3MB2 ,NewMessage Enable Clear bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU3MB1 ,NotFull Enable Clear bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU3MB1 ,NewMessage Enable Clear bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU3MB0 ,NotFull Enable Clear bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU3MB0 ,NewMessage Enable Clear bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree "MAILBOX (Mailbox Registers)"
|
|
base ad:0x480c8000
|
|
width 23.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "MAILBOX_REVISION,Mailbox IP Revision Code"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MAILBOX_SYSCONFIG,Mailbox System Configuration Register"
|
|
sif (cpu()=="AM3874")||(cpu()=="AM3872")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
|
|
bitfld.long 0x00 2.--3. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
else
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
endif
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
sif (cpu()!="AM3874")&&(cpu()!="AM3872")&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MAILBOX_SYSSTATUS,Mailbox Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "On-going,Completed"
|
|
endif
|
|
group.long 0x40++0x2f
|
|
line.long 0x0 "MAILBOX_MESSAGE_0,Mailbox Message 0 Register"
|
|
line.long 0x4 "MAILBOX_MESSAGE_1,Mailbox Message 1 Register"
|
|
line.long 0x8 "MAILBOX_MESSAGE_2,Mailbox Message 2 Register"
|
|
line.long 0xC "MAILBOX_MESSAGE_3,Mailbox Message 3 Register"
|
|
line.long 0x10 "MAILBOX_MESSAGE_4,Mailbox Message 4 Register"
|
|
line.long 0x14 "MAILBOX_MESSAGE_5,Mailbox Message 5 Register"
|
|
line.long 0x18 "MAILBOX_MESSAGE_6,Mailbox Message 6 Register"
|
|
line.long 0x1C "MAILBOX_MESSAGE_7,Mailbox Message 7 Register"
|
|
line.long 0x20 "MAILBOX_MESSAGE_8,Mailbox Message 8 Register"
|
|
line.long 0x24 "MAILBOX_MESSAGE_9,Mailbox Message 9 Register"
|
|
line.long 0x28 "MAILBOX_MESSAGE_10,Mailbox Message 10 Register"
|
|
line.long 0x2C "MAILBOX_MESSAGE_11,Mailbox Message 11 Register"
|
|
rgroup.long 0x80++0x2f
|
|
line.long 0x0 "MAILBOX_FIFOSTATUS_0 ,Mailbox FIFO Status 0 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x0 1.--31. 1. " MESSAGEVALUEMB0 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 0. " FIFOFULLMB0 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x4 "MAILBOX_FIFOSTATUS_1 ,Mailbox FIFO Status 1 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x4 1.--31. 1. " MESSAGEVALUEMB1 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 0. " FIFOFULLMB1 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x8 "MAILBOX_FIFOSTATUS_2 ,Mailbox FIFO Status 2 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x8 1.--31. 1. " MESSAGEVALUEMB2 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 0. " FIFOFULLMB2 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0xC "MAILBOX_FIFOSTATUS_3 ,Mailbox FIFO Status 3 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0xC 1.--31. 1. " MESSAGEVALUEMB3 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 0. " FIFOFULLMB3 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x10 "MAILBOX_FIFOSTATUS_4 ,Mailbox FIFO Status 4 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x10 1.--31. 1. " MESSAGEVALUEMB4 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " FIFOFULLMB4 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x14 "MAILBOX_FIFOSTATUS_5 ,Mailbox FIFO Status 5 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x14 1.--31. 1. " MESSAGEVALUEMB5 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 0. " FIFOFULLMB5 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x18 "MAILBOX_FIFOSTATUS_6 ,Mailbox FIFO Status 6 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x18 1.--31. 1. " MESSAGEVALUEMB6 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 0. " FIFOFULLMB6 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x1C "MAILBOX_FIFOSTATUS_7 ,Mailbox FIFO Status 7 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x1C 1.--31. 1. " MESSAGEVALUEMB7 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 0. " FIFOFULLMB7 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x20 "MAILBOX_FIFOSTATUS_8 ,Mailbox FIFO Status 8 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x20 1.--31. 1. " MESSAGEVALUEMB8 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 0. " FIFOFULLMB8 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x24 "MAILBOX_FIFOSTATUS_9 ,Mailbox FIFO Status 9 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x24 1.--31. 1. " MESSAGEVALUEMB9 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 0. " FIFOFULLMB9 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x28 "MAILBOX_FIFOSTATUS_10,Mailbox FIFO Status 10 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x28 1.--31. 1. " MESSAGEVALUEMB10 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 0. " FIFOFULLMB10 ,Full flag for Mailbox" "Not full,Full"
|
|
line.long 0x2C "MAILBOX_FIFOSTATUS_11,Mailbox FIFO Status 11 Register"
|
|
sif (cpuis("DRA62*"))
|
|
hexmask.long 0x2C 1.--31. 1. " MESSAGEVALUEMB11 ,Message in Mailbox"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 0. " FIFOFULLMB11 ,Full flag for Mailbox" "Not full,Full"
|
|
rgroup.long 0xC0++0x2f
|
|
line.long 0x0 "MAILBOX_MSGSTATUS_0 ,Mailbox Message Status 0 Register"
|
|
bitfld.long 0x0 0.--2. " NBOFMSGMBM0 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x4 "MAILBOX_MSGSTATUS_1 ,Mailbox Message Status 1 Register"
|
|
bitfld.long 0x4 0.--2. " NBOFMSGMBM1 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x8 "MAILBOX_MSGSTATUS_2 ,Mailbox Message Status 2 Register"
|
|
bitfld.long 0x8 0.--2. " NBOFMSGMBM2 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0xC "MAILBOX_MSGSTATUS_3 ,Mailbox Message Status 3 Register"
|
|
bitfld.long 0xC 0.--2. " NBOFMSGMBM3 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x10 "MAILBOX_MSGSTATUS_4 ,Mailbox Message Status 4 Register"
|
|
bitfld.long 0x10 0.--2. " NBOFMSGMBM4 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x14 "MAILBOX_MSGSTATUS_5 ,Mailbox Message Status 5 Register"
|
|
bitfld.long 0x14 0.--2. " NBOFMSGMBM5 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x18 "MAILBOX_MSGSTATUS_6 ,Mailbox Message Status 6 Register"
|
|
bitfld.long 0x18 0.--2. " NBOFMSGMBM6 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x1C "MAILBOX_MSGSTATUS_7 ,Mailbox Message Status 7 Register"
|
|
bitfld.long 0x1C 0.--2. " NBOFMSGMBM7 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x20 "MAILBOX_MSGSTATUS_8 ,Mailbox Message Status 8 Register"
|
|
bitfld.long 0x20 0.--2. " NBOFMSGMBM8 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x24 "MAILBOX_MSGSTATUS_9 ,Mailbox Message Status 9 Register"
|
|
bitfld.long 0x24 0.--2. " NBOFMSGMBM9 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x28 "MAILBOX_MSGSTATUS_10,Mailbox Message Status 10 Register"
|
|
bitfld.long 0x28 0.--2. " NBOFMSGMBM10 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
line.long 0x2C "MAILBOX_MSGSTATUS_11,Mailbox Message Status 11 Register"
|
|
bitfld.long 0x2C 0.--2. " NBOFMSGMBM11 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
|
|
width 25.
|
|
tree "User 0 Mailbox Interrupts"
|
|
group.long (0x100+0x0)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_0,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU0MB11 ,NotFull Raw Status bit for User 0 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU0MB11 ,NewMessage Raw Status bit for User 0 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU0MB10 ,NotFull Raw Status bit for User 0 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU0MB10 ,NewMessage Raw Status bit for User 0 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU0MB9 ,NotFull Raw Status bit for User 0 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU0MB9 ,NewMessage Raw Status bit for User 0 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU0MB8 ,NotFull Raw Status bit for User 0 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU0MB8 ,NewMessage Raw Status bit for User 0 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU0MB7 ,NotFull Raw Status bit for User 0 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU0MB7 ,NewMessage Raw Status bit for User 0 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU0MB6 ,NotFull Raw Status bit for User 0 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU0MB6 ,NewMessage Raw Status bit for User 0 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU0MB5 ,NotFull Raw Status bit for User 0 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU0MB5 ,NewMessage Raw Status bit for User 0 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU0MB4 ,NotFull Raw Status bit for User 0 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU0MB4 ,NewMessage Raw Status bit for User 0 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU0MB3 ,NotFull Raw Status bit for User 0 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU0MB3 ,NewMessage Raw Status bit for User 0 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU0MB2 ,NotFull Raw Status bit for User 0 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU0MB2 ,NewMessage Raw Status bit for User 0 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU0MB1 ,NotFull Raw Status bit for User 0 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU0MB1 ,NewMessage Raw Status bit for User 0 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU0MB0 ,NotFull Raw Status bit for User 0 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU0MB0 ,NewMessage Raw Status bit for User 0 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_0,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU0MB11 ,NotFull Clear Status bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU0MB11 ,NewMessage Clear Status bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU0MB10 ,NotFull Clear Status bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU0MB10 ,NewMessage Clear Status bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU0MB9 ,NotFull Clear Status bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU0MB9 ,NewMessage Clear Status bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU0MB8 ,NotFull Clear Status bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU0MB8 ,NewMessage Clear Status bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU0MB7 ,NotFull Clear Status bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU0MB7 ,NewMessage Clear Status bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU0MB6 ,NotFull Clear Status bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU0MB6 ,NewMessage Clear Status bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU0MB5 ,NotFull Clear Status bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU0MB5 ,NewMessage Clear Status bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU0MB4 ,NotFull Clear Status bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU0MB4 ,NewMessage Clear Status bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU0MB3 ,NotFull Clear Status bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU0MB3 ,NewMessage Clear Status bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU0MB2 ,NotFull Clear Status bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU0MB2 ,NewMessage Clear Status bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU0MB1 ,NotFull Clear Status bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU0MB1 ,NewMessage Clear Status bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU0MB0 ,NotFull Clear Status bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU0MB0 ,NewMessage Clear Status bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_0,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU0MB11 ,NotFull Enable Set bit for User 0 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU0MB11 ,NewMessage Enable Set bit for User 0 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU0MB10 ,NotFull Enable Set bit for User 0 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU0MB10 ,NewMessage Enable Set bit for User 0 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU0MB9 ,NotFull Enable Set bit for User 0 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU0MB9 ,NewMessage Enable Set bit for User 0 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU0MB8 ,NotFull Enable Set bit for User 0 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU0MB8 ,NewMessage Enable Set bit for User 0 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU0MB7 ,NotFull Enable Set bit for User 0 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU0MB7 ,NewMessage Enable Set bit for User 0 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU0MB6 ,NotFull Enable Set bit for User 0 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU0MB6 ,NewMessage Enable Set bit for User 0 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU0MB5 ,NotFull Enable Set bit for User 0 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU0MB5 ,NewMessage Enable Set bit for User 0 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU0MB4 ,NotFull Enable Set bit for User 0 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU0MB4 ,NewMessage Enable Set bit for User 0 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU0MB3 ,NotFull Enable Set bit for User 0 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU0MB3 ,NewMessage Enable Set bit for User 0 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU0MB2 ,NotFull Enable Set bit for User 0 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU0MB2 ,NewMessage Enable Set bit for User 0 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU0MB1 ,NotFull Enable Set bit for User 0 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU0MB1 ,NewMessage Enable Set bit for User 0 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU0MB0 ,NotFull Enable Set bit for User 0 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU0MB0 ,NewMessage Enable Set bit for User 0 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_0,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU0MB11 ,NotFull Enable Clear bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU0MB11 ,NewMessage Enable Clear bit for User 0 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU0MB10 ,NotFull Enable Clear bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU0MB10 ,NewMessage Enable Clear bit for User 0 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU0MB9 ,NotFull Enable Clear bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU0MB9 ,NewMessage Enable Clear bit for User 0 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU0MB8 ,NotFull Enable Clear bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU0MB8 ,NewMessage Enable Clear bit for User 0 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU0MB7 ,NotFull Enable Clear bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU0MB7 ,NewMessage Enable Clear bit for User 0 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU0MB6 ,NotFull Enable Clear bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU0MB6 ,NewMessage Enable Clear bit for User 0 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU0MB5 ,NotFull Enable Clear bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU0MB5 ,NewMessage Enable Clear bit for User 0 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU0MB4 ,NotFull Enable Clear bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU0MB4 ,NewMessage Enable Clear bit for User 0 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU0MB3 ,NotFull Enable Clear bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU0MB3 ,NewMessage Enable Clear bit for User 0 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU0MB2 ,NotFull Enable Clear bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU0MB2 ,NewMessage Enable Clear bit for User 0 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU0MB1 ,NotFull Enable Clear bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU0MB1 ,NewMessage Enable Clear bit for User 0 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU0MB0 ,NotFull Enable Clear bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU0MB0 ,NewMessage Enable Clear bit for User 0 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
tree "User 1 Mailbox Interrupts"
|
|
group.long (0x100+0x10)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_1,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU1MB11 ,NotFull Raw Status bit for User 1 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU1MB11 ,NewMessage Raw Status bit for User 1 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU1MB10 ,NotFull Raw Status bit for User 1 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU1MB10 ,NewMessage Raw Status bit for User 1 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU1MB9 ,NotFull Raw Status bit for User 1 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU1MB9 ,NewMessage Raw Status bit for User 1 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU1MB8 ,NotFull Raw Status bit for User 1 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU1MB8 ,NewMessage Raw Status bit for User 1 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU1MB7 ,NotFull Raw Status bit for User 1 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU1MB7 ,NewMessage Raw Status bit for User 1 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU1MB6 ,NotFull Raw Status bit for User 1 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU1MB6 ,NewMessage Raw Status bit for User 1 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU1MB5 ,NotFull Raw Status bit for User 1 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU1MB5 ,NewMessage Raw Status bit for User 1 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU1MB4 ,NotFull Raw Status bit for User 1 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU1MB4 ,NewMessage Raw Status bit for User 1 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU1MB3 ,NotFull Raw Status bit for User 1 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU1MB3 ,NewMessage Raw Status bit for User 1 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU1MB2 ,NotFull Raw Status bit for User 1 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU1MB2 ,NewMessage Raw Status bit for User 1 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU1MB1 ,NotFull Raw Status bit for User 1 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU1MB1 ,NewMessage Raw Status bit for User 1 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU1MB0 ,NotFull Raw Status bit for User 1 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU1MB0 ,NewMessage Raw Status bit for User 1 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_1,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU1MB11 ,NotFull Clear Status bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU1MB11 ,NewMessage Clear Status bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU1MB10 ,NotFull Clear Status bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU1MB10 ,NewMessage Clear Status bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU1MB9 ,NotFull Clear Status bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU1MB9 ,NewMessage Clear Status bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU1MB8 ,NotFull Clear Status bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU1MB8 ,NewMessage Clear Status bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU1MB7 ,NotFull Clear Status bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU1MB7 ,NewMessage Clear Status bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU1MB6 ,NotFull Clear Status bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU1MB6 ,NewMessage Clear Status bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU1MB5 ,NotFull Clear Status bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU1MB5 ,NewMessage Clear Status bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU1MB4 ,NotFull Clear Status bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU1MB4 ,NewMessage Clear Status bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU1MB3 ,NotFull Clear Status bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU1MB3 ,NewMessage Clear Status bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU1MB2 ,NotFull Clear Status bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU1MB2 ,NewMessage Clear Status bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU1MB1 ,NotFull Clear Status bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU1MB1 ,NewMessage Clear Status bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU1MB0 ,NotFull Clear Status bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU1MB0 ,NewMessage Clear Status bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_1,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU1MB11 ,NotFull Enable Set bit for User 1 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU1MB11 ,NewMessage Enable Set bit for User 1 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU1MB10 ,NotFull Enable Set bit for User 1 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU1MB10 ,NewMessage Enable Set bit for User 1 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU1MB9 ,NotFull Enable Set bit for User 1 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU1MB9 ,NewMessage Enable Set bit for User 1 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU1MB8 ,NotFull Enable Set bit for User 1 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU1MB8 ,NewMessage Enable Set bit for User 1 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU1MB7 ,NotFull Enable Set bit for User 1 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU1MB7 ,NewMessage Enable Set bit for User 1 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU1MB6 ,NotFull Enable Set bit for User 1 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU1MB6 ,NewMessage Enable Set bit for User 1 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU1MB5 ,NotFull Enable Set bit for User 1 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU1MB5 ,NewMessage Enable Set bit for User 1 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU1MB4 ,NotFull Enable Set bit for User 1 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU1MB4 ,NewMessage Enable Set bit for User 1 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU1MB3 ,NotFull Enable Set bit for User 1 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU1MB3 ,NewMessage Enable Set bit for User 1 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU1MB2 ,NotFull Enable Set bit for User 1 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU1MB2 ,NewMessage Enable Set bit for User 1 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU1MB1 ,NotFull Enable Set bit for User 1 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU1MB1 ,NewMessage Enable Set bit for User 1 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU1MB0 ,NotFull Enable Set bit for User 1 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU1MB0 ,NewMessage Enable Set bit for User 1 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_1,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU1MB11 ,NotFull Enable Clear bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU1MB11 ,NewMessage Enable Clear bit for User 1 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU1MB10 ,NotFull Enable Clear bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU1MB10 ,NewMessage Enable Clear bit for User 1 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU1MB9 ,NotFull Enable Clear bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU1MB9 ,NewMessage Enable Clear bit for User 1 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU1MB8 ,NotFull Enable Clear bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU1MB8 ,NewMessage Enable Clear bit for User 1 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU1MB7 ,NotFull Enable Clear bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU1MB7 ,NewMessage Enable Clear bit for User 1 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU1MB6 ,NotFull Enable Clear bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU1MB6 ,NewMessage Enable Clear bit for User 1 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU1MB5 ,NotFull Enable Clear bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU1MB5 ,NewMessage Enable Clear bit for User 1 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU1MB4 ,NotFull Enable Clear bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU1MB4 ,NewMessage Enable Clear bit for User 1 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU1MB3 ,NotFull Enable Clear bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU1MB3 ,NewMessage Enable Clear bit for User 1 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU1MB2 ,NotFull Enable Clear bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU1MB2 ,NewMessage Enable Clear bit for User 1 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU1MB1 ,NotFull Enable Clear bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU1MB1 ,NewMessage Enable Clear bit for User 1 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU1MB0 ,NotFull Enable Clear bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU1MB0 ,NewMessage Enable Clear bit for User 1 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
tree "User 2 Mailbox Interrupts"
|
|
group.long (0x100+0x20)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_2,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU2MB11 ,NotFull Raw Status bit for User 2 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU2MB11 ,NewMessage Raw Status bit for User 2 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU2MB10 ,NotFull Raw Status bit for User 2 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU2MB10 ,NewMessage Raw Status bit for User 2 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU2MB9 ,NotFull Raw Status bit for User 2 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU2MB9 ,NewMessage Raw Status bit for User 2 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU2MB8 ,NotFull Raw Status bit for User 2 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU2MB8 ,NewMessage Raw Status bit for User 2 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU2MB7 ,NotFull Raw Status bit for User 2 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU2MB7 ,NewMessage Raw Status bit for User 2 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU2MB6 ,NotFull Raw Status bit for User 2 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU2MB6 ,NewMessage Raw Status bit for User 2 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU2MB5 ,NotFull Raw Status bit for User 2 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU2MB5 ,NewMessage Raw Status bit for User 2 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU2MB4 ,NotFull Raw Status bit for User 2 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU2MB4 ,NewMessage Raw Status bit for User 2 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU2MB3 ,NotFull Raw Status bit for User 2 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU2MB3 ,NewMessage Raw Status bit for User 2 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU2MB2 ,NotFull Raw Status bit for User 2 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU2MB2 ,NewMessage Raw Status bit for User 2 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU2MB1 ,NotFull Raw Status bit for User 2 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU2MB1 ,NewMessage Raw Status bit for User 2 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU2MB0 ,NotFull Raw Status bit for User 2 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU2MB0 ,NewMessage Raw Status bit for User 2 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_2,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU2MB11 ,NotFull Clear Status bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU2MB11 ,NewMessage Clear Status bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU2MB10 ,NotFull Clear Status bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU2MB10 ,NewMessage Clear Status bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU2MB9 ,NotFull Clear Status bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU2MB9 ,NewMessage Clear Status bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU2MB8 ,NotFull Clear Status bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU2MB8 ,NewMessage Clear Status bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU2MB7 ,NotFull Clear Status bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU2MB7 ,NewMessage Clear Status bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU2MB6 ,NotFull Clear Status bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU2MB6 ,NewMessage Clear Status bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU2MB5 ,NotFull Clear Status bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU2MB5 ,NewMessage Clear Status bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU2MB4 ,NotFull Clear Status bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU2MB4 ,NewMessage Clear Status bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU2MB3 ,NotFull Clear Status bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU2MB3 ,NewMessage Clear Status bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU2MB2 ,NotFull Clear Status bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU2MB2 ,NewMessage Clear Status bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU2MB1 ,NotFull Clear Status bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU2MB1 ,NewMessage Clear Status bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU2MB0 ,NotFull Clear Status bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU2MB0 ,NewMessage Clear Status bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_2,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU2MB11 ,NotFull Enable Set bit for User 2 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU2MB11 ,NewMessage Enable Set bit for User 2 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU2MB10 ,NotFull Enable Set bit for User 2 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU2MB10 ,NewMessage Enable Set bit for User 2 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU2MB9 ,NotFull Enable Set bit for User 2 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU2MB9 ,NewMessage Enable Set bit for User 2 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU2MB8 ,NotFull Enable Set bit for User 2 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU2MB8 ,NewMessage Enable Set bit for User 2 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU2MB7 ,NotFull Enable Set bit for User 2 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU2MB7 ,NewMessage Enable Set bit for User 2 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU2MB6 ,NotFull Enable Set bit for User 2 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU2MB6 ,NewMessage Enable Set bit for User 2 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU2MB5 ,NotFull Enable Set bit for User 2 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU2MB5 ,NewMessage Enable Set bit for User 2 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU2MB4 ,NotFull Enable Set bit for User 2 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU2MB4 ,NewMessage Enable Set bit for User 2 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU2MB3 ,NotFull Enable Set bit for User 2 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU2MB3 ,NewMessage Enable Set bit for User 2 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU2MB2 ,NotFull Enable Set bit for User 2 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU2MB2 ,NewMessage Enable Set bit for User 2 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU2MB1 ,NotFull Enable Set bit for User 2 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU2MB1 ,NewMessage Enable Set bit for User 2 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU2MB0 ,NotFull Enable Set bit for User 2 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU2MB0 ,NewMessage Enable Set bit for User 2 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_2,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU2MB11 ,NotFull Enable Clear bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU2MB11 ,NewMessage Enable Clear bit for User 2 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU2MB10 ,NotFull Enable Clear bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU2MB10 ,NewMessage Enable Clear bit for User 2 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU2MB9 ,NotFull Enable Clear bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU2MB9 ,NewMessage Enable Clear bit for User 2 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU2MB8 ,NotFull Enable Clear bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU2MB8 ,NewMessage Enable Clear bit for User 2 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU2MB7 ,NotFull Enable Clear bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU2MB7 ,NewMessage Enable Clear bit for User 2 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU2MB6 ,NotFull Enable Clear bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU2MB6 ,NewMessage Enable Clear bit for User 2 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU2MB5 ,NotFull Enable Clear bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU2MB5 ,NewMessage Enable Clear bit for User 2 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU2MB4 ,NotFull Enable Clear bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU2MB4 ,NewMessage Enable Clear bit for User 2 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU2MB3 ,NotFull Enable Clear bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU2MB3 ,NewMessage Enable Clear bit for User 2 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU2MB2 ,NotFull Enable Clear bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU2MB2 ,NewMessage Enable Clear bit for User 2 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU2MB1 ,NotFull Enable Clear bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU2MB1 ,NewMessage Enable Clear bit for User 2 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU2MB0 ,NotFull Enable Clear bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU2MB0 ,NewMessage Enable Clear bit for User 2 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
tree "User 3 Mailbox Interrupts"
|
|
group.long (0x100+0x30)++0xf
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_3,Mailbox IRQ RAW Status Register"
|
|
bitfld.long 0x00 23. " NOTFULLSTATUSU3MB11 ,NotFull Raw Status bit for User 3 Mailbox 11" "Full,Not full"
|
|
bitfld.long 0x00 22. " NEWMSGSTATUSU3MB11 ,NewMessage Raw Status bit for User 3 Mailbox 11" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTFULLSTATUSU3MB10 ,NotFull Raw Status bit for User 3 Mailbox 10" "Full,Not full"
|
|
bitfld.long 0x00 20. " NEWMSGSTATUSU3MB10 ,NewMessage Raw Status bit for User 3 Mailbox 10" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTFULLSTATUSU3MB9 ,NotFull Raw Status bit for User 3 Mailbox 9" "Full,Not full"
|
|
bitfld.long 0x00 18. " NEWMSGSTATUSU3MB9 ,NewMessage Raw Status bit for User 3 Mailbox 9" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTFULLSTATUSU3MB8 ,NotFull Raw Status bit for User 3 Mailbox 8" "Full,Not full"
|
|
bitfld.long 0x00 16. " NEWMSGSTATUSU3MB8 ,NewMessage Raw Status bit for User 3 Mailbox 8" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTFULLSTATUSU3MB7 ,NotFull Raw Status bit for User 3 Mailbox 7" "Full,Not full"
|
|
bitfld.long 0x00 14. " NEWMSGSTATUSU3MB7 ,NewMessage Raw Status bit for User 3 Mailbox 7" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTFULLSTATUSU3MB6 ,NotFull Raw Status bit for User 3 Mailbox 6" "Full,Not full"
|
|
bitfld.long 0x00 12. " NEWMSGSTATUSU3MB6 ,NewMessage Raw Status bit for User 3 Mailbox 6" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTFULLSTATUSU3MB5 ,NotFull Raw Status bit for User 3 Mailbox 5" "Full,Not full"
|
|
bitfld.long 0x00 10. " NEWMSGSTATUSU3MB5 ,NewMessage Raw Status bit for User 3 Mailbox 5" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTFULLSTATUSU3MB4 ,NotFull Raw Status bit for User 3 Mailbox 4" "Full,Not full"
|
|
bitfld.long 0x00 8. " NEWMSGSTATUSU3MB4 ,NewMessage Raw Status bit for User 3 Mailbox 4" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTFULLSTATUSU3MB3 ,NotFull Raw Status bit for User 3 Mailbox 3" "Full,Not full"
|
|
bitfld.long 0x00 6. " NEWMSGSTATUSU3MB3 ,NewMessage Raw Status bit for User 3 Mailbox 3" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTFULLSTATUSU3MB2 ,NotFull Raw Status bit for User 3 Mailbox 2" "Full,Not full"
|
|
bitfld.long 0x00 4. " NEWMSGSTATUSU3MB2 ,NewMessage Raw Status bit for User 3 Mailbox 2" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTFULLSTATUSU3MB1 ,NotFull Raw Status bit for User 3 Mailbox 1" "Full,Not full"
|
|
bitfld.long 0x00 2. " NEWMSGSTATUSU3MB1 ,NewMessage Raw Status bit for User 3 Mailbox 1" "No action,New message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLSTATUSU3MB0 ,NotFull Raw Status bit for User 3 Mailbox 0" "Full,Not full"
|
|
bitfld.long 0x00 0. " NEWMSGSTATUSU3MB0 ,NewMessage Raw Status bit for User 3 Mailbox 0" "No action,New message"
|
|
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_3,Mailbox IRQ Clear Status Register"
|
|
eventfld.long 0x04 23. " NOTFULLSTATUSU3MB11 ,NotFull Clear Status bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x04 22. " NEWMSGSTATUSU3MB11 ,NewMessage Clear Status bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 21. " NOTFULLSTATUSU3MB10 ,NotFull Clear Status bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x04 20. " NEWMSGSTATUSU3MB10 ,NewMessage Clear Status bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 19. " NOTFULLSTATUSU3MB9 ,NotFull Clear Status bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x04 18. " NEWMSGSTATUSU3MB9 ,NewMessage Clear Status bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 17. " NOTFULLSTATUSU3MB8 ,NotFull Clear Status bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x04 16. " NEWMSGSTATUSU3MB8 ,NewMessage Clear Status bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 15. " NOTFULLSTATUSU3MB7 ,NotFull Clear Status bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x04 14. " NEWMSGSTATUSU3MB7 ,NewMessage Clear Status bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 13. " NOTFULLSTATUSU3MB6 ,NotFull Clear Status bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x04 12. " NEWMSGSTATUSU3MB6 ,NewMessage Clear Status bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 11. " NOTFULLSTATUSU3MB5 ,NotFull Clear Status bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x04 10. " NEWMSGSTATUSU3MB5 ,NewMessage Clear Status bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 9. " NOTFULLSTATUSU3MB4 ,NotFull Clear Status bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x04 8. " NEWMSGSTATUSU3MB4 ,NewMessage Clear Status bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 7. " NOTFULLSTATUSU3MB3 ,NotFull Clear Status bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x04 6. " NEWMSGSTATUSU3MB3 ,NewMessage Clear Status bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NOTFULLSTATUSU3MB2 ,NotFull Clear Status bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " NEWMSGSTATUSU3MB2 ,NewMessage Clear Status bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 3. " NOTFULLSTATUSU3MB1 ,NotFull Clear Status bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " NEWMSGSTATUSU3MB1 ,NewMessage Clear Status bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 1. " NOTFULLSTATUSU3MB0 ,NotFull Clear Status bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " NEWMSGSTATUSU3MB0 ,NewMessage Clear Status bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
line.long 0x08 "MAILBOX_IRQENABLE_SET_3,Mailbox IRQ Enable Set Register"
|
|
bitfld.long 0x08 23. " NOTFULLENABLEU3MB11 ,NotFull Enable Set bit for User 3 Mailbox 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NEWMSGENABLEU3MB11 ,NewMessage Enable Set bit for User 3 Mailbox 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " NOTFULLENABLEU3MB10 ,NotFull Enable Set bit for User 3 Mailbox 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " NEWMSGENABLEU3MB10 ,NewMessage Enable Set bit for User 3 Mailbox 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NOTFULLENABLEU3MB9 ,NotFull Enable Set bit for User 3 Mailbox 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " NEWMSGENABLEU3MB9 ,NewMessage Enable Set bit for User 3 Mailbox 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " NOTFULLENABLEU3MB8 ,NotFull Enable Set bit for User 3 Mailbox 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " NEWMSGENABLEU3MB8 ,NewMessage Enable Set bit for User 3 Mailbox 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " NOTFULLENABLEU3MB7 ,NotFull Enable Set bit for User 3 Mailbox 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NEWMSGENABLEU3MB7 ,NewMessage Enable Set bit for User 3 Mailbox 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NOTFULLENABLEU3MB6 ,NotFull Enable Set bit for User 3 Mailbox 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NEWMSGENABLEU3MB6 ,NewMessage Enable Set bit for User 3 Mailbox 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NOTFULLENABLEU3MB5 ,NotFull Enable Set bit for User 3 Mailbox 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NEWMSGENABLEU3MB5 ,NewMessage Enable Set bit for User 3 Mailbox 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " NOTFULLENABLEU3MB4 ,NotFull Enable Set bit for User 3 Mailbox 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NEWMSGENABLEU3MB4 ,NewMessage Enable Set bit for User 3 Mailbox 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NOTFULLENABLEU3MB3 ,NotFull Enable Set bit for User 3 Mailbox 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NEWMSGENABLEU3MB3 ,NewMessage Enable Set bit for User 3 Mailbox 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NOTFULLENABLEU3MB2 ,NotFull Enable Set bit for User 3 Mailbox 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NEWMSGENABLEU3MB2 ,NewMessage Enable Set bit for User 3 Mailbox 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NOTFULLENABLEU3MB1 ,NotFull Enable Set bit for User 3 Mailbox 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NEWMSGENABLEU3MB1 ,NewMessage Enable Set bit for User 3 Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NOTFULLENABLEU3MB0 ,NotFull Enable Set bit for User 3 Mailbox 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NEWMSGENABLEU3MB0 ,NewMessage Enable Set bit for User 3 Mailbox 0" "Disabled,Enabled"
|
|
line.long 0x0c "MAILBOX_IRQENABLE_CLR_3,Mailbox IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 23. " NOTFULLENABLEU3MB11 ,NotFull Enable Clear bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
eventfld.long 0x0c 22. " NEWMSGENABLEU3MB11 ,NewMessage Enable Clear bit for User 3 Mailbox 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 21. " NOTFULLENABLEU3MB10 ,NotFull Enable Clear bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
eventfld.long 0x0c 20. " NEWMSGENABLEU3MB10 ,NewMessage Enable Clear bit for User 3 Mailbox 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 19. " NOTFULLENABLEU3MB9 ,NotFull Enable Clear bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
eventfld.long 0x0c 18. " NEWMSGENABLEU3MB9 ,NewMessage Enable Clear bit for User 3 Mailbox 9" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 17. " NOTFULLENABLEU3MB8 ,NotFull Enable Clear bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
eventfld.long 0x0c 16. " NEWMSGENABLEU3MB8 ,NewMessage Enable Clear bit for User 3 Mailbox 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 15. " NOTFULLENABLEU3MB7 ,NotFull Enable Clear bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
eventfld.long 0x0c 14. " NEWMSGENABLEU3MB7 ,NewMessage Enable Clear bit for User 3 Mailbox 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 13. " NOTFULLENABLEU3MB6 ,NotFull Enable Clear bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
eventfld.long 0x0c 12. " NEWMSGENABLEU3MB6 ,NewMessage Enable Clear bit for User 3 Mailbox 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 11. " NOTFULLENABLEU3MB5 ,NotFull Enable Clear bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
eventfld.long 0x0c 10. " NEWMSGENABLEU3MB5 ,NewMessage Enable Clear bit for User 3 Mailbox 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " NOTFULLENABLEU3MB4 ,NotFull Enable Clear bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
eventfld.long 0x0c 8. " NEWMSGENABLEU3MB4 ,NewMessage Enable Clear bit for User 3 Mailbox 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 7. " NOTFULLENABLEU3MB3 ,NotFull Enable Clear bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
eventfld.long 0x0c 6. " NEWMSGENABLEU3MB3 ,NewMessage Enable Clear bit for User 3 Mailbox 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 5. " NOTFULLENABLEU3MB2 ,NotFull Enable Clear bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
eventfld.long 0x0c 4. " NEWMSGENABLEU3MB2 ,NewMessage Enable Clear bit for User 3 Mailbox 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 3. " NOTFULLENABLEU3MB1 ,NotFull Enable Clear bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
eventfld.long 0x0c 2. " NEWMSGENABLEU3MB1 ,NewMessage Enable Clear bit for User 3 Mailbox 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " NOTFULLENABLEU3MB0 ,NotFull Enable Clear bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
eventfld.long 0x0c 0. " NEWMSGENABLEU3MB0 ,NewMessage Enable Clear bit for User 3 Mailbox 0" "Not pending,Pending"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "ELM (Error Location Module)"
|
|
base ad:0x48080000
|
|
width 21.
|
|
rgroup.long 0x000++0x03
|
|
line.long 0x00 "ELM_REVISION,ELM Revision Register"
|
|
group.long 0x010++0x03
|
|
line.long 0x00 "ELM_SYSCONFIG,ELM System Configuration Register"
|
|
bitfld.long 0x00 8. " CLOCKACTIVITYOCP ,OCP Clock activity when module is in IDLE mode" "OFF,ON"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management (IDLE req/ack control)" "Force idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 1. " SOFTRESET ,Module Software Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOGATING ,Internal OCP clock gating strategy" "Free-running,Auto-gating"
|
|
rgroup.long 0x014++0x03
|
|
line.long 0x00 "ELM_SYSSTATUS,ELM System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal Reset monitoring (OCP domain)" "On-going,Completed"
|
|
group.long 0x018++0x03
|
|
line.long 0x00 "ELM_IRQSTATUS,ELM Interrupt Status Register"
|
|
eventfld.long 0x00 8. " PAGE_VALID ,Error location status for a full page" "Invalid,Valid"
|
|
eventfld.long 0x00 7. " LOC_VALID_7 ,Error location status for syndrome polynomial 7" "In progress,Completed"
|
|
eventfld.long 0x00 6. " LOC_VALID_6 ,Error location status for syndrome polynomial 6" "In progress,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 5. " LOC_VALID_5 ,Error location status for syndrome polynomial 5" "In progress,Completed"
|
|
eventfld.long 0x00 4. " LOC_VALID_4 ,Error location status for syndrome polynomial 4" "In progress,Completed"
|
|
eventfld.long 0x00 3. " LOC_VALID_3 ,Error location status for syndrome polynomial 3" "In progress,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 2. " LOC_VALID_2 ,Error location status for syndrome polynomial 2" "In progress,Completed"
|
|
eventfld.long 0x00 1. " LOC_VALID_1 ,Error location status for syndrome polynomial 1" "In progress,Completed"
|
|
eventfld.long 0x00 0. " LOC_VALID_0 ,Error location status for syndrome polynomial 0" "In progress,Completed"
|
|
group.long 0x01C++0x03
|
|
line.long 0x00 "ELM_IRQENABLE,ELM Interrupt Enable Register"
|
|
bitfld.long 0x00 8. " PAGE_MASK ,Error location interrupt enable for a full page" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " LOCATION_MASK_7 ,Error location interrupt enable for syndrome polynomial 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LOCATION_MASK_6 ,Error location interrupt enable for syndrome polynomial 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LOCATION_MASK_5 ,Error location interrupt enable for syndrome polynomial 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCATION_MASK_4 ,Error location interrupt enable for syndrome polynomial 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " LOCATION_MASK_3 ,Error location interrupt enable for syndrome polynomial 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOCATION_MASK_2 ,Error location interrupt enable for syndrome polynomial 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LOCATION_MASK_1 ,Error location interrupt enable for syndrome polynomial 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LOCATION_MASK_0 ,Error location interrupt enable for syndrome polynomial 0" "Disabled,Enabled"
|
|
group.long 0x020++0x03
|
|
line.long 0x00 "ELM_LOCATION_CONFIG,ELM Location Configuration Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " ECC_SIZE ,Maximum size of the buffers (number of nibbles)"
|
|
bitfld.long 0x00 0.--1. " ECC_BCH_LEVEL ,Error correction level" "4 bits,8 bits,16 bits,?..."
|
|
group.long 0x080++0x03
|
|
line.long 0x00 "ELM_PAGE_CTRL,ELM Page Definition Register"
|
|
bitfld.long 0x00 7. " SECTOR_7 ,Syndrome polynomial 7 is part of the page in page mode" "Not used,Used"
|
|
bitfld.long 0x00 6. " SECTOR_6 ,Syndrome polynomial 6 is part of the page in page mode" "Not used,Used"
|
|
bitfld.long 0x00 5. " SECTOR_5 ,Syndrome polynomial 5 is part of the page in page mode" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SECTOR_4 ,Syndrome polynomial 4 is part of the page in page mode" "Not used,Used"
|
|
bitfld.long 0x00 3. " SECTOR_3 ,Syndrome polynomial 3 is part of the page in page mode" "Not used,Used"
|
|
bitfld.long 0x00 2. " SECTOR_2 ,Syndrome polynomial 2 is part of the page in page mode" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SECTOR_1 ,Syndrome polynomial 1 is part of the page in page mode" "Not used,Used"
|
|
bitfld.long 0x00 0. " SECTOR_0 ,Syndrome polynomial 0 is part of the page in page mode" "Not used,Used"
|
|
width 27.
|
|
tree "Syndrome Polynomial 0"
|
|
group.long (0x400+0x0)++0x1b
|
|
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_0,Input syndrome polynomial bits 0 to 31"
|
|
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_0,Input syndrome polynomial bits 32 to 63"
|
|
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_0,Input syndrome polynomial bits 64 to 95"
|
|
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_0,Input syndrome polynomial bits 96 to 127"
|
|
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_0,Input syndrome polynomial bits 128 to 159"
|
|
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_0,Input syndrome polynomial bits 160 to 191"
|
|
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_0,Input syndrome polynomial bits 192 to 207"
|
|
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
|
|
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
|
|
rgroup.long (0x800+0x0)++0x03
|
|
line.long 0x00 "ELM_LOCATION_STATUS_0,Error Location Status Register"
|
|
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
|
|
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (0x880+0x0)++0x3f
|
|
line.long 0x00 "ELM_ERROR_LOCATION_0_0,Error Location Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x04 "ELM_ERROR_LOCATION_1_0,Error Location Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x08 "ELM_ERROR_LOCATION_2_0,Error Location Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x0c "ELM_ERROR_LOCATION_3_0,Error Location Register"
|
|
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x10 "ELM_ERROR_LOCATION_4_0,Error Location Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x14 "ELM_ERROR_LOCATION_5_0,Error Location Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x18 "ELM_ERROR_LOCATION_6_0,Error Location Register"
|
|
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x1c "ELM_ERROR_LOCATION_7_0,Error Location Register"
|
|
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x20 "ELM_ERROR_LOCATION_8_0,Error Location Register"
|
|
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x24 "ELM_ERROR_LOCATION_9_0,Error Location Register"
|
|
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x28 "ELM_ERROR_LOCATION_10_0,Error Location Register"
|
|
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x2c "ELM_ERROR_LOCATION_11_0,Error Location Register"
|
|
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x30 "ELM_ERROR_LOCATION_12_0,Error Location Register"
|
|
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x34 "ELM_ERROR_LOCATION_13_0,Error Location Register"
|
|
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x38 "ELM_ERROR_LOCATION_14_0,Error Location Register"
|
|
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x3c "ELM_ERROR_LOCATION_15_0,Error Location Register"
|
|
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
tree.end
|
|
tree "Syndrome Polynomial 1"
|
|
group.long (0x400+0x40)++0x1b
|
|
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_1,Input syndrome polynomial bits 0 to 31"
|
|
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_1,Input syndrome polynomial bits 32 to 63"
|
|
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_1,Input syndrome polynomial bits 64 to 95"
|
|
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_1,Input syndrome polynomial bits 96 to 127"
|
|
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_1,Input syndrome polynomial bits 128 to 159"
|
|
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_1,Input syndrome polynomial bits 160 to 191"
|
|
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_1,Input syndrome polynomial bits 192 to 207"
|
|
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
|
|
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
|
|
rgroup.long (0x800+0x100)++0x03
|
|
line.long 0x00 "ELM_LOCATION_STATUS_1,Error Location Status Register"
|
|
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
|
|
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (0x880+0x100)++0x3f
|
|
line.long 0x00 "ELM_ERROR_LOCATION_0_1,Error Location Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x04 "ELM_ERROR_LOCATION_1_1,Error Location Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x08 "ELM_ERROR_LOCATION_2_1,Error Location Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x0c "ELM_ERROR_LOCATION_3_1,Error Location Register"
|
|
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x10 "ELM_ERROR_LOCATION_4_1,Error Location Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x14 "ELM_ERROR_LOCATION_5_1,Error Location Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x18 "ELM_ERROR_LOCATION_6_1,Error Location Register"
|
|
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x1c "ELM_ERROR_LOCATION_7_1,Error Location Register"
|
|
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x20 "ELM_ERROR_LOCATION_8_1,Error Location Register"
|
|
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x24 "ELM_ERROR_LOCATION_9_1,Error Location Register"
|
|
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x28 "ELM_ERROR_LOCATION_10_1,Error Location Register"
|
|
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x2c "ELM_ERROR_LOCATION_11_1,Error Location Register"
|
|
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x30 "ELM_ERROR_LOCATION_12_1,Error Location Register"
|
|
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x34 "ELM_ERROR_LOCATION_13_1,Error Location Register"
|
|
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x38 "ELM_ERROR_LOCATION_14_1,Error Location Register"
|
|
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x3c "ELM_ERROR_LOCATION_15_1,Error Location Register"
|
|
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
tree.end
|
|
tree "Syndrome Polynomial 2"
|
|
group.long (0x400+0x80)++0x1b
|
|
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_2,Input syndrome polynomial bits 0 to 31"
|
|
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_2,Input syndrome polynomial bits 32 to 63"
|
|
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_2,Input syndrome polynomial bits 64 to 95"
|
|
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_2,Input syndrome polynomial bits 96 to 127"
|
|
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_2,Input syndrome polynomial bits 128 to 159"
|
|
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_2,Input syndrome polynomial bits 160 to 191"
|
|
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_2,Input syndrome polynomial bits 192 to 207"
|
|
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
|
|
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
|
|
rgroup.long (0x800+0x200)++0x03
|
|
line.long 0x00 "ELM_LOCATION_STATUS_2,Error Location Status Register"
|
|
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
|
|
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (0x880+0x200)++0x3f
|
|
line.long 0x00 "ELM_ERROR_LOCATION_0_2,Error Location Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x04 "ELM_ERROR_LOCATION_1_2,Error Location Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x08 "ELM_ERROR_LOCATION_2_2,Error Location Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x0c "ELM_ERROR_LOCATION_3_2,Error Location Register"
|
|
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x10 "ELM_ERROR_LOCATION_4_2,Error Location Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x14 "ELM_ERROR_LOCATION_5_2,Error Location Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x18 "ELM_ERROR_LOCATION_6_2,Error Location Register"
|
|
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x1c "ELM_ERROR_LOCATION_7_2,Error Location Register"
|
|
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x20 "ELM_ERROR_LOCATION_8_2,Error Location Register"
|
|
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x24 "ELM_ERROR_LOCATION_9_2,Error Location Register"
|
|
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x28 "ELM_ERROR_LOCATION_10_2,Error Location Register"
|
|
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x2c "ELM_ERROR_LOCATION_11_2,Error Location Register"
|
|
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x30 "ELM_ERROR_LOCATION_12_2,Error Location Register"
|
|
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x34 "ELM_ERROR_LOCATION_13_2,Error Location Register"
|
|
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x38 "ELM_ERROR_LOCATION_14_2,Error Location Register"
|
|
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x3c "ELM_ERROR_LOCATION_15_2,Error Location Register"
|
|
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
tree.end
|
|
tree "Syndrome Polynomial 3"
|
|
group.long (0x400+0xC0)++0x1b
|
|
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_3,Input syndrome polynomial bits 0 to 31"
|
|
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_3,Input syndrome polynomial bits 32 to 63"
|
|
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_3,Input syndrome polynomial bits 64 to 95"
|
|
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_3,Input syndrome polynomial bits 96 to 127"
|
|
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_3,Input syndrome polynomial bits 128 to 159"
|
|
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_3,Input syndrome polynomial bits 160 to 191"
|
|
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_3,Input syndrome polynomial bits 192 to 207"
|
|
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
|
|
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
|
|
rgroup.long (0x800+0x300)++0x03
|
|
line.long 0x00 "ELM_LOCATION_STATUS_3,Error Location Status Register"
|
|
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
|
|
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (0x880+0x300)++0x3f
|
|
line.long 0x00 "ELM_ERROR_LOCATION_0_3,Error Location Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x04 "ELM_ERROR_LOCATION_1_3,Error Location Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x08 "ELM_ERROR_LOCATION_2_3,Error Location Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x0c "ELM_ERROR_LOCATION_3_3,Error Location Register"
|
|
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x10 "ELM_ERROR_LOCATION_4_3,Error Location Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x14 "ELM_ERROR_LOCATION_5_3,Error Location Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x18 "ELM_ERROR_LOCATION_6_3,Error Location Register"
|
|
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x1c "ELM_ERROR_LOCATION_7_3,Error Location Register"
|
|
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x20 "ELM_ERROR_LOCATION_8_3,Error Location Register"
|
|
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x24 "ELM_ERROR_LOCATION_9_3,Error Location Register"
|
|
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x28 "ELM_ERROR_LOCATION_10_3,Error Location Register"
|
|
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x2c "ELM_ERROR_LOCATION_11_3,Error Location Register"
|
|
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x30 "ELM_ERROR_LOCATION_12_3,Error Location Register"
|
|
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x34 "ELM_ERROR_LOCATION_13_3,Error Location Register"
|
|
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x38 "ELM_ERROR_LOCATION_14_3,Error Location Register"
|
|
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x3c "ELM_ERROR_LOCATION_15_3,Error Location Register"
|
|
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
tree.end
|
|
tree "Syndrome Polynomial 4"
|
|
group.long (0x400+0x100)++0x1b
|
|
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_4,Input syndrome polynomial bits 0 to 31"
|
|
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_4,Input syndrome polynomial bits 32 to 63"
|
|
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_4,Input syndrome polynomial bits 64 to 95"
|
|
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_4,Input syndrome polynomial bits 96 to 127"
|
|
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_4,Input syndrome polynomial bits 128 to 159"
|
|
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_4,Input syndrome polynomial bits 160 to 191"
|
|
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_4,Input syndrome polynomial bits 192 to 207"
|
|
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
|
|
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
|
|
rgroup.long (0x800+0x400)++0x03
|
|
line.long 0x00 "ELM_LOCATION_STATUS_4,Error Location Status Register"
|
|
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
|
|
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (0x880+0x400)++0x3f
|
|
line.long 0x00 "ELM_ERROR_LOCATION_0_4,Error Location Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x04 "ELM_ERROR_LOCATION_1_4,Error Location Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x08 "ELM_ERROR_LOCATION_2_4,Error Location Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x0c "ELM_ERROR_LOCATION_3_4,Error Location Register"
|
|
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x10 "ELM_ERROR_LOCATION_4_4,Error Location Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x14 "ELM_ERROR_LOCATION_5_4,Error Location Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x18 "ELM_ERROR_LOCATION_6_4,Error Location Register"
|
|
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x1c "ELM_ERROR_LOCATION_7_4,Error Location Register"
|
|
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x20 "ELM_ERROR_LOCATION_8_4,Error Location Register"
|
|
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x24 "ELM_ERROR_LOCATION_9_4,Error Location Register"
|
|
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x28 "ELM_ERROR_LOCATION_10_4,Error Location Register"
|
|
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x2c "ELM_ERROR_LOCATION_11_4,Error Location Register"
|
|
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x30 "ELM_ERROR_LOCATION_12_4,Error Location Register"
|
|
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x34 "ELM_ERROR_LOCATION_13_4,Error Location Register"
|
|
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x38 "ELM_ERROR_LOCATION_14_4,Error Location Register"
|
|
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x3c "ELM_ERROR_LOCATION_15_4,Error Location Register"
|
|
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
tree.end
|
|
tree "Syndrome Polynomial 5"
|
|
group.long (0x400+0x140)++0x1b
|
|
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_5,Input syndrome polynomial bits 0 to 31"
|
|
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_5,Input syndrome polynomial bits 32 to 63"
|
|
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_5,Input syndrome polynomial bits 64 to 95"
|
|
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_5,Input syndrome polynomial bits 96 to 127"
|
|
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_5,Input syndrome polynomial bits 128 to 159"
|
|
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_5,Input syndrome polynomial bits 160 to 191"
|
|
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_5,Input syndrome polynomial bits 192 to 207"
|
|
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
|
|
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
|
|
rgroup.long (0x800+0x500)++0x03
|
|
line.long 0x00 "ELM_LOCATION_STATUS_5,Error Location Status Register"
|
|
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
|
|
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (0x880+0x500)++0x3f
|
|
line.long 0x00 "ELM_ERROR_LOCATION_0_5,Error Location Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x04 "ELM_ERROR_LOCATION_1_5,Error Location Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x08 "ELM_ERROR_LOCATION_2_5,Error Location Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x0c "ELM_ERROR_LOCATION_3_5,Error Location Register"
|
|
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x10 "ELM_ERROR_LOCATION_4_5,Error Location Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x14 "ELM_ERROR_LOCATION_5_5,Error Location Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x18 "ELM_ERROR_LOCATION_6_5,Error Location Register"
|
|
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x1c "ELM_ERROR_LOCATION_7_5,Error Location Register"
|
|
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x20 "ELM_ERROR_LOCATION_8_5,Error Location Register"
|
|
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x24 "ELM_ERROR_LOCATION_9_5,Error Location Register"
|
|
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x28 "ELM_ERROR_LOCATION_10_5,Error Location Register"
|
|
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x2c "ELM_ERROR_LOCATION_11_5,Error Location Register"
|
|
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x30 "ELM_ERROR_LOCATION_12_5,Error Location Register"
|
|
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x34 "ELM_ERROR_LOCATION_13_5,Error Location Register"
|
|
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x38 "ELM_ERROR_LOCATION_14_5,Error Location Register"
|
|
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x3c "ELM_ERROR_LOCATION_15_5,Error Location Register"
|
|
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
tree.end
|
|
tree "Syndrome Polynomial 6"
|
|
group.long (0x400+0x180)++0x1b
|
|
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_6,Input syndrome polynomial bits 0 to 31"
|
|
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_6,Input syndrome polynomial bits 32 to 63"
|
|
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_6,Input syndrome polynomial bits 64 to 95"
|
|
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_6,Input syndrome polynomial bits 96 to 127"
|
|
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_6,Input syndrome polynomial bits 128 to 159"
|
|
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_6,Input syndrome polynomial bits 160 to 191"
|
|
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_6,Input syndrome polynomial bits 192 to 207"
|
|
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
|
|
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
|
|
rgroup.long (0x800+0x600)++0x03
|
|
line.long 0x00 "ELM_LOCATION_STATUS_6,Error Location Status Register"
|
|
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
|
|
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (0x880+0x600)++0x3f
|
|
line.long 0x00 "ELM_ERROR_LOCATION_0_6,Error Location Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x04 "ELM_ERROR_LOCATION_1_6,Error Location Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x08 "ELM_ERROR_LOCATION_2_6,Error Location Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x0c "ELM_ERROR_LOCATION_3_6,Error Location Register"
|
|
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x10 "ELM_ERROR_LOCATION_4_6,Error Location Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x14 "ELM_ERROR_LOCATION_5_6,Error Location Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x18 "ELM_ERROR_LOCATION_6_6,Error Location Register"
|
|
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x1c "ELM_ERROR_LOCATION_7_6,Error Location Register"
|
|
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x20 "ELM_ERROR_LOCATION_8_6,Error Location Register"
|
|
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x24 "ELM_ERROR_LOCATION_9_6,Error Location Register"
|
|
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x28 "ELM_ERROR_LOCATION_10_6,Error Location Register"
|
|
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x2c "ELM_ERROR_LOCATION_11_6,Error Location Register"
|
|
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x30 "ELM_ERROR_LOCATION_12_6,Error Location Register"
|
|
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x34 "ELM_ERROR_LOCATION_13_6,Error Location Register"
|
|
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x38 "ELM_ERROR_LOCATION_14_6,Error Location Register"
|
|
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x3c "ELM_ERROR_LOCATION_15_6,Error Location Register"
|
|
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
tree.end
|
|
tree "Syndrome Polynomial 7"
|
|
group.long (0x400+0x1C0)++0x1b
|
|
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_7,Input syndrome polynomial bits 0 to 31"
|
|
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_7,Input syndrome polynomial bits 32 to 63"
|
|
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_7,Input syndrome polynomial bits 64 to 95"
|
|
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_7,Input syndrome polynomial bits 96 to 127"
|
|
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_7,Input syndrome polynomial bits 128 to 159"
|
|
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_7,Input syndrome polynomial bits 160 to 191"
|
|
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_7,Input syndrome polynomial bits 192 to 207"
|
|
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
|
|
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
|
|
rgroup.long (0x800+0x700)++0x03
|
|
line.long 0x00 "ELM_LOCATION_STATUS_7,Error Location Status Register"
|
|
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
|
|
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (0x880+0x700)++0x3f
|
|
line.long 0x00 "ELM_ERROR_LOCATION_0_7,Error Location Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x04 "ELM_ERROR_LOCATION_1_7,Error Location Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x08 "ELM_ERROR_LOCATION_2_7,Error Location Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x0c "ELM_ERROR_LOCATION_3_7,Error Location Register"
|
|
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x10 "ELM_ERROR_LOCATION_4_7,Error Location Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x14 "ELM_ERROR_LOCATION_5_7,Error Location Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x18 "ELM_ERROR_LOCATION_6_7,Error Location Register"
|
|
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x1c "ELM_ERROR_LOCATION_7_7,Error Location Register"
|
|
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x20 "ELM_ERROR_LOCATION_8_7,Error Location Register"
|
|
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x24 "ELM_ERROR_LOCATION_9_7,Error Location Register"
|
|
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x28 "ELM_ERROR_LOCATION_10_7,Error Location Register"
|
|
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x2c "ELM_ERROR_LOCATION_11_7,Error Location Register"
|
|
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x30 "ELM_ERROR_LOCATION_12_7,Error Location Register"
|
|
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x34 "ELM_ERROR_LOCATION_13_7,Error Location Register"
|
|
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x38 "ELM_ERROR_LOCATION_14_7,Error Location Register"
|
|
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
line.long 0x3c "ELM_ERROR_LOCATION_15_7,Error Location Register"
|
|
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
sif (!cpuis("DRA62*"))
|
|
tree "DMM (Dynamic Memory Manager)"
|
|
base ad:0x4e000000
|
|
width 23.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "DMM_REVISION,DMM Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatibility level"
|
|
hexmask.long.byte 0x00 11.--15. 1. " RRTL ,RTL Version (R)"
|
|
bitfld.long 0x00 8.--10. " XMAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Special DMM version" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision (Y)"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "DMM_SYSCONFIG,DMM Clock Management Configuration Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No idle,Smart-idle,?..."
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "DMM_LISA_LOCK,LISA Configuration Locking Register"
|
|
bitfld.long 0x00 0. " LOCK ,DMM lock map" "Unlocked,Locked"
|
|
group.long 0x40++0xf
|
|
line.long 0x0 "DMM_LISA_MAP[0],DMM LISA MAP 0 Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " SYS_ADDR ,DMM system section address MSB"
|
|
bitfld.long 0x0 20.--22. " SYS_SIZE ,DMM system section size" "16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB"
|
|
bitfld.long 0x0 18.--19. " SDRC_INTL ,EMIF controller interleaving mode" "No interleaving,128-byte,256-byte,512-byte"
|
|
bitfld.long 0x0 8.--9. " SDRC_MAP ,EMIF controller mapping" "Un-mapped,SDRC 0 (not interleaved),SDRC 1 (not interleaved),SDRC 0/1 (interleaved)"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " SDRC_ADDR ,EMIF controller address MSB"
|
|
line.long 0x4 "DMM_LISA_MAP[1],DMM LISA MAP 1 Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " SYS_ADDR ,DMM system section address MSB"
|
|
bitfld.long 0x4 20.--22. " SYS_SIZE ,DMM system section size" "16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB"
|
|
bitfld.long 0x4 18.--19. " SDRC_INTL ,EMIF controller interleaving mode" "No interleaving,128-byte,256-byte,512-byte"
|
|
bitfld.long 0x4 8.--9. " SDRC_MAP ,EMIF controller mapping" "Un-mapped,SDRC 0 (not interleaved),SDRC 1 (not interleaved),SDRC 0/1 (interleaved)"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " SDRC_ADDR ,EMIF controller address MSB"
|
|
line.long 0x8 "DMM_LISA_MAP[2],DMM LISA MAP 2 Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " SYS_ADDR ,DMM system section address MSB"
|
|
bitfld.long 0x8 20.--22. " SYS_SIZE ,DMM system section size" "16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB"
|
|
bitfld.long 0x8 18.--19. " SDRC_INTL ,EMIF controller interleaving mode" "No interleaving,128-byte,256-byte,512-byte"
|
|
bitfld.long 0x8 8.--9. " SDRC_MAP ,EMIF controller mapping" "Un-mapped,SDRC 0 (not interleaved),SDRC 1 (not interleaved),SDRC 0/1 (interleaved)"
|
|
textline " "
|
|
hexmask.long.byte 0x8 0.--7. 1. " SDRC_ADDR ,EMIF controller address MSB"
|
|
line.long 0xC "DMM_LISA_MAP[3],DMM LISA MAP 3 Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " SYS_ADDR ,DMM system section address MSB"
|
|
bitfld.long 0xC 20.--22. " SYS_SIZE ,DMM system section size" "16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB"
|
|
bitfld.long 0xC 18.--19. " SDRC_INTL ,EMIF controller interleaving mode" "No interleaving,128-byte,256-byte,512-byte"
|
|
bitfld.long 0xC 8.--9. " SDRC_MAP ,EMIF controller mapping" "Un-mapped,SDRC 0 (not interleaved),SDRC 1 (not interleaved),SDRC 0/1 (interleaved)"
|
|
textline " "
|
|
hexmask.long.byte 0xC 0.--7. 1. " SDRC_ADDR ,EMIF controller address MSB"
|
|
width 23.
|
|
group.long 0x220++0x7
|
|
line.long 0x0 "DMM_TILER_OR[0],DMM TILER Orientation 0 Register"
|
|
bitfld.long 0x0 31. " W7 ,Write-enable for OR7 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 28.--30. " OR7 ,Orientation for initiator 8.0+7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 27. " W6 ,Write-enable for OR6 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 24.--26. " OR6 ,Orientation for initiator 8.0+6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 23. " W5 ,Write-enable for OR5 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 20.--22. " OR5 ,Orientation for initiator 8.0+5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 19. " W4 ,Write-enable for OR4 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--18. " OR4 ,Orientation for initiator 8.0+4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 15. " W3 ,Write-enable for OR3 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 12.--14. " OR3 ,Orientation for initiator 8.0+3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. " W2 ,Write-enable for OR2 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 8.--10. " OR2 ,Orientation for initiator 8.0+2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 7. " W1 ,Write-enable for OR1 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 4.--6. " OR1 ,Orientation for initiator 8.0+1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. " W0 ,Write-enable for OR0 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " OR0 ,Orientation for initiator 8.0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DMM_TILER_OR[1],DMM TILER Orientation 1 Register"
|
|
bitfld.long 0x4 31. " W7 ,Write-enable for OR7 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 28.--30. " OR7 ,Orientation for initiator 8.1+7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 27. " W6 ,Write-enable for OR6 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 24.--26. " OR6 ,Orientation for initiator 8.1+6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 23. " W5 ,Write-enable for OR5 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 20.--22. " OR5 ,Orientation for initiator 8.1+5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 19. " W4 ,Write-enable for OR4 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 16.--18. " OR4 ,Orientation for initiator 8.1+4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 15. " W3 ,Write-enable for OR3 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 12.--14. " OR3 ,Orientation for initiator 8.1+3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. " W2 ,Write-enable for OR2 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 8.--10. " OR2 ,Orientation for initiator 8.1+2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. " W1 ,Write-enable for OR1 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 4.--6. " OR1 ,Orientation for initiator 8.1+1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. " W0 ,Write-enable for OR0 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " OR0 ,Orientation for initiator 8.1" "0,1,2,3,4,5,6,7"
|
|
group.long 0x410++0x3
|
|
line.long 0x00 "DMM_PAT_CONFIG,DMM PAT Configuration Register"
|
|
bitfld.long 0x00 3. " MODE3 ,Mode of refill engine 3" "Normal,Direct LUT"
|
|
bitfld.long 0x00 2. " MODE2 ,Mode of refill engine 2" "Normal,Direct LUT"
|
|
bitfld.long 0x00 1. " MODE1 ,Mode of refill engine 1" "Normal,Direct LUT"
|
|
bitfld.long 0x00 0. " MODE0 ,Mode of refill engine 0" "Normal,Direct LUT"
|
|
group.long 0x420++0xf
|
|
line.long 0x0 "DMM_PAT_VIEW[0],DMM PAT View 0 Register"
|
|
bitfld.long 0x0 31. " W7 ,Write-enable for V7 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 28.--29. " V7 ,PAT view for initiator 8.0+7" "0,1,2,3"
|
|
bitfld.long 0x0 27. " W6 ,Write-enable for V6 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 24.--25. " V6 ,PAT view for initiator 8.0+6" "0,1,2,3"
|
|
bitfld.long 0x0 23. " W5 ,Write-enable for V5 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 20.--21. " V5 ,PAT view for initiator 8.0+5" "0,1,2,3"
|
|
bitfld.long 0x0 19. " W4 ,Write-enable for V4 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--17. " V4 ,PAT view for initiator 8.0+4" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0 15. " W3 ,Write-enable for V3 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 12.--13. " V3 ,PAT view for initiator 8.0+3" "0,1,2,3"
|
|
bitfld.long 0x0 11. " W2 ,Write-enable for V2 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 8.--9. " V2 ,PAT view for initiator 8.0+2" "0,1,2,3"
|
|
bitfld.long 0x0 7. " W1 ,Write-enable for V1 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 4.--5. " V1 ,PAT view for initiator 8.0+1" "0,1,2,3"
|
|
bitfld.long 0x0 3. " W0 ,Write-enable for V0 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--1. " V0 ,PAT view for initiator 8.0+0" "0,1,2,3"
|
|
line.long 0x4 "DMM_PAT_VIEW[1],DMM PAT View 1 Register"
|
|
bitfld.long 0x4 31. " W7 ,Write-enable for V7 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 28.--29. " V7 ,PAT view for initiator 8.1+7" "0,1,2,3"
|
|
bitfld.long 0x4 27. " W6 ,Write-enable for V6 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 24.--25. " V6 ,PAT view for initiator 8.1+6" "0,1,2,3"
|
|
bitfld.long 0x4 23. " W5 ,Write-enable for V5 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 20.--21. " V5 ,PAT view for initiator 8.1+5" "0,1,2,3"
|
|
bitfld.long 0x4 19. " W4 ,Write-enable for V4 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 16.--17. " V4 ,PAT view for initiator 8.1+4" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x4 15. " W3 ,Write-enable for V3 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 12.--13. " V3 ,PAT view for initiator 8.1+3" "0,1,2,3"
|
|
bitfld.long 0x4 11. " W2 ,Write-enable for V2 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 8.--9. " V2 ,PAT view for initiator 8.1+2" "0,1,2,3"
|
|
bitfld.long 0x4 7. " W1 ,Write-enable for V1 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 4.--5. " V1 ,PAT view for initiator 8.1+1" "0,1,2,3"
|
|
bitfld.long 0x4 3. " W0 ,Write-enable for V0 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--1. " V0 ,PAT view for initiator 8.1+0" "0,1,2,3"
|
|
line.long 0x8 "DMM_PAT_VIEW[2],DMM PAT View 2 Register"
|
|
bitfld.long 0x8 31. " W7 ,Write-enable for V7 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x8 28.--29. " V7 ,PAT view for initiator 8.2+7" "0,1,2,3"
|
|
bitfld.long 0x8 27. " W6 ,Write-enable for V6 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x8 24.--25. " V6 ,PAT view for initiator 8.2+6" "0,1,2,3"
|
|
bitfld.long 0x8 23. " W5 ,Write-enable for V5 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x8 20.--21. " V5 ,PAT view for initiator 8.2+5" "0,1,2,3"
|
|
bitfld.long 0x8 19. " W4 ,Write-enable for V4 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x8 16.--17. " V4 ,PAT view for initiator 8.2+4" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x8 15. " W3 ,Write-enable for V3 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x8 12.--13. " V3 ,PAT view for initiator 8.2+3" "0,1,2,3"
|
|
bitfld.long 0x8 11. " W2 ,Write-enable for V2 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x8 8.--9. " V2 ,PAT view for initiator 8.2+2" "0,1,2,3"
|
|
bitfld.long 0x8 7. " W1 ,Write-enable for V1 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x8 4.--5. " V1 ,PAT view for initiator 8.2+1" "0,1,2,3"
|
|
bitfld.long 0x8 3. " W0 ,Write-enable for V0 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--1. " V0 ,PAT view for initiator 8.2+0" "0,1,2,3"
|
|
line.long 0xC "DMM_PAT_VIEW[3],DMM PAT View 3 Register"
|
|
bitfld.long 0xC 31. " W7 ,Write-enable for V7 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0xC 28.--29. " V7 ,PAT view for initiator 8.3+7" "0,1,2,3"
|
|
bitfld.long 0xC 27. " W6 ,Write-enable for V6 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0xC 24.--25. " V6 ,PAT view for initiator 8.3+6" "0,1,2,3"
|
|
bitfld.long 0xC 23. " W5 ,Write-enable for V5 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0xC 20.--21. " V5 ,PAT view for initiator 8.3+5" "0,1,2,3"
|
|
bitfld.long 0xC 19. " W4 ,Write-enable for V4 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0xC 16.--17. " V4 ,PAT view for initiator 8.3+4" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0xC 15. " W3 ,Write-enable for V3 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0xC 12.--13. " V3 ,PAT view for initiator 8.3+3" "0,1,2,3"
|
|
bitfld.long 0xC 11. " W2 ,Write-enable for V2 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0xC 8.--9. " V2 ,PAT view for initiator 8.3+2" "0,1,2,3"
|
|
bitfld.long 0xC 7. " W1 ,Write-enable for V1 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0xC 4.--5. " V1 ,PAT view for initiator 8.3+1" "0,1,2,3"
|
|
bitfld.long 0xC 3. " W0 ,Write-enable for V0 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--1. " V0 ,PAT view for initiator 8.3+0" "0,1,2,3"
|
|
width 23.
|
|
group.long 0x440++0xf
|
|
line.long 0x0 "DMM_PAT_VIEW_MAP[0],DMM View Map 0 Register"
|
|
bitfld.long 0x0 31. " ACCESS_PAGE ,Kind of access for this page mode container" "Direct,LUT"
|
|
bitfld.long 0x0 24.--27. " CONT_PAGE ,Container for page mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 23. " ACCESS_32 ,Kind of access for this 32-bit mode container" "Direct,LUT"
|
|
bitfld.long 0x0 16.--19. " CONT_32 ,Container for 32-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 15. " ACCESS_16 ,Kind of access for this 16-bit mode container" "Direct,LUT"
|
|
bitfld.long 0x0 8.--11. " CONT_16 ,Container for 16-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 7. " ACCESS_8 ,Kind of access for this 8-bit mode container" "Direct,LUT"
|
|
bitfld.long 0x0 0.--3. " CONT_8 ,Container for 8-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "DMM_PAT_VIEW_MAP[1],DMM View Map 1 Register"
|
|
bitfld.long 0x4 31. " ACCESS_PAGE ,Kind of access for this page mode container" "Direct,LUT"
|
|
bitfld.long 0x4 24.--27. " CONT_PAGE ,Container for page mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 23. " ACCESS_32 ,Kind of access for this 32-bit mode container" "Direct,LUT"
|
|
bitfld.long 0x4 16.--19. " CONT_32 ,Container for 32-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 15. " ACCESS_16 ,Kind of access for this 16-bit mode container" "Direct,LUT"
|
|
bitfld.long 0x4 8.--11. " CONT_16 ,Container for 16-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 7. " ACCESS_8 ,Kind of access for this 8-bit mode container" "Direct,LUT"
|
|
bitfld.long 0x4 0.--3. " CONT_8 ,Container for 8-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "DMM_PAT_VIEW_MAP[2],DMM View Map 2 Register"
|
|
bitfld.long 0x8 31. " ACCESS_PAGE ,Kind of access for this page mode container" "Direct,LUT"
|
|
bitfld.long 0x8 24.--27. " CONT_PAGE ,Container for page mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 23. " ACCESS_32 ,Kind of access for this 32-bit mode container" "Direct,LUT"
|
|
bitfld.long 0x8 16.--19. " CONT_32 ,Container for 32-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 15. " ACCESS_16 ,Kind of access for this 16-bit mode container" "Direct,LUT"
|
|
bitfld.long 0x8 8.--11. " CONT_16 ,Container for 16-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 7. " ACCESS_8 ,Kind of access for this 8-bit mode container" "Direct,LUT"
|
|
bitfld.long 0x8 0.--3. " CONT_8 ,Container for 8-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "DMM_PAT_VIEW_MAP[3],DMM View Map 3 Register"
|
|
bitfld.long 0xC 31. " ACCESS_PAGE ,Kind of access for this page mode container" "Direct,LUT"
|
|
bitfld.long 0xC 24.--27. " CONT_PAGE ,Container for page mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 23. " ACCESS_32 ,Kind of access for this 32-bit mode container" "Direct,LUT"
|
|
bitfld.long 0xC 16.--19. " CONT_32 ,Container for 32-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 15. " ACCESS_16 ,Kind of access for this 16-bit mode container" "Direct,LUT"
|
|
bitfld.long 0xC 8.--11. " CONT_16 ,Container for 16-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 7. " ACCESS_8 ,Kind of access for this 8-bit mode container" "Direct,LUT"
|
|
bitfld.long 0xC 0.--3. " CONT_8 ,Container for 8-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x460++0x3
|
|
line.long 0x00 "DMM_PAT_VIEW_MAP_BASE,DMM PAT View Mapping Base Address Register"
|
|
bitfld.long 0x00 31. " BASE_ADDR ,MSB of the PAT view mapping base address" "0,1"
|
|
width 23.
|
|
group.long 0x478++0x3
|
|
line.long 0x00 "DMM_PAT_IRQ_EOI,DMM PAT End Of Interrupt (Status/Set) Register"
|
|
bitfld.long 0x00 31. " ERR_LUT_MISS3 ,Unexpected Access to a yet-to-be-refilled area event in area 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " ERR_UPD_DATA3 ,Data register update whilst refilling error event in area 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " ERR_UPD_CTRL3 ,Control register update whilst refilling error event in area 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " ERR_UPD_AREA3 ,Area register update whilst refilling error event in area 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ERR_INV_DATA3 ,Invalid entry-table pointer error event in area 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " ERR_INV_DSC3 ,Invalid descriptor pointer error event in area 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " FILL_LST3 ,End of refill event for the last descriptor in area 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " FILL_DSC3 ,End of refill event for any descriptor in area 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ERR_LUT_MISS2 ,Unexpected Access to a yet-to-be-refilled area event in area 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " ERR_UPD_DATA2 ,Data register update whilst refilling error event in area 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " ERR_UPD_CTRL2 ,Control register update whilst refilling error event in area 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " ERR_UPD_AREA2 ,Area register update whilst refilling error event in area 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERR_INV_DATA2 ,Invalid entry-table pointer error event in area 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " ERR_INV_DSC2 ,Invalid descriptor pointer error event in area 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " FILL_LST2 ,End of refill event for the last descriptor in area 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " FILL_DSC2 ,End of refill event for any descriptor in area 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERR_LUT_MISS1 ,Unexpected Access to a yet-to-be-refilled area event in area 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " FILL_LST1 ,End of refill event for the last descriptor in area 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " FILL_DSC1 ,End of refill event for any descriptor in area 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERR_LUT_MISS0 ,Unexpected Access to a yet-to-be-refilled area event in area 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " FILL_LST0 ,End of refill event for the last descriptor in area 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " FILL_DSC0 ,End of refill event for any descriptor in area 0" "No interrupt,Interrupt"
|
|
group.long 0x480++0x3
|
|
line.long 0x00 "DMM_PAT_IRQSTATUS_RAW,PDMM PAT Raw Interrupt Status/Set Register"
|
|
bitfld.long 0x00 31. " ERR_LUT_MISS3 ,Unexpected Access to a yet-to-be-refilled area event in area 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " ERR_UPD_DATA3 ,Data register update whilst refilling error event in area 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " ERR_UPD_CTRL3 ,Control register update whilst refilling error event in area 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " ERR_UPD_AREA3 ,Area register update whilst refilling error event in area 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ERR_INV_DATA3 ,Invalid entry-table pointer error event in area 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " ERR_INV_DSC3 ,Invalid descriptor pointer error event in area 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " FILL_LST3 ,End of refill event for the last descriptor in area 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " FILL_DSC3 ,End of refill event for any descriptor in area 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ERR_LUT_MISS2 ,Unexpected Access to a yet-to-be-refilled area event in area 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " ERR_UPD_DATA2 ,Data register update whilst refilling error event in area 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " ERR_UPD_CTRL2 ,Control register update whilst refilling error event in area 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " ERR_UPD_AREA2 ,Area register update whilst refilling error event in area 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERR_INV_DATA2 ,Invalid entry-table pointer error event in area 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " ERR_INV_DSC2 ,Invalid descriptor pointer error event in area 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " FILL_LST2 ,End of refill event for the last descriptor in area 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " FILL_DSC2 ,End of refill event for any descriptor in area 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERR_LUT_MISS1 ,Unexpected Access to a yet-to-be-refilled area event in area 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " FILL_LST1 ,End of refill event for the last descriptor in area 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " FILL_DSC1 ,End of refill event for any descriptor in area 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERR_LUT_MISS0 ,Unexpected Access to a yet-to-be-refilled area event in area 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " FILL_LST0 ,End of refill event for the last descriptor in area 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " FILL_DSC0 ,End of refill event for any descriptor in area 0" "No interrupt,Interrupt"
|
|
group.long 0x490++0x3
|
|
line.long 0x00 "DMM_PAT_IRQSTATUS,PDMM PAT Interrupt Status/Clear Register"
|
|
eventfld.long 0x00 31. " ERR_LUT_MISS3 ,Unexpected Access to a yet-to-be-refilled area event in area 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " ERR_UPD_DATA3 ,Data register update whilst refilling error event in area 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ERR_UPD_CTRL3 ,Control register update whilst refilling error event in area 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " ERR_UPD_AREA3 ,Area register update whilst refilling error event in area 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " ERR_INV_DATA3 ,Invalid entry-table pointer error event in area 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " ERR_INV_DSC3 ,Invalid descriptor pointer error event in area 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " FILL_LST3 ,End of refill event for the last descriptor in area 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " FILL_DSC3 ,End of refill event for any descriptor in area 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " ERR_LUT_MISS2 ,Unexpected Access to a yet-to-be-refilled area event in area 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " ERR_UPD_DATA2 ,Data register update whilst refilling error event in area 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ERR_UPD_CTRL2 ,Control register update whilst refilling error event in area 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " ERR_UPD_AREA2 ,Area register update whilst refilling error event in area 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ERR_INV_DATA2 ,Invalid entry-table pointer error event in area 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ERR_INV_DSC2 ,Invalid descriptor pointer error event in area 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " FILL_LST2 ,End of refill event for the last descriptor in area 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " FILL_DSC2 ,End of refill event for any descriptor in area 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " ERR_LUT_MISS1 ,Unexpected Access to a yet-to-be-refilled area event in area 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " FILL_LST1 ,End of refill event for the last descriptor in area 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " FILL_DSC1 ,End of refill event for any descriptor in area 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ERR_LUT_MISS0 ,Unexpected Access to a yet-to-be-refilled area event in area 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " FILL_LST0 ,End of refill event for the last descriptor in area 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " FILL_DSC0 ,End of refill event for any descriptor in area 0" "No interrupt,Interrupt"
|
|
group.long 0x4a0++0x3
|
|
line.long 0x00 "DMM_PAT_IRQENABLE_SET,PDMM PAT Raw Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " ERR_LUT_MISS3 ,Unexpected Access to a yet-to-be-refilled area event in area 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ERR_UPD_DATA3 ,Data register update whilst refilling error event in area 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ERR_UPD_CTRL3 ,Control register update whilst refilling error event in area 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ERR_UPD_AREA3 ,Area register update whilst refilling error event in area 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ERR_INV_DATA3 ,Invalid entry-table pointer error event in area 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ERR_INV_DSC3 ,Invalid descriptor pointer error event in area 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " FILL_LST3 ,End of refill event for the last descriptor in area 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FILL_DSC3 ,End of refill event for any descriptor in area 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ERR_LUT_MISS2 ,Unexpected Access to a yet-to-be-refilled area event in area 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ERR_UPD_DATA2 ,Data register update whilst refilling error event in area 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ERR_UPD_CTRL2 ,Control register update whilst refilling error event in area 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ERR_UPD_AREA2 ,Area register update whilst refilling error event in area 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERR_INV_DATA2 ,Invalid entry-table pointer error event in area 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ERR_INV_DSC2 ,Invalid descriptor pointer error event in area 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " FILL_LST2 ,End of refill event for the last descriptor in area 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " FILL_DSC2 ,End of refill event for any descriptor in area 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERR_LUT_MISS1 ,Unexpected Access to a yet-to-be-refilled area event in area 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FILL_LST1 ,End of refill event for the last descriptor in area 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILL_DSC1 ,End of refill event for any descriptor in area 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERR_LUT_MISS0 ,Unexpected Access to a yet-to-be-refilled area event in area 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FILL_LST0 ,End of refill event for the last descriptor in area 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILL_DSC0 ,End of refill event for any descriptor in area 0" "Disabled,Enabled"
|
|
group.long 0x4b0++0x3
|
|
line.long 0x00 "DMM_PAT_IRQENABLE_CLR,PDMM PAT Interrupt Disable Register"
|
|
eventfld.long 0x00 31. " ERR_LUT_MISS3 ,Unexpected Access to a yet-to-be-refilled area event in area 3" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " ERR_UPD_DATA3 ,Data register update whilst refilling error event in area 3" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " ERR_UPD_CTRL3 ,Control register update whilst refilling error event in area 3" "Disabled,Enabled"
|
|
eventfld.long 0x00 28. " ERR_UPD_AREA3 ,Area register update whilst refilling error event in area 3" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 27. " ERR_INV_DATA3 ,Invalid entry-table pointer error event in area 3" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " ERR_INV_DSC3 ,Invalid descriptor pointer error event in area 3" "Disabled,Enabled"
|
|
eventfld.long 0x00 25. " FILL_LST3 ,End of refill event for the last descriptor in area 3" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " FILL_DSC3 ,End of refill event for any descriptor in area 3" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 23. " ERR_LUT_MISS2 ,Unexpected Access to a yet-to-be-refilled area event in area 2" "Disabled,Enabled"
|
|
eventfld.long 0x00 22. " ERR_UPD_DATA2 ,Data register update whilst refilling error event in area 2" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " ERR_UPD_CTRL2 ,Control register update whilst refilling error event in area 2" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " ERR_UPD_AREA2 ,Area register update whilst refilling error event in area 2" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ERR_INV_DATA2 ,Invalid entry-table pointer error event in area 2" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " ERR_INV_DSC2 ,Invalid descriptor pointer error event in area 2" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " FILL_LST2 ,End of refill event for the last descriptor in area 2" "Disabled,Enabled"
|
|
eventfld.long 0x00 16. " FILL_DSC2 ,End of refill event for any descriptor in area 2" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 15. " ERR_LUT_MISS1 ,Unexpected Access to a yet-to-be-refilled area event in area 1" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 1" "Disabled,Enabled"
|
|
eventfld.long 0x00 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 1" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 1" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 1" "Disabled,Enabled"
|
|
eventfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 1" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " FILL_LST1 ,End of refill event for the last descriptor in area 1" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " FILL_DSC1 ,End of refill event for any descriptor in area 1" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ERR_LUT_MISS0 ,Unexpected Access to a yet-to-be-refilled area event in area 0" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 0" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 0" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 0" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 0" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 0" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " FILL_LST0 ,End of refill event for the last descriptor in area 0" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " FILL_DSC0 ,End of refill event for any descriptor in area 0" "Disabled,Enabled"
|
|
width 23.
|
|
rgroup.long 0x4c0++0xf
|
|
line.long 0x0 "DMM_PAT_STATUS[0],DMM PAT Status 0 Register"
|
|
bitfld.long 0x0 10.--15. " ERROR ,Error occurred in engine 0" "No error,Invalid descriptor,Invalid data pointer,Reserved,Unexpected area register update,Reserved,Reserved,Reserved,Unexpected control register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected data register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected access to a yet-to-be-refilled location,?..."
|
|
textline " "
|
|
hexmask.long.word 0x0 16.--24. 1. " CNT ,Counter of remaining lines to re-load for engine 0"
|
|
bitfld.long 0x0 7. " BYPASSED ,Engine 0 bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x0 3. " DONE ,Area reloading finished for engine 0" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RUN ,Area currently reloading for engine 0" "Not reloading,Reloading"
|
|
bitfld.long 0x0 1. " VALID ,Valid area description for engine 0" "Invalid,Valid"
|
|
bitfld.long 0x0 0. " READY ,Area registers ready for engine 0" "Not ready,Ready"
|
|
line.long 0x4 "DMM_PAT_STATUS[1],DMM PAT Status 1 Register"
|
|
bitfld.long 0x4 10.--15. " ERROR ,Error occurred in engine 1" "No error,Invalid descriptor,Invalid data pointer,Reserved,Unexpected area register update,Reserved,Reserved,Reserved,Unexpected control register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected data register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected access to a yet-to-be-refilled location,?..."
|
|
textline " "
|
|
hexmask.long.word 0x4 16.--24. 1. " CNT ,Counter of remaining lines to re-load for engine 1"
|
|
bitfld.long 0x4 7. " BYPASSED ,Engine 1 bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x4 3. " DONE ,Area reloading finished for engine 1" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x4 2. " RUN ,Area currently reloading for engine 1" "Not reloading,Reloading"
|
|
bitfld.long 0x4 1. " VALID ,Valid area description for engine 1" "Invalid,Valid"
|
|
bitfld.long 0x4 0. " READY ,Area registers ready for engine 1" "Not ready,Ready"
|
|
line.long 0x8 "DMM_PAT_STATUS[2],DMM PAT Status 2 Register"
|
|
bitfld.long 0x8 10.--15. " ERROR ,Error occurred in engine 2" "No error,Invalid descriptor,Invalid data pointer,Reserved,Unexpected area register update,Reserved,Reserved,Reserved,Unexpected control register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected data register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected access to a yet-to-be-refilled location,?..."
|
|
textline " "
|
|
hexmask.long.word 0x8 16.--24. 1. " CNT ,Counter of remaining lines to re-load for engine 2"
|
|
bitfld.long 0x8 7. " BYPASSED ,Engine 2 bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x8 3. " DONE ,Area reloading finished for engine 2" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x8 2. " RUN ,Area currently reloading for engine 2" "Not reloading,Reloading"
|
|
bitfld.long 0x8 1. " VALID ,Valid area description for engine 2" "Invalid,Valid"
|
|
bitfld.long 0x8 0. " READY ,Area registers ready for engine 2" "Not ready,Ready"
|
|
line.long 0xC "DMM_PAT_STATUS[3],DMM PAT Status 3 Register"
|
|
bitfld.long 0xC 10.--15. " ERROR ,Error occurred in engine 3" "No error,Invalid descriptor,Invalid data pointer,Reserved,Unexpected area register update,Reserved,Reserved,Reserved,Unexpected control register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected data register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected access to a yet-to-be-refilled location,?..."
|
|
textline " "
|
|
hexmask.long.word 0xC 16.--24. 1. " CNT ,Counter of remaining lines to re-load for engine 3"
|
|
bitfld.long 0xC 7. " BYPASSED ,Engine 3 bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0xC 3. " DONE ,Area reloading finished for engine 3" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0xC 2. " RUN ,Area currently reloading for engine 3" "Not reloading,Reloading"
|
|
bitfld.long 0xC 1. " VALID ,Valid area description for engine 3" "Invalid,Valid"
|
|
bitfld.long 0xC 0. " READY ,Area registers ready for engine 3" "Not ready,Ready"
|
|
width 23.
|
|
group.long 0x500++0x3f
|
|
line.long 0x0 "DMM_PAT_DESCR[0],DMM PAT Descriptor 0 Register"
|
|
hexmask.long 0x0 4.--31. 0x10 " ADDR ,Physical address of the next table refill descriptor"
|
|
line.long (0x0+0x4) "DMM_PAT_AREA[0],DMM PAT Area Geometry 0 Register"
|
|
hexmask.long.byte (0x0+0x4) 24.--30. 1. " Y1 ,Y-coordinate of the bottom right corner of the PAT area"
|
|
hexmask.long.byte (0x0+0x4) 16.--23. 1. " X1 ,X-coordinate of the bottom right corner of the PAT area"
|
|
hexmask.long.byte (0x0+0x4) 8.--14. 1. " Y0 ,Y-coordinate of the top left corner of the PAT area "
|
|
hexmask.long.byte (0x0+0x4) 0.--7. 1. " X0 ,X-coordinate of the top left corner of the PAT area"
|
|
line.long (0x0+0x8) "DMM_PAT_CTRL[0],DMM PAT Control 0 Register"
|
|
bitfld.long (0x0+0x8) 28.--31. " INITIATOR ,DMM PAT initiator for synchronisation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long (0x0+0x8) 16. " SYNC ,DMM PAT table reload synchronisation" "Not synchronised,Synchronised"
|
|
bitfld.long (0x0+0x8) 8.--9. " LUT_ID ,PAT LUT index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long (0x0+0x8) 4.--6. " DIRECTION ,Direction of this PAT table refill" "0,1,2,3,4,5,6,7"
|
|
bitfld.long (0x0+0x8) 0. " START ,Start PAT table refill" "Not started,Started"
|
|
line.long (0x0+0xc) "DMM_PAT_DATA[0],DMM PAT Area Entry Data 0 Register"
|
|
hexmask.long (0x0+0xc) 4.--31. 0x10 " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode"
|
|
line.long 0x10 "DMM_PAT_DESCR[1],DMM PAT Descriptor 1 Register"
|
|
hexmask.long 0x10 4.--31. 0x10 " ADDR ,Physical address of the next table refill descriptor"
|
|
line.long (0x10+0x4) "DMM_PAT_AREA[1],DMM PAT Area Geometry 1 Register"
|
|
hexmask.long.byte (0x10+0x4) 24.--30. 1. " Y1 ,Y-coordinate of the bottom right corner of the PAT area"
|
|
hexmask.long.byte (0x10+0x4) 16.--23. 1. " X1 ,X-coordinate of the bottom right corner of the PAT area"
|
|
hexmask.long.byte (0x10+0x4) 8.--14. 1. " Y0 ,Y-coordinate of the top left corner of the PAT area "
|
|
hexmask.long.byte (0x10+0x4) 0.--7. 1. " X0 ,X-coordinate of the top left corner of the PAT area"
|
|
line.long (0x10+0x8) "DMM_PAT_CTRL[1],DMM PAT Control 1 Register"
|
|
bitfld.long (0x10+0x8) 28.--31. " INITIATOR ,DMM PAT initiator for synchronisation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long (0x10+0x8) 16. " SYNC ,DMM PAT table reload synchronisation" "Not synchronised,Synchronised"
|
|
bitfld.long (0x10+0x8) 8.--9. " LUT_ID ,PAT LUT index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long (0x10+0x8) 4.--6. " DIRECTION ,Direction of this PAT table refill" "0,1,2,3,4,5,6,7"
|
|
bitfld.long (0x10+0x8) 0. " START ,Start PAT table refill" "Not started,Started"
|
|
line.long (0x10+0xc) "DMM_PAT_DATA[1],DMM PAT Area Entry Data 1 Register"
|
|
hexmask.long (0x10+0xc) 4.--31. 0x10 " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode"
|
|
line.long 0x20 "DMM_PAT_DESCR[2],DMM PAT Descriptor 2 Register"
|
|
hexmask.long 0x20 4.--31. 0x10 " ADDR ,Physical address of the next table refill descriptor"
|
|
line.long (0x20+0x4) "DMM_PAT_AREA[2],DMM PAT Area Geometry 2 Register"
|
|
hexmask.long.byte (0x20+0x4) 24.--30. 1. " Y1 ,Y-coordinate of the bottom right corner of the PAT area"
|
|
hexmask.long.byte (0x20+0x4) 16.--23. 1. " X1 ,X-coordinate of the bottom right corner of the PAT area"
|
|
hexmask.long.byte (0x20+0x4) 8.--14. 1. " Y0 ,Y-coordinate of the top left corner of the PAT area "
|
|
hexmask.long.byte (0x20+0x4) 0.--7. 1. " X0 ,X-coordinate of the top left corner of the PAT area"
|
|
line.long (0x20+0x8) "DMM_PAT_CTRL[2],DMM PAT Control 2 Register"
|
|
bitfld.long (0x20+0x8) 28.--31. " INITIATOR ,DMM PAT initiator for synchronisation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long (0x20+0x8) 16. " SYNC ,DMM PAT table reload synchronisation" "Not synchronised,Synchronised"
|
|
bitfld.long (0x20+0x8) 8.--9. " LUT_ID ,PAT LUT index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long (0x20+0x8) 4.--6. " DIRECTION ,Direction of this PAT table refill" "0,1,2,3,4,5,6,7"
|
|
bitfld.long (0x20+0x8) 0. " START ,Start PAT table refill" "Not started,Started"
|
|
line.long (0x20+0xc) "DMM_PAT_DATA[2],DMM PAT Area Entry Data 2 Register"
|
|
hexmask.long (0x20+0xc) 4.--31. 0x10 " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode"
|
|
line.long 0x30 "DMM_PAT_DESCR[3],DMM PAT Descriptor 3 Register"
|
|
hexmask.long 0x30 4.--31. 0x10 " ADDR ,Physical address of the next table refill descriptor"
|
|
line.long (0x30+0x4) "DMM_PAT_AREA[3],DMM PAT Area Geometry 3 Register"
|
|
hexmask.long.byte (0x30+0x4) 24.--30. 1. " Y1 ,Y-coordinate of the bottom right corner of the PAT area"
|
|
hexmask.long.byte (0x30+0x4) 16.--23. 1. " X1 ,X-coordinate of the bottom right corner of the PAT area"
|
|
hexmask.long.byte (0x30+0x4) 8.--14. 1. " Y0 ,Y-coordinate of the top left corner of the PAT area "
|
|
hexmask.long.byte (0x30+0x4) 0.--7. 1. " X0 ,X-coordinate of the top left corner of the PAT area"
|
|
line.long (0x30+0x8) "DMM_PAT_CTRL[3],DMM PAT Control 3 Register"
|
|
bitfld.long (0x30+0x8) 28.--31. " INITIATOR ,DMM PAT initiator for synchronisation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long (0x30+0x8) 16. " SYNC ,DMM PAT table reload synchronisation" "Not synchronised,Synchronised"
|
|
bitfld.long (0x30+0x8) 8.--9. " LUT_ID ,PAT LUT index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long (0x30+0x8) 4.--6. " DIRECTION ,Direction of this PAT table refill" "0,1,2,3,4,5,6,7"
|
|
bitfld.long (0x30+0x8) 0. " START ,Start PAT table refill" "Not started,Started"
|
|
line.long (0x30+0xc) "DMM_PAT_DATA[3],DMM PAT Area Entry Data 3 Register"
|
|
hexmask.long (0x30+0xc) 4.--31. 0x10 " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode"
|
|
width 23.
|
|
group.long 0x620++0x7
|
|
line.long 0x0 "DMM_PEG_PRIO[0],DMM PEG Priority 0 Register"
|
|
bitfld.long 0x0 31. " W7 ,Write-enable for P7 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 28.--30. " P7 ,Priority for initiator 8.0+7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 27. " W6 ,Write-enable for P6 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 24.--26. " P6 ,Priority for initiator 8.0+6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 23. " W5 ,Write-enable for P5 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 20.--22. " P5 ,Priority for initiator 8.0+5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 19. " W4 ,Write-enable for P4 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--18. " P4 ,Priority for initiator 8.0+4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 15. " W3 ,Write-enable for P3 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 12.--14. " P3 ,Priority for initiator 8.0+3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. " W2 ,Write-enable for P2 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 8.--10. " P2 ,Priority for initiator 8.0+2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 7. " W1 ,Write-enable for P1 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 4.--6. " P1 ,Priority for initiator 8.0+1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. " W0 ,Write-enable for P0 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " P0 ,Priority for initiator 8.0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DMM_PEG_PRIO[1],DMM PEG Priority 1 Register"
|
|
bitfld.long 0x4 31. " W7 ,Write-enable for P7 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 28.--30. " P7 ,Priority for initiator 8.1+7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 27. " W6 ,Write-enable for P6 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 24.--26. " P6 ,Priority for initiator 8.1+6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 23. " W5 ,Write-enable for P5 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 20.--22. " P5 ,Priority for initiator 8.1+5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 19. " W4 ,Write-enable for P4 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 16.--18. " P4 ,Priority for initiator 8.1+4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 15. " W3 ,Write-enable for P3 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 12.--14. " P3 ,Priority for initiator 8.1+3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. " W2 ,Write-enable for P2 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 8.--10. " P2 ,Priority for initiator 8.1+2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. " W1 ,Write-enable for P1 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 4.--6. " P1 ,Priority for initiator 8.1+1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. " W0 ,Write-enable for P0 bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " P0 ,Priority for initiator 8.1" "0,1,2,3,4,5,6,7"
|
|
group.long 0x640++0x3
|
|
line.long 0x00 "DMM_PEG_PRIO_PAT,DMM PEG Priority register for PAT"
|
|
bitfld.long 0x00 3. " W_PAT ,Write-enable for P_PAT bit-field" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " P_PAT ,Priority for PAT engine" "0,1,2,3,4,5,6,7"
|
|
width 11.
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AM387*"))
|
|
tree "DDR2/3/mDDR Memory Controller"
|
|
tree "DDR0"
|
|
base ad:0x4c000000
|
|
width 14.
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "SDRSTAT,SDRAM Status Register"
|
|
bitfld.long 0x00 31. " BE ,Big/Little Endian Definition" "Little,Big"
|
|
bitfld.long 0x00 30. " DUAL_CLK_MODE ,Dual Clock mode" "Async,Sync"
|
|
bitfld.long 0x00 29. " FAST_INIT ,Initialization mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RDLVLGATETO ,Read DQS Gate Training Timeout" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " RDLVLTO ,Read Data Eye Training Timeout" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " WRLVLTO ,Write Leveling Timeout" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PHYRDY ,DDR2 memory controller DLL ready" "Not ready,Ready"
|
|
if (((d.l(ad:0x4c000000+0x8))&0xE0000000)==0x20000000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SDRCR,SDRAM Bank Configuration Register"
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,LPDDR1,DDR2,DDR3,?..."
|
|
bitfld.long 0x00 27.--28. " IBANK_POS ,Internal Bank position selection" "0,1,2,3"
|
|
bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL Select" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SDRAM_DRIVE ,SDRAM Drive strength" "Full,1/2,1/4,1/8"
|
|
bitfld.long 0x00 14.--15. " NARROW_MODE ,Data Bus Width" "32 bits,16 bits,?..."
|
|
bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size Selection" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,?..."
|
|
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 bank,2 banks,4 banks,8 banks,?..."
|
|
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0 only,CS0/CS1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 words,512 words,1024 words,2048 words,?..."
|
|
elif (((d.l(ad:0x4c000000+0x8))&0xE0000000)==0x40000000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SDRCR,SDRAM Bank Configuration Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,Reserved,DDR2,DDR3,?..."
|
|
else
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,LPDDR1,DDR2,DDR3,?..."
|
|
endif
|
|
bitfld.long 0x00 27.--28. " IBANK_POS ,Internal Bank position selection" "0,1,2,3"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 & DDR3 termination resistor value" "Disabled,75 Ohm,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 & DDR3 termination resistor value" "Disabled,75 Ohm,150 Ohm,50 Ohm,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " DDR2_DDQS ,DDR2 Differential DQS Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL Select" "Yes,No"
|
|
bitfld.long 0x00 18.--19. " SDRAM_DRIVE ,SDRAM Drive strength" "RZQ/6,RZQ/67,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NARROW_MODE ,Data Bus Width" "32 bits,16 bits,?..."
|
|
bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size Selection" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 bank,2 banks,4 banks,8 banks,?..."
|
|
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0,CS0/CS1"
|
|
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 words,512 words,1024 words,2048 words,?..."
|
|
elif (((d.l(ad:0x4c000000+0x8))&0xE0000000)==0x60000000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SDRCR,SDRAM Bank Configuration Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,Reserved,DDR2,DDR3,?..."
|
|
else
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,LPDDR1,DDR2,DDR3,?..."
|
|
endif
|
|
bitfld.long 0x00 27.--28. " IBANK_POS ,Internal Bank position selection" "0,1,2,3"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 & DDR3 termination resistor value" "Disabled,RZQ/4,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 & DDR3 termination resistor value" "Disabled,RZQ/4,RZQ/2,RZQ/6,RZQ/12,RZQ/8,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " DDR3_DDQS ,DDR3 Differential DQS Enable" "Reserved,Enabled"
|
|
bitfld.long 0x00 21.--22. " DYN_ODT ,DDR3 Dynamic ODT" "OFF,RZQ/4,RZQ/2,?..."
|
|
bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL Select" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CWL ,DDR3 CAS Write Latency" "5,6,7,8"
|
|
bitfld.long 0x00 14.--15. " NARROW_MODE ,Data Bus Width" "32 bits,16 bits,?..."
|
|
bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,5,Reserved,6,Reserved,7,Reserved,8,Reserved,9,Reserved,10,Reserved,11,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size Selection" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,?..."
|
|
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 bank,2 banks,4 banks,8 banks,?..."
|
|
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0,CS0/CS1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 words,512 words,1024 words,2048 words,?..."
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SDRCR,SDRAM Bank Configuration Register"
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,LPDDR1,DDR2,DDR3,?..."
|
|
bitfld.long 0x00 27.--28. " IBANK_POS ,Internal Bank position selection" "0,1,2,3"
|
|
bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL Select" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CWL ,DDR3 CAS Write Latency" "5,6,7,8"
|
|
bitfld.long 0x00 14.--15. " NARROW_MODE ,Data Bus Width" "32 bits,16 bits,?..."
|
|
bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size Selection" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 bank,2 banks,4 banks,8 banks,?..."
|
|
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0,CS0/CS1"
|
|
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 words,512 words,1024 words,2048 words,?..."
|
|
endif
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "SDRCR2,SDRAM Configuration Register 2"
|
|
bitfld.long 0x00 27. " EBANK_POS ,External Bank Position" "Lower OCP address,Higher OCP address"
|
|
if (((d.l(ad:0x4c000000+0x8))&0xE0000000)==0x20000000)
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRRCR,SDRAM Refresh Control Register"
|
|
bitfld.long 0x00 31. " INITREF_DIS ,Initialization and Refresh Disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SRT ,DDR2 and DDR3 Self Refresh Temparature Range" "Normal,Extended"
|
|
bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " PASR ,Partial Array Self Refresh" "Full,1/2,1/4,Reserved,Reserved,1/8,1/16,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE ,Refresh rate"
|
|
elif (((d.l(ad:0x4c000000+0x8))&0xE0000000)==(0x40000000||0x60000000))
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRRCR,SDRAM Refresh Control Register"
|
|
bitfld.long 0x00 31. " INITREF_DIS ,Initialization and Refresh Disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SRT ,DDR2 and DDR3 Self Refresh Temparature Range" "Normal,Extended"
|
|
bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 24.--26. " PASR ,Partial Array Self Refresh" "Full,1/2,1/4,1/8,3/4,1/2,1/4,1/8"
|
|
else
|
|
bitfld.long 0x00 24.--26. " PASR ,Partial Array Self Refresh" "Reserved,Full,1/2,1/4,1/8,Full,1/2,1/4"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE ,Refresh rate"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRRCR,SDRAM Refresh Control Register"
|
|
bitfld.long 0x00 31. " INITREF_DIS ,Initialization and Refresh Disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SRT ,DDR2 and DDR3 Self Refresh Temparature Range" "Normal,Extended"
|
|
bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE ,Refresh rate"
|
|
endif
|
|
group.long 0x14++0x1b
|
|
line.long 0x00 "SDRRCSR,SDRAM Refresh Control Shadow Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE_SHDW ,Shadow field for refresh rate in SDRRCR"
|
|
line.long 0x04 "SDRTIM1,SDRAM Timing 1 Register"
|
|
bitfld.long 0x04 25.--28. " T_RP ,Mimimum number of DDR[X]_CLK cycles from a precharge command to a refresh or activate command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 21.--24. " T_RCD ,Mimimum number of DDR[X]_CLK cycles from an activate command to read or write command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 17.--20. " T_WR ,Minimum number of DDR[X]_CLK cycles from the last write transfer to a pre-charge command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--16. " T_RAS ,Mimimum number of DDR[X]_CLK cycles from an active command to a pre-charge command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 6.--11. " T_RC ,Mimimum number of DDR[X]_CLK cycles from an active command to an active command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 3.--5. " T_RRD ,Mimimum number of DDR[X]_CLK cycles from an activate command to an activate command in a different bank minus 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " T_WTR ,Minimum number of DDR[X]_CLK cycles from the last write to a read command minus 1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "SDRTIM1SR,SDRAM Timing 1 Shadow Register"
|
|
bitfld.long 0x08 25.--28. " T_RP_SHDW ,Shadow field for T_RP in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 21.--24. " T_RCD_SHDW ,Shadow field for T_RCD in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 17.--20. " T_WR_SHDW ,Shadow field for T_WR in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 12.--16. " T_RAS_SHDW ,Shadow field for T_RAS in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 6.--11. " T_RC_SHDW ,Shadow field for T_RC in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 3.--5. " T_RRD_SHDW ,Shadow field for T_RRD in SDRTIMR1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " T_WTR_SHDW ,Shadow field for T_WTR in SDRTIMR1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0c "SDRTIM2,SDRAM Timing 2 Register"
|
|
bitfld.long 0x0c 28.--30. " T_XP ,Minimum number of DDR[X]_CLK cycles from power down exit to any other command except read command minus 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x0c 25.--27. " T_ODT ,Minimum number of DDR[X]_CLK cycles from ODT enable to write data driven for DDR2 and DDR3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x0c 16.--24. 1. " T_XSNR ,Minimum number of DDR[X]_CLK cycles from a self-refresh exit to any other command except a read command minus 1"
|
|
textline " "
|
|
hexmask.long.word 0x0c 6.--15. 1. " T_XSRD ,Minimum number of DDR[X]_CLK cycles from a self-refresh exit to a read command minus 1"
|
|
bitfld.long 0x0c 3.--5. " T_RTP ,Minimum number of DDR[X]_CLK cycles from a last read command to a precharge command minus 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 0.--2. " T_CKE ,Minimum number of DDR[X]_CLK cycles between transitions on the DDR[X]_CKE[X] pin minus 1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "SDRTIM2SR,SDRAM Timing 2 Shadow Register"
|
|
bitfld.long 0x10 28.--30. " T_XP_SHDW ,Shadow field for T_XP in SDRTIMR2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x10 25.--27. " T_ODT_SHDW ,Shadow field for T_ODT in SDRTIMR2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x10 16.--24. 1. " T_XSNR_SHDW ,Shadow field for T_XSNR in SDRTIMR2"
|
|
textline " "
|
|
hexmask.long.word 0x10 6.--15. 1. " T_XSRD_SHDW ,Shadow field for T_XSRD in SDRTIMR2"
|
|
bitfld.long 0x10 3.--5. " T_RTP_SHDW ,Shadow field for T_RTP in SDRTIMR2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. " T_CKE_SHDW ,Shadow field for T_CKE in SDRTIMR2" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "SDRTIM3,SDRAM Timing 3 Register"
|
|
bitfld.long 0x14 28.--31. " T_PDLL_UL ,Minimum number of DDR[X]_CLK cycles for PHY DLL to unlock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " T_CSTA ,Mimimum number of DDR[X]_CLK cycles between write-to-write or read-to-read data phases to different chip selects minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 15.--20. " T_ZQCS ,Mimimum number of DDR[X]_CLK cycles for a ZQCS command minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.word 0x14 4.--12. 1. " T_RFC ,Mimimum number of DDR[X]_CLK cycles from Refresh or Load Mode to Refresh or Activate minus one"
|
|
bitfld.long 0x14 0.--3. " T_RAS_MAX ,Maximum number of refresh rate intervals from Active to Precharge command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "SDRTIM3SR,SDRAM Timing 3 Shadow Register"
|
|
bitfld.long 0x18 28.--31. " T_PDLL_UL_SHDW ,Shadow field for T_PDLL_UL in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " T_CSTA_SHDW ,Shadow field for T_CSTA in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 15.--20. " T_ZQCS_SHDW ,Shadow field for T_ZQCS in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.word 0x18 4.--12. 1. " T_RFC_SHDW ,Shadow field for T_RFC in SDRTIMR3"
|
|
bitfld.long 0x18 0.--3. " T_RAS_MAX_SHDW ,Shadow field for T_RAS_MAX in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "PMCR,Power Management Control Register"
|
|
bitfld.long 0x00 12.--15. " PD_TIM ,Power Management timer for Power Down" "Immediately,After 16 cycles,After 32 cycles,After 64 cycles,After 128 cycles,After 256 cycles,After 512 cycles,After 1024 cycles,After 2048 cycles,After 4096 cycles,After 8192 cycles,After 16384 cycles,After 32768 cycles,After 65536 cycles,After 131072 cycles,After 262144 cycles"
|
|
bitfld.long 0x00 11. " DPD_DEN ,Deep Power Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " LP_MODE ,Automatic Power Management Enable" "Disabled,CLK stop mode,Self-Refresh mode,Disabled,Power down mode,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SR_TIM ,Power Management timer for Self Refresh" "Immediately,After 16 clk's,After 32 clk's,After 64 clk's,After 128 clk's,After 256 clk's,After 512 clk's,After 1024 clk's,After 2048 clk's,After 4096 clk's,After 8192 clk's,After 16384 clk's,After 32768 clk's,After 65536 clk's,After 131072 clk's,After 262144 clk's"
|
|
bitfld.long 0x00 0.--3. " CS_TIM ,Power Management timer for Clock Stop" "Immediately,After 16 clk's,After 32 clk's,After 64 clk's,After 128 clk's,After 256 clk's,After 512 clk's,After 1024 clk's,After 2048 clk's,After 4096 clk's,After 8192 clk's,After 16384 clk's,After 32768 clk's,After 65536 clk's,After 131072 clk's,After 262144 clk's"
|
|
line.long 0x04 "PMCSR,Power Management Control Shadow Register"
|
|
bitfld.long 0x04 12.--15. " PD_TIM_SHDW ,Shadow field for PD_TIM in PMCR" "Immediately,After 16 cycles,After 32 cycles,After 64 cycles,After 128 cycles,After 256 cycles,After 512 cycles,After 1024 cycles,After 2048 cycles,After 4096 cycles,After 8192 cycles,After 16384 cycles,After 32768 cycles,After 65536 cycles,After 131072 cycles,After 262144 cycles"
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|
bitfld.long 0x04 4.--7. " SR_TIM_SHDW ,Shadow field for SR_TIM in PMCR" "Immediately,After 16 clk's,After 32 clk's,After 64 clk's,After 128 clk's,After 256 clk's,After 512 clk's,After 1024 clk's,After 2048 clk's,After 4096 clk's,After 8192 clk's,After 16384 clk's,After 32768 clk's,After 65536 clk's,After 131072 clk's,After 262144 clk's"
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|
bitfld.long 0x04 0.--3. " CS_TIM_SHDW ,Shadow field for CS_TIM in PMCR" "Immediately,After 16 clk's,After 32 clk's,After 64 clk's,After 128 clk's,After 256 clk's,After 512 clk's,After 1024 clk's,After 2048 clk's,After 4096 clk's,After 8192 clk's,After 16384 clk's,After 32768 clk's,After 65536 clk's,After 131072 clk's,After 262144 clk's"
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|
group.long 0x54++0x03
|
|
line.long 0x00 "PBBPR,Peripheral Bus Burst Priority Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " COS_COUNT_1 ,Priority Raise Counter for class of service 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " COS_COUNT_2 ,Priority Raise Counter for class of service 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PR_OLD_COUNT ,Priority Raise Old Counter"
|
|
sif (cpuis("DRA62*"))
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x00 "PERF_CNT_1,Performance Counter 1 Register"
|
|
line.long 0x04 "PERF_CNT_2,Performance Counter 2 Register"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "PERF_CNT_CFG,Performance Counter Config Register"
|
|
bitfld.long 0x00 31. " CNTR2_MCONNID_EN ,MConnID filter enable for Performance Counter 2 register" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " CNTR2_CFG ,Filter configuration for Performance Counter 2" "SDRAM accesses,SDRAM activates,Reads,Writes,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " CNTR1_MCONNID_EN ,MConnID filter enable for Performance Counter 1 register" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " CNTR1_CFG ,Filter configuration for Performance Counter 1" "SDRAM accesses,SDRAM activates,Reads,Writes,?..."
|
|
line.long 0x04 "PERF_CNT_SEL,Performance Counter Master Region Select Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MCONNID2 ,MConnID for Performance Counter2 register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " MCONNID1 ,MConnID for Performance Counter1 register"
|
|
endif
|
|
group.long 0xa0++0x03
|
|
line.long 0x00 "EOI,End of Interrupt Register"
|
|
bitfld.long 0x00 0. " EOI ,Software End of Interrupt Control" "OCP Interrupt,?..."
|
|
wgroup.long 0xa4++0x03
|
|
line.long 0x00 "SOIRSR,System OCP Interrup RAW Status Register"
|
|
bitfld.long 0x00 0. " ERR_SYS ,Raw status of system OCP interrupt for command or address error" "No effect,High"
|
|
sif (!cpuis("DRA62*"))
|
|
wgroup.long 0xac++0x03
|
|
line.long 0x00 "SOISR,System OCP Interrupt Status Register"
|
|
bitfld.long 0x00 0. " ERR_SYS ,Enable status of system OCP interrupt for SDRAM command or address error" "No effect,Enabled"
|
|
else
|
|
group.long 0xac++0x03
|
|
line.long 0x00 "SOISR,System OCP Interrupt Status Register"
|
|
eventfld.long 0x00 0. " ERR_SYS ,Enable status of system OCP interrupt for SDRAM command or address error" "No effect,Enabled"
|
|
endif
|
|
wgroup.long 0xb4++0x03
|
|
line.long 0x00 "SOIESR,System OCP Interrupt Enable Set Register"
|
|
bitfld.long 0x00 0. " ERRSYSSET ,Enable set for sytem OCP interrupt for SDRAM command or address error" "Disabled,Enabled"
|
|
sif (!cpuis("DRA62*"))
|
|
wgroup.long 0xbc++0x03
|
|
line.long 0x00 "SOIECR,System OCP Interrupt Enable Clear Register"
|
|
bitfld.long 0x00 0. " ERRSYSCLR ,Enable Clear for system OCP interrupt for SDRAM command or address error" "No effect,Clear"
|
|
else
|
|
group.long 0xbc++0x03
|
|
line.long 0x00 "SOIECR,System OCP Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 0. " ERRSYSCLR ,Enable Clear for system OCP interrupt for SDRAM command or address error" "No effect,Clear"
|
|
endif
|
|
group.long 0xc8++0x03
|
|
line.long 0x00 "ZQCR,SDRAM Output Impedance Calibration Configuration Register"
|
|
bitfld.long 0x00 31. " ZQ_CS1EN ,ZQ calibration for CS1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ZQ_CS0EN ,ZQ calibration for CS0" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ZQ_DUALCALEN ,ZQ Dual Calibration Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ZQ_SFEXITEN ,Issuing of ZQCL on Self-Refresh/Active Power-Down/Precharge Power Down Exit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " ZQ_ZQINIT_MULT ,Indicates number of ZQCL intervals that make up a ZQINIT interval minus 1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " ZQ_ZQCL_MULT ,Indicates number of ZQCS intervals that make up a ZQCL interval minus 1" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " ZQ_REFINTERVAL ,Number of refresh periods between ZQCS commands"
|
|
width 19.
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0xd4++0x0b
|
|
line.long 0x00 "RDWR_LVL_RMP_WIN,Read Write Leveling Ramp Window Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " RDWRLVLINC_RMP_WIN ,Incremental leveling ramp window in number of refresh periods"
|
|
line.long 0x04 "RDWR_LVL_RMP_CTRL,Read Write Leveling Ramp Control Register"
|
|
bitfld.long 0x04 31. " RDWRLVL_EN ,Read-Write Leveling enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 24.--30. 1. " RDWRLVLINC_RMP_PRE ,Incremental leveling pre-scalar in number of refresh periods during ramp window"
|
|
hexmask.long.byte 0x04 16.--23. 1. " RDLVLINC_RMP_INT ,Incremental read data eye training interval during ramp window"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " RDLVLGATEINC_RMP_INT ,Incremental read DQS gate training interval during ramp window"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WRLVLINC_RMP_INT ,Incremental write leveling interval during ramp window"
|
|
line.long 0x08 "RWLCR,Read-Write Leveling Control Register"
|
|
bitfld.long 0x08 31. " RDWRLVLFULL_START ,Full leveling trigger" "Not triggered,Triggered"
|
|
hexmask.long.byte 0x08 24.--30. 1. " RDWRLVLINC_PRE ,Incremental leveling pre-scalar in number of refresh periods"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RDLVLINC_INT ,Incremental read data eye training interval"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " RDLVLGATEINC_INT ,Incremental read DQS gate training interval"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WRLVLINC_INT ,Incremental write leveling interval"
|
|
endif
|
|
group.long 0xe4++0x07
|
|
line.long 0x00 "DDRPHYCR,DDR PHY Control Register"
|
|
bitfld.long 0x00 20. " DYN_PWRDN_EN ,Dynamically power down enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RDEYE_LVL_DIS ,Read eye auto-leveling disable" "No,Yes"
|
|
bitfld.long 0x00 17. " GATE_LVL_DIS ,Read gate auto-leveling disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " WR_LVL_DIS ,Write auto-leveling disable" "No,Yes"
|
|
bitfld.long 0x00 15. " PHY_RST ,DDR PHY Reset" "No,Yes"
|
|
bitfld.long 0x00 12.--13. " IDLE_LOCAL_ODT ,ODT powered down" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RD_LOCAL_ODT ,Read ODT Termination" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " READ_LATENCY ,Latency for read data from DDR SDRAM in number of 1x cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DDRPHYCSR,DDR PHY Control Shadow Register"
|
|
bitfld.long 0x04 20. " DYN_PWRDN_EN ,Shadow field for DYN_PWRDN_EN in DDRPHYCR" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " RDEYE_LVL_DIS ,Shadow field for RDEYE_LVL_DIS in DDR" "No,Yes"
|
|
bitfld.long 0x04 17. " GATE_LVL_DIS ,Shadow field for GATE_LVL_DIS in DDRPHYCR" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 16. " WR_LVL_DIS ,Shadow field for WR_LVL_DIS in DDRPHYCR" "No,Yes"
|
|
bitfld.long 0x04 15. " PHY_RST ,Shadow field for PHY_RST in DDRPHYCR" "No,Yes"
|
|
bitfld.long 0x04 12.--13. " IDLE_LOCAL_ODT ,Shadow field for IDLE_LOCAL_ODT in DDRPHYCR" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " RD_LOCAL_ODT ,Shadow field for READ_LATENCY in DDRPHYCR" "0,1,2,3"
|
|
bitfld.long 0x04 0.--4. " READ_LATENCY ,Shadow field for READ_LATENCY in DDRPHYCR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "PRI_COS_MAP,Priority to Class of Service Mapping Register"
|
|
bitfld.long 0x00 31. " PRI_COS_MAP_EN ,Priority class of service enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PRI_7_COS ,Class of service for commands with priority of 7" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 12.--13. " PRI_6_COS ,Class of service for commands with priority of 6" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " PRI_5_COS ,Class of service for commands with priority of 5" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 8.--9. " PRI_4_COS ,Class of service for commands with priority of 4" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 6.--7. " PRI_3_COS ,Class of service for commands with priority of 3" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PRI_2_COS ,Class of service for commands with priority of 2" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 2.--3. " PRI_1_COS ,Class of service for commands with priority of 1" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 0.--1. " PRI_0_COS ,Class of service for commands with priority of 0" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
line.long 0x04 "CONNID_COS_1_MAP,Connection ID to Class of Service 1 Mapping Register"
|
|
bitfld.long 0x04 31. " CONNID_COS_1_MAP_EN ,Connection ID to class of service" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 23.--30. 1. " CONNID_1_COS_1 ,Connection ID value 1 for class of service 1"
|
|
bitfld.long 0x04 20.--22. " MSK_1_COS_1 ,Mask for connection ID value 1 for class of service 1" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0,ID bits 3:0,ID bits 4:0,ID bits 5:0,ID bits 6:0"
|
|
textline " "
|
|
hexmask.long.byte 0x04 12.--19. 1. " CONNID_2_COS_1 ,Connection ID value 2 for class of service 1"
|
|
bitfld.long 0x04 10.--11. " MSK_2_COS_1 ,Mask for connection ID value 2 for class of service 1" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0"
|
|
hexmask.long.byte 0x04 2.--9. 1. " CONNID_3_COS_1 ,Connection ID value 3 for class of service 1"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MSK_3_COS_1 ,Mask for connection ID value 3 for class of service 1" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0"
|
|
line.long 0x08 "CONNID_COS_2_MAP,Connection ID to Class of Service 2 Mapping Register"
|
|
bitfld.long 0x08 31. " CONNID_COS_2_MAP_EN ,Connection ID to class of service" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 23.--30. 1. " CONNID_1_COS_2 ,Connection ID value 1 for class of service 2"
|
|
bitfld.long 0x08 20.--22. " MSK_1_COS_2 ,Mask for connection ID value 1 for class of service 2" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0,ID bits 3:0,ID bits 4:0,ID bits 5:0,ID bits 6:0"
|
|
textline " "
|
|
hexmask.long.byte 0x08 12.--19. 1. " CONNID_2_COS_2 ,Connection ID value 2 for class of service 2"
|
|
bitfld.long 0x08 10.--11. " MSK_2_COS_2 ,Mask for connection ID value 2 for class of service 2" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0"
|
|
hexmask.long.byte 0x08 2.--9. 1. " CONNID_3_COS_2 ,Connection ID value 3 for class of service 2"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " MSK_3_COS_2 ,Mask for connection ID value 3 for class of service 2" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "RD_WR_EXEC_THRSH,Read Write Execution Threshold Register"
|
|
bitfld.long 0x00 8.--12. " WR_THRSH ,Write Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " RD_THRSH ,Read Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0xb
|
|
tree.end
|
|
tree "DDR1"
|
|
base ad:0x4d000000
|
|
width 14.
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "SDRSTAT,SDRAM Status Register"
|
|
bitfld.long 0x00 31. " BE ,Big/Little Endian Definition" "Little,Big"
|
|
bitfld.long 0x00 30. " DUAL_CLK_MODE ,Dual Clock mode" "Async,Sync"
|
|
bitfld.long 0x00 29. " FAST_INIT ,Initialization mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RDLVLGATETO ,Read DQS Gate Training Timeout" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " RDLVLTO ,Read Data Eye Training Timeout" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " WRLVLTO ,Write Leveling Timeout" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PHYRDY ,DDR2 memory controller DLL ready" "Not ready,Ready"
|
|
if (((d.l(ad:0x4d000000+0x8))&0xE0000000)==0x20000000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SDRCR,SDRAM Bank Configuration Register"
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,LPDDR1,DDR2,DDR3,?..."
|
|
bitfld.long 0x00 27.--28. " IBANK_POS ,Internal Bank position selection" "0,1,2,3"
|
|
bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL Select" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SDRAM_DRIVE ,SDRAM Drive strength" "Full,1/2,1/4,1/8"
|
|
bitfld.long 0x00 14.--15. " NARROW_MODE ,Data Bus Width" "32 bits,16 bits,?..."
|
|
bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size Selection" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,?..."
|
|
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 bank,2 banks,4 banks,8 banks,?..."
|
|
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0 only,CS0/CS1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 words,512 words,1024 words,2048 words,?..."
|
|
elif (((d.l(ad:0x4d000000+0x8))&0xE0000000)==0x40000000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SDRCR,SDRAM Bank Configuration Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,Reserved,DDR2,DDR3,?..."
|
|
else
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,LPDDR1,DDR2,DDR3,?..."
|
|
endif
|
|
bitfld.long 0x00 27.--28. " IBANK_POS ,Internal Bank position selection" "0,1,2,3"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 & DDR3 termination resistor value" "Disabled,75 Ohm,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 & DDR3 termination resistor value" "Disabled,75 Ohm,150 Ohm,50 Ohm,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " DDR2_DDQS ,DDR2 Differential DQS Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL Select" "Yes,No"
|
|
bitfld.long 0x00 18.--19. " SDRAM_DRIVE ,SDRAM Drive strength" "RZQ/6,RZQ/67,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NARROW_MODE ,Data Bus Width" "32 bits,16 bits,?..."
|
|
bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size Selection" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 bank,2 banks,4 banks,8 banks,?..."
|
|
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0,CS0/CS1"
|
|
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 words,512 words,1024 words,2048 words,?..."
|
|
elif (((d.l(ad:0x4d000000+0x8))&0xE0000000)==0x60000000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SDRCR,SDRAM Bank Configuration Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,Reserved,DDR2,DDR3,?..."
|
|
else
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,LPDDR1,DDR2,DDR3,?..."
|
|
endif
|
|
bitfld.long 0x00 27.--28. " IBANK_POS ,Internal Bank position selection" "0,1,2,3"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 & DDR3 termination resistor value" "Disabled,RZQ/4,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 & DDR3 termination resistor value" "Disabled,RZQ/4,RZQ/2,RZQ/6,RZQ/12,RZQ/8,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " DDR3_DDQS ,DDR3 Differential DQS Enable" "Reserved,Enabled"
|
|
bitfld.long 0x00 21.--22. " DYN_ODT ,DDR3 Dynamic ODT" "OFF,RZQ/4,RZQ/2,?..."
|
|
bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL Select" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CWL ,DDR3 CAS Write Latency" "5,6,7,8"
|
|
bitfld.long 0x00 14.--15. " NARROW_MODE ,Data Bus Width" "32 bits,16 bits,?..."
|
|
bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,5,Reserved,6,Reserved,7,Reserved,8,Reserved,9,Reserved,10,Reserved,11,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size Selection" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,?..."
|
|
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 bank,2 banks,4 banks,8 banks,?..."
|
|
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0,CS0/CS1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 words,512 words,1024 words,2048 words,?..."
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SDRCR,SDRAM Bank Configuration Register"
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,LPDDR1,DDR2,DDR3,?..."
|
|
bitfld.long 0x00 27.--28. " IBANK_POS ,Internal Bank position selection" "0,1,2,3"
|
|
bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL Select" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CWL ,DDR3 CAS Write Latency" "5,6,7,8"
|
|
bitfld.long 0x00 14.--15. " NARROW_MODE ,Data Bus Width" "32 bits,16 bits,?..."
|
|
bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size Selection" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 bank,2 banks,4 banks,8 banks,?..."
|
|
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0,CS0/CS1"
|
|
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 words,512 words,1024 words,2048 words,?..."
|
|
endif
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "SDRCR2,SDRAM Configuration Register 2"
|
|
bitfld.long 0x00 27. " EBANK_POS ,External Bank Position" "Lower OCP address,Higher OCP address"
|
|
if (((d.l(ad:0x4d000000+0x8))&0xE0000000)==0x20000000)
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRRCR,SDRAM Refresh Control Register"
|
|
bitfld.long 0x00 31. " INITREF_DIS ,Initialization and Refresh Disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SRT ,DDR2 and DDR3 Self Refresh Temparature Range" "Normal,Extended"
|
|
bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " PASR ,Partial Array Self Refresh" "Full,1/2,1/4,Reserved,Reserved,1/8,1/16,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE ,Refresh rate"
|
|
elif (((d.l(ad:0x4d000000+0x8))&0xE0000000)==(0x40000000||0x60000000))
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRRCR,SDRAM Refresh Control Register"
|
|
bitfld.long 0x00 31. " INITREF_DIS ,Initialization and Refresh Disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SRT ,DDR2 and DDR3 Self Refresh Temparature Range" "Normal,Extended"
|
|
bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 24.--26. " PASR ,Partial Array Self Refresh" "Full,1/2,1/4,1/8,3/4,1/2,1/4,1/8"
|
|
else
|
|
bitfld.long 0x00 24.--26. " PASR ,Partial Array Self Refresh" "Reserved,Full,1/2,1/4,1/8,Full,1/2,1/4"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE ,Refresh rate"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRRCR,SDRAM Refresh Control Register"
|
|
bitfld.long 0x00 31. " INITREF_DIS ,Initialization and Refresh Disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SRT ,DDR2 and DDR3 Self Refresh Temparature Range" "Normal,Extended"
|
|
bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE ,Refresh rate"
|
|
endif
|
|
group.long 0x14++0x1b
|
|
line.long 0x00 "SDRRCSR,SDRAM Refresh Control Shadow Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE_SHDW ,Shadow field for refresh rate in SDRRCR"
|
|
line.long 0x04 "SDRTIM1,SDRAM Timing 1 Register"
|
|
bitfld.long 0x04 25.--28. " T_RP ,Mimimum number of DDR[X]_CLK cycles from a precharge command to a refresh or activate command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 21.--24. " T_RCD ,Mimimum number of DDR[X]_CLK cycles from an activate command to read or write command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 17.--20. " T_WR ,Minimum number of DDR[X]_CLK cycles from the last write transfer to a pre-charge command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--16. " T_RAS ,Mimimum number of DDR[X]_CLK cycles from an active command to a pre-charge command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 6.--11. " T_RC ,Mimimum number of DDR[X]_CLK cycles from an active command to an active command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 3.--5. " T_RRD ,Mimimum number of DDR[X]_CLK cycles from an activate command to an activate command in a different bank minus 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " T_WTR ,Minimum number of DDR[X]_CLK cycles from the last write to a read command minus 1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "SDRTIM1SR,SDRAM Timing 1 Shadow Register"
|
|
bitfld.long 0x08 25.--28. " T_RP_SHDW ,Shadow field for T_RP in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 21.--24. " T_RCD_SHDW ,Shadow field for T_RCD in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 17.--20. " T_WR_SHDW ,Shadow field for T_WR in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 12.--16. " T_RAS_SHDW ,Shadow field for T_RAS in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 6.--11. " T_RC_SHDW ,Shadow field for T_RC in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 3.--5. " T_RRD_SHDW ,Shadow field for T_RRD in SDRTIMR1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " T_WTR_SHDW ,Shadow field for T_WTR in SDRTIMR1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0c "SDRTIM2,SDRAM Timing 2 Register"
|
|
bitfld.long 0x0c 28.--30. " T_XP ,Minimum number of DDR[X]_CLK cycles from power down exit to any other command except read command minus 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x0c 25.--27. " T_ODT ,Minimum number of DDR[X]_CLK cycles from ODT enable to write data driven for DDR2 and DDR3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x0c 16.--24. 1. " T_XSNR ,Minimum number of DDR[X]_CLK cycles from a self-refresh exit to any other command except a read command minus 1"
|
|
textline " "
|
|
hexmask.long.word 0x0c 6.--15. 1. " T_XSRD ,Minimum number of DDR[X]_CLK cycles from a self-refresh exit to a read command minus 1"
|
|
bitfld.long 0x0c 3.--5. " T_RTP ,Minimum number of DDR[X]_CLK cycles from a last read command to a precharge command minus 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 0.--2. " T_CKE ,Minimum number of DDR[X]_CLK cycles between transitions on the DDR[X]_CKE[X] pin minus 1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "SDRTIM2SR,SDRAM Timing 2 Shadow Register"
|
|
bitfld.long 0x10 28.--30. " T_XP_SHDW ,Shadow field for T_XP in SDRTIMR2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x10 25.--27. " T_ODT_SHDW ,Shadow field for T_ODT in SDRTIMR2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x10 16.--24. 1. " T_XSNR_SHDW ,Shadow field for T_XSNR in SDRTIMR2"
|
|
textline " "
|
|
hexmask.long.word 0x10 6.--15. 1. " T_XSRD_SHDW ,Shadow field for T_XSRD in SDRTIMR2"
|
|
bitfld.long 0x10 3.--5. " T_RTP_SHDW ,Shadow field for T_RTP in SDRTIMR2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. " T_CKE_SHDW ,Shadow field for T_CKE in SDRTIMR2" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "SDRTIM3,SDRAM Timing 3 Register"
|
|
bitfld.long 0x14 28.--31. " T_PDLL_UL ,Minimum number of DDR[X]_CLK cycles for PHY DLL to unlock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " T_CSTA ,Mimimum number of DDR[X]_CLK cycles between write-to-write or read-to-read data phases to different chip selects minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 15.--20. " T_ZQCS ,Mimimum number of DDR[X]_CLK cycles for a ZQCS command minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.word 0x14 4.--12. 1. " T_RFC ,Mimimum number of DDR[X]_CLK cycles from Refresh or Load Mode to Refresh or Activate minus one"
|
|
bitfld.long 0x14 0.--3. " T_RAS_MAX ,Maximum number of refresh rate intervals from Active to Precharge command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "SDRTIM3SR,SDRAM Timing 3 Shadow Register"
|
|
bitfld.long 0x18 28.--31. " T_PDLL_UL_SHDW ,Shadow field for T_PDLL_UL in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " T_CSTA_SHDW ,Shadow field for T_CSTA in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 15.--20. " T_ZQCS_SHDW ,Shadow field for T_ZQCS in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.word 0x18 4.--12. 1. " T_RFC_SHDW ,Shadow field for T_RFC in SDRTIMR3"
|
|
bitfld.long 0x18 0.--3. " T_RAS_MAX_SHDW ,Shadow field for T_RAS_MAX in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "PMCR,Power Management Control Register"
|
|
bitfld.long 0x00 12.--15. " PD_TIM ,Power Management timer for Power Down" "Immediately,After 16 cycles,After 32 cycles,After 64 cycles,After 128 cycles,After 256 cycles,After 512 cycles,After 1024 cycles,After 2048 cycles,After 4096 cycles,After 8192 cycles,After 16384 cycles,After 32768 cycles,After 65536 cycles,After 131072 cycles,After 262144 cycles"
|
|
bitfld.long 0x00 11. " DPD_DEN ,Deep Power Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " LP_MODE ,Automatic Power Management Enable" "Disabled,CLK stop mode,Self-Refresh mode,Disabled,Power down mode,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SR_TIM ,Power Management timer for Self Refresh" "Immediately,After 16 clk's,After 32 clk's,After 64 clk's,After 128 clk's,After 256 clk's,After 512 clk's,After 1024 clk's,After 2048 clk's,After 4096 clk's,After 8192 clk's,After 16384 clk's,After 32768 clk's,After 65536 clk's,After 131072 clk's,After 262144 clk's"
|
|
bitfld.long 0x00 0.--3. " CS_TIM ,Power Management timer for Clock Stop" "Immediately,After 16 clk's,After 32 clk's,After 64 clk's,After 128 clk's,After 256 clk's,After 512 clk's,After 1024 clk's,After 2048 clk's,After 4096 clk's,After 8192 clk's,After 16384 clk's,After 32768 clk's,After 65536 clk's,After 131072 clk's,After 262144 clk's"
|
|
line.long 0x04 "PMCSR,Power Management Control Shadow Register"
|
|
bitfld.long 0x04 12.--15. " PD_TIM_SHDW ,Shadow field for PD_TIM in PMCR" "Immediately,After 16 cycles,After 32 cycles,After 64 cycles,After 128 cycles,After 256 cycles,After 512 cycles,After 1024 cycles,After 2048 cycles,After 4096 cycles,After 8192 cycles,After 16384 cycles,After 32768 cycles,After 65536 cycles,After 131072 cycles,After 262144 cycles"
|
|
bitfld.long 0x04 4.--7. " SR_TIM_SHDW ,Shadow field for SR_TIM in PMCR" "Immediately,After 16 clk's,After 32 clk's,After 64 clk's,After 128 clk's,After 256 clk's,After 512 clk's,After 1024 clk's,After 2048 clk's,After 4096 clk's,After 8192 clk's,After 16384 clk's,After 32768 clk's,After 65536 clk's,After 131072 clk's,After 262144 clk's"
|
|
bitfld.long 0x04 0.--3. " CS_TIM_SHDW ,Shadow field for CS_TIM in PMCR" "Immediately,After 16 clk's,After 32 clk's,After 64 clk's,After 128 clk's,After 256 clk's,After 512 clk's,After 1024 clk's,After 2048 clk's,After 4096 clk's,After 8192 clk's,After 16384 clk's,After 32768 clk's,After 65536 clk's,After 131072 clk's,After 262144 clk's"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PBBPR,Peripheral Bus Burst Priority Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " COS_COUNT_1 ,Priority Raise Counter for class of service 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " COS_COUNT_2 ,Priority Raise Counter for class of service 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PR_OLD_COUNT ,Priority Raise Old Counter"
|
|
sif (cpuis("DRA62*"))
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x00 "PERF_CNT_1,Performance Counter 1 Register"
|
|
line.long 0x04 "PERF_CNT_2,Performance Counter 2 Register"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "PERF_CNT_CFG,Performance Counter Config Register"
|
|
bitfld.long 0x00 31. " CNTR2_MCONNID_EN ,MConnID filter enable for Performance Counter 2 register" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " CNTR2_CFG ,Filter configuration for Performance Counter 2" "SDRAM accesses,SDRAM activates,Reads,Writes,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " CNTR1_MCONNID_EN ,MConnID filter enable for Performance Counter 1 register" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " CNTR1_CFG ,Filter configuration for Performance Counter 1" "SDRAM accesses,SDRAM activates,Reads,Writes,?..."
|
|
line.long 0x04 "PERF_CNT_SEL,Performance Counter Master Region Select Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MCONNID2 ,MConnID for Performance Counter2 register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " MCONNID1 ,MConnID for Performance Counter1 register"
|
|
endif
|
|
group.long 0xa0++0x03
|
|
line.long 0x00 "EOI,End of Interrupt Register"
|
|
bitfld.long 0x00 0. " EOI ,Software End of Interrupt Control" "OCP Interrupt,?..."
|
|
wgroup.long 0xa4++0x03
|
|
line.long 0x00 "SOIRSR,System OCP Interrup RAW Status Register"
|
|
bitfld.long 0x00 0. " ERR_SYS ,Raw status of system OCP interrupt for command or address error" "No effect,High"
|
|
sif (!cpuis("DRA62*"))
|
|
wgroup.long 0xac++0x03
|
|
line.long 0x00 "SOISR,System OCP Interrupt Status Register"
|
|
bitfld.long 0x00 0. " ERR_SYS ,Enable status of system OCP interrupt for SDRAM command or address error" "No effect,Enabled"
|
|
else
|
|
group.long 0xac++0x03
|
|
line.long 0x00 "SOISR,System OCP Interrupt Status Register"
|
|
eventfld.long 0x00 0. " ERR_SYS ,Enable status of system OCP interrupt for SDRAM command or address error" "No effect,Enabled"
|
|
endif
|
|
wgroup.long 0xb4++0x03
|
|
line.long 0x00 "SOIESR,System OCP Interrupt Enable Set Register"
|
|
bitfld.long 0x00 0. " ERRSYSSET ,Enable set for sytem OCP interrupt for SDRAM command or address error" "Disabled,Enabled"
|
|
sif (!cpuis("DRA62*"))
|
|
wgroup.long 0xbc++0x03
|
|
line.long 0x00 "SOIECR,System OCP Interrupt Enable Clear Register"
|
|
bitfld.long 0x00 0. " ERRSYSCLR ,Enable Clear for system OCP interrupt for SDRAM command or address error" "No effect,Clear"
|
|
else
|
|
group.long 0xbc++0x03
|
|
line.long 0x00 "SOIECR,System OCP Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 0. " ERRSYSCLR ,Enable Clear for system OCP interrupt for SDRAM command or address error" "No effect,Clear"
|
|
endif
|
|
group.long 0xc8++0x03
|
|
line.long 0x00 "ZQCR,SDRAM Output Impedance Calibration Configuration Register"
|
|
bitfld.long 0x00 31. " ZQ_CS1EN ,ZQ calibration for CS1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ZQ_CS0EN ,ZQ calibration for CS0" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ZQ_DUALCALEN ,ZQ Dual Calibration Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ZQ_SFEXITEN ,Issuing of ZQCL on Self-Refresh/Active Power-Down/Precharge Power Down Exit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " ZQ_ZQINIT_MULT ,Indicates number of ZQCL intervals that make up a ZQINIT interval minus 1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " ZQ_ZQCL_MULT ,Indicates number of ZQCS intervals that make up a ZQCL interval minus 1" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " ZQ_REFINTERVAL ,Number of refresh periods between ZQCS commands"
|
|
width 19.
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0xd4++0x0b
|
|
line.long 0x00 "RDWR_LVL_RMP_WIN,Read Write Leveling Ramp Window Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " RDWRLVLINC_RMP_WIN ,Incremental leveling ramp window in number of refresh periods"
|
|
line.long 0x04 "RDWR_LVL_RMP_CTRL,Read Write Leveling Ramp Control Register"
|
|
bitfld.long 0x04 31. " RDWRLVL_EN ,Read-Write Leveling enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 24.--30. 1. " RDWRLVLINC_RMP_PRE ,Incremental leveling pre-scalar in number of refresh periods during ramp window"
|
|
hexmask.long.byte 0x04 16.--23. 1. " RDLVLINC_RMP_INT ,Incremental read data eye training interval during ramp window"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " RDLVLGATEINC_RMP_INT ,Incremental read DQS gate training interval during ramp window"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WRLVLINC_RMP_INT ,Incremental write leveling interval during ramp window"
|
|
line.long 0x08 "RWLCR,Read-Write Leveling Control Register"
|
|
bitfld.long 0x08 31. " RDWRLVLFULL_START ,Full leveling trigger" "Not triggered,Triggered"
|
|
hexmask.long.byte 0x08 24.--30. 1. " RDWRLVLINC_PRE ,Incremental leveling pre-scalar in number of refresh periods"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RDLVLINC_INT ,Incremental read data eye training interval"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " RDLVLGATEINC_INT ,Incremental read DQS gate training interval"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WRLVLINC_INT ,Incremental write leveling interval"
|
|
endif
|
|
group.long 0xe4++0x07
|
|
line.long 0x00 "DDRPHYCR,DDR PHY Control Register"
|
|
bitfld.long 0x00 20. " DYN_PWRDN_EN ,Dynamically power down enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RDEYE_LVL_DIS ,Read eye auto-leveling disable" "No,Yes"
|
|
bitfld.long 0x00 17. " GATE_LVL_DIS ,Read gate auto-leveling disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " WR_LVL_DIS ,Write auto-leveling disable" "No,Yes"
|
|
bitfld.long 0x00 15. " PHY_RST ,DDR PHY Reset" "No,Yes"
|
|
bitfld.long 0x00 12.--13. " IDLE_LOCAL_ODT ,ODT powered down" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RD_LOCAL_ODT ,Read ODT Termination" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " READ_LATENCY ,Latency for read data from DDR SDRAM in number of 1x cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DDRPHYCSR,DDR PHY Control Shadow Register"
|
|
bitfld.long 0x04 20. " DYN_PWRDN_EN ,Shadow field for DYN_PWRDN_EN in DDRPHYCR" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " RDEYE_LVL_DIS ,Shadow field for RDEYE_LVL_DIS in DDR" "No,Yes"
|
|
bitfld.long 0x04 17. " GATE_LVL_DIS ,Shadow field for GATE_LVL_DIS in DDRPHYCR" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 16. " WR_LVL_DIS ,Shadow field for WR_LVL_DIS in DDRPHYCR" "No,Yes"
|
|
bitfld.long 0x04 15. " PHY_RST ,Shadow field for PHY_RST in DDRPHYCR" "No,Yes"
|
|
bitfld.long 0x04 12.--13. " IDLE_LOCAL_ODT ,Shadow field for IDLE_LOCAL_ODT in DDRPHYCR" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " RD_LOCAL_ODT ,Shadow field for READ_LATENCY in DDRPHYCR" "0,1,2,3"
|
|
bitfld.long 0x04 0.--4. " READ_LATENCY ,Shadow field for READ_LATENCY in DDRPHYCR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "PRI_COS_MAP,Priority to Class of Service Mapping Register"
|
|
bitfld.long 0x00 31. " PRI_COS_MAP_EN ,Priority class of service enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PRI_7_COS ,Class of service for commands with priority of 7" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 12.--13. " PRI_6_COS ,Class of service for commands with priority of 6" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " PRI_5_COS ,Class of service for commands with priority of 5" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 8.--9. " PRI_4_COS ,Class of service for commands with priority of 4" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 6.--7. " PRI_3_COS ,Class of service for commands with priority of 3" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PRI_2_COS ,Class of service for commands with priority of 2" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 2.--3. " PRI_1_COS ,Class of service for commands with priority of 1" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 0.--1. " PRI_0_COS ,Class of service for commands with priority of 0" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
line.long 0x04 "CONNID_COS_1_MAP,Connection ID to Class of Service 1 Mapping Register"
|
|
bitfld.long 0x04 31. " CONNID_COS_1_MAP_EN ,Connection ID to class of service" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 23.--30. 1. " CONNID_1_COS_1 ,Connection ID value 1 for class of service 1"
|
|
bitfld.long 0x04 20.--22. " MSK_1_COS_1 ,Mask for connection ID value 1 for class of service 1" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0,ID bits 3:0,ID bits 4:0,ID bits 5:0,ID bits 6:0"
|
|
textline " "
|
|
hexmask.long.byte 0x04 12.--19. 1. " CONNID_2_COS_1 ,Connection ID value 2 for class of service 1"
|
|
bitfld.long 0x04 10.--11. " MSK_2_COS_1 ,Mask for connection ID value 2 for class of service 1" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0"
|
|
hexmask.long.byte 0x04 2.--9. 1. " CONNID_3_COS_1 ,Connection ID value 3 for class of service 1"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MSK_3_COS_1 ,Mask for connection ID value 3 for class of service 1" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0"
|
|
line.long 0x08 "CONNID_COS_2_MAP,Connection ID to Class of Service 2 Mapping Register"
|
|
bitfld.long 0x08 31. " CONNID_COS_2_MAP_EN ,Connection ID to class of service" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 23.--30. 1. " CONNID_1_COS_2 ,Connection ID value 1 for class of service 2"
|
|
bitfld.long 0x08 20.--22. " MSK_1_COS_2 ,Mask for connection ID value 1 for class of service 2" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0,ID bits 3:0,ID bits 4:0,ID bits 5:0,ID bits 6:0"
|
|
textline " "
|
|
hexmask.long.byte 0x08 12.--19. 1. " CONNID_2_COS_2 ,Connection ID value 2 for class of service 2"
|
|
bitfld.long 0x08 10.--11. " MSK_2_COS_2 ,Mask for connection ID value 2 for class of service 2" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0"
|
|
hexmask.long.byte 0x08 2.--9. 1. " CONNID_3_COS_2 ,Connection ID value 3 for class of service 2"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " MSK_3_COS_2 ,Mask for connection ID value 3 for class of service 2" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "RD_WR_EXEC_THRSH,Read Write Execution Threshold Register"
|
|
bitfld.long 0x00 8.--12. " WR_THRSH ,Write Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " RD_THRSH ,Read Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0xb
|
|
tree.end
|
|
; tree "DDR PHY Registers"
|
|
; base ad:0x4e000000
|
|
; %include mpu/ddr_phy.ph ad:0x4e000000
|
|
; tree.end
|
|
tree.end
|
|
elif (cpuis("DRA6x?"))
|
|
tree "DDR2/3/mDDR Memory Controller"
|
|
base ad:0x4c000000
|
|
width 14.
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "SDRSTAT,SDRAM Status Register"
|
|
bitfld.long 0x00 31. " BE ,Big/Little Endian Definition" "Little,Big"
|
|
bitfld.long 0x00 30. " DUAL_CLK_MODE ,Dual Clock mode" "Async,Sync"
|
|
bitfld.long 0x00 29. " FAST_INIT ,Initialization mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RDLVLGATETO ,Read DQS Gate Training Timeout" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " RDLVLTO ,Read Data Eye Training Timeout" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " WRLVLTO ,Write Leveling Timeout" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PHYRDY ,DDR2 memory controller DLL ready" "Not ready,Ready"
|
|
if (((d.l(ad:0x4c000000+0x8))&0xE0000000)==0x20000000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SDRCR,SDRAM Bank Configuration Register"
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,LPDDR1,DDR2,DDR3,?..."
|
|
bitfld.long 0x00 27.--28. " IBANK_POS ,Internal Bank position selection" "0,1,2,3"
|
|
bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL Select" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SDRAM_DRIVE ,SDRAM Drive strength" "Full,1/2,1/4,1/8"
|
|
bitfld.long 0x00 14.--15. " NARROW_MODE ,Data Bus Width" "32 bits,16 bits,?..."
|
|
bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size Selection" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,?..."
|
|
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 bank,2 banks,4 banks,8 banks,?..."
|
|
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0 only,CS0/CS1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 words,512 words,1024 words,2048 words,?..."
|
|
elif (((d.l(ad:0x4c000000+0x8))&0xE0000000)==0x40000000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SDRCR,SDRAM Bank Configuration Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,Reserved,DDR2,DDR3,?..."
|
|
else
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,LPDDR1,DDR2,DDR3,?..."
|
|
endif
|
|
bitfld.long 0x00 27.--28. " IBANK_POS ,Internal Bank position selection" "0,1,2,3"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 & DDR3 termination resistor value" "Disabled,75 Ohm,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 & DDR3 termination resistor value" "Disabled,75 Ohm,150 Ohm,50 Ohm,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " DDR2_DDQS ,DDR2 Differential DQS Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL Select" "Yes,No"
|
|
bitfld.long 0x00 18.--19. " SDRAM_DRIVE ,SDRAM Drive strength" "RZQ/6,RZQ/67,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NARROW_MODE ,Data Bus Width" "32 bits,16 bits,?..."
|
|
bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size Selection" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 bank,2 banks,4 banks,8 banks,?..."
|
|
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0,CS0/CS1"
|
|
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 words,512 words,1024 words,2048 words,?..."
|
|
elif (((d.l(ad:0x4c000000+0x8))&0xE0000000)==0x60000000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SDRCR,SDRAM Bank Configuration Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,Reserved,DDR2,DDR3,?..."
|
|
else
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,LPDDR1,DDR2,DDR3,?..."
|
|
endif
|
|
bitfld.long 0x00 27.--28. " IBANK_POS ,Internal Bank position selection" "0,1,2,3"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 & DDR3 termination resistor value" "Disabled,RZQ/4,?..."
|
|
else
|
|
bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 & DDR3 termination resistor value" "Disabled,RZQ/4,RZQ/2,RZQ/6,RZQ/12,RZQ/8,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " DDR3_DDQS ,DDR3 Differential DQS Enable" "Reserved,Enabled"
|
|
bitfld.long 0x00 21.--22. " DYN_ODT ,DDR3 Dynamic ODT" "OFF,RZQ/4,RZQ/2,?..."
|
|
bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL Select" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CWL ,DDR3 CAS Write Latency" "5,6,7,8"
|
|
bitfld.long 0x00 14.--15. " NARROW_MODE ,Data Bus Width" "32 bits,16 bits,?..."
|
|
bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,5,Reserved,6,Reserved,7,Reserved,8,Reserved,9,Reserved,10,Reserved,11,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size Selection" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,?..."
|
|
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 bank,2 banks,4 banks,8 banks,?..."
|
|
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0,CS0/CS1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 words,512 words,1024 words,2048 words,?..."
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SDRCR,SDRAM Bank Configuration Register"
|
|
bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type Selection" "Reserved,LPDDR1,DDR2,DDR3,?..."
|
|
bitfld.long 0x00 27.--28. " IBANK_POS ,Internal Bank position selection" "0,1,2,3"
|
|
bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL Select" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CWL ,DDR3 CAS Write Latency" "5,6,7,8"
|
|
bitfld.long 0x00 14.--15. " NARROW_MODE ,Data Bus Width" "32 bits,16 bits,?..."
|
|
bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size Selection" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 bank,2 banks,4 banks,8 banks,?..."
|
|
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0,CS0/CS1"
|
|
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 words,512 words,1024 words,2048 words,?..."
|
|
endif
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "SDRCR2,SDRAM Configuration Register 2"
|
|
bitfld.long 0x00 27. " EBANK_POS ,External Bank Position" "Lower OCP address,Higher OCP address"
|
|
if (((d.l(ad:0x4c000000+0x8))&0xE0000000)==0x20000000)
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRRCR,SDRAM Refresh Control Register"
|
|
bitfld.long 0x00 31. " INITREF_DIS ,Initialization and Refresh Disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SRT ,DDR2 and DDR3 Self Refresh Temparature Range" "Normal,Extended"
|
|
bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " PASR ,Partial Array Self Refresh" "Full,1/2,1/4,Reserved,Reserved,1/8,1/16,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE ,Refresh rate"
|
|
elif (((d.l(ad:0x4c000000+0x8))&0xE0000000)==(0x40000000||0x60000000))
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRRCR,SDRAM Refresh Control Register"
|
|
bitfld.long 0x00 31. " INITREF_DIS ,Initialization and Refresh Disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SRT ,DDR2 and DDR3 Self Refresh Temparature Range" "Normal,Extended"
|
|
bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 24.--26. " PASR ,Partial Array Self Refresh" "Full,1/2,1/4,1/8,3/4,1/2,1/4,1/8"
|
|
else
|
|
bitfld.long 0x00 24.--26. " PASR ,Partial Array Self Refresh" "Reserved,Full,1/2,1/4,1/8,Full,1/2,1/4"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE ,Refresh rate"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRRCR,SDRAM Refresh Control Register"
|
|
bitfld.long 0x00 31. " INITREF_DIS ,Initialization and Refresh Disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SRT ,DDR2 and DDR3 Self Refresh Temparature Range" "Normal,Extended"
|
|
bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE ,Refresh rate"
|
|
endif
|
|
group.long 0x14++0x1b
|
|
line.long 0x00 "SDRRCSR,SDRAM Refresh Control Shadow Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE_SHDW ,Shadow field for refresh rate in SDRRCR"
|
|
line.long 0x04 "SDRTIM1,SDRAM Timing 1 Register"
|
|
bitfld.long 0x04 25.--28. " T_RP ,Mimimum number of DDR[X]_CLK cycles from a precharge command to a refresh or activate command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 21.--24. " T_RCD ,Mimimum number of DDR[X]_CLK cycles from an activate command to read or write command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 17.--20. " T_WR ,Minimum number of DDR[X]_CLK cycles from the last write transfer to a pre-charge command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--16. " T_RAS ,Mimimum number of DDR[X]_CLK cycles from an active command to a pre-charge command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 6.--11. " T_RC ,Mimimum number of DDR[X]_CLK cycles from an active command to an active command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 3.--5. " T_RRD ,Mimimum number of DDR[X]_CLK cycles from an activate command to an activate command in a different bank minus 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " T_WTR ,Minimum number of DDR[X]_CLK cycles from the last write to a read command minus 1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "SDRTIM1SR,SDRAM Timing 1 Shadow Register"
|
|
bitfld.long 0x08 25.--28. " T_RP_SHDW ,Shadow field for T_RP in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 21.--24. " T_RCD_SHDW ,Shadow field for T_RCD in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 17.--20. " T_WR_SHDW ,Shadow field for T_WR in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 12.--16. " T_RAS_SHDW ,Shadow field for T_RAS in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 6.--11. " T_RC_SHDW ,Shadow field for T_RC in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 3.--5. " T_RRD_SHDW ,Shadow field for T_RRD in SDRTIMR1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " T_WTR_SHDW ,Shadow field for T_WTR in SDRTIMR1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0c "SDRTIM2,SDRAM Timing 2 Register"
|
|
bitfld.long 0x0c 28.--30. " T_XP ,Minimum number of DDR[X]_CLK cycles from power down exit to any other command except read command minus 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x0c 25.--27. " T_ODT ,Minimum number of DDR[X]_CLK cycles from ODT enable to write data driven for DDR2 and DDR3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x0c 16.--24. 1. " T_XSNR ,Minimum number of DDR[X]_CLK cycles from a self-refresh exit to any other command except a read command minus 1"
|
|
textline " "
|
|
hexmask.long.word 0x0c 6.--15. 1. " T_XSRD ,Minimum number of DDR[X]_CLK cycles from a self-refresh exit to a read command minus 1"
|
|
bitfld.long 0x0c 3.--5. " T_RTP ,Minimum number of DDR[X]_CLK cycles from a last read command to a precharge command minus 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 0.--2. " T_CKE ,Minimum number of DDR[X]_CLK cycles between transitions on the DDR[X]_CKE[X] pin minus 1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "SDRTIM2SR,SDRAM Timing 2 Shadow Register"
|
|
bitfld.long 0x10 28.--30. " T_XP_SHDW ,Shadow field for T_XP in SDRTIMR2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (!cpuis("DRA62*"))
|
|
bitfld.long 0x10 25.--27. " T_ODT_SHDW ,Shadow field for T_ODT in SDRTIMR2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x10 16.--24. 1. " T_XSNR_SHDW ,Shadow field for T_XSNR in SDRTIMR2"
|
|
textline " "
|
|
hexmask.long.word 0x10 6.--15. 1. " T_XSRD_SHDW ,Shadow field for T_XSRD in SDRTIMR2"
|
|
bitfld.long 0x10 3.--5. " T_RTP_SHDW ,Shadow field for T_RTP in SDRTIMR2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. " T_CKE_SHDW ,Shadow field for T_CKE in SDRTIMR2" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "SDRTIM3,SDRAM Timing 3 Register"
|
|
bitfld.long 0x14 28.--31. " T_PDLL_UL ,Minimum number of DDR[X]_CLK cycles for PHY DLL to unlock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " T_CSTA ,Mimimum number of DDR[X]_CLK cycles between write-to-write or read-to-read data phases to different chip selects minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 15.--20. " T_ZQCS ,Mimimum number of DDR[X]_CLK cycles for a ZQCS command minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.word 0x14 4.--12. 1. " T_RFC ,Mimimum number of DDR[X]_CLK cycles from Refresh or Load Mode to Refresh or Activate minus one"
|
|
bitfld.long 0x14 0.--3. " T_RAS_MAX ,Maximum number of refresh rate intervals from Active to Precharge command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "SDRTIM3SR,SDRAM Timing 3 Shadow Register"
|
|
bitfld.long 0x18 28.--31. " T_PDLL_UL_SHDW ,Shadow field for T_PDLL_UL in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " T_CSTA_SHDW ,Shadow field for T_CSTA in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 15.--20. " T_ZQCS_SHDW ,Shadow field for T_ZQCS in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.word 0x18 4.--12. 1. " T_RFC_SHDW ,Shadow field for T_RFC in SDRTIMR3"
|
|
bitfld.long 0x18 0.--3. " T_RAS_MAX_SHDW ,Shadow field for T_RAS_MAX in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "PMCR,Power Management Control Register"
|
|
bitfld.long 0x00 12.--15. " PD_TIM ,Power Management timer for Power Down" "Immediately,After 16 cycles,After 32 cycles,After 64 cycles,After 128 cycles,After 256 cycles,After 512 cycles,After 1024 cycles,After 2048 cycles,After 4096 cycles,After 8192 cycles,After 16384 cycles,After 32768 cycles,After 65536 cycles,After 131072 cycles,After 262144 cycles"
|
|
bitfld.long 0x00 11. " DPD_DEN ,Deep Power Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " LP_MODE ,Automatic Power Management Enable" "Disabled,CLK stop mode,Self-Refresh mode,Disabled,Power down mode,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SR_TIM ,Power Management timer for Self Refresh" "Immediately,After 16 clk's,After 32 clk's,After 64 clk's,After 128 clk's,After 256 clk's,After 512 clk's,After 1024 clk's,After 2048 clk's,After 4096 clk's,After 8192 clk's,After 16384 clk's,After 32768 clk's,After 65536 clk's,After 131072 clk's,After 262144 clk's"
|
|
bitfld.long 0x00 0.--3. " CS_TIM ,Power Management timer for Clock Stop" "Immediately,After 16 clk's,After 32 clk's,After 64 clk's,After 128 clk's,After 256 clk's,After 512 clk's,After 1024 clk's,After 2048 clk's,After 4096 clk's,After 8192 clk's,After 16384 clk's,After 32768 clk's,After 65536 clk's,After 131072 clk's,After 262144 clk's"
|
|
line.long 0x04 "PMCSR,Power Management Control Shadow Register"
|
|
bitfld.long 0x04 12.--15. " PD_TIM_SHDW ,Shadow field for PD_TIM in PMCR" "Immediately,After 16 cycles,After 32 cycles,After 64 cycles,After 128 cycles,After 256 cycles,After 512 cycles,After 1024 cycles,After 2048 cycles,After 4096 cycles,After 8192 cycles,After 16384 cycles,After 32768 cycles,After 65536 cycles,After 131072 cycles,After 262144 cycles"
|
|
bitfld.long 0x04 4.--7. " SR_TIM_SHDW ,Shadow field for SR_TIM in PMCR" "Immediately,After 16 clk's,After 32 clk's,After 64 clk's,After 128 clk's,After 256 clk's,After 512 clk's,After 1024 clk's,After 2048 clk's,After 4096 clk's,After 8192 clk's,After 16384 clk's,After 32768 clk's,After 65536 clk's,After 131072 clk's,After 262144 clk's"
|
|
bitfld.long 0x04 0.--3. " CS_TIM_SHDW ,Shadow field for CS_TIM in PMCR" "Immediately,After 16 clk's,After 32 clk's,After 64 clk's,After 128 clk's,After 256 clk's,After 512 clk's,After 1024 clk's,After 2048 clk's,After 4096 clk's,After 8192 clk's,After 16384 clk's,After 32768 clk's,After 65536 clk's,After 131072 clk's,After 262144 clk's"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PBBPR,Peripheral Bus Burst Priority Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " COS_COUNT_1 ,Priority Raise Counter for class of service 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " COS_COUNT_2 ,Priority Raise Counter for class of service 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PR_OLD_COUNT ,Priority Raise Old Counter"
|
|
sif (cpuis("DRA62*"))
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x00 "PERF_CNT_1,Performance Counter 1 Register"
|
|
line.long 0x04 "PERF_CNT_2,Performance Counter 2 Register"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "PERF_CNT_CFG,Performance Counter Config Register"
|
|
bitfld.long 0x00 31. " CNTR2_MCONNID_EN ,MConnID filter enable for Performance Counter 2 register" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " CNTR2_CFG ,Filter configuration for Performance Counter 2" "SDRAM accesses,SDRAM activates,Reads,Writes,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " CNTR1_MCONNID_EN ,MConnID filter enable for Performance Counter 1 register" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " CNTR1_CFG ,Filter configuration for Performance Counter 1" "SDRAM accesses,SDRAM activates,Reads,Writes,?..."
|
|
line.long 0x04 "PERF_CNT_SEL,Performance Counter Master Region Select Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MCONNID2 ,MConnID for Performance Counter2 register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " MCONNID1 ,MConnID for Performance Counter1 register"
|
|
endif
|
|
group.long 0xa0++0x03
|
|
line.long 0x00 "EOI,End of Interrupt Register"
|
|
bitfld.long 0x00 0. " EOI ,Software End of Interrupt Control" "OCP Interrupt,?..."
|
|
wgroup.long 0xa4++0x03
|
|
line.long 0x00 "SOIRSR,System OCP Interrup RAW Status Register"
|
|
bitfld.long 0x00 0. " ERR_SYS ,Raw status of system OCP interrupt for command or address error" "No effect,High"
|
|
sif (!cpuis("DRA62*"))
|
|
wgroup.long 0xac++0x03
|
|
line.long 0x00 "SOISR,System OCP Interrupt Status Register"
|
|
bitfld.long 0x00 0. " ERR_SYS ,Enable status of system OCP interrupt for SDRAM command or address error" "No effect,Enabled"
|
|
else
|
|
group.long 0xac++0x03
|
|
line.long 0x00 "SOISR,System OCP Interrupt Status Register"
|
|
eventfld.long 0x00 0. " ERR_SYS ,Enable status of system OCP interrupt for SDRAM command or address error" "No effect,Enabled"
|
|
endif
|
|
wgroup.long 0xb4++0x03
|
|
line.long 0x00 "SOIESR,System OCP Interrupt Enable Set Register"
|
|
bitfld.long 0x00 0. " ERRSYSSET ,Enable set for sytem OCP interrupt for SDRAM command or address error" "Disabled,Enabled"
|
|
sif (!cpuis("DRA62*"))
|
|
wgroup.long 0xbc++0x03
|
|
line.long 0x00 "SOIECR,System OCP Interrupt Enable Clear Register"
|
|
bitfld.long 0x00 0. " ERRSYSCLR ,Enable Clear for system OCP interrupt for SDRAM command or address error" "No effect,Clear"
|
|
else
|
|
group.long 0xbc++0x03
|
|
line.long 0x00 "SOIECR,System OCP Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 0. " ERRSYSCLR ,Enable Clear for system OCP interrupt for SDRAM command or address error" "No effect,Clear"
|
|
endif
|
|
group.long 0xc8++0x03
|
|
line.long 0x00 "ZQCR,SDRAM Output Impedance Calibration Configuration Register"
|
|
bitfld.long 0x00 31. " ZQ_CS1EN ,ZQ calibration for CS1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ZQ_CS0EN ,ZQ calibration for CS0" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ZQ_DUALCALEN ,ZQ Dual Calibration Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ZQ_SFEXITEN ,Issuing of ZQCL on Self-Refresh/Active Power-Down/Precharge Power Down Exit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " ZQ_ZQINIT_MULT ,Indicates number of ZQCL intervals that make up a ZQINIT interval minus 1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " ZQ_ZQCL_MULT ,Indicates number of ZQCS intervals that make up a ZQCL interval minus 1" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " ZQ_REFINTERVAL ,Number of refresh periods between ZQCS commands"
|
|
width 19.
|
|
sif (!cpuis("DRA62*"))
|
|
group.long 0xd4++0x0b
|
|
line.long 0x00 "RDWR_LVL_RMP_WIN,Read Write Leveling Ramp Window Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " RDWRLVLINC_RMP_WIN ,Incremental leveling ramp window in number of refresh periods"
|
|
line.long 0x04 "RDWR_LVL_RMP_CTRL,Read Write Leveling Ramp Control Register"
|
|
bitfld.long 0x04 31. " RDWRLVL_EN ,Read-Write Leveling enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 24.--30. 1. " RDWRLVLINC_RMP_PRE ,Incremental leveling pre-scalar in number of refresh periods during ramp window"
|
|
hexmask.long.byte 0x04 16.--23. 1. " RDLVLINC_RMP_INT ,Incremental read data eye training interval during ramp window"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " RDLVLGATEINC_RMP_INT ,Incremental read DQS gate training interval during ramp window"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WRLVLINC_RMP_INT ,Incremental write leveling interval during ramp window"
|
|
line.long 0x08 "RWLCR,Read-Write Leveling Control Register"
|
|
bitfld.long 0x08 31. " RDWRLVLFULL_START ,Full leveling trigger" "Not triggered,Triggered"
|
|
hexmask.long.byte 0x08 24.--30. 1. " RDWRLVLINC_PRE ,Incremental leveling pre-scalar in number of refresh periods"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RDLVLINC_INT ,Incremental read data eye training interval"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " RDLVLGATEINC_INT ,Incremental read DQS gate training interval"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WRLVLINC_INT ,Incremental write leveling interval"
|
|
endif
|
|
group.long 0xe4++0x07
|
|
line.long 0x00 "DDRPHYCR,DDR PHY Control Register"
|
|
bitfld.long 0x00 20. " DYN_PWRDN_EN ,Dynamically power down enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RDEYE_LVL_DIS ,Read eye auto-leveling disable" "No,Yes"
|
|
bitfld.long 0x00 17. " GATE_LVL_DIS ,Read gate auto-leveling disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " WR_LVL_DIS ,Write auto-leveling disable" "No,Yes"
|
|
bitfld.long 0x00 15. " PHY_RST ,DDR PHY Reset" "No,Yes"
|
|
bitfld.long 0x00 12.--13. " IDLE_LOCAL_ODT ,ODT powered down" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RD_LOCAL_ODT ,Read ODT Termination" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " READ_LATENCY ,Latency for read data from DDR SDRAM in number of 1x cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DDRPHYCSR,DDR PHY Control Shadow Register"
|
|
bitfld.long 0x04 20. " DYN_PWRDN_EN ,Shadow field for DYN_PWRDN_EN in DDRPHYCR" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " RDEYE_LVL_DIS ,Shadow field for RDEYE_LVL_DIS in DDR" "No,Yes"
|
|
bitfld.long 0x04 17. " GATE_LVL_DIS ,Shadow field for GATE_LVL_DIS in DDRPHYCR" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 16. " WR_LVL_DIS ,Shadow field for WR_LVL_DIS in DDRPHYCR" "No,Yes"
|
|
bitfld.long 0x04 15. " PHY_RST ,Shadow field for PHY_RST in DDRPHYCR" "No,Yes"
|
|
bitfld.long 0x04 12.--13. " IDLE_LOCAL_ODT ,Shadow field for IDLE_LOCAL_ODT in DDRPHYCR" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " RD_LOCAL_ODT ,Shadow field for READ_LATENCY in DDRPHYCR" "0,1,2,3"
|
|
bitfld.long 0x04 0.--4. " READ_LATENCY ,Shadow field for READ_LATENCY in DDRPHYCR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "PRI_COS_MAP,Priority to Class of Service Mapping Register"
|
|
bitfld.long 0x00 31. " PRI_COS_MAP_EN ,Priority class of service enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PRI_7_COS ,Class of service for commands with priority of 7" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 12.--13. " PRI_6_COS ,Class of service for commands with priority of 6" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " PRI_5_COS ,Class of service for commands with priority of 5" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 8.--9. " PRI_4_COS ,Class of service for commands with priority of 4" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 6.--7. " PRI_3_COS ,Class of service for commands with priority of 3" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PRI_2_COS ,Class of service for commands with priority of 2" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 2.--3. " PRI_1_COS ,Class of service for commands with priority of 1" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
bitfld.long 0x00 0.--1. " PRI_0_COS ,Class of service for commands with priority of 0" "Not assigned,Assigned,Assigned,Not Assigned"
|
|
line.long 0x04 "CONNID_COS_1_MAP,Connection ID to Class of Service 1 Mapping Register"
|
|
bitfld.long 0x04 31. " CONNID_COS_1_MAP_EN ,Connection ID to class of service" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 23.--30. 1. " CONNID_1_COS_1 ,Connection ID value 1 for class of service 1"
|
|
bitfld.long 0x04 20.--22. " MSK_1_COS_1 ,Mask for connection ID value 1 for class of service 1" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0,ID bits 3:0,ID bits 4:0,ID bits 5:0,ID bits 6:0"
|
|
textline " "
|
|
hexmask.long.byte 0x04 12.--19. 1. " CONNID_2_COS_1 ,Connection ID value 2 for class of service 1"
|
|
bitfld.long 0x04 10.--11. " MSK_2_COS_1 ,Mask for connection ID value 2 for class of service 1" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0"
|
|
hexmask.long.byte 0x04 2.--9. 1. " CONNID_3_COS_1 ,Connection ID value 3 for class of service 1"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MSK_3_COS_1 ,Mask for connection ID value 3 for class of service 1" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0"
|
|
line.long 0x08 "CONNID_COS_2_MAP,Connection ID to Class of Service 2 Mapping Register"
|
|
bitfld.long 0x08 31. " CONNID_COS_2_MAP_EN ,Connection ID to class of service" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 23.--30. 1. " CONNID_1_COS_2 ,Connection ID value 1 for class of service 2"
|
|
bitfld.long 0x08 20.--22. " MSK_1_COS_2 ,Mask for connection ID value 1 for class of service 2" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0,ID bits 3:0,ID bits 4:0,ID bits 5:0,ID bits 6:0"
|
|
textline " "
|
|
hexmask.long.byte 0x08 12.--19. 1. " CONNID_2_COS_2 ,Connection ID value 2 for class of service 2"
|
|
bitfld.long 0x08 10.--11. " MSK_2_COS_2 ,Mask for connection ID value 2 for class of service 2" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0"
|
|
hexmask.long.byte 0x08 2.--9. 1. " CONNID_3_COS_2 ,Connection ID value 3 for class of service 2"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " MSK_3_COS_2 ,Mask for connection ID value 3 for class of service 2" "Disabled,ID bit 0,ID bits 1:0,ID bits 2:0"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "RD_WR_EXEC_THRSH,Read Write Execution Threshold Register"
|
|
bitfld.long 0x00 8.--12. " WR_THRSH ,Write Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " RD_THRSH ,Read Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.open "Ethernet"
|
|
sif (cpuis("AM387*"))
|
|
tree "CPSW_3G"
|
|
base ad:0x4a100000
|
|
width 19.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CPSW_ID_VER,CPSW ID Version Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " IDENT ,Identification value"
|
|
bitfld.long 0x00 11.--15. " RTL_VER ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MAJOR_VER ,Major version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MINOR_VER ,Minor version"
|
|
width 19.
|
|
group.long 0x04++0x27
|
|
line.long 0x00 "CPSW_CONTROL,Switch Control Register"
|
|
bitfld.long 0x00 5. " P2_PASS_PRI_TAGGED ,Port 2 Pass Priority Tagged" "Not processed,Processed"
|
|
bitfld.long 0x00 4. " P1_PASS_PRI_TAGGED ,Port 1 Pass Priority Tagged" "Not processed,Processed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0_PASS_PRI_TAGGED ,Port 0 Pass Priority Tagged" "Not processed,Processed"
|
|
bitfld.long 0x00 2. " RX_VLAN_ENCAP ,Port 2 VLAN Encapsulation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " VLAN_AWARE ,VLAN Aware Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FIFO_LOOPBACK ,FIFO Loopback Mode" "Disabled,Enabled"
|
|
line.long 0x04 "CPSW_SOFT_RESET,Soft Reset Register"
|
|
bitfld.long 0x04 0. " SOFT_RESET ,Software reset" "No effect,Reset"
|
|
line.long 0x08 "CPSW_STAT_PORT_EN,Statistics Port Enable Register"
|
|
bitfld.long 0x08 2. " P2_STAT_EN ,Port 2 Statistics Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " P1_STAT_EN ,Port 1 (GMII 1 and Port 1 FIFO) Statistics Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " P0_STAT_EN ,Port 0 (GMII 0 and Port 0 FIFO) Statistics Enable" "Disabled,Enabled"
|
|
line.long 0x0c "CPSW_PTYPE,Transmit Priority Type Register"
|
|
bitfld.long 0x0c 21. " P2_PRI3_SHAPE_EN ,Port 2 Queue Priority 3 Transmit Shape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " P2_PRI2_SHAPE_EN ,Port 2 Queue Priority 2 Transmit Shape Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " P2_PRI1_SHAPE_EN ,Port 2 Queue Priority 1 Transmit Shape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " P1_PRI3_SHAPE_EN ,Port 1 Queue Priority 3 Transmit Shape Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " P1_PRI2_SHAPE_EN ,Port 1 Queue Priority 2 Transmit Shape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " P1_PRI1_SHAPE_EN ,Port 1 Queue Priority 1 Transmit Shape Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " P2_PTYPE_ESC ,Port 2 priority type escalate" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " P1_PTYPE_ESC ,Port 1 priority type escalate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 8. " P0_PTYPE_ESC ,Port 0 priority type escalate" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0.--4. " ESC_PRI_LD_VAL ,Escalate priority load value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "CPSW_SOFT_IDLE,Software Idle Register"
|
|
bitfld.long 0x10 0. " SOFT_IDLE ,Software Idle" "Not idle,Idle"
|
|
line.long 0x14 "CPSW_THRU_RATE,Throughput Rate Register"
|
|
bitfld.long 0x14 12.--15. " SL_RX_THRU_RATE ,CPGMAC_SL Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " CPDMA_THRU_RATE ,CPDMA Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "CPSW_GAP_THRESH,CPGMAC_SL Short Gap Threshold Register"
|
|
bitfld.long 0x18 0.--4. " GAP_THRESH ,CPGMAC_SL Short Gap Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1c "CPSW_TX_START_WDS,Transmit Start Words Register"
|
|
hexmask.long.word 0x1c 0.--10. 1. " TX_START_WDS ,FIFO Packet Transmit (egress) Start Words"
|
|
line.long 0x20 "CPSW_FLOW_CONTROL,CPSW Flow Control Register"
|
|
bitfld.long 0x20 2. " P2_FLOW_EN ,Port 2 Receive flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 1. " P1_FLOW_EN ,Port 1 Receive flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0. " P0_FLOW_EN ,Port 0 Receive flow control enable" "Disabled,Enabled"
|
|
line.long 0x24 "P0_MAX_BLKS,CPSW Port 0 Maximum FIFO Blocks Register"
|
|
bitfld.long 0x24 4.--8. " P0_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x24 0.--3. " P0_RX_MAX_BLKS ,Receive FIFO Maximum Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x2c++0x03
|
|
line.long 0x00 "P0_BLK_CNT,Port 0 FIFO Block Usage Count Register"
|
|
bitfld.long 0x00 4.--8. " P0_TX_BLK_COUNT ,Port 0 transmit block count usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " P0_RX_BLK_COUNT ,Port 0 receive block count usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P0_TX_IN_CTL,CPSW Port 0 Transmit FIFO Control Register"
|
|
bitfld.long 0x00 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select" "Normal,Dual MAC,Rate Limit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TX_BLKS_REM ,Transmit FIFO Input Blocks to subtract in dual mac mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue"
|
|
line.long 0x04 "P0_PORT_VLAN,Port 0 VLAN Register"
|
|
bitfld.long 0x04 13.--15. " PORT_PRI ,Port VLAN priority" "Lowest,1,2,3,4,5,6,Highest"
|
|
bitfld.long 0x04 12. " PORT_CFI ,Port CFI bit" "Low,High"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--11. 1. " PORT_VID ,Port VLAN ID"
|
|
line.long 0x08 "P0_TX_PRI_MAP,Port 0 TX Header Priority to Switch Priority Mapping Register"
|
|
bitfld.long 0x08 28.--29. " PRI7 ,Priority 7" "0,1,2,3"
|
|
bitfld.long 0x08 24.--25. " PRI6 ,Priority 6" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 20.--21. " PRI5 ,Priority 5" "0,1,2,3"
|
|
bitfld.long 0x08 16.--17. " PRI4 ,Priority 4" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " PRI3 ,Priority 3" "0,1,2,3"
|
|
bitfld.long 0x08 8.--9. " PRI2 ,Priority 2" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " PRI1 ,Priority 1" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " PRI0 ,Priority 0" "0,1,2,3"
|
|
line.long 0x0c "CPDMA_TX_PRI_MAP,CPDMA TX (Port 0 Rx) Packet Priority to Header Priority Mapping Register"
|
|
bitfld.long 0x0c 28.--30. " PRI7 ,Priority 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 24.--26. " PRI6 ,Priority 6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " PRI5 ,Priority 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 16.--18. " PRI4 ,Priority 4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 12.--14. " PRI3 ,Priority 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 8.--10. " PRI2 ,Priority 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--6. " PRI1 ,Priority 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 0.--2. " PRI0 ,Priority 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "CPDMA_RX_CH_MAP,CPDMA RX (Port 0 TX) Switch Priority to DMA Channel Mapping Register"
|
|
bitfld.long 0x10 28.--30. " P2_PRI3 ,Port 2 Priority 3 packets go to this CPDMA RX Channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 24.--26. " P2_PRI2 ,Port 2 Priority 2 packets go to this CPDMA RX Channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 20.--22. " P2_PRI1 ,Port 2 Priority 1 packets go to this CPDMA RX Channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 16.--18. " P2_PRI4 ,Port 2 Priority 0 packets go to this CPDMA RX Channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 12.--14. " P1_PRI3 ,Port 1 Priority 3 packets go to this CPDMA RX Channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 8.--10. " P1_PRI2 ,Port 1 Priority 2 packets go to this CPDMA RX Channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 4.--6. " P1_PRI1 ,Port 1 Priority 1 packets go to this CPDMA RX Channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. " P1_PRI0 ,Port 1 Priority 0 packets go to this CPDMA RX Channel" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P1_MAX_BLKS,CPSW Port 1 Maximum FIFO Blocks Register"
|
|
bitfld.long 0x00 4.--8. " P1_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " P1_RX_MAX_BLKS ,Receive FIFO Maximum Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "P1_BLK_CNT,Port 1 FIFO Block Usage Count Register"
|
|
bitfld.long 0x00 4.--8. " P1_TX_BLK_COUNT ,Port 1 transmit block count usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " P1_RX_BLK_COUNT ,Port 1 receive block count usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x58++0x23
|
|
line.long 0x00 "P1_TX_IN_CTL,CPSW Port 1 Transmit FIFO Control Register"
|
|
bitfld.long 0x00 24.--27. " HOST_BLKS_REM ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select" "Normal,Reserved,Rate Limit,?..."
|
|
bitfld.long 0x00 12.--15. " TX_BLKS_REM ,Transmit FIFO Input Blocks to subtract in dual mac mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue"
|
|
line.long 0x04 "P1_PORT_VLAN,Port 1 VLAN Register"
|
|
bitfld.long 0x04 13.--15. " PORT_PRI ,Port VLAN priority" "Lowest,1,2,3,4,5,6,Highest"
|
|
bitfld.long 0x04 12. " PORT_CFI ,Port CFI bit" "Low,High"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--11. 1. " PORT_VID ,Port VLAN ID"
|
|
line.long 0x08 "P1_TX_PRI_MAP,Port 1 TX Header Priority to Switch Priority Mapping Register"
|
|
bitfld.long 0x08 28.--29. " PRI7 ,Priority 7" "0,1,2,3"
|
|
bitfld.long 0x08 24.--25. " PRI6 ,Priority 6" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 20.--21. " PRI5 ,Priority 5" "0,1,2,3"
|
|
bitfld.long 0x08 16.--17. " PRI4 ,Priority 4" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " PRI3 ,Priority 3" "0,1,2,3"
|
|
bitfld.long 0x08 8.--9. " PRI2 ,Priority 2" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " PRI1 ,Priority 1" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " PRI0 ,Priority 0" "0,1,2,3"
|
|
width 19.
|
|
line.long 0x0c "P1_TS_CTL,CPSW_3G Port 1 Time Sync Control Register"
|
|
bitfld.long 0x0c 31. " P1_TX_MSG_TYPE_EN[15] ,Port 1 Time Sync Message Type 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " P1_TX_MSG_TYPE_EN[14] ,Port 1 Time Sync Message Type 14 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " P1_TX_MSG_TYPE_EN[13] ,Port 1 Time Sync Message Type 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " P1_TX_MSG_TYPE_EN[12] ,Port 1 Time Sync Message Type 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " P1_TX_MSG_TYPE_EN[11] ,Port 1 Time Sync Message Type 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " P1_TX_MSG_TYPE_EN[10] ,Port 1 Time Sync Message Type 10 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " P1_TX_MSG_TYPE_EN[9] ,Port 1 Time Sync Message Type 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " P1_TX_MSG_TYPE_EN[8] ,Port 1 Time Sync Message Type 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " P1_TX_MSG_TYPE_EN[7] ,Port 1 Time Sync Message Type 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " P1_TX_MSG_TYPE_EN[6] ,Port 1 Time Sync Message Type 6 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " P1_TX_MSG_TYPE_EN[5] ,Port 1 Time Sync Message Type 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " P1_TX_MSG_TYPE_EN[4] ,Port 1 Time Sync Message Type 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " P1_TX_MSG_TYPE_EN[3] ,Port 1 Time Sync Message Type 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " P1_TX_MSG_TYPE_EN[2] ,Port 1 Time Sync Message Type 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " P1_TX_MSG_TYPE_EN[1] ,Port 1 Time Sync Message Type 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " P1_TX_MSG_TYPE_EN[0] ,Port 1 Time Sync Message Type 0 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " P1_TS_TX_VLAN_LTYPE2_EN ,Port 1 Time Sync Transmit VLAN LTYPE 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " P1_TS_TX_VLAN_LTYPE1_EN ,Port 1 Time Sync Transmit VLAN LTYPE 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " P1_TS_TX_EN ,Port 1 Time Sync Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " P1_TS_RX_VLAN_LTYPE2_EN ,Port 1 Time Sync Receive VLAN LTYPE 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " P1_TS_RX_VLAN_LTYPE1_EN ,Port 1 Time Sync Receive VLAN LTYPE 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " P1_TS_RX_EN ,Port 1 Time Sync Receive Enable" "Disabled,Enabled"
|
|
line.long 0x10 "P1_TS_SEQ_LTYPE,CPSW_3G Port 1 Time Sync Sequence ID and LTYPE Register"
|
|
bitfld.long 0x10 16.--21. " P1_TS_SEQ_ID_OFFSET ,Port 1 Time Sync Sequence ID Offset" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
hexmask.long.word 0x10 0.--15. 1. " P1_TS_LTYPE ,Port 1 Time Sync LTYPE"
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line.long 0x14 "P1_TS_VLAN,CPSW_3G Port 1 Time Sync VLAN2 and VLAN2 Register"
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hexmask.long.word 0x14 16.--31. 1. " P1_TS_VLAN_LTYPE2 ,Port 1 Time Sync VLAN LTYPE2"
|
|
hexmask.long.word 0x14 0.--15. 1. " P1_TS_VLAN_LTYPE1 ,Port 1 Time Sync VLAN LTYPE1"
|
|
line.long 0x18 "SL1_SA_LO,CPSW CPGMAC_SL1 Source Address Low Register"
|
|
hexmask.long.byte 0x18 8.--15. 1. " MACSRCADDR(7:0) ,Source Address Lower 8 bits (byte 0)"
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|
hexmask.long.byte 0x18 0.--7. 1. " MACSRCADDR(15:8) ,Source Address bits 15:8 (byte 1)"
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line.long 0x1c "SL1_SA_HI,CPSW CPGMAC_SL1 Source Address High Register"
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hexmask.long.byte 0x1c 24.--31. 1. " MACSRCADDR(23:16) ,Source Address bits 23:16 (byte 2)"
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hexmask.long.byte 0x1c 16.--23. 1. " MACSRCADDR(31:24) ,Source Address bits 31:24 (byte 3)"
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|
textline " "
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hexmask.long.byte 0x1c 8.--15. 1. " MACSRCADDR(39:32) ,Source Address bits 39:32 (byte 4)"
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hexmask.long.byte 0x1c 0.--7. 1. " MACSRCADDR(47:40) ,Source Address bits 47:40 (byte 5)"
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line.long 0x20 "P1_SEND_PERCENT,CPSW Port 1 Transmit Queue Send Percentages Register"
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hexmask.long.byte 0x20 16.--22. 1. " PRI3_SEND_PERCENT ,Priority 3 Transmit Percentage"
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|
hexmask.long.byte 0x20 8.--14. 1. " PRI2_SEND_PERCENT ,Priority 2 Transmit Percentage"
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|
textline " "
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hexmask.long.byte 0x20 0.--6. 1. " PRI1_SEND_PERCENT ,Priority 1 Transmit Percentage"
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|
group.long 0x90++0x03
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|
line.long 0x00 "P2_MAX_BLKS,CPSW Port 2 Maximum FIFO Blocks Register"
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bitfld.long 0x00 4.--8. " P2_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--3. " P2_RX_MAX_BLKS ,Receive FIFO Maximum Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x94++0x03
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line.long 0x00 "P2_BLK_CNT,Port 2 FIFO Block Usage Count Register"
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bitfld.long 0x00 4.--8. " P1_TX_BLK_COUNT ,Port 2 transmit block count usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--3. " P1_RX_BLK_COUNT ,Port 2 receive block count usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x98++0x23
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line.long 0x00 "P2_TX_IN_CTL,CPSW Port 2 Transmit FIFO Control Register"
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bitfld.long 0x00 24.--27. " HOST_BLKS_REM ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select" "Normal,Reserved,Rate Limit,?..."
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bitfld.long 0x00 12.--15. " TX_BLKS_REM ,Transmit FIFO Input Blocks to subtract in dual mac mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue"
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line.long 0x04 "P2_PORT_VLAN,Port 2 VLAN Register"
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bitfld.long 0x04 13.--15. " PORT_PRI ,Port VLAN priority" "Lowest,1,2,3,4,5,6,Highest"
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|
bitfld.long 0x04 12. " PORT_CFI ,Port CFI bit" "Low,High"
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textline " "
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hexmask.long.word 0x04 0.--11. 1. " PORT_VID ,Port VLAN ID"
|
|
line.long 0x08 "P2_TX_PRI_MAP,Port 2 TX Header Priority to Switch Priority Mapping Register"
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bitfld.long 0x08 28.--29. " PRI7 ,Priority 7" "0,1,2,3"
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bitfld.long 0x08 24.--25. " PRI6 ,Priority 6" "0,1,2,3"
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textline " "
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bitfld.long 0x08 20.--21. " PRI5 ,Priority 5" "0,1,2,3"
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bitfld.long 0x08 16.--17. " PRI4 ,Priority 4" "0,1,2,3"
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textline " "
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bitfld.long 0x08 12.--13. " PRI3 ,Priority 3" "0,1,2,3"
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bitfld.long 0x08 8.--9. " PRI2 ,Priority 2" "0,1,2,3"
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textline " "
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bitfld.long 0x08 4.--5. " PRI1 ,Priority 1" "0,1,2,3"
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bitfld.long 0x08 0.--1. " PRI0 ,Priority 0" "0,1,2,3"
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line.long 0x0c "P2_TS_CTL,CPSW_3G Port 2 Time Sync Control Register"
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bitfld.long 0x0c 31. " P2_TX_MSG_TYPE_EN[15] ,Port 2 Time Sync Message Type 15 Enable" "Disabled,Enabled"
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bitfld.long 0x0c 30. " P2_TX_MSG_TYPE_EN[14] ,Port 2 Time Sync Message Type 14 Enable" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x0c 29. " P2_TX_MSG_TYPE_EN[13] ,Port 2 Time Sync Message Type 13 Enable" "Disabled,Enabled"
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bitfld.long 0x0c 28. " P2_TX_MSG_TYPE_EN[12] ,Port 2 Time Sync Message Type 12 Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0c 27. " P2_TX_MSG_TYPE_EN[11] ,Port 2 Time Sync Message Type 11 Enable" "Disabled,Enabled"
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|
bitfld.long 0x0c 26. " P2_TX_MSG_TYPE_EN[10] ,Port 2 Time Sync Message Type 10 Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0c 25. " P2_TX_MSG_TYPE_EN[9] ,Port 2 Time Sync Message Type 9 Enable" "Disabled,Enabled"
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|
bitfld.long 0x0c 24. " P2_TX_MSG_TYPE_EN[8] ,Port 2 Time Sync Message Type 8 Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0c 23. " P2_TX_MSG_TYPE_EN[7] ,Port 2 Time Sync Message Type 7 Enable" "Disabled,Enabled"
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bitfld.long 0x0c 22. " P2_TX_MSG_TYPE_EN[6] ,Port 2 Time Sync Message Type 6 Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0c 21. " P2_TX_MSG_TYPE_EN[5] ,Port 2 Time Sync Message Type 5 Enable" "Disabled,Enabled"
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bitfld.long 0x0c 20. " P2_TX_MSG_TYPE_EN[4] ,Port 2 Time Sync Message Type 4 Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0c 19. " P2_TX_MSG_TYPE_EN[3] ,Port 2 Time Sync Message Type 3 Enable" "Disabled,Enabled"
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bitfld.long 0x0c 18. " P2_TX_MSG_TYPE_EN[2] ,Port 2 Time Sync Message Type 2 Enable" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x0c 17. " P2_TX_MSG_TYPE_EN[1] ,Port 2 Time Sync Message Type 1 Enable" "Disabled,Enabled"
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bitfld.long 0x0c 16. " P2_TX_MSG_TYPE_EN[0] ,Port 2 Time Sync Message Type 0 Enable" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x0c 6. " P2_TS_TX_VLAN_LTYPE2_EN ,Port 2 Time Sync Transmit VLAN LTYPE 2 enable" "Disabled,Enabled"
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bitfld.long 0x0c 5. " P2_TS_TX_VLAN_LTYPE1_EN ,Port 2 Time Sync Transmit VLAN LTYPE 1 enable" "Disabled,Enabled"
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textline " "
|
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bitfld.long 0x0c 4. " P2_TS_TX_EN ,Port 2 Time Sync Transmit Enable" "Disabled,Enabled"
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|
bitfld.long 0x0c 2. " P2_TS_RX_VLAN_LTYPE2_EN ,Port 2 Time Sync Receive VLAN LTYPE 2 enable" "Disabled,Enabled"
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textline " "
|
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bitfld.long 0x0c 1. " P2_TS_RX_VLAN_LTYPE1_EN ,Port 2 Time Sync Receive VLAN LTYPE 1 enable" "Disabled,Enabled"
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bitfld.long 0x0c 0. " P2_TS_RX_EN ,Port 2 Time Sync Receive Enable" "Disabled,Enabled"
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line.long 0x10 "P2_TS_SEQ_LTYPE,CPSW_3G Port 2 Time Sync Sequence ID and LTYPE Register"
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bitfld.long 0x10 16.--21. " P2_TS_SEQ_ID_OFFSET ,Port 2 Time Sync Sequence ID Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x10 0.--15. 1. " P2_TS_LTYPE ,Port 2 Time Sync LTYPE"
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line.long 0x14 "P2_TS_VLAN,CPSW_3G Port 2 Time Sync VLAN2 and VLAN2 Register"
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hexmask.long.word 0x14 16.--31. 1. " P2_TS_VLAN_LTYPE2 ,Port 2 Time Sync VLAN LTYPE2"
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hexmask.long.word 0x14 0.--15. 1. " P2_TS_VLAN_LTYPE1 ,Port 2 Time Sync VLAN LTYPE1"
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line.long 0x18 "SL2_SA_LO,CPSW CPGMAC_SL2 Source Address Low Register"
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hexmask.long.byte 0x18 8.--15. 1. " MACSRCADDR(7:0) ,Source Address Lower 8 bits (byte 0)"
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hexmask.long.byte 0x18 0.--7. 1. " MACSRCADDR(15:8) ,Source Address bits 15:8 (byte 1)"
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line.long 0x1c "SL2_SA_HI,CPSW CPGMAC_SL2 Source Address High Register"
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hexmask.long.byte 0x1c 24.--31. 1. " MACSRCADDR(23:16) ,Source Address bits 23:16 (byte 2)"
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hexmask.long.byte 0x1c 16.--23. 1. " MACSRCADDR(31:24) ,Source Address bits 31:24 (byte 3)"
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textline " "
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hexmask.long.byte 0x1c 8.--15. 1. " MACSRCADDR(39:32) ,Source Address bits 39:32 (byte 4)"
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hexmask.long.byte 0x1c 0.--7. 1. " MACSRCADDR(47:40) ,Source Address bits 47:40 (byte 5)"
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line.long 0x20 "P2_SEND_PERCENT,CPSW Port 2 Transmit Queue Send Percentages Register"
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hexmask.long.byte 0x20 16.--22. 1. " PRI3_SEND_PERCENT ,Priority 3 Transmit Percentage"
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hexmask.long.byte 0x20 8.--14. 1. " PRI2_SEND_PERCENT ,Priority 2 Transmit Percentage"
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textline " "
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hexmask.long.byte 0x20 0.--6. 1. " PRI1_SEND_PERCENT ,Priority 1 Transmit Percentage"
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width 19.
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rgroup.long 0x100++0x03 "CPDMA Registers"
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line.long 0x00 "TX_IDVER,TX Identification and Version Register"
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hexmask.long.word 0x00 16.--31. 1. " TX_IDENT ,TX Identification value"
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hexmask.long.byte 0x00 8.--15. 1. " TX_MAJOR_VER ,TX major version value"
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hexmask.long.byte 0x00 0.--7. 1. " TX_MINOR_VER ,TX minor version value"
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group.long 0x104++0x07
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line.long 0x00 "TX_CONTROL,TX Control Register"
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bitfld.long 0x00 0. " TX_EN ,Transmit enable" "Disabled,Enabled"
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line.long 0x04 "TX_TEARDOWN,TX Teardown Register"
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sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
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bitfld.long 0x04 0.--2. " TX_TDN_CH ,TX teardown channel" "0,1,2,3,4,5,6,7"
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else
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bitfld.long 0x04 31. " TX_TDN_READY ,TX teardown ready" "Not ready,Ready"
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bitfld.long 0x04 0.--2. " TX_TDN_CH ,TX teardown channel" "0,1,2,3,4,5,6,7"
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endif
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rgroup.long 0x110++0x03
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line.long 0x00 "RX_IDVER,RX Identification and Version Register"
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hexmask.long.word 0x00 16.--31. 1. " RX_IDENT ,RX Identification value"
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hexmask.long.byte 0x00 8.--15. 1. " RX_MAJOR_VER ,RX major version value"
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hexmask.long.byte 0x00 0.--7. 1. " RX_MINOR_VER ,RX minor version value"
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group.long 0x114++0x0f
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line.long 0x00 "RX_CONTROL,RX Control Register"
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bitfld.long 0x00 0. " RX_EN ,Transmit enable" "Disabled,Enabled"
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line.long 0x04 "RX_TEARDOWN,RX Teardown Register"
|
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sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
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bitfld.long 0x04 0.--2. " RX_TDN_CH ,RX teardown channel" "0,1,2,3,4,5,6,7"
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else
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bitfld.long 0x04 31. " RX_TDN_READY ,RX teardown ready" "Not ready,Ready"
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bitfld.long 0x04 0.--2. " RX_TDN_CH ,RX teardown channel" "0,1,2,3,4,5,6,7"
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endif
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line.long 0x08 "SOFT_RESET,Soft Reset Register"
|
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bitfld.long 0x08 0. " SOFT_RESET ,Software reset" "No reset,Reset"
|
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line.long 0x0c "DMACONTROL,CPDMA Control Register"
|
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hexmask.long.byte 0x0c 8.--15. 1. " TX_RLIM ,Transmit Rate Limit Channel Bus"
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bitfld.long 0x0c 4. " RX_CEF ,RX copy error frames enable" "Disabled,Enabled"
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bitfld.long 0x0c 3. " CMD_IDLE ,Command idle" "Not idle,Idle"
|
|
textline " "
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bitfld.long 0x0c 2. " RX_OFFLEN_BLOCK ,Receive Offset/Length word write block" "Disabled,Enabled"
|
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bitfld.long 0x0c 1. " RX_OWNERSHIP ,Receive ownership write bit value" "Not received,Received"
|
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bitfld.long 0x0c 0. " TX_PTYPE ,Transmit queue priority type" "Round robin,Fixed"
|
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rgroup.long 0x124++0x03
|
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line.long 0x00 "DMASTATUS,CPDMA Status Register"
|
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bitfld.long 0x00 31. " IDLE ,Idle Status" "Not idle,Idle"
|
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textline " "
|
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bitfld.long 0x00 20.--23. " TX_HOST_ERR_CODE ,TX host error code" "No error,SOP error,Ownership bit not set in SOP buffer,Zero next buffer without EOP,Zero buffer pointer,Zero buffer length,Packet length error,?..."
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textline " "
|
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bitfld.long 0x00 16.--18. " TX_ERR_CH ,TX host error channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
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bitfld.long 0x00 12.--15. " RX_HOST_ERR_CODE ,RX host error code" "No error,Reserved,Ownership bit not set in input buffer,Reserved,Zero Buffer Pointer,Zero buffer length (Non-SOP),SOP buffer length <= Offset,?..."
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|
textline " "
|
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bitfld.long 0x00 8.--10. " RX_ERROR_CH ,RX host error channel" "0,1,2,3,4,5,6,7"
|
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group.long 0x128++0x07
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line.long 0x00 "RX_BUFFER_OFFSET,Receive Buffer Offset Register"
|
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hexmask.long.word 0x00 0.--15. 1. " RX_BUFFER_OFFSET ,Receive buffer offset value"
|
|
line.long 0x04 "EMCONTROL,Emulation Control Register"
|
|
bitfld.long 0x04 1. " SOFT ,Emulation soft bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " FREE ,Emulation free bit" "Disabled,Enabled"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TX_PRI0_RATE,Transmit Priority 0 Rate Register"
|
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hexmask.long.word 0x00 16.--29. 1. " PRI0_IDLE_CNT ,Priority 0 idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRI0_SEND_CNT ,Priority 0 send count"
|
|
group.long 0x134++0x03
|
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line.long 0x00 "TX_PRI1_RATE,Transmit Priority 1 Rate Register"
|
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hexmask.long.word 0x00 16.--29. 1. " PRI1_IDLE_CNT ,Priority 1 idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRI1_SEND_CNT ,Priority 1 send count"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TX_PRI2_RATE,Transmit Priority 2 Rate Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRI2_IDLE_CNT ,Priority 2 idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRI2_SEND_CNT ,Priority 2 send count"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TX_PRI3_RATE,Transmit Priority 3 Rate Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRI3_IDLE_CNT ,Priority 3 idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRI3_SEND_CNT ,Priority 3 send count"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TX_PRI4_RATE,Transmit Priority 4 Rate Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRI4_IDLE_CNT ,Priority 4 idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRI4_SEND_CNT ,Priority 4 send count"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "TX_PRI5_RATE,Transmit Priority 5 Rate Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRI5_IDLE_CNT ,Priority 5 idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRI5_SEND_CNT ,Priority 5 send count"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "TX_PRI6_RATE,Transmit Priority 6 Rate Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRI6_IDLE_CNT ,Priority 6 idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRI6_SEND_CNT ,Priority 6 send count"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "TX_PRI7_RATE,Transmit Priority 7 Rate Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRI7_IDLE_CNT ,Priority 7 idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRI7_SEND_CNT ,Priority 7 send count"
|
|
width 19.
|
|
rgroup.long 0x180++0x07 "CPDMA Interrupts"
|
|
line.long 0x00 "TX_INTSTAT_RAW,TX Interrupt Status Register (Raw Value)"
|
|
bitfld.long 0x00 7. " TX7_PEND ,TX7_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " TX6_PEND ,TX6_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TX5_PEND ,TX5_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " TX4_PEND ,TX4_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TX3_PEND ,TX3_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " TX2_PEND ,TX2_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX1_PEND ,TX1_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " TX0_PEND ,TX0_PEND raw interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "TX_INTSTAT_MASKED,TX Interrupt Status Register"
|
|
bitfld.long 0x04 7. " TX7_PEND ,TX7_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " TX6_PEND ,TX6_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX5_PEND ,TX5_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " TX4_PEND ,TX4_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TX3_PEND ,TX3_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " TX2_PEND ,TX2_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX1_PEND ,TX1_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " TX0_PEND ,TX0_PEND interrupt" "No interrupt,Interrupt"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "TX_INTMASK_SET,TX Interrupt Mask Set Register"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TX7_PEND_MASK_set/clr ,TX Channel 7 pending interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TX6_PEND_MASK_set/clr ,TX Channel 6 pending interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " TX5_PEND_MASK_set/clr ,TX Channel 5 pending interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TX4_PEND_MASK_set/clr ,TX Channel 4 pending interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TX3_PEND_MASK_set/clr ,TX Channel 3 pending interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TX2_PEND_MASK_set/clr ,TX Channel 2 pending interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TX1_PEND_MASK_set/clr ,TX Channel 1 pending interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " TX0_PEND_MASK_set/clr ,TX Channel 0 pending interrupt mask" "Disabled,Enabled"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "CPDMA_IN_VECTOR,Input Vector Register"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "CPDMA_EOI_VECTOR,End Of Interrupt Vector Register"
|
|
bitfld.long 0x00 0.--4. " DMA_EOI_VECTOR ,DMA end of interrupt vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x1a0++0x07
|
|
line.long 0x00 "RX_INTSTAT_RAW,RX Interrupt Status Register (Raw Value)"
|
|
bitfld.long 0x00 15. " RX7_THRESH_PEND ,RX7_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " RX6_THRESH_PEND ,RX6_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RX5_THRESH_PEND ,RX5_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " RX4_THRESH_PEND ,RX4_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RX3_THRESH_PEND ,RX3_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " RX2_THRESH_PEND ,RX2_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX1_THRESH_PEND ,RX1_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RX0_THRESH_PEND ,RX0_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RX7_PEND ,RX7_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RX6_PEND ,RX6_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RX5_PEND ,RX5_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RX4_PEND ,RX4_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX3_PEND ,RX3_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RX2_PEND ,RX2_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX1_PEND ,RX1_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RX0_PEND ,RX0_PEND raw interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "RX_INTSTAT_MASKED,RX Interrupt Status Register"
|
|
bitfld.long 0x04 15. " RX7_THRESH_PEND ,RX7_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " RX6_THRESH_PEND ,RX6_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RX5_THRESH_PEND ,RX5_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " RX4_THRESH_PEND ,RX4_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RX3_THRESH_PEND ,RX3_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " RX2_THRESH_PEND ,RX2_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX1_THRESH_PEND ,RX1_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RX0_THRESH_PEND ,RX0_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RX7_PEND ,RX7_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " RX6_PEND ,RX6_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RX5_PEND ,RX5_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RX4_PEND ,RX4_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX3_PEND ,RX3_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RX2_PEND ,RX2_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RX1_PEND ,RX1_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RX0_PEND ,RX0_PEND interrupt" "No interrupt,Interrupt"
|
|
group.long 0x1a8++0x03
|
|
line.long 0x00 "RX_INTMASK,RX Interrupt Mask Set Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " RX7_THRESH_PEND_MASK_set/clr ,RX Channel 7 threshold pending interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " RX6_THRESH_PEND_MASK_set/clr ,RX Channel 6 threshold pending interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " RX5_THRESH_PEND_MASK_set/clr ,RX Channel 5 threshold pending interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " RX4_THRESH_PEND_MASK_set/clr ,RX Channel 4 threshold pending interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " RX3_THRESH_PEND_MASK_set/clr ,RX Channel 3 threshold pending interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " RX2_THRESH_PEND_MASK_set/clr ,RX Channel 2 threshold pending interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX1_THRESH_PEND_MASK_set/clr ,RX Channel 1 threshold pending interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " RX0_THRESH_PEND_MASK_set/clr ,RX Channel 0 threshold pending interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " RX7_PEND_MASK_set/clr ,RX Channel 7 pending interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " RX6_PEND_MASK_set/clr ,RX Channel 6 pending interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " RX5_PEND_MASK_set/clr ,RX Channel 5 pending interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " RX4_PEND_MASK_set/clr ,RX Channel 4 pending interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " RX3_PEND_MASK_set/clr ,RX Channel 3 pending interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " RX2_PEND_MASK_set/clr ,RX Channel 2 pending interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " RX1_PEND_MASK_set/clr ,RX Channel 1 pending interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RX0_PEND_MASK_set/clr ,RX Channel 0 pending interrupt mask" "Disabled,Enabled"
|
|
rgroup.long 0x1b0++0x07
|
|
line.long 0x00 "DMA_INTSTAT_RAW,DMA Interrupt Status Register (Raw Value)"
|
|
bitfld.long 0x00 1. " HOST_PEND ,Host pending raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " STAT_PEND ,Statistics pending raw interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "DMA_INTSTAT_MASKED,DMA Interrupt Status Register"
|
|
bitfld.long 0x04 1. " HOST_PEND ,Host pending interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " STAT_PEND ,Statistics pending interrupt" "No interrupt,Interrupt"
|
|
group.long 0x1b8++0x03
|
|
line.long 0x00 "DMA_INTMASK_SET,DMA Interrupt Mask Set Register"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " HOST_ERR_INT_MASK ,Host error interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " STAT_INT_MASK ,Statistics interrupt mask" "Disabled,Enabled"
|
|
group.long 0x1c0++0x1f
|
|
line.long 0x0 "RX0_PENDTHRESH,Receive Threshold Pending Register Channel 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " RX0_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0x4 "RX1_PENDTHRESH,Receive Threshold Pending Register Channel 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " RX1_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0x8 "RX2_PENDTHRESH,Receive Threshold Pending Register Channel 2"
|
|
hexmask.long.byte 0x8 0.--7. 1. " RX2_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0xC "RX3_PENDTHRESH,Receive Threshold Pending Register Channel 3"
|
|
hexmask.long.byte 0xC 0.--7. 1. " RX3_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0x10 "RX4_PENDTHRESH,Receive Threshold Pending Register Channel 4"
|
|
hexmask.long.byte 0x10 0.--7. 1. " RX4_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0x14 "RX5_PENDTHRESH,Receive Threshold Pending Register Channel 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. " RX5_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0x18 "RX6_PENDTHRESH,Receive Threshold Pending Register Channel 6"
|
|
hexmask.long.byte 0x18 0.--7. 1. " RX6_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0x1C "RX7_PENDTHRESH,Receive Threshold Pending Register Channel 7"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " RX7_PENDTHRESH ,Receive flow threshold"
|
|
wgroup.long 0x1e0++0x1f
|
|
line.long 0x0 "RX0_FREEBUFFER,Receive Free Buffer Register Channel 0"
|
|
hexmask.long.word 0x0 0.--15. 1. " RX0_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0x4 "RX1_FREEBUFFER,Receive Free Buffer Register Channel 1"
|
|
hexmask.long.word 0x4 0.--15. 1. " RX1_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0x8 "RX2_FREEBUFFER,Receive Free Buffer Register Channel 2"
|
|
hexmask.long.word 0x8 0.--15. 1. " RX2_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0xC "RX3_FREEBUFFER,Receive Free Buffer Register Channel 3"
|
|
hexmask.long.word 0xC 0.--15. 1. " RX3_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0x10 "RX4_FREEBUFFER,Receive Free Buffer Register Channel 4"
|
|
hexmask.long.word 0x10 0.--15. 1. " RX4_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0x14 "RX5_FREEBUFFER,Receive Free Buffer Register Channel 5"
|
|
hexmask.long.word 0x14 0.--15. 1. " RX5_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0x18 "RX6_FREEBUFFER,Receive Free Buffer Register Channel 6"
|
|
hexmask.long.word 0x18 0.--15. 1. " RX6_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0x1C "RX7_FREEBUFFER,Receive Free Buffer Register Channel 7"
|
|
hexmask.long.word 0x1C 0.--15. 1. " RX7_FREEBUFFER ,Receive free buffer count"
|
|
group.long 0x200++0x7f
|
|
line.long 0x0 "TX0_HDP,TX Channel 0 Head Descriptor Pointer Register"
|
|
line.long 0x4 "TX1_HDP,TX Channel 1 Head Descriptor Pointer Register"
|
|
line.long 0x8 "TX2_HDP,TX Channel 2 Head Descriptor Pointer Register"
|
|
line.long 0xC "TX3_HDP,TX Channel 3 Head Descriptor Pointer Register"
|
|
line.long 0x10 "TX4_HDP,TX Channel 4 Head Descriptor Pointer Register"
|
|
line.long 0x14 "TX5_HDP,TX Channel 5 Head Descriptor Pointer Register"
|
|
line.long 0x18 "TX6_HDP,TX Channel 6 Head Descriptor Pointer Register"
|
|
line.long 0x1C "TX7_HDP,TX Channel 7 Head Descriptor Pointer Register"
|
|
line.long 0x20 "RX0_HDP,RX Channel 0 Head Descriptor Pointer Register"
|
|
line.long 0x24 "RX1_HDP,RX Channel 1 Head Descriptor Pointer Register"
|
|
line.long 0x28 "RX2_HDP,RX Channel 2 Head Descriptor Pointer Register"
|
|
line.long 0x2C "RX3_HDP,RX Channel 3 Head Descriptor Pointer Register"
|
|
line.long 0x30 "RX4_HDP,RX Channel 4 Head Descriptor Pointer Register"
|
|
line.long 0x34 "RX5_HDP,RX Channel 5 Head Descriptor Pointer Register"
|
|
line.long 0x38 "RX6_HDP,RX Channel 6 Head Descriptor Pointer Register"
|
|
line.long 0x3C "RX7_HDP,RX Channel 7 Head Descriptor Pointer Register"
|
|
line.long 0x40 "TX0_CP,TX Channel 0 Completion Pointer Register"
|
|
line.long 0x44 "TX1_CP,TX Channel 1 Completion Pointer Register"
|
|
line.long 0x48 "TX2_CP,TX Channel 2 Completion Pointer Register"
|
|
line.long 0x4C "TX3_CP,TX Channel 3 Completion Pointer Register"
|
|
line.long 0x50 "TX4_CP,TX Channel 4 Completion Pointer Register"
|
|
line.long 0x54 "TX5_CP,TX Channel 5 Completion Pointer Register"
|
|
line.long 0x58 "TX6_CP,TX Channel 6 Completion Pointer Register"
|
|
line.long 0x5C "TX7_CP,TX Channel 7 Completion Pointer Register"
|
|
line.long 0x60 "RX0_CP,RX Channel 0 Completion Pointer Register"
|
|
line.long 0x64 "RX1_CP,RX Channel 1 Completion Pointer Register"
|
|
line.long 0x68 "RX2_CP,RX Channel 2 Completion Pointer Register"
|
|
line.long 0x6C "RX3_CP,RX Channel 3 Completion Pointer Register"
|
|
line.long 0x70 "RX4_CP,RX Channel 4 Completion Pointer Register"
|
|
line.long 0x74 "RX5_CP,RX Channel 5 Completion Pointer Register"
|
|
line.long 0x78 "RX6_CP,RX Channel 6 Completion Pointer Register"
|
|
line.long 0x7C "RX7_CP,RX Channel 7 Completion Pointer Register"
|
|
width 22.
|
|
group.long 0x400++0x27 "Statistics Interface Registers"
|
|
line.long 0x00 "RXGOODFRAMES,Total Number of Good Frames Received Register"
|
|
line.long 0x04 "RXBROADCASTFRAMES,Total Number of Good Broadcast Frames Received Register"
|
|
line.long 0x08 "RXMULTICASTFRAMES,Total Number of Good Multicast Frames Received Register"
|
|
line.long 0x0c "RXPAUSEFRAMES,PauseRxFrames Register"
|
|
line.long 0x10 "RXCRCERRORS,Total Number of CRC Errors Frames Received Register"
|
|
line.long 0x14 "RXALIGNCODEERRORS,Total Number of Alignment/Code Errors Received Register"
|
|
line.long 0x18 "RXOVERSIZEDFRAMES,Total Number of Oversized Frames Received Register"
|
|
line.long 0x1c "RXJABBERFRAMES,Total Number of Jabber Frames Received Register"
|
|
line.long 0x20 "RXUNDERSIZEDFRAMES,Total Number of Undersized Frames Received Register"
|
|
line.long 0x24 "RXFRAGMENTS,RxFragments Received Register"
|
|
group.long 0x430++0x5f
|
|
line.long 0x00 "RXOCTETS,Total Number of Received Bytes in Good Frames Register"
|
|
line.long 0x04 "TXGOODFRAMES,GoodTXFrames Register"
|
|
line.long 0x08 "TXBROADCASTFRAMES,Broadcast TX Frames Register Register"
|
|
line.long 0x0c "TXMULTICASTFRAMES,Multicast TX Frames Register"
|
|
line.long 0x10 "TXPAUSEFRAMES,Pause TX Frames Register"
|
|
line.long 0x14 "TXDEFERREDFRAMES,Deferred Frames Register"
|
|
line.long 0x18 "TXCOLLISIONFRAMES,Collisions Register"
|
|
line.long 0x1c "TXSINGLECOLLFRAMES,Single Collision TX Frames Register"
|
|
line.long 0x20 "TXMULTCOLLFRAMES,Multiple Collision TX Frames Register"
|
|
line.long 0x24 "TXEXCESSIVECOLLISIONS,Excessive Collisions Register"
|
|
line.long 0x28 "TXLATECOLLISIONS,Late Collisions Register"
|
|
line.long 0x2c "TXUNDERRUN,Transmit Underrun Error Register"
|
|
line.long 0x30 "TXCARRIERSENSEERRORS,Carrier Sense Errors Register"
|
|
line.long 0x34 "TXOCTETS,TXOctets Register"
|
|
line.long 0x38 "64OCTETFRAMES,64 Octet Frames Register"
|
|
line.long 0x3c "65T127OCTETFRAMES,65-127 Octet Frames Register"
|
|
line.long 0x40 "128T255OCTETFRAMES,128-255 Octet Frames Register"
|
|
line.long 0x44 "256T511OCTETFRAMES,256-511 Octet Frames Register"
|
|
line.long 0x48 "512T1023OCTETFRAMES,512-1023 Octet Frames Register"
|
|
line.long 0x4c "1024TUPOCTETFRAMES,1023-1518 Octet Frames Register"
|
|
line.long 0x50 "NETOCTETS,NetOctets Register"
|
|
line.long 0x54 "RXSOFOVERRUNS,Receive FIFO or DMA Start of Frame Overruns Register"
|
|
line.long 0x58 "RXMOFOVERRUNS,Receive FIFO or DMA Mid of Frame Overruns Register"
|
|
line.long 0x5c "RXDMAOVERRUNS,Receive DMA Start of Frame and Middle of Frame Overruns Register"
|
|
width 19.
|
|
rgroup.long 0x500++0x03 "CPTS Registers"
|
|
line.long 0x00 "CPTS_IDVER,Identification and Version Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TX_IDENT ,TX Identification value"
|
|
bitfld.long 0x00 11.--15. " RTL_VER ,RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MAJ_VER ,Major Version Value" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MINOR_VER ,Minor version value"
|
|
group.long 0x504++0x07
|
|
line.long 0x00 "CPTS_CONTROL,Time Sync Control Register"
|
|
bitfld.long 0x00 11. " HW4_TS_PUSH_EN ,Hardware push 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HW3_TS_PUSH_EN ,Hardware push 3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HW2_TS_PUSH_EN ,Hardware push 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HW1_TS_PUSH_EN ,Hardware push 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INT_TEST ,Interrupt Test" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CPTS_EN ,Time Sync Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CPTS_RFTCLK_SEL,Reference Clock Select Register"
|
|
bitfld.long 0x04 0.--4. " RFTCLK_SEL ,Reference Clock Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
wgroup.long 0x50c++0x03
|
|
line.long 0x00 "CPTS_TS_PUSH,Time Stamp Event Push Register"
|
|
bitfld.long 0x00 0. " TS_PUSH ,Time stamp event push" "No effect,Push"
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "CPTS_TS_LOAD_VAL,Time Stamp Load Value Register"
|
|
wgroup.long 0x514++0x03
|
|
line.long 0x00 "CPTS_TS_LOAD_EN,Time Stamp Load Enable Register"
|
|
bitfld.long 0x00 0. " TS_LOAD_EN ,Time Stamp Load" "Disabled,Enabled"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "CPTS_INTSTAT_RAW,Time Sync Interrupt Status Register Raw Register"
|
|
bitfld.long 0x00 0. " TS_PEND_RAW ,TS_PEND raw interrupt" "No interrupt,Interrupt"
|
|
rgroup.long 0x524++0x03
|
|
line.long 0x00 "CPTS_INTSTAT_MASKED,Time Sync Interrupt Status Register Masked Register"
|
|
bitfld.long 0x00 0. " TS_PEND ,TS_PEND masked interrupt" "No interrupt,Interrupt"
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "CPTS_INT_ENABLE,Time Sync Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " TS_PEND_EN ,TS_PEND masked interrupt enable" "Disabled,Enabled"
|
|
wgroup.long 0x530++0x03
|
|
line.long 0x00 "CPTS_EVENT_POP,Event Interrupt Pop Register"
|
|
bitfld.long 0x00 0. " EVENT_POP ,Event Pop" "No effect,Pop"
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "CPTS_EVENT_LOW,Event Low Register"
|
|
rgroup.long 0x538++0x03
|
|
line.long 0x00 "CPTS_EVENT_HIGH,Event High Register"
|
|
bitfld.long 0x00 24.--28. " PORT_NUMBER ,Port Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20.--23. " EVENT_TYPE ,Time Sync Event Type" "Time Stamp Push,Time Stamp Rollover,Time Stamp Half Rollover,Hardware Time Stamp Push,Ethernet Receive,Ethernet Transmit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MESSAGE_TYPE ,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " SEQUENCE_ID ,Sequence ID"
|
|
rgroup.long 0x600++0x03 "Address Lookup Engine Registers"
|
|
line.long 0x00 "ALE_IDVER,Address Lookup Engine ID/Version Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ALE_IDENT ,Address Lookup Engine Identification Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALE_MAJ_VER ,Address Lookup Engine Major Version Value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALE_MINOR_VER ,Address Lookup Engine Minor Version Value"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "ALE_CONTROL,Address Lookup Engine Control Register"
|
|
bitfld.long 0x00 31. " ENABLE_ALE ,Enable ALE" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CLEAR_TABLE ,Clear ALE address table" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " AGE_OUT_NOW ,Age Out Address Table Now" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " LEARN_NO_VID ,Learn No VID" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EN_VID0_MODE ,Enable VLAN ID = 0 Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENABLE_OUI_DENY ,Enable OUI Deny Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ALE_BYPASS ,ALE Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 3. " RATE_LIMIT_TX ,Rate Limit Transmit mode" "Received,Transmit"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ALE_VLAN_AWARE ,ALE VLAN Aware" "Flood,Drop"
|
|
bitfld.long 0x00 1. " ENABLE_AUTH_MODE ,Enable MAC Authorization Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE_RATE_LIMIT ,Enable Broadcast and Multicast Rate Limit" "Flood,Drop"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "ALE_PRESCALE,Address Lookup Engine Prescale Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " ALE_PRESCALE ,ALE Prescaler"
|
|
width 19.
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "ALE_UNKNOWN_VLAN,Address Lookup Engine Unknown VLAN Register"
|
|
bitfld.long 0x00 24.--29. " UNKNOWN_FORCE_UNTAGGED_EGRESS ,Unknown VLAN Force Untagged Egress" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " UNKNOWN_REG_MCAST_FLOOD_MASK ,Unknown VLAN Registered Multicast Flood Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " UNKNOWN_MCAST_FLOOD_MASK ,Unknown VLAN Multicast Flood Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " UNKNOWN_VLAN_MEMBER_LIST ,Unknown VLAN Member List" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "ALE_TBLCTL,Address Lookup Engine Table Control Register"
|
|
bitfld.long 0x00 31. " WRITE_RDZ ,Write bit" "Read,Write"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " ENTRY_POINTER ,Table Entry Pointer"
|
|
group.long 0x634++0x17
|
|
line.long 0x00 "ALE_TBLW2,Address Lookup Engine Table Word 2 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ENTRY(71:64) ,Table entry bits 71-64"
|
|
line.long 0x04 "ALE_TBLW1,Address Lookup Engine Table Word 1 Register"
|
|
line.long 0x08 "ALE_TBLW0,Address Lookup Engine Table Word 0 Register"
|
|
width 19.
|
|
line.long 0xC "ALE_PORTCTL0,Address Lookup Engine Port 0 Control Registers"
|
|
hexmask.long.byte 0xC 24.--31. 1. " BCAST_LIMIT ,Broadcast packet rate limit"
|
|
textline " "
|
|
hexmask.long.byte 0xC 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit"
|
|
textline " "
|
|
bitfld.long 0xC 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward"
|
|
line.long 0x10 "ALE_PORTCTL1,Address Lookup Engine Port 1 Control Registers"
|
|
hexmask.long.byte 0x10 24.--31. 1. " BCAST_LIMIT ,Broadcast packet rate limit"
|
|
textline " "
|
|
hexmask.long.byte 0x10 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit"
|
|
textline " "
|
|
bitfld.long 0x10 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward"
|
|
line.long 0x14 "ALE_PORTCTL2,Address Lookup Engine Port 2 Control Registers"
|
|
hexmask.long.byte 0x14 24.--31. 1. " BCAST_LIMIT ,Broadcast packet rate limit"
|
|
textline " "
|
|
hexmask.long.byte 0x14 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit"
|
|
textline " "
|
|
bitfld.long 0x14 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward"
|
|
width 19.
|
|
rgroup.long (0x700)++0x03 "CPGMAC SL1 Registers"
|
|
line.long 0x00 "SL1_IDVER,CPGMAC_SL1 IDVER Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " IDENT ,RX Identification value"
|
|
bitfld.long 0x00 11.--15. " Z ,RX Z value (X.Y.Z)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " X ,RX X value (major)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Y ,RX Y value (minor)"
|
|
group.long (0x700+0x04)++0x03
|
|
line.long 0x00 "SL1_MACCONTROL,CPGMAC_SL1 MAC Control Register"
|
|
bitfld.long 0x00 24. " RX_CMF_EN ,RX Copy MAC Control Frames Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RX_CSF_EN ,RX Copy Short Frames Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RX_CEF_EN ,RX Copy Error Frames Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " TX_SHORT_GAP_LIM_EN ,Transmit Short Gap Limit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXT_EN ,Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " GIG_FORCE ,Gigabit Mode Force" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IFCTL_B ,Interface Control B" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " IFCTL_A ,Interface Control A" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CMD_IDLE ,Command Idle" "No idle,Idle"
|
|
bitfld.long 0x00 10. " TX_SHORT_GAP_EN ,Transmit Short Gap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GIG ,Gigabit Mode" "10/100 Mbit,Gigabit"
|
|
bitfld.long 0x00 6. " TX_PACE ,Transmit Pacing Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GMII_EN ,G/MII Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TX_FLOW_EN ,Transmit Flow Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX_FLOW_EN ,Receive Flow Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MTEST ,Manufacturing Test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOOPBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FULLDUPLEX ,Full Duplex mode" "Disabled,Enabled"
|
|
rgroup.long (0x700+0x08)++0x03
|
|
line.long 0x00 "SL1_MACSTATUS,CPGMAC_SL1 MAC Status Register"
|
|
bitfld.long 0x00 31. " IDLE ,CPGMAC_SL1 IDLE" "No idle,Idle"
|
|
bitfld.long 0x00 4. " EXT_GIG ,External GIG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EXT_FULLDUPLEX ,External Fullduplex" "Low,High"
|
|
bitfld.long 0x00 1. " RX_FLOW_ACT ,Receive Flow Control Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TX_FLOW_ACT ,Transmit Flow Control Active" "Not active,Active"
|
|
group.long (0x700+0x0c)++0x1b
|
|
line.long 0x00 "SL1_SOFT_RESET,CPGMAC_SL1 Software Reset Register"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "No reset,Reset"
|
|
line.long 0x04 "SL1_RX_MAXLEN,CPGMAC_SL1 RX Maximum Length Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " RX_MAXLEN ,RX Maximum Frame Length"
|
|
line.long 0x08 "SL1_BOFFTEST,CPGMAC_SL1 Backoff Random Number Generator Test Register"
|
|
bitfld.long 0x08 26.--30. " PACEVAL ,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x08 16.--25. 1. " RNDNUM ,Backoff Random Number Generator"
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " COLL_COUNT ,Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x08 0.--9. 1. " TX_BACKOFF ,Backoff Count"
|
|
line.long 0x0c "SL1_RX_PAUSE,CPGMAC_SL1 RX Pause Timer Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " RX_PAUSETIMER ,RX Pause Timer Value"
|
|
line.long 0x10 "SL1_TX_PAUSE,CPGMAC_SL1 TX Pause Timer Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TX_PAUSETIMER ,TX Pause Timer Value"
|
|
line.long 0x14 "SL1_EMCONTROL,CPGMAC_SL1 Emulation Control Register"
|
|
bitfld.long 0x14 1. " SOFT ,Emulation soft bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " FREE ,Emulation free bit" "Disabled,Enabled"
|
|
line.long 0x18 "SL1_RX_PRI_MAP,CPGMAC_SL1 RX Packet Priority to Header Priority Mapping Register"
|
|
bitfld.long 0x18 28.--30. " PRI7 ,Priority 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 24.--26. " PRI6 ,Priority 6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 20.--22. " PRI5 ,Priority 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 16.--18. " PRI4 ,Priority 4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 12.--14. " PRI3 ,Priority 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 8.--10. " PRI2 ,Priority 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 4.--6. " PRI1 ,Priority 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. " PRI0 ,Priority 0" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0x740)++0x03 "CPGMAC SL2 Registers"
|
|
line.long 0x00 "SL2_IDVER,CPGMAC_SL2 IDVER Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " IDENT ,RX Identification value"
|
|
bitfld.long 0x00 11.--15. " Z ,RX Z value (X.Y.Z)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " X ,RX X value (major)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Y ,RX Y value (minor)"
|
|
group.long (0x740+0x04)++0x03
|
|
line.long 0x00 "SL2_MACCONTROL,CPGMAC_SL2 MAC Control Register"
|
|
bitfld.long 0x00 24. " RX_CMF_EN ,RX Copy MAC Control Frames Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RX_CSF_EN ,RX Copy Short Frames Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RX_CEF_EN ,RX Copy Error Frames Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " TX_SHORT_GAP_LIM_EN ,Transmit Short Gap Limit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXT_EN ,Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " GIG_FORCE ,Gigabit Mode Force" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IFCTL_B ,Interface Control B" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " IFCTL_A ,Interface Control A" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CMD_IDLE ,Command Idle" "No idle,Idle"
|
|
bitfld.long 0x00 10. " TX_SHORT_GAP_EN ,Transmit Short Gap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GIG ,Gigabit Mode" "10/100 Mbit,Gigabit"
|
|
bitfld.long 0x00 6. " TX_PACE ,Transmit Pacing Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GMII_EN ,G/MII Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TX_FLOW_EN ,Transmit Flow Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX_FLOW_EN ,Receive Flow Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MTEST ,Manufacturing Test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOOPBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FULLDUPLEX ,Full Duplex mode" "Disabled,Enabled"
|
|
rgroup.long (0x740+0x08)++0x03
|
|
line.long 0x00 "SL2_MACSTATUS,CPGMAC_SL2 MAC Status Register"
|
|
bitfld.long 0x00 31. " IDLE ,CPGMAC_SL1 IDLE" "No idle,Idle"
|
|
bitfld.long 0x00 4. " EXT_GIG ,External GIG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EXT_FULLDUPLEX ,External Fullduplex" "Low,High"
|
|
bitfld.long 0x00 1. " RX_FLOW_ACT ,Receive Flow Control Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TX_FLOW_ACT ,Transmit Flow Control Active" "Not active,Active"
|
|
group.long (0x740+0x0c)++0x1b
|
|
line.long 0x00 "SL2_SOFT_RESET,CPGMAC_SL2 Software Reset Register"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "No reset,Reset"
|
|
line.long 0x04 "SL2_RX_MAXLEN,CPGMAC_SL2 RX Maximum Length Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " RX_MAXLEN ,RX Maximum Frame Length"
|
|
line.long 0x08 "SL2_BOFFTEST,CPGMAC_SL2 Backoff Random Number Generator Test Register"
|
|
bitfld.long 0x08 26.--30. " PACEVAL ,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x08 16.--25. 1. " RNDNUM ,Backoff Random Number Generator"
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " COLL_COUNT ,Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x08 0.--9. 1. " TX_BACKOFF ,Backoff Count"
|
|
line.long 0x0c "SL2_RX_PAUSE,CPGMAC_SL2 RX Pause Timer Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " RX_PAUSETIMER ,RX Pause Timer Value"
|
|
line.long 0x10 "SL2_TX_PAUSE,CPGMAC_SL2 TX Pause Timer Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TX_PAUSETIMER ,TX Pause Timer Value"
|
|
line.long 0x14 "SL2_EMCONTROL,CPGMAC_SL2 Emulation Control Register"
|
|
bitfld.long 0x14 1. " SOFT ,Emulation soft bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " FREE ,Emulation free bit" "Disabled,Enabled"
|
|
line.long 0x18 "SL2_RX_PRI_MAP,CPGMAC_SL2 RX Packet Priority to Header Priority Mapping Register"
|
|
bitfld.long 0x18 28.--30. " PRI7 ,Priority 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 24.--26. " PRI6 ,Priority 6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 20.--22. " PRI5 ,Priority 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 16.--18. " PRI4 ,Priority 4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 12.--14. " PRI3 ,Priority 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 8.--10. " PRI2 ,Priority 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 4.--6. " PRI1 ,Priority 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. " PRI0 ,Priority 0" "0,1,2,3,4,5,6,7"
|
|
width 12.
|
|
tree.end
|
|
tree "MDIO"
|
|
base ad:0x4a100800
|
|
width 16.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERSION,MDIO Version Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MODID ,Identifies type of peripheral"
|
|
hexmask.long.byte 0x00 8.--15. 1. " REVMAJ ,Management interface module major revision value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVMIN ,Management interface module minor revision value"
|
|
group.long 0x04++0x13
|
|
line.long 0x00 "CONTROL,MDIO Control Register"
|
|
bitfld.long 0x00 31. " IDLE ,MDIO state machine IDLE" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ENABLE ,Enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " PREAMBLE ,Preamble disable" "Enabled,Disabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " FAULT ,Fault indicator" "No failure,Fault"
|
|
bitfld.long 0x00 18. " FAULT_DETECT_ENABLE ,Fault detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " INT_TEST_ENABLE ,Interrupt test enable." "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divider"
|
|
line.long 0x04 "ALIVE,MDIO alive"
|
|
eventfld.long 0x04 31. " ALIVE[31] , MDIO Alive bit 31" "Not alive,Alive"
|
|
eventfld.long 0x04 30. " ALIVE[30] , MDIO Alive bit 30" "Not alive,Alive"
|
|
eventfld.long 0x04 29. " ALIVE[29] , MDIO Alive bit 29" "Not alive,Alive"
|
|
eventfld.long 0x04 28. " ALIVE[28] , MDIO Alive bit 28" "Not alive,Alive"
|
|
textline " "
|
|
eventfld.long 0x04 27. " ALIVE[27] , MDIO Alive bit 27" "Not alive,Alive"
|
|
eventfld.long 0x04 26. " ALIVE[26] , MDIO Alive bit 26" "Not alive,Alive"
|
|
eventfld.long 0x04 25. " ALIVE[25] , MDIO Alive bit 25" "Not alive,Alive"
|
|
eventfld.long 0x04 24. " ALIVE[24] , MDIO Alive bit 24" "Not alive,Alive"
|
|
textline " "
|
|
eventfld.long 0x04 23. " ALIVE[23] , MDIO Alive bit 23" "Not alive,Alive"
|
|
eventfld.long 0x04 22. " ALIVE[22] , MDIO Alive bit 22" "Not alive,Alive"
|
|
eventfld.long 0x04 21. " ALIVE[21] , MDIO Alive bit 21" "Not alive,Alive"
|
|
eventfld.long 0x04 20. " ALIVE[20] , MDIO Alive bit 20" "Not alive,Alive"
|
|
textline " "
|
|
eventfld.long 0x04 19. " ALIVE[19] , MDIO Alive bit 19" "Not alive,Alive"
|
|
eventfld.long 0x04 18. " ALIVE[18] , MDIO Alive bit 18" "Not alive,Alive"
|
|
eventfld.long 0x04 17. " ALIVE[17] , MDIO Alive bit 17" "Not alive,Alive"
|
|
eventfld.long 0x04 16. " ALIVE[16] , MDIO Alive bit 16" "Not alive,Alive"
|
|
textline " "
|
|
eventfld.long 0x04 15. " ALIVE[15] , MDIO Alive bit 15" "Not alive,Alive"
|
|
eventfld.long 0x04 14. " ALIVE[14] , MDIO Alive bit 14" "Not alive,Alive"
|
|
eventfld.long 0x04 13. " ALIVE[13] , MDIO Alive bit 13" "Not alive,Alive"
|
|
eventfld.long 0x04 12. " ALIVE[12] , MDIO Alive bit 12" "Not alive,Alive"
|
|
textline " "
|
|
eventfld.long 0x04 11. " ALIVE[11] , MDIO Alive bit 11" "Not alive,Alive"
|
|
eventfld.long 0x04 10. " ALIVE[10] , MDIO Alive bit 10" "Not alive,Alive"
|
|
eventfld.long 0x04 9. " ALIVE[9] , MDIO Alive bit 9" "Not alive,Alive"
|
|
eventfld.long 0x04 8. " ALIVE[8] , MDIO Alive bit 8" "Not alive,Alive"
|
|
textline " "
|
|
eventfld.long 0x04 7. " ALIVE[7] , MDIO Alive bit 7" "Not alive,Alive"
|
|
eventfld.long 0x04 6. " ALIVE[6] , MDIO Alive bit 6" "Not alive,Alive"
|
|
eventfld.long 0x04 5. " ALIVE[5] , MDIO Alive bit 5" "Not alive,Alive"
|
|
eventfld.long 0x04 4. " ALIVE[4] , MDIO Alive bit 4" "Not alive,Alive"
|
|
textline " "
|
|
eventfld.long 0x04 3. " ALIVE[3] , MDIO Alive bit 3" "Not alive,Alive"
|
|
eventfld.long 0x04 2. " ALIVE[2] , MDIO Alive bit 2" "Not alive,Alive"
|
|
eventfld.long 0x04 1. " ALIVE[1] , MDIO Alive bit 1" "Not alive,Alive"
|
|
eventfld.long 0x04 0. " ALIVE[0] , MDIO Alive bit 0" "Not alive,Alive"
|
|
line.long 0x08 "LINK,MDIO link state"
|
|
line.long 0x0c "LINKINTRAW,MDIO link status change interrupt register"
|
|
eventfld.long 0x0C 1. " LINKINTRAW[1] ,MDIO link change event" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " LINKINTRAW[0] ,MDIO link change event" "No interrupt,Interrupt"
|
|
line.long 0x10 "LINKINTMASKED,MDIO Link Status Change Interrupt Register"
|
|
eventfld.long 0x10 1. " LINKINTMASKED[1] ,MDIO link change interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 0. " LINKINTMASKED[0] ,MDIO link change interrupt" "No interrupt,Interrupt"
|
|
group.long 0x1c++0x0f
|
|
line.long 0x00 "USERINTRAW,MDIO User Command Complete Interrupt Register"
|
|
eventfld.long 0x00 1. " USERINTRAW[1] ,Raw value of MDIO user command complete event" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " USERINTRAW[0] ,Raw value of MDIO user command complete event" "No interrupt,Interrupt"
|
|
line.long 0x04 "USERINTMASKED,MDIO User Command Complete Interrupt (masked value) Register"
|
|
eventfld.long 0x04 1. " USERINTMASKED[1] ,Masked value of MDIO user command" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " USERINTMASKED[0] ,Masked value of MDIO user command" "No interrupt,Interrupt"
|
|
line.long 0x08 "USERINTMASKSET,MDIO User Command Complete Interrupt Mask Set Register"
|
|
bitfld.long 0x08 1. " USERINTMASKSET[1] ,MDIO user command complete interrupt mask set" "No effect,Set"
|
|
bitfld.long 0x08 0. " USERINTMASKSET[0] ,MDIO user command complete interrupt mask set" "No effect,Set"
|
|
line.long 0x0c "USERINTMASKCLR,MDIO User Command Complete Interrupt Mask Clear Register"
|
|
bitfld.long 0x0c 1. " USERINTMASKCLEAR[1] ,MDIO user command complete interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x0c 0. " USERINTMASKCLEAR[0] ,MDIO user command complete interrupt mask clear" "No effect,Clear"
|
|
group.long 0x7c++0x0f
|
|
line.long 0x0 "USERACCESS0,The MDIO user access register 0"
|
|
bitfld.long 0x0 31. " GO ,Go" "No effect,Enabled"
|
|
bitfld.long 0x0 30. " WRITE ,Write enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " ACK ,Acknowledge" "Disabled,Enabled"
|
|
hexmask.long.word 0x0 21.--25. 0x20 " REGADR ,Register address"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--20. 1. " PHYADR ,PHY address"
|
|
hexmask.long.word 0x0 0.--15. 1. " DATA ,User data"
|
|
line.long (0x0+0x04) "USERPHYSEL0,MDIO User PHY Select Register 0"
|
|
bitfld.long (0x0+0x04) 7. " LINKSEL ,Link status determination select" "MDIO,MLINK"
|
|
bitfld.long (0x0+0x04) 6. " LINKINT_ENABLE ,Link change interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte (0x0+0x04) 0.--4. 1. " PHYADDRMON ,PHY address"
|
|
line.long 0x8 "USERACCESS1,The MDIO user access register 1"
|
|
bitfld.long 0x8 31. " GO ,Go" "No effect,Enabled"
|
|
bitfld.long 0x8 30. " WRITE ,Write enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 29. " ACK ,Acknowledge" "Disabled,Enabled"
|
|
hexmask.long.word 0x8 21.--25. 0x20 " REGADR ,Register address"
|
|
textline " "
|
|
hexmask.long.byte 0x8 16.--20. 1. " PHYADR ,PHY address"
|
|
hexmask.long.word 0x8 0.--15. 1. " DATA ,User data"
|
|
line.long (0x8+0x04) "USERPHYSEL1,MDIO User PHY Select Register 1"
|
|
bitfld.long (0x8+0x04) 7. " LINKSEL ,Link status determination select" "MDIO,MLINK"
|
|
bitfld.long (0x8+0x04) 6. " LINKINT_ENABLE ,Link change interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte (0x8+0x04) 0.--4. 1. " PHYADDRMON ,PHY address"
|
|
width 0x0b
|
|
tree.end
|
|
tree "CPSW Subsytem"
|
|
base ad:0x4a100900
|
|
width 16.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IDVER,Subsystem ID Version Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,SCHEME" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNCTION ,Function value"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major version" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x04++0x1b
|
|
line.long 0x00 "SOFT_RESET,Subsystem Software Reset Register"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "No reset,Reset"
|
|
line.long 0x04 "CONTROL,SWITCH CONTROL REGISTER"
|
|
bitfld.long 0x04 2.--3. " MMR_STDBYMODE ,Standbymode MMR bits" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " MMR_IDLEMODE ,Idlemode MMR bits" "0,1,2,3"
|
|
line.long 0x08 "INT_CONTROL,Subsystem Interrupt Control Register"
|
|
bitfld.long 0x08 31. " INT_TEST ,Interrupt Test" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " INT_PACE_EN[5] ,Interrupt Pacing Enable Bus 5" "RX_Pulse,TX_Pulse"
|
|
bitfld.long 0x08 20. " INT_PACE_EN[4] ,Interrupt Pacing Enable Bus 4" "RX_Pulse,TX_Pulse"
|
|
bitfld.long 0x08 19. " INT_PACE_EN[3] ,Interrupt Pacing Enable Bus 3" "RX_Pulse,TX_Pulse"
|
|
textline " "
|
|
bitfld.long 0x08 18. " INT_PACE_EN[2] ,Interrupt Pacing Enable Bus 2" "RX_Pulse,TX_Pulse"
|
|
bitfld.long 0x08 17. " INT_PACE_EN[1] ,Interrupt Pacing Enable Bus 1" "RX_Pulse,TX_Pulse"
|
|
bitfld.long 0x08 16. " INT_PACE_EN[0] ,Interrupt Pacing Enable Bus 0" "RX_Pulse,TX_Pulse"
|
|
hexmask.long.word 0x08 0.--11. 1. " INT_PRESCALE ,Interrupt Counter Prescaler"
|
|
line.long 0x0c "RX_THRESH_EN,Subsystem Receive Threshold Interrupt Enable Register"
|
|
bitfld.long 0x0c 7. " RX_THRESH_EN[7] ,Receive Threshold Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " RX_THRESH_EN[6] ,Receive Threshold Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " RX_THRESH_EN[5] ,Receive Threshold Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " RX_THRESH_EN[4] ,Receive Threshold Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " RX_THRESH_EN[3] ,Receive Threshold Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " RX_THRESH_EN[2] ,Receive Threshold Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x0c 1. " RX_THRESH_EN[1] ,Receive Threshold Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " RX_THRESH_EN[0] ,Receive Threshold Enable 0" "Disabled,Enabled"
|
|
line.long 0x10 "RX_EN,Subsystem Receive Interrupt Enable Register"
|
|
bitfld.long 0x10 7. " RX_EN[7] ,Receive Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " RX_EN[6] ,Receive Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " RX_EN[5] ,Receive Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " RX_EN[4] ,Receive Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " RX_EN[3] ,Receive Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " RX_EN[2] ,Receive Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " RX_EN[1] ,Receive Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " RX_EN[0] ,Receive Enable 0" "Disabled,Enabled"
|
|
line.long 0x14 "TX_EN,Subsystem Transmit Interrupt Enable Register"
|
|
bitfld.long 0x14 7. " TX_EN[7] ,Transmit Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " TX_EN[6] ,Transmit Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " TX_EN[5] ,Transmit Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " TX_EN[4] ,Transmit Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " TX_EN[3] ,Transmit Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " TX_EN[2] ,Transmit Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " TX_EN[1] ,Transmit Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TX_EN[0] ,Transmit Enable 0" "Disabled,Enabled"
|
|
line.long 0x18 "MISC_EN,Subsystem Miscellaneous Interrupt Enable Register"
|
|
bitfld.long 0x18 4. " MISC_EN[4] ,Misc Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x18 3. " MISC_EN[3] ,Misc Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " MISC_EN[2] ,Misc Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " MISC_EN[1] ,Misc Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " MISC_EN[0] ,Misc Enable 0" "Disabled,Enabled"
|
|
rgroup.long 0x40++0x0f
|
|
line.long 0x00 "RX_THRESH_STAT,Subsystem Receive Threshold Masked Interrupt Status Register"
|
|
bitfld.long 0x00 7. " RX_THRESH_STAT[7] ,Receive Threshold Masked Interrupt Status 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RX_THRESH_STAT[6] ,Receive Threshold Masked Interrupt Status 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RX_THRESH_STAT[5] ,Receive Threshold Masked Interrupt Status 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RX_THRESH_STAT[4] ,Receive Threshold Masked Interrupt Status 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX_THRESH_STAT[3] ,Receive Threshold Masked Interrupt Status 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RX_THRESH_STAT[2] ,Receive Threshold Masked Interrupt Status 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RX_THRESH_STAT[1] ,Receive Threshold Masked Interrupt Status 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RX_THRESH_STAT[0] ,Receive Threshold Masked Interrupt Status 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "RX_STAT,Subsystem Receive Masked Interrupt Status Register"
|
|
bitfld.long 0x04 7. " RX_STAT[7] ,Receive Masked Interrupt Status 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " RX_STAT[6] ,Receive Masked Interrupt Status 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " RX_STAT[5] ,Receive Masked Interrupt Status 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RX_STAT[4] ,Receive Masked Interrupt Status 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX_STAT[3] ,Receive Masked Interrupt Status 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RX_STAT[2] ,Receive Masked Interrupt Status 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " RX_STAT[1] ,Receive Masked Interrupt Status 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RX_STAT[0] ,Receive Masked Interrupt Status 0" "No interrupt,Interrupt"
|
|
line.long 0x08 "TX_STAT,Subsystem Transmit Masked Interrupt Status Register"
|
|
bitfld.long 0x08 7. " TX_STAT[7] ,Transmit Masked Interrupt Status 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " TX_STAT[6] ,Transmit Masked Interrupt Status 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 5. " TX_STAT[5] ,Transmit Masked Interrupt Status 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " TX_STAT[4] ,Transmit Masked Interrupt Status 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 3. " TX_STAT[3] ,Transmit Masked Interrupt Status 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " TX_STAT[2] ,Transmit Masked Interrupt Status 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 1. " TX_STAT[1] ,Transmit Masked Interrupt Status 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " TX_STAT[0] ,Transmit Masked Interrupt Status 0" "No interrupt,Interrupt"
|
|
line.long 0x0c "MISC_STAT,Subsystem Miscellaneous Masked Interrupt Status Register"
|
|
bitfld.long 0x0c 4. " MISC_STAT[4] ,Misc Masked Interrupt Status 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x0c 3. " MISC_STAT[3] ,Misc Masked Interrupt Status 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x0c 2. " MISC_STAT[2] ,Misc Masked Interrupt Status 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x0c 1. " MISC_STAT[1] ,Misc Masked Interrupt Status 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " MISC_STAT[0] ,Misc Masked Interrupt Status 0" "No interrupt,Interrupt"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "RX_IMAX,Subsystem Receive Interrupts per Millisecond Register"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x00 0.--5. " RX_IMAX ,Receive Interrupts per Millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hexmask.long.byte 0x00 0.--6. 1. " RX_IMAX ,Receive Interrupts per Millisecond"
|
|
endif
|
|
line.long 0x04 "TX_IMAX,Subsystem Transmit Interrupts per Millisecond Register"
|
|
bitfld.long 0x04 0.--5. " TX_IMAX ,Transmit Interrupts per Millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "RGMII_CTL,RGMII Control Read Register"
|
|
bitfld.long 0x00 7. " RGMII1_FULLDUPLEX ,RGMII 2 Fullduplex" "Half-duplex,Full-duplex"
|
|
bitfld.long 0x00 5.--6. " RGMII1_SPEED ,RGMII 2 Speed" "10Mbps,100Mbps,1000Mbps,?..."
|
|
bitfld.long 0x00 4. " RGMII1_LINK ,RGMII 2 Link Indicator" "Down,Up"
|
|
bitfld.long 0x00 3. " RGMII0_FULLDUPLEX ,RGMII 1 Fullduplex" "Half-duplex,Full-duplex"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " RGMII0_SPEED ,RGMII 1 Speed" "10Mbps,100Mbps,1000Mbps,?..."
|
|
bitfld.long 0x00 0. " RGMII0_LINK ,RGMII 1 Link Indicator" "Down,Up"
|
|
width 0x0b
|
|
tree.end
|
|
elif (cpuis("DRA62*"))
|
|
tree "CPSW ALE (Ethernet Address Lookup Engine)"
|
|
base ad:0x4A100D00
|
|
width 19.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CPSW_ID_VER,ALE ID Version Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " IDENT ,ALE identification value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MAJOR_VER ,ALE Major Version Value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " MINOR_VER ,ALE Minor Version Value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CPSW_CONTROL,CONTROL Register"
|
|
bitfld.long 0x00 31. " ENABLE_ALE ,Enable ALE" "Drop all packets,Enabled"
|
|
bitfld.long 0x00 30. " CLEAR_TABLE ,Clear ALE address table" "No effect,Clear"
|
|
bitfld.long 0x00 29. " AGE_OUT_NOW ,Age Out Address Table Now" "Has completed,Free up"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EN_P0_UNI_FLOOD ,Enable Port 0 (Host Port) unicast floo" "Do not flood,Flood"
|
|
bitfld.long 0x00 7. " LEARN_NO_VID ,Learn No VID" "Learned,Not learned"
|
|
bitfld.long 0x00 6. " EN_VID0_MODE ,Enable VLAN ID = 0 Mode" "PORT_VLAN,0"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENABLE_OUI_DENY ,Enable OUI Deny Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BYPASS ,ALE Bypass" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RATE_LIMIT_TX ,Rate Limit Transmit mode" "Received,Transmit"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VLAN_AWARE ,Determines what is done if VLAN not found." "Flood,Drop packet"
|
|
bitfld.long 0x00 1. " ENABLE_AUTH_MODE ,Enable MAC Authorization Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE_RATE_LIMIT ,Enable Broadcast and Multicast Rate Limit" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRESCALE,ALE Prescale Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " PRESCALE ,The input clock is divided by this value for use in the multicast/broadcast rate limiters"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "UNKNOWN_VLAN,ADDRESS LOOKUP ENGINE UNKNOWN VLAN REGISTER"
|
|
hexmask.long.byte 0x00 24.--29. 1. " UNKNOWN_FORCE_UNTAGGED_EGRESS ,Unknown VLAN Force Untagged Egress"
|
|
hexmask.long.byte 0x00 16.--21. 1. " UNKNOWN_REG_MCAST_FLOOD_MASK ,Unknown VLAN Registered Multicast Flood Mask"
|
|
hexmask.long.byte 0x00 8.--13. 1. " UNKNOWN_MCAST_FLOOD_MASK ,Unknown VLAN Multicast Flood Mask"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " UNKNOWN_VLAN_MEMBER_LIST ,Unknown VLAN Member List"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TBLCTL,ADDRESS LOOKUP ENGINE TABLE CONTROL"
|
|
bitfld.long 0x00 31. " WRITE_RDZ ,Write Bit" "Read,Write"
|
|
hexmask.long.word 0x00 0.--9. 1. " ENTRY_POINTER ,Table Entry Pointer"
|
|
group.long 0x34++0x23
|
|
line.long 0x00 "TBLW2,ADDRESS LOOKUP ENGINE TABLE WORD 2 REGISTER"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ENTRY71-64 ,Table entry bits 71:64"
|
|
line.long 0x04 "TBLW1,ADDRESS LOOKUP ENGINE TABLE WORD 1 REGISTER"
|
|
line.long 0x08 "TBLW0,ADDRESS LOOKUP ENGINE TABLE WORD 0 REGISTER"
|
|
line.long 0x0c "PORTCTL0,ADDRESS LOOKUP ENGINE PORT 0 CONTROL REGISTER"
|
|
hexmask.long.byte 0x0c 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit"
|
|
hexmask.long.byte 0x0c 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit"
|
|
bitfld.long 0x0C 5. " NO_SA_UPDATE ,No Souce Address Update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward"
|
|
line.long 0x10 "PORTCTL1,ADDRESS LOOKUP ENGINE PORT 1 CONTROL REGISTER"
|
|
hexmask.long.byte 0x10 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit"
|
|
hexmask.long.byte 0x10 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit"
|
|
bitfld.long 0x10 5. " NO_SA_UPDATE ,No Souce Address Update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward"
|
|
line.long 0x14 "PORTCTL2,ADDRESS LOOKUP ENGINE PORT 2 CONTROL REGISTER"
|
|
hexmask.long.byte 0x14 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit"
|
|
hexmask.long.byte 0x14 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit"
|
|
bitfld.long 0x14 5. " NO_SA_UPDATE ,No Souce Address Update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward"
|
|
line.long 0x18 "PORTCTL3,ADDRESS LOOKUP ENGINE PORT 3 CONTROL REGISTER"
|
|
hexmask.long.byte 0x18 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit"
|
|
hexmask.long.byte 0x18 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit"
|
|
bitfld.long 0x18 5. " NO_SA_UPDATE ,No Souce Address Update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled"
|
|
bitfld.long 0x18 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward"
|
|
line.long 0x1c "PORTCTL4,ADDRESS LOOKUP ENGINE PORT 4 CONTROL REGISTER"
|
|
hexmask.long.byte 0x1c 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit"
|
|
hexmask.long.byte 0x1c 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit"
|
|
bitfld.long 0x1c 5. " NO_SA_UPDATE ,No Souce Address Update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled"
|
|
bitfld.long 0x1c 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled"
|
|
bitfld.long 0x1c 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward"
|
|
line.long 0x20 "PORTCTL5,ADDRESS LOOKUP ENGINE PORT 5 CONTROL REGISTER"
|
|
hexmask.long.byte 0x20 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit"
|
|
hexmask.long.byte 0x20 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit"
|
|
bitfld.long 0x20 5. " NO_SA_UPDATE ,No Souce Address Update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled"
|
|
bitfld.long 0x20 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x20 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,?..."
|
|
else
|
|
bitfld.long 0x20 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "CPSW CPDMA (CPPI DMA Controller Module)"
|
|
base ad:0x4A100800
|
|
width 20.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "TX_IDVER,TX IDENTIFICATION AND VERSION REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " TX_IDENT ,TX Identification Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TX_MAJOR_VER ,TX Major Version Value - The value read is the major version number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_MINOR_VER ,TX Minor Version Value - The value read is the minor version number"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TX_CONTROL,TX CONTROL REGISTER"
|
|
bitfld.long 0x00 0. " TX_EN ,TX Enable" "Disabled,Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TX_TEARDOWN,TX TEARDOWN REGISTER"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x00 31. " TX_TDN_RDY ,Tx Teardown Ready" "Not ready,Ready"
|
|
else
|
|
bitfld.long 0x00 31. " TX_TDN_RDY ,Tx Teardown Ready" "Not ready,Ready"
|
|
endif
|
|
bitfld.long 0x00 0.--2. " TX_TDN_CH ,Tx Teardown Channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RX_IDVER,RX IDENTIFICATION AND VERSION REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " RX_IDENT ,RX Identification Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_MAJOR_VER ,RX Major Version Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_MINOR_VER ,RX Minor Version Value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RX_CONTROL,RX CONTROL REGISTER"
|
|
bitfld.long 0x00 0. " RX_EN ,RX DMA Enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RX_TEARDOWN,RX TEARDOWN REGISTER"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x00 31. " RX_TDN_RDY ,RX Teardown Ready" "Not ready,Ready"
|
|
else
|
|
bitfld.long 0x00 31. " RX_TDN_RDY ,RX Teardown Ready" "Not ready,Ready"
|
|
endif
|
|
bitfld.long 0x00 0.--2. " RX_TDN_CH ,Rx Teardown Channel" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CPDMA_SOFT_RESET,SOFT RESET REGISTER"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "No reset,Reset"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DMACONTROL,CPDMA CONTROL REGISTER"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TX_RLIM ,Transmit Rate Limit Channel Bus"
|
|
bitfld.long 0x00 4. " RX_CEF ,RX Copy Error Frames Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CMD_IDLE ,Command Idle" "Not idle,Idle"
|
|
bitfld.long 0x00 2. " RX_OFFLEN_BLOCK ,Receive Offset/Length word write block" "CPPI 3.0,Block all CPDMA"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_OWNERSHIP ,Receive Ownership Write Bit Value" "CPPI 3.0,Buffer descriptor is used"
|
|
bitfld.long 0x00 0. " TX_PTYPE ,Transmit Queue Priority Type " "Robin scheme,Fixed priority"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMASTATUS,CPDMA STATUS REGISTER"
|
|
bitfld.long 0x00 31. " IDLE ,Idle Status Bit" "Transferring,Not transferring"
|
|
bitfld.long 0x00 20.--23. " TX_HOST_ERR_CODE ,TX Host Error Code" "No error,SOP error,Not set in SOP,Zero Without EOP,Zero Buffer Pointer,Zero Buffer Length,Length Error,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_ERR_CH ,TX Host Error Channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--15. " RX_HOST_ERR_CODE ,RX Host Error Code" "No error,Reserved,Ownership bit not set in input buffer,Reserved,Zero Buffer Pointer,Zero buffer length on non-SOP descriptor,SOP buffer length not greater than offset,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " RX_ERR_CH ,RX Host Error Channel" "0,1,2,3,4,5,6,7"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RX_BUFFER_OFFSET,RECEIVE BUFFER OFFSET"
|
|
hexmask.long.word 0x00 0.--15. 1. " RX_BUFFER_OFFSET ,Receive Buffer Offset Value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "EMCONTROL,EMULATION CONTROL"
|
|
bitfld.long 0x00 1. " SOFT ,Emulation Soft Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FREE ,Emulation Free Bit" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TX_PRI0_RATE,TRANSMIT (INGRESS) PRIORITY 0 RATE"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TX_PRI1_RATE,TRANSMIT (INGRESS) PRIORITY 1 RATE"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TX_PRI2_RATE,TRANSMIT (INGRESS) PRIORITY 2 RATE"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TX_PRI3_RATE,TRANSMIT (INGRESS) PRIORITY 3 RATE"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TX_PRI4_RATE,TRANSMIT (INGRESS) PRIORITY 4 RATE"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TX_PRI5_RATE,TRANSMIT (INGRESS) PRIORITY 5 RATE"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TX_PRI6_RATE,TRANSMIT (INGRESS) PRIORITY 6 RATE"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TX_PRI7_RATE,TRANSMIT (INGRESS) PRIORITY 7 RATE"
|
|
hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count"
|
|
hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "TX_INTSTAT_RAW,CPDMA_INT TX INTERRUPT STATUS REGISTER"
|
|
bitfld.long 0x00 7. " TX7_PEND ,TX7_PEND raw int read (before mask)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TX6_PEND ,TX6_PEND raw int read (before mask)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TX5_PEND ,TX5_PEND raw int read (before mask)." "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TX4_PEND ,TX4_PEND raw int read (before mask)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TX3_PEND ,TX3_PEND raw int read (before mask)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TX2_PEND ,TX2_PEND raw int read (before mask)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX1_PEND ,TX1_PEND raw int read (before mask)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TX0_PEND ,TX0_PEND raw int read (before mask)" "Disabled,Enabled"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TX_INTSTAT_MASKED,CPDMA_INT TX INTERRUPT STATUS REGISTER"
|
|
bitfld.long 0x00 7. " TX7_PEND ,TX7_PEND masked interrupt read" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TX6_PEND ,TX6_PEND masked interrupt read" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TX5_PEND ,TX5_PEND masked interrupt read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TX4_PEND ,TX4_PEND masked interrupt read" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TX3_PEND ,TX3_PEND masked interrupt read" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TX2_PEND ,TX2_PEND masked interrupt read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX1_PEND ,TX1_PEND masked interrupt read" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TX0_PEND ,TX0_PEND masked interrupt read" "Disabled,Enabled"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TX_INTMASK_SET,CPDMA_INT TX INTERRUPT MASK SET REGISTER"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x00 7. " TX7_MASK ,TX Channel 7 Mask" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " TX6_MASK ,TX Channel 6 Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TX5_MASK ,TX Channel 5 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " TX4_MASK ,TX Channel 4 Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TX3_MASK ,TX Channel 3 Mask" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " TX2_MASK ,TX Channel 2 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX1_MASK ,TX Channel 1 Mask" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " TX0_MASK ,TX Channel 0 Mask" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 7. " TX7_MASK ,TX Channel 7 Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TX6_MASK ,TX Channel 6 Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TX5_MASK ,TX Channel 5 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TX4_MASK ,TX Channel 4 Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TX3_MASK ,TX Channel 3 Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TX2_MASK ,TX Channel 2 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX1_MASK ,TX Channel 1 Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TX0_MASK ,TX Channel 0 Mask" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TX_INTMASK_CLEAR,CPDMA_INT TX INTERRUPT MASK CLEAR REGISTER"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
bitfld.long 0x00 7. " TX7_MASK ,TX Channel 7 Mask" "Enabled,Disabled"
|
|
rbitfld.long 0x00 6. " TX6_MASK ,TX Channel 6 Mask" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " TX5_MASK ,TX Channel 5 Mask" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " TX4_MASK ,TX Channel 4 Mask" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " TX3_MASK ,TX Channel 3 Mask" "Enabled,Disabled"
|
|
rbitfld.long 0x00 2. " TX2_MASK ,TX Channel 2 Mask" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX1_MASK ,TX Channel 1 Mask" "Enabled,Disabled"
|
|
rbitfld.long 0x00 0. " TX0_MASK ,TX Channel 0 Mask" "Enabled,Disabled"
|
|
else
|
|
bitfld.long 0x00 7. " TX7_MASK ,TX Channel 7 Mask" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " TX6_MASK ,TX Channel 6 Mask" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " TX5_MASK ,TX Channel 5 Mask" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TX4_MASK ,TX Channel 4 Mask" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " TX3_MASK ,TX Channel 3 Mask" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " TX2_MASK ,TX Channel 2 Mask" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX1_MASK ,TX Channel 1 Mask" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " TX0_MASK ,TX Channel 0 Mask" "Enabled,Disabled"
|
|
endif
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "CPDMA_IN_VECTOR,CPDMA_INT INPUT VECTOR"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CPDMA_EOI_VECTOR,CPDMA_INT END OF INTERRUPT VECTOR"
|
|
bitfld.long 0x00 0.--4. " DMA_EOI_VECTOR ,DMA End of Interrupt Vector " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "RX_INTSTAT_RAW,CPDMA_INT RX INTERRUPT STATUS REGISTER "
|
|
bitfld.long 0x00 15. " RX7_THRESH_PEND ,RX7_THRESH_PEND raw int read " "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RX6_THRESH_PEND ,RX6_THRESH_PEND raw int read " "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RX5_THRESH_PEND ,RX5_THRESH_PEND raw int read " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX4_THRESH_PEND ,RX4_THRESH_PEND raw int read " "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RX3_THRESH_PEND ,RX3_THRESH_PEND raw int read " "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RX2_THRESH_PEND ,RX2_THRESH_PEND raw int read " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX1_THRESH_PEND ,RX1_THRESH_PEND raw int read " "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RX0_THRESH_PEND ,RX0_THRESH_PEND raw int read " "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RX7_PEND ,RX7_PEND raw int read " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RX6_PEND ,RX6_PEND raw int read " "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RX5_PEND ,RX5_PEND raw int read " "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RX4_PEND ,RX4_PEND raw int read " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX3_PEND ,RX3_PEND raw int read " "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RX2_PEND ,RX2_PEND raw int read " "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RX1_PEND ,RX1_PEND raw int read " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RX0_PEND ,RX0_PEND raw int read " "Disabled,Enabled"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "RX_INTSTAT_MASKED,CPDMA_INT RX INTERRUPT STATUS REGISTER"
|
|
bitfld.long 0x00 15. " RX7_THRESH_PEND ,RX7_THRESH_PEND masked int read" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RX6_THRESH_PEND ,RX6_THRESH_PEND masked int read" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RX5_THRESH_PEND ,RX5_THRESH_PEND masked int read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX4_THRESH_PEND ,RX4_THRESH_PEND masked int read" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RX3_THRESH_PEND ,RX3_THRESH_PEND masked int read" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RX2_THRESH_PEND ,RX2_THRESH_PEND masked int read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX1_THRESH_PEND ,RX1_THRESH_PEND masked int read" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RX0_THRESH_PEND ,RX0_THRESH_PEND masked int read" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RX7_PEND ,RX7_PEND masked int read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RX6_PEND ,RX6_PEND masked int read" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RX5_PEND ,RX5_PEND masked int read" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RX4_PEND ,RX4_PEND masked int read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX3_PEND ,RX3_PEND masked int read" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RX2_PEND ,RX2_PEND masked int read" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RX1_PEND ,RX1_PEND masked int read" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RX0_PEND ,RX0_PEND masked int read" "Disabled,Enabled"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RX_INTMASK_SET,CPDMA_INT RX INTERRUPT MASK SET REGISTER"
|
|
bitfld.long 0x00 15. " RX7_THRESH_PEND_MASK ,RX Channel 7 Threshold Pending Int. Mask " "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RX6_THRESH_PEND_MASK ,RX Channel 6 Threshold Pending Int. Mask " "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RX5_THRESH_PEND_MASK ,RX Channel 5 Threshold Pending Int. Mask " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX4_THRESH_PEND_MASK ,RX Channel 4 Threshold Pending Int. Mask " "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RX3_THRESH_PEND_MASK ,RX Channel 3 Threshold Pending Int. Mask " "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RX2_THRESH_PEND_MASK ,RX Channel 2 Threshold Pending Int. Mask " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX1_THRESH_PEND_MASK ,RX Channel 1 Threshold Pending Int. Mask " "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RX0_THRESH_PEND_MASK ,RX Channel 0 Threshold Pending Int. Mask " "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RX7_PEND_MASK ,RX Channel 7 Pending Int. Mask " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RX6_PEND_MASK ,RX Channel 6 Pending Int. Mask " "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RX5_PEND_MASK ,RX Channel 5 Pending Int. Mask " "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RX4_PEND_MASK ,RX Channel 4 Pending Int. Mask " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX3_PEND_MASK ,RX Channel 3 Pending Int. Mask " "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RX2_PEND_MASK ,RX Channel 2 Pending Int. Mask " "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RX1_PEND_MASK ,RX Channel 1 Pending Int. Mask " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RX0_PEND_MASK ,RX Channel 0 Pending Int. Mask " "Disabled,Enabled"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "RX_INTMASK_CLEAR,CPDMA_INT RX INTERRUPT MASK CLEAR REGISTER"
|
|
bitfld.long 0x00 15. " RX7_THRESH_PEND_MASK ,RX Channel 7 Threshold Pending Int. Mask " "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " RX6_THRESH_PEND_MASK ,RX Channel 6 Threshold Pending Int. Mask " "Enabled,Disabled"
|
|
bitfld.long 0x00 13. " RX5_THRESH_PEND_MASK ,RX Channel 5 Threshold Pending Int. Mask " "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX4_THRESH_PEND_MASK ,RX Channel 4 Threshold Pending Int. Mask " "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " RX3_THRESH_PEND_MASK ,RX Channel 3 Threshold Pending Int. Mask " "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " RX2_THRESH_PEND_MASK ,RX Channel 2 Threshold Pending Int. Mask " "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX1_THRESH_PEND_MASK ,RX Channel 1 Threshold Pending Int. Mask " "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " RX0_THRESH_PEND_MASK ,RX Channel 0 Threshold Pending Int. Mask " "Enabled,Disabled"
|
|
bitfld.long 0x00 7. " RX7_PEND_MASK ,RX Channel 7 Pending Int. Mask " "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RX6_PEND_MASK ,RX Channel 6 Pending Int. Mask " "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " RX5_PEND_MASK ,RX Channel 5 Pending Int. Mask " "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " RX4_PEND_MASK ,RX Channel 4 Pending Int. Mask " "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX3_PEND_MASK ,RX Channel 3 Pending Int. Mask " "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RX2_PEND_MASK ,RX Channel 2 Pending Int. Mask " "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " RX1_PEND_MASK ,RX Channel 1 Pending Int. Mask " "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RX0_PEND_MASK ,RX Channel 0 Pending Int. Mask " "Enabled,Disabled"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DMA_INTSTAT_RAW,CPDMA_INT DMA INTERRUPT STATUS REGISTER "
|
|
bitfld.long 0x00 1. " HOST_PEND ,Host Pending Interrupt " "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " STAT_PEND ,Statistics Pending Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "DMA_INTSTAT_MASKED,CPDMA_INT DMA INTERRUPT STATUS REGISTER"
|
|
bitfld.long 0x00 1. " HOST_PEND ,Host Pending Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " STAT_PEND ,Statistics Pending Interrupt" "Disabled,Enabled"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "DMA_INTMASK_SET,CPDMA_INT DMA INTERRUPT MASK SET REGISTER"
|
|
bitfld.long 0x00 1. " HOST_ERR_INT_MASK ,Host Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x00 0. " STAT_INT_MASK ,Statistics Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 0. " STAT_INT_MASK ,Statistics Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "DMA_INTMASK_CLEAR,CPDMA_INT DMA INTERRUPT MASK CLEAR REGISTER"
|
|
bitfld.long 0x00 1. " HOST_ERR_INT_MASK ,Host Error Interrupt Mask " "Enabled,Disabled"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x00 0. " STAT_INT_MASK ,Statistics Interrupt Mask " "Enabled,Disabled"
|
|
else
|
|
bitfld.long 0x00 0. " STAT_INT_MASK ,Statistics Interrupt Mask " "Enabled,Disabled"
|
|
endif
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RX0_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "RX1_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "RX2_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "RX3_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "RX4_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "RX5_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "RX6_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "RX7_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold"
|
|
wgroup.long 0xE0++0x03
|
|
line.long 0x00 "RX0_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count"
|
|
wgroup.long 0xE4++0x03
|
|
line.long 0x00 "RX1_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count"
|
|
wgroup.long 0xE8++0x03
|
|
line.long 0x00 "RX2_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count"
|
|
wgroup.long 0xEC++0x03
|
|
line.long 0x00 "RX3_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count"
|
|
wgroup.long 0xF0++0x03
|
|
line.long 0x00 "RX4_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count"
|
|
wgroup.long 0xF4++0x03
|
|
line.long 0x00 "RX5_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 5"
|
|
hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count"
|
|
wgroup.long 0xF8++0x03
|
|
line.long 0x00 "RX6_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 6"
|
|
hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count"
|
|
wgroup.long 0xFC++0x03
|
|
line.long 0x00 "RX7_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 7"
|
|
hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count"
|
|
sif (!cpuis("AM335*")&&!cpuis("DRA62*"))
|
|
group.long 0xA00++0x7F
|
|
line.long 0x00 "TX0_HDP,CPDMA_STATERAM TX CHANNEL 0 HEAD DESC POINTER Register"
|
|
line.long 0x04 "TX1_HDP,CPDMA_STATERAM TX CHANNEL 1 HEAD DESC POINTER Register"
|
|
line.long 0x08 "TX2_HDP,CPDMA_STATERAM TX CHANNEL 2 HEAD DESC POINTER Register"
|
|
line.long 0x0C "TX3_HDP,CPDMA_STATERAM TX CHANNEL 3 HEAD DESC POINTER Register"
|
|
line.long 0x10 "TX4_HDP,CPDMA_STATERAM TX CHANNEL 4 HEAD DESC POINTER Register"
|
|
line.long 0x14 "TX5_HDP,CPDMA_STATERAM TX CHANNEL 5 HEAD DESC POINTER Register"
|
|
line.long 0x18 "TX6_HDP,CPDMA_STATERAM TX CHANNEL 6 HEAD DESC POINTER Register"
|
|
line.long 0x1C "TX7_HDP,CPDMA_STATERAM TX CHANNEL 7 HEAD DESC POINTER Register"
|
|
line.long 0x20 "RX0_HDP,CPDMA_STATERAM RX 0 CHANNEL 0 HEAD DESC POINTER Register"
|
|
line.long 0x24 "RX1_HDP,CPDMA_STATERAM RX 1 CHANNEL 1 HEAD DESC POINTER Register"
|
|
line.long 0x28 "RX2_HDP,CPDMA_STATERAM RX 2 CHANNEL 2 HEAD DESC POINTER Register"
|
|
line.long 0x2C "RX3_HDP,CPDMA_STATERAM RX 3 CHANNEL 3 HEAD DESC POINTER Register"
|
|
line.long 0x30 "RX4_HDP,CPDMA_STATERAM RX 4 CHANNEL 4 HEAD DESC POINTER Register"
|
|
line.long 0x34 "RX5_HDP,CPDMA_STATERAM RX 5 CHANNEL 5 HEAD DESC POINTER Register"
|
|
line.long 0x38 "RX6_HDP,CPDMA_STATERAM RX 6 CHANNEL 6 HEAD DESC POINTER Register"
|
|
line.long 0x3C "RX7_HDP,CPDMA_STATERAM RX 7 CHANNEL 7 HEAD DESC POINTER Register"
|
|
line.long 0x40 "TX0_CP,CPDMA_STATERAM TX CHANNEL 0 COMPLETION POINTER REGISTER"
|
|
line.long 0x44 "TX1_CP,CPDMA_STATERAM TX CHANNEL 1 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x48 "TX2_CP,CPDMA_STATERAM TX CHANNEL 2 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x4C "TX3_CP,CPDMA_STATERAM TX CHANNEL 3 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x50 "TX4_CP,CPDMA_STATERAM TX CHANNEL 4 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x54 "TX5_CP,CPDMA_STATERAM TX CHANNEL 5 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x58 "TX6_CP,CPDMA_STATERAM TX CHANNEL 6 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x5C "TX7_CP,CPDMA_STATERAM TX CHANNEL 7 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x60 "RX0_CP,CPDMA_STATERAM RX CHANNEL 0 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x64 "RX1_CP,CPDMA_STATERAM RX CHANNEL 1 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x68 "RX2_CP,CPDMA_STATERAM RX CHANNEL 2 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x6C "RX3_CP,CPDMA_STATERAM RX CHANNEL 3 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x70 "RX4_CP,CPDMA_STATERAM RX CHANNEL 4 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x74 "RX5_CP,CPDMA_STATERAM RX CHANNEL 5 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x78 "RX6_CP,CPDMA_STATERAM RX CHANNEL 6 COMPLETION POINTER REGISTER Register"
|
|
line.long 0x7C "RX7_CP,CPDMA_STATERAM RX CHANNEL 7 COMPLETION POINTER REGISTER Register"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "CPSW CPTS (Ethernet Time Sync Module)"
|
|
base ad:0x4A100C00
|
|
width 21.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CPTS_IDVER,IDENTIFICATION AND VERSION REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " TX_IDENT ,TX Identification Value"
|
|
hexmask.long.byte 0x00 11.--15. 1. " REG_RTL_VERSION ,RTL Version"
|
|
hexmask.long.byte 0x00 8.--10. 1. " REG_MAJOR_REVISION ,Major Revision"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " MINOR_VER ,Minor Version Value"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CPTS_CONTROL,TIME SYNC CONTROL REGISTER"
|
|
bitfld.long 0x00 11. " HW4_TS_PUSH_EN ,Hardware push 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HW3_TS_PUSH_EN ,Hardware push 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HW2_TS_PUSH_EN ,Hardware push 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HW1_TS_PUSH_EN ,Hardware push 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_TEST ,Interrupt Test" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CPTS_EN ,Time Sync Enable" "Disabled,Enabled"
|
|
sif (!cpuis("DRA62*")&&!cpuis("AM335*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CPTS_RFTCLK_SEL,REFERENCE CLOCK SELECT REGISTER"
|
|
bitfld.long 0x00 0.--4. " RFTCLK_SEL ,Reference Clock Select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
endif
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CPTS_TS_PUSH,TIME STAMP EVENT PUSH REGISTER"
|
|
bitfld.long 0x00 0. " TS_PUSH ,Time stamp event push" "No effect,Push"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CPTS_TS_LOAD_VAL,TIME STAMP LOAD VALUE REGISTER"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "CPTS_TS_LOAD_EN,TIME STAMP LOAD ENABLE REGISTER"
|
|
bitfld.long 0x00 0. " TS_LOAD_EN ,Time Stamp Load" "Disable,Enable"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CPTS_INTSTAT_RAW,TIME SYNC INTERRUPT STATUS RAW REGISTER"
|
|
bitfld.long 0x00 0. " TS_PEND_RAW ,TS_PEND_RAW int read " "Enabled,Disabled"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CPTS_INTSTAT_MASKED,TIME SYNC INTERRUPT STATUS MASKED REGISTER"
|
|
bitfld.long 0x00 0. " TS_PEND ,TS_PEND masked interrupt read" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CPTS_INT_ENABLE,TIME SYNC INTERRUPT ENABLE REGISTER"
|
|
bitfld.long 0x00 0. " TS_PEND_EN ,TS_PEND masked interrupt enable" "Disabled,Enabled"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "CPTS_EVENT_POP,EVENT INTERRUPT POP REGISTER"
|
|
bitfld.long 0x00 0. " EVENT_POP ,Event Pop" "Disabled,Enabled"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CPTS_EVENT_LOW,LOWER 32-BITS OF THE EVENT VALUE"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CPTS_EVENT_HIGH,UPPER 32-BITS OF THE EVENT VALUE"
|
|
bitfld.long 0x00 24.--28. " PORT_NUMBER ,Port Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20.--23. " EVENT_TYPE ,Time Sync Event Type," "Time Stamp Push Event,Time Stamp Rollover Event,Time Stamp Half Rollover Event,Hardware Time Stamp Push Event,Ethernet Receive Event,Ethernet Transmit Event,?..."
|
|
bitfld.long 0x00 16.--19. " MESSAGE_TYPE ,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " SEQUENCE_ID ,The 16-bit sequence id is the value that was contained in an ethernet transmit or receivetime sync packet"
|
|
width 0xb
|
|
tree.end
|
|
tree "CPSW PORT (Ethernet SS - Ethernet Switch Port Control)"
|
|
tree "PORT 0"
|
|
base ad:0x4A100100
|
|
width 21.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P0_CONTROL,CPSW PORT 0 CONTROL REGISTER"
|
|
bitfld.long 0x00 28.--30. " P0_DLR_CPDMA_CH ,Port 0 DLR CPDMA Channel This field indicates the CPDMA channel that DLR packets will be received on" "0,1,2,3,4,5,6,7"
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|
textline " "
|
|
bitfld.long 0x00 24. " P0_PASS_PRI_TAGGED ,Port 0 Pass Priority Tagged" "P0_PORT_VLAN[11:0],Unchanged"
|
|
bitfld.long 0x00 21. " P0_VLAN_LTYPE2_EN ,Port 0 VLAN LTYPE 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P0_VLAN_LTYPE1_EN ,Port 0 VLAN LTYPE 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P0_DSCP_PRI_EN ,Port 0 DSCP Priority Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P0_MAX_BLKS,CPSW PORT 0 MAXIMUM FIFO BLOCKS REGISTER"
|
|
bitfld.long 0x00 4.--8. " P0_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " P0_RX_MAX_BLKS ,Receive FIFO Maximum Blocks" "Reserved,Reserved,Reserved,3,4,5,6,?..."
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "P0_BLK_CNT,CPSW PORT 0 FIFO BLOCK USAGE COUNT (READ ONLY)"
|
|
bitfld.long 0x00 4.--8. " P0_TX_BLK_CNT ,This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--3. " P0_RX_BLK_CNT ,This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x10++0x03
|
|
line.long 0x00 "P0_TX_IN_CTL,CPSW PORT 0 TRANSMIT FIFO CONTROL"
|
|
bitfld.long 0x00 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select" "Normal priority mode,Dual MAC mode,Rate Limit mode,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TX_BLKS_REM ,Transmit FIFO Input Blocks to subtract in dual mac mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "P0_PORT_VLAN,CPSW PORT 0 VLAN REGISTER"
|
|
bitfld.long 0x00 13.--15. " PORT_PRI ,Port VLAN Priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. " PORT_CFI ,Port CFI bit" "Enabled,Disabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " PORT_VID ,Port VLAN ID"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "P0_TX_PRI_MAP,CPSW PORT 0 TX HEADER PRI TO SWITCH PRI MAPPING REGISTER"
|
|
bitfld.long 0x00 28.--29. " PRI7 ,Priority 7 - A packet header priority of 0x7 is given this switch queue pri" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " PRI6 ,Priority 6 - A packet header priority of 0x6 is given this switch queue pri" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " PRI5 ,Priority 5 - A packet header priority of 0x5 is given this switch queue pri" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " PRI4 ,Priority 4 - A packet header priority of 0x4 is given this switch queue pri" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " PRI3 ,Priority 3 - A packet header priority of 0x3 is given this switch queue pri" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " PRI2 ,Priority 2 - A packet header priority of 0x2 is given this switch queue pri" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PRI1 ,Priority 1 - A packet header priority of 0x1 is given this switch queue pri" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " PRI0 ,Priority 0 - A packet header priority of 0x0 is given this switch queue pri" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "P0_CPDMA_TX_PRI_MAP,CPSW CPDMA TX (PORT 0 RX) PKT PRIORITY TO HEADER PRIORITY"
|
|
bitfld.long 0x00 28.--30. " PRI7 ,Priority 7 - A packet pri of 0x7 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI6 ,Priority 6 - A packet pri of 0x6 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI5 ,Priority 5 - A packet pri of 0x5 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI4 ,Priority 4 - A packet pri of 0x4 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI3 ,Priority 3 - A packet pri of 0x3 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI2 ,Priority 2 - A packet pri of 0x2 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI1 ,Priority 1 - A packet pri of 0x1 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI0 ,Priority 0 - A packet pri of 0x0 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "P0_CPDMA_RX_CH_MAP,CPSW CPDMA RX (PORT 0 TX) SWITCH PRIORITY TO DMA CHANNEL"
|
|
bitfld.long 0x00 28.--30. " P2_PRI3 ,Port 2 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " P2_PRI2 ,Port 2 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " P2_PRI1 ,Port 2 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " P2_PRI0 ,Port 2 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " P1_PRI3 ,Port 1 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " P1_PRI2 ,Port 1 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " P1_PRI1 ,Port 1 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " P1_PRI0 ,Port 1 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "P0_RX_DSCP_PRI_MAP0,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0 "
|
|
bitfld.long 0x00 28.--30. " PRI7 ,Priority 7 - A packet TOS of 0d7 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI6 ,Priority 6 - A packet TOS of 0d6 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI5 ,Priority 5 - A packet TOS of 0d5 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI4 ,Priority 4 - A packet TOS of 0d4 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI3 ,Priority 3 - A packet TOS of 0d3 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI2 ,Priority 2 - A packet TOS of 0d2 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI1 ,Priority 1 - A packet TOS of 0d1 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI0 ,Priority 0 - A packet TOS of 0d0 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "P0_RX_DSCP_PRI_MAP1,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1"
|
|
bitfld.long 0x00 28.--30. " PRI15 ,Priority 15 - A packet TOS of 0d15 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI14 ,Priority 14 - A packet TOS of 0d14 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI13 ,Priority 13 - A packet TOS of 0d13 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI12 ,Priority 12 - A packet TOS of 0d12 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI11 ,Priority 11 - A packet TOS of 0d11 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI10 ,Priority 10 - A packet TOS of 0d10 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI9 ,Priority 9 - A packet TOS of 0d9 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI8 ,Priority 8 - A packet TOS of 0d8 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "P0_RX_DSCP_PRI_MAP2,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2"
|
|
bitfld.long 0x00 28.--30. " PRI23 ,Priority 23 - A packet TOS of 0d23 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI22 ,Priority 22 - A packet TOS of 0d22 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI21 ,Priority 21 - A packet TOS of 0d21 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI20 ,Priority 20 - A packet TOS of 0d20 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI19 ,Priority 19 - A packet TOS of 0d19 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI18 ,Priority 18 - A packet TOS of 0d18 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI17 ,Priority 17 - A packet TOS of 0d17 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI16 ,Priority 16 - A packet TOS of 0d16 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "P0_RX_DSCP_PRI_MAP3,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3"
|
|
bitfld.long 0x00 28.--30. " PRI31 ,Priority 31 - A packet TOS of 0d31 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI30 ,Priority 30 - A packet TOS of 0d30 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI29 ,Priority 29 - A packet TOS of 0d39 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI28 ,Priority 28 - A packet TOS of 0d28 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI27 ,Priority 27 - A packet TOS of 0d27 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI26 ,Priority 26 - A packet TOS of 0d26 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI25 ,Priority 25 - A packet TOS of 0d25 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI24 ,Priority 24 - A packet TOS of 0d24 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "P0_RX_DSCP_PRI_MAP4,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4"
|
|
bitfld.long 0x00 28.--30. " PRI39 ,Priority 39 - A packet TOS of 0d39 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI38 ,Priority 38 - A packet TOS of 0d38 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI37 ,Priority 37 - A packet TOS of 0d37 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI36 ,Priority 36 - A packet TOS of 0d36 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI35 ,Priority 35 - A packet TOS of 0d35 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI34 ,Priority 34 - A packet TOS of 0d34 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI33 ,Priority 33 - A packet TOS of 0d33 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI32 ,Priority 32 - A packet TOS of 0d32 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "P0_RX_DSCP_PRI_MAP5,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5"
|
|
bitfld.long 0x00 28.--30. " PRI47 ,Priority 47 - A packet TOS of 0d47 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI46 ,Priority 46 - A packet TOS of 0d46 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI45 ,Priority 45 - A packet TOS of 0d45 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI44 ,Priority 44 - A packet TOS of 0d44 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI43 ,Priority 43 - A packet TOS of 0d43 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI42 ,Priority 42 - A packet TOS of 0d42 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI41 ,Priority 41 - A packet TOS of 0d41 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI40 ,Priority 40 - A packet TOS of 0d40 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "P0_RX_DSCP_PRI_MAP6,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6"
|
|
bitfld.long 0x00 28.--30. " PRI55 ,Priority 55 - A packet TOS of 0d55 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI54 ,Priority 54 - A packet TOS of 0d54 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI53 ,Priority 53 - A packet TOS of 0d53 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI52 ,Priority 52 - A packet TOS of 0d52 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI51 ,Priority 51 - A packet TOS of 0d51 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI50 ,Priority 50 - A packet TOS of 0d50 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI49 ,Priority 49 - A packet TOS of 0d49 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI48 ,Priority 48 - A packet TOS of 0d48 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "P0_RX_DSCP_PRI_MAP7,CPSW PORT 0 TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE"
|
|
bitfld.long 0x00 28.--30. " PRI63 ,Priority 63 - A packet TOS of 0d63 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI62 ,Priority 62 - A packet TOS of 0d62 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI61 ,Priority 61 - A packet TOS of 0d61 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI60 ,Priority 60 - A packet TOS of 0d60 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI59 ,Priority 59 - A packet TOS of 0d59 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI58 ,Priority 58 - A packet TOS of 0d58 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI57 ,Priority 57 - A packet TOS of 0d57 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI56 ,Priority 56 - A packet TOS of 0d56 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
width 0xb
|
|
tree.end
|
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tree "PORT 1"
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|
base ad:0x4A100200
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width 21.
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group.long 0x00++0x03
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line.long 0x00 "P1_CONTROL,CPSW PORT 1 CONTROL REGISTER"
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bitfld.long 0x00 24. " P1_PASS_PRI_TAGGED ,Port 1 Pass Priority Tagged" "P1_PORT_VLAN[11:0],Unchanged"
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bitfld.long 0x00 21. " P1_VLAN_LTYPE2_EN ,Port 1 VLAN LTYPE 2 enable" "Disabled,Enabled"
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bitfld.long 0x00 20. " P1_VLAN_LTYPE1_EN ,Port 1 VLAN LTYPE 1 enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 16. " P1_DSCP_PRI_EN ,Port 1 DSCP Priority Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 14. " P1_TS_320 ,Port 1 Time Sync Destination Port Number 320 enable" "Disabled,Annex D (UDP/IPv4)"
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bitfld.long 0x00 13. " P1_TS_319 ,Port 1 Time Sync Destination Port Number 319 enable" "Disabled,Annex D (UDP/IPv4)"
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bitfld.long 0x00 12. " P1_TS_132 ,Port 1 Time Sync Destination IP Address 132 enable" "Disabled,Annex D (UDP/IPv4)"
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textline " "
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bitfld.long 0x00 11. " P1_TS_131 ,Port 1 Time Sync Destination IP Address 131 enable" "Disabled,Annex D (UDP/IPv4)"
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bitfld.long 0x00 10. " P1_TS_130 ,Port 1 Time Sync Destination IP Address 130 enable" "Disabled,Annex D (UDP/IPv4)"
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textline " "
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bitfld.long 0x00 9. " P1_TS_129 ,Port 1 Time Sync Destination IP Address 129 enable" "Disabled,Annex D (UDP/IPv4)"
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bitfld.long 0x00 8. " P1_TS_TTL_NONZERO ,Port #1 Time Sync Time To Live Non-zero enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 4. " P1_TS_ANNEX_D_EN ,Port 1 Time Sync Annex D enable" "Disabled,Annex D (UDP/IPv4)"
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sif (cpuis("DRA62*")||cpuis("AM335*"))
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rbitfld.long 0x00 3. " P1_TS_LTYPE2_EN ,Port 1 Time Sync LTYPE 2 enable" "Disabled,Enabled"
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else
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bitfld.long 0x00 3. " P1_TS_LTYPE2_EN ,Port 1 Time Sync LTYPE 2 enable" "Disabled,Enabled"
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endif
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bitfld.long 0x00 2. " P1_TS_LTYPE1_EN ,Port 1 Time Sync LTYPE 1" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 1. " P1_TS_TX_EN ,Port 1 Time Sync Transmit Enable 0 " "Disabled,Enabled"
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bitfld.long 0x00 0. " P1_TS_RX_EN ,Port 1 Time Sync Receive Enable" "Disabled,Enabled"
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group.long 0x08++0x03
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line.long 0x00 "P1_MAX_BLKS,CPSW PORT 1 MAXIMUM FIFO BLOCKS REGISTER"
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bitfld.long 0x00 4.--8. " P1_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--3. " P1_RX_MAX_BLKS ,Receive FIFO Maximum Blocks" "Reserved,Reserved,Reserved,3,4,5,6,?..."
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rgroup.long 0x0C++0x03
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line.long 0x00 "P1_BLK_CNT,CPSW PORT 1 FIFO BLOCK USAGE COUNT (READ ONLY)"
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bitfld.long 0x00 4.--8. " P1_TX_BLK_CNT ,This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--3. " P1_RX_BLK_CNT ,This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x10++0x03
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line.long 0x00 "P1_TX_IN_CTL,CPSW PORT 1 TRANSMIT FIFO CONTROL"
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bitfld.long 0x00 24.--27. " HOST_BLKS_REM ,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select" "Normal priority mode,Reserved,Rate Limit mode,?..."
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textline " "
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bitfld.long 0x00 12.--15. " TX_BLKS_REM ,Transmit FIFO Input Blocks to subtract in dual mac mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue"
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group.long 0x14++0x03
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line.long 0x00 "P1_PORT_VLAN,CPSW PORT 1 VLAN REGISTER"
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bitfld.long 0x00 13.--15. " PORT_PRI ,Port VLAN Priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12. " PORT_CFI ,Port CFI bit" "Enabled,Disabled"
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hexmask.long.word 0x00 0.--11. 1. " PORT_VID ,Port VLAN ID"
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group.long 0x18++0x03
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line.long 0x00 "P1_TX_PRI_MAP,CPSW PORT 1 TX HEADER PRI TO SWITCH PRI MAPPING REGISTER"
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bitfld.long 0x00 28.--29. " PRI7 ,Priority 7 - A packet header priority of 0x7 is given this switch queue pri" "0,1,2,3"
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bitfld.long 0x00 24.--25. " PRI6 ,Priority 6 - A packet header priority of 0x6 is given this switch queue pri" "0,1,2,3"
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bitfld.long 0x00 20.--21. " PRI5 ,Priority 5 - A packet header priority of 0x5 is given this switch queue pri" "0,1,2,3"
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bitfld.long 0x00 16.--17. " PRI4 ,Priority 4 - A packet header priority of 0x4 is given this switch queue pri" "0,1,2,3"
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textline " "
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bitfld.long 0x00 12.--13. " PRI3 ,Priority 3 - A packet header priority of 0x3 is given this switch queue pri" "0,1,2,3"
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bitfld.long 0x00 8.--9. " PRI2 ,Priority 2 - A packet header priority of 0x2 is given this switch queue pri" "0,1,2,3"
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bitfld.long 0x00 4.--5. " PRI1 ,Priority 1 - A packet header priority of 0x1 is given this switch queue pri" "0,1,2,3"
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bitfld.long 0x00 0.--1. " PRI0 ,Priority 0 - A packet header priority of 0x0 is given this switch queue pri" "0,1,2,3"
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group.long 0x1C++0x03
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line.long 0x00 "P1_TS_SEQ_MTYPE,TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE REGISTER"
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hexmask.long.byte 0x00 16.--21. 1. " P1_TS_SEQ_ID_OFFSET ,Port 1 Time Sync Sequence ID Offset"
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hexmask.long.word 0x00 0.--15. 1. " P1_TS_MSG_TYPE_EN ,Port 1 Time Sync Message Type Enable"
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group.long 0x20++0x03
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line.long 0x00 "P1_SA_LO,SOURCE ADDRESS LOW REGISTER"
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hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_7_0 ,Source Address bits 0:7"
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hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR_15_8 ,Source Address bits 8:15"
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group.long 0x24++0x03
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line.long 0x00 "P1_SA_HI,CPSW CPGMAC_SL1 SOURCE ADDRESS HIGH REGISTER"
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hexmask.long.byte 0x00 24.--31. 1. " MACSRCADDR_23_16 ,Source Address bits 23:16"
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hexmask.long.byte 0x00 16.--23. 1. " MACSRCADDR_31_24 ,Source Address bits 31:24"
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|
hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_39_32 ,Source Address bits 39:32"
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hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR_47_40 ,Source Address bits 47:40 "
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group.long 0x28++0x03
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line.long 0x00 "P1_SEND_PERCENT,CPSW PORT 1 TRANSMIT QUEUE SEND PERCENTAGES"
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hexmask.long.byte 0x00 16.--22. 1. " PRI3_SEND_PERCENT ,SPriority 3 Transmit Percentage"
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hexmask.long.byte 0x00 8.--14. 1. " PRI2_SEND_PERCENT ,SPriority 2 Transmit Percentage"
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|
hexmask.long.byte 0x00 0.--6. 1. " PRI1_SEND_PERCENT ,SPriority 1 Transmit Percentage"
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|
group.long 0x30++0x03
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|
line.long 0x00 "P1_RX_DSCP_PRI_MAP0,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0 "
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bitfld.long 0x00 28.--30. " PRI7 ,Priority 7 - A packet TOS of 0d7 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. " PRI6 ,Priority 6 - A packet TOS of 0d6 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20.--22. " PRI5 ,Priority 5 - A packet TOS of 0d5 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " PRI4 ,Priority 4 - A packet TOS of 0d4 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 12.--14. " PRI3 ,Priority 3 - A packet TOS of 0d3 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " PRI2 ,Priority 2 - A packet TOS of 0d2 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4.--6. " PRI1 ,Priority 1 - A packet TOS of 0d1 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " PRI0 ,Priority 0 - A packet TOS of 0d0 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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group.long 0x34++0x03
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line.long 0x00 "P1_RX_DSCP_PRI_MAP1,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1"
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bitfld.long 0x00 28.--30. " PRI15 ,Priority 15 - A packet TOS of 0d15 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. " PRI14 ,Priority 14 - A packet TOS of 0d14 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20.--22. " PRI13 ,Priority 13 - A packet TOS of 0d13 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " PRI12 ,Priority 12 - A packet TOS of 0d12 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 12.--14. " PRI11 ,Priority 11 - A packet TOS of 0d11 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " PRI10 ,Priority 10 - A packet TOS of 0d10 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4.--6. " PRI9 ,Priority 9 - A packet TOS of 0d9 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " PRI8 ,Priority 8 - A packet TOS of 0d8 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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group.long 0x38++0x03
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line.long 0x00 "P1_RX_DSCP_PRI_MAP2,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2"
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bitfld.long 0x00 28.--30. " PRI23 ,Priority 23 - A packet TOS of 0d23 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. " PRI22 ,Priority 22 - A packet TOS of 0d22 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20.--22. " PRI21 ,Priority 21 - A packet TOS of 0d21 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " PRI20 ,Priority 20 - A packet TOS of 0d20 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 12.--14. " PRI19 ,Priority 19 - A packet TOS of 0d19 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. " PRI18 ,Priority 18 - A packet TOS of 0d18 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4.--6. " PRI17 ,Priority 17 - A packet TOS of 0d17 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " PRI16 ,Priority 16 - A packet TOS of 0d16 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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group.long 0x3C++0x03
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line.long 0x00 "P1_RX_DSCP_PRI_MAP3,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3"
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bitfld.long 0x00 28.--30. " PRI31 ,Priority 31 - A packet TOS of 0d31 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. " PRI30 ,Priority 30 - A packet TOS of 0d30 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20.--22. " PRI29 ,Priority 29 - A packet TOS of 0d39 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI28 ,Priority 28 - A packet TOS of 0d28 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
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textline " "
|
|
bitfld.long 0x00 12.--14. " PRI27 ,Priority 27 - A packet TOS of 0d27 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI26 ,Priority 26 - A packet TOS of 0d26 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 4.--6. " PRI25 ,Priority 25 - A packet TOS of 0d25 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 0.--2. " PRI24 ,Priority 24 - A packet TOS of 0d24 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
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group.long 0x40++0x03
|
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line.long 0x00 "P1_RX_DSCP_PRI_MAP4,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4"
|
|
bitfld.long 0x00 28.--30. " PRI39 ,Priority 39 - A packet TOS of 0d39 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 24.--26. " PRI38 ,Priority 38 - A packet TOS of 0d38 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI37 ,Priority 37 - A packet TOS of 0d37 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI36 ,Priority 36 - A packet TOS of 0d36 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI35 ,Priority 35 - A packet TOS of 0d35 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI34 ,Priority 34 - A packet TOS of 0d34 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI33 ,Priority 33 - A packet TOS of 0d33 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI32 ,Priority 32 - A packet TOS of 0d32 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "P1_RX_DSCP_PRI_MAP5,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5"
|
|
bitfld.long 0x00 28.--30. " PRI47 ,Priority 47 - A packet TOS of 0d47 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI46 ,Priority 46 - A packet TOS of 0d46 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI45 ,Priority 45 - A packet TOS of 0d45 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI44 ,Priority 44 - A packet TOS of 0d44 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI43 ,Priority 43 - A packet TOS of 0d43 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI42 ,Priority 42 - A packet TOS of 0d42 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI41 ,Priority 41 - A packet TOS of 0d41 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI40 ,Priority 40 - A packet TOS of 0d40 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "P1_RX_DSCP_PRI_MAP6,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6"
|
|
bitfld.long 0x00 28.--30. " PRI55 ,Priority 55 - A packet TOS of 0d55 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI54 ,Priority 54 - A packet TOS of 0d54 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI53 ,Priority 53 - A packet TOS of 0d53 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI52 ,Priority 52 - A packet TOS of 0d52 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI51 ,Priority 51 - A packet TOS of 0d51 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI50 ,Priority 50 - A packet TOS of 0d50 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI49 ,Priority 49 - A packet TOS of 0d49 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI48 ,Priority 48 - A packet TOS of 0d48 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "P1_RX_DSCP_PRI_MAP7,CPSW PORT 1 TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE"
|
|
bitfld.long 0x00 28.--30. " PRI63 ,Priority 63 - A packet TOS of 0d63 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI62 ,Priority 62 - A packet TOS of 0d62 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI61 ,Priority 61 - A packet TOS of 0d61 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI60 ,Priority 60 - A packet TOS of 0d60 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI59 ,Priority 59 - A packet TOS of 0d59 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI58 ,Priority 58 - A packet TOS of 0d58 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI57 ,Priority 57 - A packet TOS of 0d57 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI56 ,Priority 56 - A packet TOS of 0d56 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
width 0xb
|
|
tree.end
|
|
tree "PORT 2"
|
|
base ad:0x4A100300
|
|
width 21.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P2_CONTROL,CPSW PORT 2 CONTROL REGISTER"
|
|
bitfld.long 0x00 24. " P2_PASS_PRI_TAGGED ,Port 2 Pass Priority Tagged" "P2_PORT_VLAN[11:0],Unchanged"
|
|
bitfld.long 0x00 21. " P2_VLAN_LTYPE2_EN ,Port 2 VLAN LTYPE 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P2_VLAN_LTYPE1_EN ,Port 2 VLAN LTYPE 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P2_DSCP_PRI_EN ,Port 2 DSCP Priority Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P1_TS_320 ,Port 2 Time Sync Destination Port Number 320 enable" "Disabled,Annex D (UDP/IPv4)"
|
|
bitfld.long 0x00 13. " P1_TS_319 ,Port 2 Time Sync Destination Port Number 319 enable" "Disabled,Annex D (UDP/IPv4)"
|
|
bitfld.long 0x00 12. " P1_TS_132 ,Port 2 Time Sync Destination IP Address 132 enable" "Disabled,Annex D (UDP/IPv4)"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_TS_131 ,Port 2 Time Sync Destination IP Address 131 enable" "Disabled,Annex D (UDP/IPv4)"
|
|
bitfld.long 0x00 10. " P1_TS_130 ,Port 2 Time Sync Destination IP Address 130 enable" "Disabled,Annex D (UDP/IPv4)"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P2_TS_129 ,Port 2 Time Sync Destination IP Address 129 enable" "Disabled,Annex D (UDP/IPv4)"
|
|
bitfld.long 0x00 8. " P2_TS_TTL_NONZERO ,Port #1 Time Sync Time To Live Non-zero enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P1_TS_ANNEX_D_EN ,Port 2 Time Sync Annex D enable" "Disabled,Annex D (UDP/IPv4)"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x00 3. " P1_TS_LTYPE2_EN ,Port 2 Time Sync LTYPE 2 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 3. " P1_TS_LTYPE2_EN ,Port 2 Time Sync LTYPE 2 enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 2. " P1_TS_LTYPE1_EN ,Port 2 Time Sync LTYPE 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1_TS_TX_EN ,Port 2 Time Sync Transmit Enable 0 " "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P1_TS_RX_EN ,Port 2 Time Sync Receive Enable" "Disabled,Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P2_MAX_BLKS,CPSW PORT 2 MAXIMUM FIFO BLOCKS REGISTER"
|
|
bitfld.long 0x00 4.--8. " P2_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " P2_RX_MAX_BLKS ,Receive FIFO Maximum Blocks" "Reserved,Reserved,Reserved,3,4,5,6,?..."
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "P2_BLK_CNT,CPSW PORT 2 FIFO BLOCK USAGE COUNT (READ ONLY)"
|
|
bitfld.long 0x00 4.--8. " P2_TX_BLK_CNT ,This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " P2_RX_BLK_CNT ,This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "P2_TX_IN_CTL,CPSW PORT 2 TRANSMIT FIFO CONTROL"
|
|
bitfld.long 0x00 24.--27. " HOST_BLKS_REM ,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select" "Normal priority mode,Reserved,Rate Limit mode,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TX_BLKS_REM ,Transmit FIFO Input Blocks to subtract in dual mac mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "P2_PORT_VLAN,CPSW PORT 2 VLAN REGISTER"
|
|
bitfld.long 0x00 13.--15. " PORT_PRI ,Port VLAN Priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. " PORT_CFI ,Port CFI bit" "Enabled,Disabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " PORT_VID ,Port VLAN ID"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "P2_TX_PRI_MAP,CPSW PORT 2 TX HEADER PRI TO SWITCH PRI MAPPING REGISTER"
|
|
bitfld.long 0x00 28.--29. " PRI7 ,Priority 7 - A packet header priority of 0x7 is given this switch queue pri" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " PRI6 ,Priority 6 - A packet header priority of 0x6 is given this switch queue pri" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " PRI5 ,Priority 5 - A packet header priority of 0x5 is given this switch queue pri" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " PRI4 ,Priority 4 - A packet header priority of 0x4 is given this switch queue pri" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " PRI3 ,Priority 3 - A packet header priority of 0x3 is given this switch queue pri" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " PRI2 ,Priority 2 - A packet header priority of 0x2 is given this switch queue pri" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " PRI1 ,Priority 1 - A packet header priority of 0x1 is given this switch queue pri" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " PRI0 ,Priority 0 - A packet header priority of 0x0 is given this switch queue pri" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "P2_TS_SEQ_MTYPE,TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE REGISTER"
|
|
hexmask.long.byte 0x00 16.--21. 1. " P2_TS_SEQ_ID_OFFSET ,Port 2 Time Sync Sequence ID Offset"
|
|
hexmask.long.word 0x00 0.--15. 1. " P2_TS_MSG_TYPE_EN ,Port 2 Time Sync Message Type Enable"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "P2_SA_LO,SOURCE ADDRESS LOW REGISTER"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_7_0 ,Source Address bits 0:7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR_15_8 ,Source Address bits 8:15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "P2_SA_HI,CPSW CPGMAC_SL1 SOURCE ADDRESS HIGH REGISTER"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MACSRCADDR_23_16 ,Source Address bits 23:16"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MACSRCADDR_31_24 ,Source Address bits 31:24"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_39_32 ,Source Address bits 39:32"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR_47_40 ,Source Address bits 47:40 "
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "P2_SEND_PERCENT,CPSW PORT 2 TRANSMIT QUEUE SEND PERCENTAGES"
|
|
hexmask.long.byte 0x00 16.--22. 1. " PRI3_SEND_PERCENT ,SPriority 3 Transmit Percentage"
|
|
hexmask.long.byte 0x00 8.--14. 1. " PRI2_SEND_PERCENT ,SPriority 2 Transmit Percentage"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PRI1_SEND_PERCENT ,SPriority 1 Transmit Percentage"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "P2_RX_DSCP_PRI_MAP0,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0 "
|
|
bitfld.long 0x00 28.--30. " PRI7 ,Priority 7 - A packet TOS of 0d7 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI6 ,Priority 6 - A packet TOS of 0d6 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI5 ,Priority 5 - A packet TOS of 0d5 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI4 ,Priority 4 - A packet TOS of 0d4 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI3 ,Priority 3 - A packet TOS of 0d3 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI2 ,Priority 2 - A packet TOS of 0d2 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI1 ,Priority 1 - A packet TOS of 0d1 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI0 ,Priority 0 - A packet TOS of 0d0 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "P2_RX_DSCP_PRI_MAP1,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1"
|
|
bitfld.long 0x00 28.--30. " PRI15 ,Priority 15 - A packet TOS of 0d15 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI14 ,Priority 14 - A packet TOS of 0d14 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI13 ,Priority 13 - A packet TOS of 0d13 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI12 ,Priority 12 - A packet TOS of 0d12 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI11 ,Priority 11 - A packet TOS of 0d11 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI10 ,Priority 10 - A packet TOS of 0d10 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI9 ,Priority 9 - A packet TOS of 0d9 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI8 ,Priority 8 - A packet TOS of 0d8 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "P2_RX_DSCP_PRI_MAP2,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2"
|
|
bitfld.long 0x00 28.--30. " PRI23 ,Priority 23 - A packet TOS of 0d23 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI22 ,Priority 22 - A packet TOS of 0d22 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI21 ,Priority 21 - A packet TOS of 0d21 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI20 ,Priority 20 - A packet TOS of 0d20 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI19 ,Priority 19 - A packet TOS of 0d19 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI18 ,Priority 18 - A packet TOS of 0d18 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI17 ,Priority 17 - A packet TOS of 0d17 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI16 ,Priority 16 - A packet TOS of 0d16 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "P2_RX_DSCP_PRI_MAP3,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3"
|
|
bitfld.long 0x00 28.--30. " PRI31 ,Priority 31 - A packet TOS of 0d31 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI30 ,Priority 30 - A packet TOS of 0d30 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI29 ,Priority 29 - A packet TOS of 0d39 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI28 ,Priority 28 - A packet TOS of 0d28 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI27 ,Priority 27 - A packet TOS of 0d27 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI26 ,Priority 26 - A packet TOS of 0d26 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI25 ,Priority 25 - A packet TOS of 0d25 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI24 ,Priority 24 - A packet TOS of 0d24 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "P2_RX_DSCP_PRI_MAP4,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4"
|
|
bitfld.long 0x00 28.--30. " PRI39 ,Priority 39 - A packet TOS of 0d39 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI38 ,Priority 38 - A packet TOS of 0d38 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI37 ,Priority 37 - A packet TOS of 0d37 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI36 ,Priority 36 - A packet TOS of 0d36 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI35 ,Priority 35 - A packet TOS of 0d35 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI34 ,Priority 34 - A packet TOS of 0d34 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI33 ,Priority 33 - A packet TOS of 0d33 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI32 ,Priority 32 - A packet TOS of 0d32 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "P2_RX_DSCP_PRI_MAP5,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5"
|
|
bitfld.long 0x00 28.--30. " PRI47 ,Priority 47 - A packet TOS of 0d47 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI46 ,Priority 46 - A packet TOS of 0d46 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI45 ,Priority 45 - A packet TOS of 0d45 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI44 ,Priority 44 - A packet TOS of 0d44 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI43 ,Priority 43 - A packet TOS of 0d43 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI42 ,Priority 42 - A packet TOS of 0d42 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI41 ,Priority 41 - A packet TOS of 0d41 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI40 ,Priority 40 - A packet TOS of 0d40 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "P2_RX_DSCP_PRI_MAP6,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6"
|
|
bitfld.long 0x00 28.--30. " PRI55 ,Priority 55 - A packet TOS of 0d55 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI54 ,Priority 54 - A packet TOS of 0d54 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI53 ,Priority 53 - A packet TOS of 0d53 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI52 ,Priority 52 - A packet TOS of 0d52 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI51 ,Priority 51 - A packet TOS of 0d51 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI50 ,Priority 50 - A packet TOS of 0d50 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI49 ,Priority 49 - A packet TOS of 0d49 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI48 ,Priority 48 - A packet TOS of 0d48 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "P2_RX_DSCP_PRI_MAP7,CPSW PORT 2 TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE"
|
|
bitfld.long 0x00 28.--30. " PRI63 ,Priority 63 - A packet TOS of 0d63 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PRI62 ,Priority 62 - A packet TOS of 0d62 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PRI61 ,Priority 61 - A packet TOS of 0d61 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " PRI60 ,Priority 60 - A packet TOS of 0d60 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PRI59 ,Priority 59 - A packet TOS of 0d59 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PRI58 ,Priority 58 - A packet TOS of 0d58 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI57 ,Priority 57 - A packet TOS of 0d57 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PRI56 ,Priority 56 - A packet TOS of 0d56 is mapped to this received packet priority" "0,1,2,3,4,5,6,7"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "CPSW SL (Ethernet Sliver)"
|
|
tree "CPSW SL 1"
|
|
base ad:0x4A100D80
|
|
width 19.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IDVER,ID/VERSION REGISTER"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
hexmask.long.word 0x00 16.--31. 1. " IDENT ,Rx Identification Value"
|
|
bitfld.long 0x00 11.--15. " Z ,Rx Z value (X.Y.Z)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " X ,Rx X value (major)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Y ,Rx Y value (minor)"
|
|
else
|
|
hexmask.long.word 0x00 20.--31. 1. " SCHEME ,Scheme value"
|
|
bitfld.long 0x00 11.--15. " RTL ,Rx Z value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Rx X value" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR_VER ,Minor version"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MACCONTROL,CPGMAC_SL MAC CONTROL REGISTER"
|
|
bitfld.long 0x00 24. " RX_CMF_EN ,RX Copy MAC Control Frames Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RX_CSF_EN ,RX Copy Short Frames Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RX_CEF_EN ,RX Copy Error Frames Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TX_SHORT_GAP_LIM_EN ,Transmit Short Gap Limit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EXT_EN ,Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " GIG_FORCE ,Gigabit Mode Force" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IFCTL_B ,Connects to the speed_in input of the respective RMII gasket" "10Mbps,100Mbps"
|
|
bitfld.long 0x00 15. " IFCTL_A ,Connects to the speed_in input of the respective RMII gasket" "10Mbps,100Mbps"
|
|
bitfld.long 0x00 11. " CMD_IDLE ,Command Idle" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TX_SHORT_GAP_EN ,Transmit Short Gap Enable" "Disabled IPG,Enabled IPG"
|
|
bitfld.long 0x00 7. " GIG ,Gigabit Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TX_PACE ,Transmit Pacing Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GMII_EN ,GMII Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TX_FLOW_EN ,Transmit Flow Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RX_FLOW_EN ,Receive Flow Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MTEST ,Manufacturing Test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LOOPBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FULLDUPLEX ,Full Duplex mode" "Half duplex,Full duplex"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "MACSTATUS,CPGMAC_SL MAC STATUS REGISTER"
|
|
bitfld.long 0x00 31. " IDLE ,CPGMAC_SL IDLE" "Not idle,Idle"
|
|
bitfld.long 0x00 4. " EXT_GIG ,External GIG" "Low,High"
|
|
bitfld.long 0x00 3. " EXT_FULLDUPLEX ,External Fullduplex" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FLOW_ACT ,Receive Flow Control Active" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TX_FLOW_ACT ,Transmit Flow Control Active" "Disabled,Enabled"
|
|
group.long 0x0c++0x0b
|
|
line.long 0x00 "SOFT_RESET,Software reset"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "No effect,Reset"
|
|
line.long 0x04 "RX_MAXLEN,RX_MAXLEN Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " RX_MAXLEN ,RX Maximum Frame Length"
|
|
line.long 0x08 "BOFFTEST,CPGMAC_SL BACKOFF TEST REGISTER"
|
|
bitfld.long 0x08 26.--30. " PACEVAL ,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x08 16.--25. 1. " RNDNUM ,Backoff Random Number Generator"
|
|
bitfld.long 0x08 12.--15. " COLL_COUNT ,Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
hexmask.long.word 0x08 0.--9. 1. " TX_BACKOFF ,Backoff Count"
|
|
else
|
|
hexmask.long.word 0x08 0.--10. 1. " TX_BACKOFF ,Backoff Count"
|
|
endif
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "RX_PAUSE,CPGMAC_SL RECEIVE PAUSE TIMER REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " RX_PAUSETIMER ,RX Pause Timer Value"
|
|
line.long 0x04 "TX_PAUSE,CPGMAC_SL TRANSMIT PAUSE TIMER REGISTER"
|
|
hexmask.long.word 0x04 16.--31. 1. " TX_PAUSETIMER ,TX Pause Timer Value"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "EMCONTROL,CPGMAC_SL EMULATION CONTROL REGISTER"
|
|
bitfld.long 0x00 1. " SOFT ,Emulation Soft Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FREE ,Emulation Free Bit" "Disabled,Enabled"
|
|
line.long 0x04 "RX_PRI_MAP,CPGMAC_SL RX PKT PRIORITY TO HEADER PRIORITY MAPPING REGISTER"
|
|
bitfld.long 0x04 28.--30. " PRI7 ,Priority 7 - A packet pri of 0x7 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 24.--26. " PRI6 ,Priority 6 - A packet pri of 0x6 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 20.--22. " PRI5 ,Priority 5 - A packet pri of 0x5 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " PRI4 ,Priority 4 - A packet pri of 0x4 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 12.--14. " PRI3 ,Priority 3 - A packet pri of 0x3 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. " PRI2 ,Priority 2 - A packet pri of 0x2 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " PRI1 ,Priority 1 - A packet pri of 0x1 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " PRI0 ,Priority 0 - A packet pri of 0x0 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "TX_GAP,TRANSMIT INTER-PACKET GAP REGISTER"
|
|
hexmask.long.word 0x08 0.--8. 1. " TX_GAP ,Transmit Inter-Packet Gap"
|
|
width 0xb
|
|
tree.end
|
|
tree "CPSW SL 2"
|
|
base ad:0x4A100DC0
|
|
width 19.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IDVER,ID/VERSION REGISTER"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
hexmask.long.word 0x00 16.--31. 1. " IDENT ,Rx Identification Value"
|
|
bitfld.long 0x00 11.--15. " Z ,Rx Z value (X.Y.Z)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " X ,Rx X value (major)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Y ,Rx Y value (minor)"
|
|
else
|
|
hexmask.long.word 0x00 20.--31. 1. " SCHEME ,Scheme value"
|
|
bitfld.long 0x00 11.--15. " RTL ,Rx Z value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Rx X value" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR_VER ,Minor version"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MACCONTROL,CPGMAC_SL MAC CONTROL REGISTER"
|
|
bitfld.long 0x00 24. " RX_CMF_EN ,RX Copy MAC Control Frames Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RX_CSF_EN ,RX Copy Short Frames Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RX_CEF_EN ,RX Copy Error Frames Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TX_SHORT_GAP_LIM_EN ,Transmit Short Gap Limit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EXT_EN ,Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " GIG_FORCE ,Gigabit Mode Force" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IFCTL_B ,Connects to the speed_in input of the respective RMII gasket" "10Mbps,100Mbps"
|
|
bitfld.long 0x00 15. " IFCTL_A ,Connects to the speed_in input of the respective RMII gasket" "10Mbps,100Mbps"
|
|
bitfld.long 0x00 11. " CMD_IDLE ,Command Idle" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TX_SHORT_GAP_EN ,Transmit Short Gap Enable" "Disabled IPG,Enabled IPG"
|
|
bitfld.long 0x00 7. " GIG ,Gigabit Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TX_PACE ,Transmit Pacing Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GMII_EN ,GMII Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TX_FLOW_EN ,Transmit Flow Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RX_FLOW_EN ,Receive Flow Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MTEST ,Manufacturing Test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LOOPBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FULLDUPLEX ,Full Duplex mode" "Half duplex,Full duplex"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "MACSTATUS,CPGMAC_SL MAC STATUS REGISTER"
|
|
bitfld.long 0x00 31. " IDLE ,CPGMAC_SL IDLE" "Not idle,Idle"
|
|
bitfld.long 0x00 4. " EXT_GIG ,External GIG" "Low,High"
|
|
bitfld.long 0x00 3. " EXT_FULLDUPLEX ,External Fullduplex" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FLOW_ACT ,Receive Flow Control Active" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TX_FLOW_ACT ,Transmit Flow Control Active" "Disabled,Enabled"
|
|
group.long 0x0c++0x0b
|
|
line.long 0x00 "SOFT_RESET,Software reset"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "No effect,Reset"
|
|
line.long 0x04 "RX_MAXLEN,RX_MAXLEN Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " RX_MAXLEN ,RX Maximum Frame Length"
|
|
line.long 0x08 "BOFFTEST,CPGMAC_SL BACKOFF TEST REGISTER"
|
|
bitfld.long 0x08 26.--30. " PACEVAL ,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x08 16.--25. 1. " RNDNUM ,Backoff Random Number Generator"
|
|
bitfld.long 0x08 12.--15. " COLL_COUNT ,Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
hexmask.long.word 0x08 0.--9. 1. " TX_BACKOFF ,Backoff Count"
|
|
else
|
|
hexmask.long.word 0x08 0.--10. 1. " TX_BACKOFF ,Backoff Count"
|
|
endif
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "RX_PAUSE,CPGMAC_SL RECEIVE PAUSE TIMER REGISTER"
|
|
hexmask.long.word 0x00 16.--31. 1. " RX_PAUSETIMER ,RX Pause Timer Value"
|
|
line.long 0x04 "TX_PAUSE,CPGMAC_SL TRANSMIT PAUSE TIMER REGISTER"
|
|
hexmask.long.word 0x04 16.--31. 1. " TX_PAUSETIMER ,TX Pause Timer Value"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "EMCONTROL,CPGMAC_SL EMULATION CONTROL REGISTER"
|
|
bitfld.long 0x00 1. " SOFT ,Emulation Soft Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FREE ,Emulation Free Bit" "Disabled,Enabled"
|
|
line.long 0x04 "RX_PRI_MAP,CPGMAC_SL RX PKT PRIORITY TO HEADER PRIORITY MAPPING REGISTER"
|
|
bitfld.long 0x04 28.--30. " PRI7 ,Priority 7 - A packet pri of 0x7 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 24.--26. " PRI6 ,Priority 6 - A packet pri of 0x6 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 20.--22. " PRI5 ,Priority 5 - A packet pri of 0x5 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " PRI4 ,Priority 4 - A packet pri of 0x4 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 12.--14. " PRI3 ,Priority 3 - A packet pri of 0x3 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. " PRI2 ,Priority 2 - A packet pri of 0x2 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " PRI1 ,Priority 1 - A packet pri of 0x1 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " PRI0 ,Priority 0 - A packet pri of 0x0 is mapped to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "TX_GAP,TRANSMIT INTER-PACKET GAP REGISTER"
|
|
hexmask.long.word 0x08 0.--8. 1. " TX_GAP ,Transmit Inter-Packet Gap"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "CPSW SS (32KB Ethernet Switch Subsystem)"
|
|
base ad:0x4A100000
|
|
width 19.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ID_VER,ID Version Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CPSW_3G_IDENT ,Rx Identification Value"
|
|
bitfld.long 0x00 11.--15. " CPSW_3G_RTL_VER ,3G RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " CPSW_3G_MAJ_VER ,3G Major Version Value" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPSW_3G_MINOR_VER ,3G Minor Version Value"
|
|
group.long 0x04++0x2f
|
|
line.long 0x00 "CONTROL,SWITCH CONTROL REGISTER"
|
|
bitfld.long 0x00 3. " DLR_EN ,DLR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RX_VLAN_ENCAP ,Port 0 VLAN Encapsulation" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " VLAN_AWARE ,VLAN Aware Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFO_LOOPBACK ,FIFO Loopback Mode" "Disabled,Enabled"
|
|
line.long 0x04 "SOFT_RESET, Soft Reset Register"
|
|
bitfld.long 0x04 0. " SOFT_RESET ,Software reset" "No reset,Reset"
|
|
line.long 0x08 "STAT_PORT_EN,Statistics port enable register"
|
|
bitfld.long 0x08 2. " P2_STAT_EN ,Port 2 (GMII2 and Port 2 FIFO) Statistics Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " P1_STAT_EN ,Port 1 (GMII1 and Port 1 FIFO) Statistics Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " P0_STAT_EN ,Port 0 Statistics Enable" "Disabled,Enabled"
|
|
line.long 0x0c "PTYPE,Transmit priority type register"
|
|
bitfld.long 0x0C 21. " P2_PRI3_SHAPE_EN ,Port 2 Queue Priority 3 Transmit Shape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " P2_PRI2_SHAPE_EN ,Port 2 Queue Priority 2 Transmit Shape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " P2_PRI1_SHAPE_EN ,Port 2 Queue Priority 1 Transmit Shape Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " P1_PRI3_SHAPE_EN ,Port 1 Queue Priority 3 Transmit Shape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " P1_PRI2_SHAPE_EN ,Port 1 Queue Priority 2 Transmit Shape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " P1_PRI1_SHAPE_EN ,Port 1 Queue Priority 1 Transmit Shape Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " P2_PTYPE_ESC ,Port 2 Priority Type Escalate" "Fixed,Escalate"
|
|
bitfld.long 0x0C 9. " P1_PTYPE_ESC ,Port 1 Priority Type Escalate" "Fixed,Escalate"
|
|
bitfld.long 0x0C 8. " P0_PTYPE_ESC ,Port 0 Priority Type Escalate" "Fixed,Escalate"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--4. " ESC_PRI_LD_VAL ,Escalate Priority Load Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "SOFT_IDLE,Software idle"
|
|
bitfld.long 0x10 0. " SOFT_IDLE ,Software Idle" "Not idle,Idle"
|
|
line.long 0x14 "THRU_RATE,Throughput rate"
|
|
bitfld.long 0x14 12.--15. " SL_RX_THRU_RATE ,CPGMAC_SL Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " CPDMA_THRU_RATE ,CPDMA Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "GAP_THRESH,Short Gap Threshold"
|
|
bitfld.long 0x18 0.--4. " GAP_THRESH ,CPGMAC_SL Short Gap Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1c "TX_START_WDS,Transmit start words"
|
|
hexmask.long.word 0x1c 0.--10. 1. " TX_START_WDS ,FIFO Packet Transmit (egress) Start Words"
|
|
line.long 0x20 "FLOW_CONTROL,Flow control Register"
|
|
bitfld.long 0x20 2. " P2_FLOW_EN ,Port 2 Receive flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 1. " P1_FLOW_EN ,Port 1 Receive flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " P0_FLOW_EN ,Port 0 Receive flow control enable" "Disabled,Enabled"
|
|
line.long 0x24 "VLAN_LTYPE,LTYPE1 and LTYPE 2 register"
|
|
hexmask.long.word 0x24 16.--31. 1. " VLAN_LTYPE2 ,Time Sync VLAN LTYPE2"
|
|
hexmask.long.word 0x24 0.--15. 1. " VLAN_LTYPE1 ,Time Sync VLAN LTYPE1"
|
|
line.long 0x28 "TS_LTYPE,VLAN_LTYPE1 and VLAN_LTYPE2 register"
|
|
hexmask.long.byte 0x28 16.--21. 1. " TS_LTYPE2 ,Time Sync LTYPE2 This is an Ethertype value"
|
|
hexmask.long.word 0x28 0.--15. 1. " TS_LTYPE1 ,Time Sync LTYPE1 This is an Ethertype value"
|
|
line.long 0x2C "DLR_LTYPE,DLR LTYPE register"
|
|
hexmask.long.word 0x2C 0.--15. 1. " DLR_LTYPE2 ,Time Sync LTYPE1 This is an ethertype value"
|
|
width 0xb
|
|
tree.end
|
|
tree "CPSW WR (RMII/RGMII Wrapper)"
|
|
base ad:0x4A101200
|
|
width 19.
|
|
tree "Others"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IDVER,SUBSYSTEM ID VERSION REGISTER"
|
|
hexmask.long.word 0x00 30.--31. 1. " SCHEME ,Scheme value"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNCTION ,Function value"
|
|
bitfld.long 0x00 11.--15. " RTL ,Rtl version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor version"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SOFT_RESET,SUBSYSTEM SOFT RESET REGISTER"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "Not occured,Occurred"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONTROL,SUBSYSTEM CONTROL REGISTER"
|
|
bitfld.long 0x00 2.--3. " MMR_STDBYMODE ,Standbymode MMR bits" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MMR_IDLEMODE ,Idlemode MMR bits" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "INT_CONTROL,SUBSYSTEM INTERRUPT CONTROL"
|
|
bitfld.long 0x00 31. " INT_TEST ,Interrupt Test" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " INT_PACE_EN[5] ,Enables C0_Rx_Pulse" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INT_PACE_EN[4] ,Enables C0_Tx_Pulse" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INT_PACE_EN[3] ,Enables C1_Rx_Pulse" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INT_PACE_EN[2] ,Enables C1_Tx_Pulse" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " INT_PACE_EN[1] ,Enables C2_Rx_Pulse" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INT_PACE_EN[0] ,Enables C2_Tx_Pulse" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " INT_PRESCALE ,Interrupt Counter Prescaler"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "RGMII_CTL,RGMII CONTROL SIGNAL REGISTER"
|
|
bitfld.long 0x00 7. " RGMII2_FULLDUPLEX ,RGMII 2 Fullduplex" "Half-duplex,Full-duplex"
|
|
bitfld.long 0x00 5.--6. " RGMII2_SPEED ,CPRGMI speed output signal" "10Mbps,100Mbps,1000Mbps,?..."
|
|
bitfld.long 0x00 4. " RGMII2_LINK ,CPRGMII link" "Down,Up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RGMII1_FULLDUPLEX ,CPRGMII fullduplex output signal" "Half-duplex,Fullduplex"
|
|
bitfld.long 0x00 1.--2. " RGMII1_SPEED ,CRGMII1 Speed" "10Mbps,100Mbps,1000Mbps,?..."
|
|
bitfld.long 0x00 0. " RGMII1_LINK ,RGMII1 Link Indicator - This is the CPRGMII link output signal 0 - RGMII1 link is down " "Down,Up"
|
|
tree.end
|
|
base ad:0x4A101210
|
|
width 20.
|
|
tree "Channel 0"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "C0_RX_THRESH_EN,SUBSYSTEM CORE 0RECEIVE THRESHOLD INT ENABLE REGISTER"
|
|
bitfld.long 0x00 7. " C0_RX_THRESH_EN[7] ,Core 0 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " C0_RX_THRESH_EN[6] ,Core 0 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " C0_RX_THRESH_EN[5] ,Core 1 Receive Threshold Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C0_RX_THRESH_EN[4] ,Core 0 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C0_RX_THRESH_EN[3] ,Core 0 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C0_RX_THRESH_EN[2] ,Core 0 Receive Threshold Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C0_RX_THRESH_EN[1] ,Core 0 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C0_RX_THRESH_EN[0] ,Core 0 Receive Threshold Enable" "Disabled,Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "C0_RX_EN,SUBSYSTEM CORE 0RECEIVE INTERRUPT ENABLE REGISTER"
|
|
bitfld.long 0x00 7. " C0_RX_EN[7] ,Core 0Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " C0_RX_EN[6] ,Core 0Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " C0_RX_EN[5] ,Core 0Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C0_RX_EN[4] ,Core 0Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C0_RX_EN[3] ,Core 0Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C0_RX_EN[2] ,Core 0Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C0_RX_EN[1] ,Core 0Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C0_RX_EN[0] ,Core 0Receive Enable" "Disabled,Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "C0_TX_EN,SUBSYSTEM CORE 0TRANSMIT INTERRUPT ENABLE REGISTER"
|
|
bitfld.long 0x00 7. " C0_TX_EN[7] ,Core 0Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " C0_TX_EN[6] ,Core 0Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " C0_TX_EN[5] ,Core 0Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C0_TX_EN[4] ,Core 0Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C0_TX_EN[3] ,Core 0Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C0_TX_EN[2] ,Core 0Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C0_TX_EN[1] ,Core 0Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C0_TX_EN[0] ,Core 0Transmit Enable" "Disabled,Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "C0_MISC_EN,SUBSYSTEM Core 0MISC INTERRUPT ENABLE REGISTER"
|
|
bitfld.long 0x00 4. " C0_MISC_EN[4] ,Core 0Misc Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C0_MISC_EN[3] ,Core 0Misc Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C0_MISC_EN[2] ,Core 0Misc Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C0_MISC_EN[1] ,Core 0Misc Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C0_MISC_EN[0] ,Core 0Misc Enable" "Disabled,Enaabled"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "C0_RX_THRESH_STAT,SUBSYSTEM CORE 0RX THRESHOLD MASKED INT STATUS REGISTER"
|
|
bitfld.long 0x00 7. " C0_RX_THRESH_STAT[7] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " C0_RX_THRESH_STAT[6] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " C0_RX_THRESH_STAT[5] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C0_RX_THRESH_STAT[4] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " C0_RX_THRESH_STAT[3] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " C0_RX_THRESH_STAT[2] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C0_RX_THRESH_STAT[1] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " C0_RX_THRESH_STAT[0] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "C0_RX_STAT,SUBSYSTEM CORE 0RX INTERRUPT MASKED INT STATUS REGISTER"
|
|
bitfld.long 0x00 7. " C0_RX_STAT[7] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " C0_RX_STAT[6] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " C0_RX_STAT[5] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C0_RX_STAT[4] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " C0_RX_STAT[3] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " C0_RX_STAT[2] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C0_RX_STAT[1] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " C0_RX_STAT[0] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "C0_TX_STAT,SUBSYSTEM CORE 0TX INTERRUPT MASKED INT STATUS REGISTER"
|
|
bitfld.long 0x00 7. " C0_TX_STAT[7] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " C0_TX_STAT[6] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " C0_TX_STAT[5] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C0_TX_STAT[4] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " C0_TX_STAT[3] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " C0_TX_STAT[2] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C0_TX_STAT[1] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " C0_TX_STAT[0] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "C0_MISC_STAT,SUBSYSTEM CORE 0MISC INTERRUPT MASKED INT STATUS REGISTER"
|
|
bitfld.long 0x00 4. " C0_MISC_STAT[4] ,Core 0Misc Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C0_MISC_STAT[3] ,Core 0Misc Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C0_MISC_STAT[2] ,Core 0Misc Masked Interrupt Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C0_MISC_STAT[1] ,Core 0Misc Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C0_MISC_STAT[0] ,Core 0Misc Masked Interrupt Status" "Disabled,Enaabled"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "C0_RX_IMAX,SUBSYSTEM CORE 0RECEIVE INTERRUPTS PER MILLISECOND"
|
|
hexmask.long.byte 0x00 0.--5. 1. " C0_RX_IMAX ,Core 0Receive Interrupts per Millisecond"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "C0_TX_IMAX,SUBSYSTEM CORE 0TRANSMIT INTERRUPTS PER MILLISECOND"
|
|
hexmask.long.byte 0x00 0.--5. 1. " C0_TX_IMAX ,Core 0Transmit Interrupts per Millisecond"
|
|
tree.end
|
|
base ad:0x4A101220
|
|
width 20.
|
|
tree "Channel 1"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "C1_RX_THRESH_EN,SUBSYSTEM CORE 1RECEIVE THRESHOLD INT ENABLE REGISTER"
|
|
bitfld.long 0x00 7. " C1_RX_THRESH_EN[7] ,Core 1 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " C1_RX_THRESH_EN[6] ,Core 1 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " C1_RX_THRESH_EN[5] ,Core 1 Receive Threshold Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C1_RX_THRESH_EN[4] ,Core 1 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C1_RX_THRESH_EN[3] ,Core 1 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C1_RX_THRESH_EN[2] ,Core 1 Receive Threshold Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C1_RX_THRESH_EN[1] ,Core 1 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C1_RX_THRESH_EN[0] ,Core 1 Receive Threshold Enable" "Disabled,Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "C1_RX_EN,SUBSYSTEM CORE 1RECEIVE INTERRUPT ENABLE REGISTER"
|
|
bitfld.long 0x00 7. " C1_RX_EN[7] ,Core 1Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " C1_RX_EN[6] ,Core 1Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " C1_RX_EN[5] ,Core 1Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C1_RX_EN[4] ,Core 1Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C1_RX_EN[3] ,Core 1Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C1_RX_EN[2] ,Core 1Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C1_RX_EN[1] ,Core 1Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C1_RX_EN[0] ,Core 1Receive Enable" "Disabled,Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "C1_TX_EN,SUBSYSTEM CORE 1TRANSMIT INTERRUPT ENABLE REGISTER"
|
|
bitfld.long 0x00 7. " C1_TX_EN[7] ,Core 1Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " C1_TX_EN[6] ,Core 1Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " C1_TX_EN[5] ,Core 1Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C1_TX_EN[4] ,Core 1Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C1_TX_EN[3] ,Core 1Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C1_TX_EN[2] ,Core 1Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C1_TX_EN[1] ,Core 1Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C1_TX_EN[0] ,Core 1Transmit Enable" "Disabled,Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "C1_MISC_EN,SUBSYSTEM Core 1MISC INTERRUPT ENABLE REGISTER"
|
|
bitfld.long 0x00 4. " C1_MISC_EN[4] ,Core 1Misc Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C1_MISC_EN[3] ,Core 1Misc Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C1_MISC_EN[2] ,Core 1Misc Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C1_MISC_EN[1] ,Core 1Misc Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C1_MISC_EN[0] ,Core 1Misc Enable" "Disabled,Enaabled"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "C1_RX_THRESH_STAT,SUBSYSTEM CORE 1RX THRESHOLD MASKED INT STATUS REGISTER"
|
|
bitfld.long 0x00 7. " C1_RX_THRESH_STAT[7] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " C1_RX_THRESH_STAT[6] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " C1_RX_THRESH_STAT[5] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C1_RX_THRESH_STAT[4] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " C1_RX_THRESH_STAT[3] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " C1_RX_THRESH_STAT[2] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C1_RX_THRESH_STAT[1] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " C1_RX_THRESH_STAT[0] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "C1_RX_STAT,SUBSYSTEM CORE 1RX INTERRUPT MASKED INT STATUS REGISTER"
|
|
bitfld.long 0x00 7. " C1_RX_STAT[7] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " C1_RX_STAT[6] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " C1_RX_STAT[5] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C1_RX_STAT[4] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " C1_RX_STAT[3] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " C1_RX_STAT[2] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C1_RX_STAT[1] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " C1_RX_STAT[0] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "C1_TX_STAT,SUBSYSTEM CORE 1TX INTERRUPT MASKED INT STATUS REGISTER"
|
|
bitfld.long 0x00 7. " C1_TX_STAT[7] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " C1_TX_STAT[6] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " C1_TX_STAT[5] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C1_TX_STAT[4] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " C1_TX_STAT[3] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " C1_TX_STAT[2] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C1_TX_STAT[1] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " C1_TX_STAT[0] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "C1_MISC_STAT,SUBSYSTEM CORE 1MISC INTERRUPT MASKED INT STATUS REGISTER"
|
|
bitfld.long 0x00 4. " C1_MISC_STAT[4] ,Core 1Misc Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C1_MISC_STAT[3] ,Core 1Misc Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C1_MISC_STAT[2] ,Core 1Misc Masked Interrupt Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C1_MISC_STAT[1] ,Core 1Misc Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C1_MISC_STAT[0] ,Core 1Misc Masked Interrupt Status" "Disabled,Enaabled"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "C1_RX_IMAX,SUBSYSTEM CORE 1RECEIVE INTERRUPTS PER MILLISECOND"
|
|
hexmask.long.byte 0x00 0.--5. 1. " C1_RX_IMAX ,Core 1Receive Interrupts per Millisecond"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "C1_TX_IMAX,SUBSYSTEM CORE 1TRANSMIT INTERRUPTS PER MILLISECOND"
|
|
hexmask.long.byte 0x00 0.--5. 1. " C1_TX_IMAX ,Core 1Transmit Interrupts per Millisecond"
|
|
tree.end
|
|
base ad:0x4A101230
|
|
width 20.
|
|
tree "Channel 3"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "C3_RX_THRESH_EN,SUBSYSTEM CORE 3RECEIVE THRESHOLD INT ENABLE REGISTER"
|
|
bitfld.long 0x00 7. " C3_RX_THRESH_EN[7] ,Core 3 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " C3_RX_THRESH_EN[6] ,Core 3 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " C3_RX_THRESH_EN[5] ,Core 1 Receive Threshold Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C3_RX_THRESH_EN[4] ,Core 3 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C3_RX_THRESH_EN[3] ,Core 3 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C3_RX_THRESH_EN[2] ,Core 3 Receive Threshold Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C3_RX_THRESH_EN[1] ,Core 3 Receive Threshold Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C3_RX_THRESH_EN[0] ,Core 3 Receive Threshold Enable" "Disabled,Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "C3_RX_EN,SUBSYSTEM CORE 3RECEIVE INTERRUPT ENABLE REGISTER"
|
|
bitfld.long 0x00 7. " C3_RX_EN[7] ,Core 3Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " C3_RX_EN[6] ,Core 3Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " C3_RX_EN[5] ,Core 3Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C3_RX_EN[4] ,Core 3Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C3_RX_EN[3] ,Core 3Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C3_RX_EN[2] ,Core 3Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C3_RX_EN[1] ,Core 3Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C3_RX_EN[0] ,Core 3Receive Enable" "Disabled,Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "C3_TX_EN,SUBSYSTEM CORE 3TRANSMIT INTERRUPT ENABLE REGISTER"
|
|
bitfld.long 0x00 7. " C3_TX_EN[7] ,Core 3Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " C3_TX_EN[6] ,Core 3Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " C3_TX_EN[5] ,Core 3Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C3_TX_EN[4] ,Core 3Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C3_TX_EN[3] ,Core 3Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C3_TX_EN[2] ,Core 3Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C3_TX_EN[1] ,Core 3Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C3_TX_EN[0] ,Core 3Transmit Enable" "Disabled,Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "C3_MISC_EN,SUBSYSTEM Core 3MISC INTERRUPT ENABLE REGISTER"
|
|
bitfld.long 0x00 4. " C3_MISC_EN[4] ,Core 3Misc Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C3_MISC_EN[3] ,Core 3Misc Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C3_MISC_EN[2] ,Core 3Misc Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C3_MISC_EN[1] ,Core 3Misc Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C3_MISC_EN[0] ,Core 3Misc Enable" "Disabled,Enaabled"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "C3_RX_THRESH_STAT,SUBSYSTEM CORE 3RX THRESHOLD MASKED INT STATUS REGISTER"
|
|
bitfld.long 0x00 7. " C3_RX_THRESH_STAT[7] ,Core 3Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " C3_RX_THRESH_STAT[6] ,Core 3Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " C3_RX_THRESH_STAT[5] ,Core 3Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C3_RX_THRESH_STAT[4] ,Core 3Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " C3_RX_THRESH_STAT[3] ,Core 3Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " C3_RX_THRESH_STAT[2] ,Core 3Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C3_RX_THRESH_STAT[1] ,Core 3Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " C3_RX_THRESH_STAT[0] ,Core 3Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "C3_RX_STAT,SUBSYSTEM CORE 3RX INTERRUPT MASKED INT STATUS REGISTER"
|
|
bitfld.long 0x00 7. " C3_RX_STAT[7] ,Core 3Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " C3_RX_STAT[6] ,Core 3Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " C3_RX_STAT[5] ,Core 3Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C3_RX_STAT[4] ,Core 3Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " C3_RX_STAT[3] ,Core 3Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " C3_RX_STAT[2] ,Core 3Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C3_RX_STAT[1] ,Core 3Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " C3_RX_STAT[0] ,Core 3Receive Masked Interrupt Status" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "C3_TX_STAT,SUBSYSTEM CORE 3TX INTERRUPT MASKED INT STATUS REGISTER"
|
|
bitfld.long 0x00 7. " C3_TX_STAT[7] ,Core 3Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " C3_TX_STAT[6] ,Core 3Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " C3_TX_STAT[5] ,Core 3Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C3_TX_STAT[4] ,Core 3Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " C3_TX_STAT[3] ,Core 3Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " C3_TX_STAT[2] ,Core 3Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C3_TX_STAT[1] ,Core 3Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " C3_TX_STAT[0] ,Core 3Transmit Masked Interrupt Status" "No interrupt,Interrupt"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "C3_MISC_STAT,SUBSYSTEM CORE 3MISC INTERRUPT MASKED INT STATUS REGISTER"
|
|
bitfld.long 0x00 4. " C3_MISC_STAT[4] ,Core 3Misc Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C3_MISC_STAT[3] ,Core 3Misc Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C3_MISC_STAT[2] ,Core 3Misc Masked Interrupt Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C3_MISC_STAT[1] ,Core 3Misc Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " C3_MISC_STAT[0] ,Core 3Misc Masked Interrupt Status" "Disabled,Enaabled"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "C3_RX_IMAX,SUBSYSTEM CORE 3RECEIVE INTERRUPTS PER MILLISECOND"
|
|
hexmask.long.byte 0x00 0.--5. 1. " C3_RX_IMAX ,Core 3Receive Interrupts per Millisecond"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "C3_TX_IMAX,SUBSYSTEM CORE 3TRANSMIT INTERRUPTS PER MILLISECOND"
|
|
hexmask.long.byte 0x00 0.--5. 1. " C3_TX_IMAX ,Core 3Transmit Interrupts per Millisecond"
|
|
tree.end
|
|
tree.end
|
|
tree "CPSW MDIO (Ethernet MDIO Controller)"
|
|
base ad:0x4A101000
|
|
width 20.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VER, Version Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MODID ,Identifies type of peripheral"
|
|
hexmask.long.byte 0x00 8.--15. 1. " REVMAJ ,Management interface module major revision value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVMIN ,Management interface module minor revision value"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CONTROL, Control Register"
|
|
bitfld.long 0x00 31. " IDLE , state machine IDLE" "Not idle,Idle"
|
|
bitfld.long 0x00 30. " ENABLE ,Enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PREAMBLE ,Preamble disable" "No,Yes"
|
|
eventfld.long 0x00 19. " FAULT ,Fault indicator" "No failure,Fault"
|
|
bitfld.long 0x00 18. " FAULTENB ,Fault detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTTESTENB ,Interrupt test enable." "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divider"
|
|
line.long 0x04 "ALIVE, alive"
|
|
group.long 0x0C++0x13
|
|
sif (cpuis("DRA62*"))
|
|
line.long 0x00 "LINK, link state"
|
|
line.long 0x04 "LINKINTRAW, Link Status Change Interrupt Register"
|
|
eventfld.long 0x04 1. " LINKINTRAW[1] , link change event" "Not changed,Changed"
|
|
eventfld.long 0x04 0. " LINKINTRAW[0] , link change event" "Not changed,Changed"
|
|
line.long 0x08 "LINKINTMASKED, Link Status Change Interrupt Register (Masked Value)"
|
|
eventfld.long 0x08 1. " LINKINTMASKED[1] , link change interrupt" "Not completed,Completed"
|
|
eventfld.long 0x08 0. " LINKINTMASKED[0] , link change interrupt" "Not completed,Completed"
|
|
else
|
|
line.long 0x00 "LINK, link state"
|
|
line.long 0x00 "LINKINTMASKED, Link Status Change Interrupt Register (Masked Value)"
|
|
eventfld.long 0x00 1. " LINKINTRAW[1] , link change event" "Not changed,Changed"
|
|
eventfld.long 0x00 0. " LINKINTRAW[0] , link change event" "Not changed,Changed"
|
|
line.long 0x04 "USERINTMASKED, User Command Complete Interrupt Register (Masked Value)"
|
|
eventfld.long 0x04 1. " LINKINTMASKED[1] , link change interrupt" "Not completed,Completed"
|
|
eventfld.long 0x04 0. " LINKINTMASKED[0] , link change interrupt" "Not completed,Completed"
|
|
endif
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "USERINTRAW, User Command Complete Interrupt Register"
|
|
eventfld.long 0x00 1. " USERINTRAW[1] ,Raw value of user command complete event" "No Effect,Clear"
|
|
eventfld.long 0x00 0. " USERINTRAW[0] ,Raw value of user command complete event" "No Effect,Clear"
|
|
line.long 0x04 "USERINTMASKED, User Command Complete Interrupt Register (Masked Value)"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0c 1. " USERINTMASKED[1]_Set/Clr ,Masked value of user command" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0c 0. " USERINTMASKED[0]_Set/Clr ,Masked value of user command" "No interrupt,Interrupt"
|
|
group.long 0x80++0x0f
|
|
line.long 0x00 "USERACCESS0,The user access register 0"
|
|
bitfld.long 0x00 31. " GO ,Go" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " WRITE ,Write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ACK ,Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 21.--25. 0x20 " REGADR ,Register address"
|
|
hexmask.long.byte 0x00 16.--20. 1. " PHYADR ,PHY address"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,User data"
|
|
line.long 0x04 "USERPHYSEL0, User PHY Select Register 0"
|
|
bitfld.long 0x04 7. " LINKSEL ,Link status determination select" ",MLINK"
|
|
bitfld.long 0x04 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 0.--4. 1. " PHYADDRMON ,PHY address"
|
|
line.long 0x08 "USERACCESS1,The user access register 1"
|
|
bitfld.long 0x08 31. " GO ,Go" "No effect,Enabled"
|
|
bitfld.long 0x08 30. " WRITE ,Write enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " ACK ,Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x08 21.--25. 0x20 " REGADR ,Register address"
|
|
hexmask.long.byte 0x08 16.--20. 1. " PHYADR ,PHY address"
|
|
hexmask.long.word 0x08 0.--15. 1. " DATA ,User data"
|
|
line.long 0x0c "USERPHYSEL1, User PHY Select Register 1"
|
|
bitfld.long 0x0c 7. " LINKSEL ,Link status determination select" ",MLINK"
|
|
bitfld.long 0x0c 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x0c 0.--4. 1. " PHYADDRMON ,PHY address"
|
|
width 0xb
|
|
tree.end
|
|
else
|
|
tree "Chip Level Configuration"
|
|
base ad:0x02049000
|
|
width 8.
|
|
group.long 0xa8++0x03
|
|
line.long 0x00 "CFGPLL,PLL Configuration Register"
|
|
bitfld.long 0x00 8.--9. " LB ,LB" "0,?..."
|
|
bitfld.long 0x00 1.--4. " MPY ,Multiplication Factor" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,20x,25x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENPLL ,Enable PLL" "Disabled,Enabled"
|
|
group.long 0xb0++0xf
|
|
line.long 0x0 "CFGRX0,Receiver Configuration Register 0"
|
|
bitfld.long 0x0 19.--22. " EQ ,Equalizer (LowFreq/ZeroFreq)" "Maximum/-,Adaptive,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Adaptive/365 MHz,Adaptive/275 MHz,Adaptive/195 MHz,Adaptive/140 MHz,Adaptive/105 MHz,Adaptive/75 MHz,Adaptive/55 MHz,Adaptive/50 MHz"
|
|
bitfld.long 0x0 16.--18. " CDR ,Clock/data recovery" "First order and threshold of 1,First order and threshold of 16,Second order: high precision and threshold of 1,Second order: high precision and threshold of 16,Second order: low precision and threshold of 1,Second order: low precision and threshold of 16,First order: threshold of 1 with fast lock,Second order: low precision with fast lock"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " LOS ,Loss of Signal detection" "Disabled,Reserved,Enabled,?..."
|
|
bitfld.long 0x0 12.--13. " ALIGN ,Alignment" "Disabled,Comma,Jog,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8.--10. " TERM ,Input termination" "Reserved,0.8 VDDT,?..."
|
|
bitfld.long 0x0 7. " INVPAIR ,Invert polarity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5.--6. " RATE ,Operating rate" "Full,Half,Quarter,?..."
|
|
bitfld.long 0x0 2.--4. " BUSWIDTH ,Bus Width" "10-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x0 0. " ENRX ,Enable receiver" "Disabled,Enabled"
|
|
line.long 0x4 "CFGRX1,Receiver Configuration Register 1"
|
|
bitfld.long 0x4 19.--22. " EQ ,Equalizer (LowFreq/ZeroFreq)" "Maximum/-,Adaptive,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Adaptive/365 MHz,Adaptive/275 MHz,Adaptive/195 MHz,Adaptive/140 MHz,Adaptive/105 MHz,Adaptive/75 MHz,Adaptive/55 MHz,Adaptive/50 MHz"
|
|
bitfld.long 0x4 16.--18. " CDR ,Clock/data recovery" "First order and threshold of 1,First order and threshold of 16,Second order: high precision and threshold of 1,Second order: high precision and threshold of 16,Second order: low precision and threshold of 1,Second order: low precision and threshold of 16,First order: threshold of 1 with fast lock,Second order: low precision with fast lock"
|
|
textline " "
|
|
bitfld.long 0x4 14.--15. " LOS ,Loss of Signal detection" "Disabled,Reserved,Enabled,?..."
|
|
bitfld.long 0x4 12.--13. " ALIGN ,Alignment" "Disabled,Comma,Jog,?..."
|
|
textline " "
|
|
bitfld.long 0x4 8.--10. " TERM ,Input termination" "Reserved,0.8 VDDT,?..."
|
|
bitfld.long 0x4 7. " INVPAIR ,Invert polarity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5.--6. " RATE ,Operating rate" "Full,Half,Quarter,?..."
|
|
bitfld.long 0x4 2.--4. " BUSWIDTH ,Bus Width" "10-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x4 0. " ENRX ,Enable receiver" "Disabled,Enabled"
|
|
line.long 0x8 "CFGTX0,Transmitter Configuration Register 0"
|
|
bitfld.long 0x8 16. " ENFTP ,Fixed Phase Relationship" "Reserved,Enabled"
|
|
bitfld.long 0x8 12.--15. " DE ,De-emphasis ( LowFreq/ZeroFreq)" "0,4.76/-0.42,9.52/-0.87,14.28/-1.34,19.04/-1.83,23.8/-2.36,28.56/-2.92,33.32/-3.52,38.08/-4.16,42.85/-4.86,47.61/-5.61,52.38/-6.44,57.14/-7.35,61.9/-8.38,66.66/-9.54,71.42/-10.87"
|
|
textline " "
|
|
bitfld.long 0x8 9.--11. " SWING ,The output swing " "Reserved,Reserved,Reserved,Reserved,750,1000,1250,1375"
|
|
bitfld.long 0x8 8. " CM ,Common mode of the differential signal output" "Normal,Raised"
|
|
textline " "
|
|
bitfld.long 0x8 7. " INVPAIR ,Invert polarity" "Disabled,Enabled"
|
|
bitfld.long 0x8 5.--6. " RATE ,Operating rate" "Full,Half,Quarter,?..."
|
|
textline " "
|
|
bitfld.long 0x8 2.--4. " BUSWIDTH ,Bus Width" "10-bit,?..."
|
|
bitfld.long 0x8 0. " ENTX ,Enable transmiter" "Disabled,Enabled"
|
|
line.long 0xC "CFGTX1,Transmitter Configuration Register 1"
|
|
bitfld.long 0xC 16. " ENFTP ,Fixed Phase Relationship" "Reserved,Enabled"
|
|
bitfld.long 0xC 12.--15. " DE ,De-emphasis ( LowFreq/ZeroFreq)" "0,4.76/-0.42,9.52/-0.87,14.28/-1.34,19.04/-1.83,23.8/-2.36,28.56/-2.92,33.32/-3.52,38.08/-4.16,42.85/-4.86,47.61/-5.61,52.38/-6.44,57.14/-7.35,61.9/-8.38,66.66/-9.54,71.42/-10.87"
|
|
textline " "
|
|
bitfld.long 0xC 9.--11. " SWING ,The output swing " "Reserved,Reserved,Reserved,Reserved,750,1000,1250,1375"
|
|
bitfld.long 0xC 8. " CM ,Common mode of the differential signal output" "Normal,Raised"
|
|
textline " "
|
|
bitfld.long 0xC 7. " INVPAIR ,Invert polarity" "Disabled,Enabled"
|
|
bitfld.long 0xC 5.--6. " RATE ,Operating rate" "Full,Half,Quarter,?..."
|
|
textline " "
|
|
bitfld.long 0xC 2.--4. " BUSWIDTH ,Bus Width" "10-bit,?..."
|
|
bitfld.long 0xC 0. " ENTX ,Enable transmiter" "Disabled,Enabled"
|
|
width 12.
|
|
tree.end
|
|
tree "EMAC SW (Ethernet MAC Switch)"
|
|
base ad:0x4a100000
|
|
width 19.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CPSW_ID_VER,3pGSw ID Version Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " IDENT ,3pGSw identification value"
|
|
bitfld.long 0x00 11.--15. " RTL_VER ,3pGSw RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR_VER ,3pGSw major version" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " MINOR_VER ,3pGSw minor version"
|
|
width 19.
|
|
group.long 0x04++0x13
|
|
line.long 0x00 "CPSW_CONTROL,3pGSw Switch Control Register"
|
|
bitfld.long 0x00 12. " P2_PASS_PRI_TAGGED ,Port 2 Pass Priority Tagged" "Not processed,Processed"
|
|
bitfld.long 0x00 11. " P1_PASS_PRI_TAGGED ,Port 1 Pass Priority Tagged" "Not processed,Processed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P0_PASS_PRI_TAGGED ,Port 0 Pass Priority Tagged" "Not processed,Processed"
|
|
bitfld.long 0x00 9. " VLAN_AWARE ,3pGSw VLAN Aware Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RX_VLAN_ENCAP ,Port 2 VLAN Encapsulation" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P2_P2RX_FLOW_EN ,Port 2 transmit flow control enable from Port 2 receive FIFO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P2_P1TX_FLOW_EN ,Port 2 transmit flow control enable from Port 1 transmit FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P2_P0TX_FLOW_EN ,Port 2 transmit flow control enable from Port 0 transmit FIFO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P1_P2TX_FLOW_EN ,Port 1 receive flow control enable from Port 2 transmit FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P1_P0TX_FLOW_EN ,Port 1 receive flow control enable from Port 0 transmit FIFO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P0_P2TX_FLOW_EN ,Port 0 receive flow control enable from Port 2 transmit FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P0_P1TX_FLOW_EN ,Port 0 receive flow control enable from Port 1 transmit FIFO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFO_LOOPBACK ,FIFO Loopback Mode" "Disabled,Enabled"
|
|
line.long 0x04 "CPSW_SOFT_RESET,3pGSw Soft Reset Register"
|
|
bitfld.long 0x04 0. " SOFT_RESET ,Software reset" "No reset,Reset"
|
|
line.long 0x08 "CPSW_STAT_PORT_EN,3pGSw Statistics Port Enable Register"
|
|
bitfld.long 0x08 2. " P2_STAT_EN ,Port 2 Statistics Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " P1_STAT_EN ,Port 1 (GMII 1 and Port 1 FIFO) Statistics Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " P0_STAT_EN ,Port 0 (GMII 0 and Port 0 FIFO) Statistics Enable" "Disabled,Enabled"
|
|
line.long 0x0c "CPSW_PTYPE,3pGSw Transmit Priority Type Register"
|
|
bitfld.long 0x0c 10. " P2_PTYPE_ESC ,Port 2 priority type escalate" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " P1_PTYPE_ESC ,Port 1 priority type escalate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 8. " P0_PTYPE_ESC ,Port 0 priority type escalate" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0.--4. " ESC_PRI_LD_VAL ,Escalate priority load value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "P0_MAX_BLKS,3pGSw Port 0 Maximum FIFO Blocks Register"
|
|
bitfld.long 0x10 4.--8. " P0_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 0.--3. " P0_RX_MAX_BLKS ,Receive FIFO Maximum Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "P0_BLK_CNT,3pGSw Port 0 FIFO Block Usage Count Register"
|
|
bitfld.long 0x00 4.--8. " TX_BLK_COUNT ,Port 0 transmit block count usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " RX_BLK_COUNT ,Port 0 receive block count usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1c++0x17
|
|
line.long 0x00 "P0_FLOW_THRESH,3pGSw Port 0 Flow Control Threshold Register"
|
|
bitfld.long 0x00 8.--12. " P0_P2TX_THRESH ,Port 2 transmit FIFO threshold value to trigger Port 0 receive flow control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " P0_P1TX_THRESH ,Port 1 transmit FIFO threshold value to trigger Port 0 receive flow control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "P0_PORT_VLAN,3pGSw Port 0 VLAN Register"
|
|
bitfld.long 0x04 13.--15. " PORT_PRI ,Port VLAN priority" "Lowest,1,2,3,4,5,6,Highest"
|
|
bitfld.long 0x04 12. " PORT_CFI ,Port CFI bit" "Low,High"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--11. 1. " PORT_VID ,Port VLAN ID"
|
|
line.long 0x08 "P0_TX_PRI_MAP,3pGSw Port 0 TX Header Priority to Switch Priority Mapping Register"
|
|
bitfld.long 0x08 28.--29. " PRI7 ,Priority 7" "0,1,2,3"
|
|
bitfld.long 0x08 24.--25. " PRI6 ,Priority 6" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 20.--21. " PRI5 ,Priority 5" "0,1,2,3"
|
|
bitfld.long 0x08 16.--17. " PRI4 ,Priority 4" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " PRI3 ,Priority 3" "0,1,2,3"
|
|
bitfld.long 0x08 8.--9. " PRI2 ,Priority 2" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " PRI1 ,Priority 1" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " PRI0 ,Priority 0" "0,1,2,3"
|
|
line.long 0x0c "GMAC0_GAP_THRESH,3pGSw GMAC0 Short Gap Threshold Register"
|
|
bitfld.long 0x0c 0.--4. " P0_GAP_THRESH ,Port 0 short gap threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "GMAC0_SA_LO,3pGSw GMAC0 Source Address Low Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " MACSRCADDR_0 ,Source address lower 8 bits (byte 0)"
|
|
hexmask.long.byte 0x10 0.--7. 1. " MACSRCADDR_1 ,Source address bits 15:8 (byte 1)"
|
|
line.long 0x14 "GMAC0_SA_HI,3pGSw GMAC0 Source Address High Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " MACSRCADDR_2 ,Source address bits 23:16 (byte 2)"
|
|
hexmask.long.byte 0x14 16.--23. 1. " MACSRCADDR_3 ,Source address bits 31:24 (byte 3)"
|
|
textline " "
|
|
hexmask.long.byte 0x14 8.--15. 1. " MACSRCADDR_4 ,Source address bits 39:32 (byte 4)"
|
|
hexmask.long.byte 0x14 0.--7. 1. " MACSRCADDR_5 ,Source address bits 47:40 (byte 5)"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "P2_MAX_BLKS,3pGSw Port 2 Maximum FIFO Blocks Register"
|
|
bitfld.long 0x00 4.--8. " TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " RX_MAX_BLKS ,Receive FIFO Maximum Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "P2_BLK_CNT,3pGSw Port 2 FIFO Block Usage Count Register"
|
|
bitfld.long 0x00 4.--8. " TX_BLK_COUNT ,Port 1 transmit block count usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " RX_BLK_COUNT ,Port 1 receive block count usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5c++0x13
|
|
line.long 0x00 "P2_FLOW_THRESH,3pGSw Port 2 Flow Control Threshold Register"
|
|
bitfld.long 0x00 16.--19. " P2_P2TX_THRESH ,Port 2 transmit FIFO threshold value to trigger Port 2 receive flow control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--12. " P2_P1TX_THRESH ,Port 1 transmit FIFO threshold value to trigger Port 2 receive flow control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " P2_P0TX_THRESH ,Port 0 transmit FIFO threshold value to trigger Port 2 receive flow control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "P2_PORT_VLAN,3pGSw Port 2 VLAN Register"
|
|
bitfld.long 0x04 13.--15. " PORT_PRI ,Port VLAN priority" "Lowest,1,2,3,4,5,6,Highest"
|
|
bitfld.long 0x04 12. " PORT_CFI ,Port CFI bit" "Low,High"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--11. 1. " PORT_VID ,Port VLAN ID"
|
|
line.long 0x08 "P2_TX_PRI_MAP,3pGSw Port 2 TX Header Priority to Switch Priority Mapping Register"
|
|
bitfld.long 0x08 28.--29. " PRI7 ,Priority 7" "0,1,2,3"
|
|
bitfld.long 0x08 24.--25. " PRI6 ,Priority 6" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 20.--21. " PRI5 ,Priority 5" "0,1,2,3"
|
|
bitfld.long 0x08 16.--17. " PRI4 ,Priority 4" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " PRI3 ,Priority 3" "0,1,2,3"
|
|
bitfld.long 0x08 8.--9. " PRI2 ,Priority 2" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " PRI1 ,Priority 1" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " PRI0 ,Priority 0" "0,1,2,3"
|
|
line.long 0x0c "CPDMA_TX_PRI_MAP,3pGSw CPDMA TX (Port 2 Rx) Packet Priority to Header Priority Mapping Register"
|
|
bitfld.long 0x0c 28.--30. " PRI7 ,Priority 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 24.--26. " PRI6 ,Priority 6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " PRI5 ,Priority 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 16.--18. " PRI4 ,Priority 4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 12.--14. " PRI3 ,Priority 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 8.--10. " PRI2 ,Priority 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--6. " PRI1 ,Priority 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 0.--2. " PRI0 ,Priority 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "CPDMA_RX_CH_MAP,3pGSw CPDMA RX (Port 2 TX) Switch Priority to DMA Channel Mapping Register"
|
|
bitfld.long 0x10 28.--30. " SU_CH7 ,Channel 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 24.--26. " SU_CH6 ,Channel 6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 20.--22. " SU_CH5 ,Channel 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 16.--18. " SU_CH4 ,Channel 4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 12.--14. " SU_CH3 ,Channel 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 8.--10. " SU_CH2 ,Channel 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 4.--6. " SU_CH1 ,Channel 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. " SU_CH0 ,Channel 0" "0,1,2,3,4,5,6,7"
|
|
width 19.
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "GMAC0_IDVER,GMAC0 ID/Version Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RX_IDENT ,RX identification value"
|
|
bitfld.long 0x00 11.--15. " RX_Z ,RX Z value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " RX_X ,Rx X value" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_Y ,Rx Y value"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GMAC0_MACCONTROL,GMAC0 MAC Control Register"
|
|
bitfld.long 0x00 24. " RX_CMF_EN ,RX copy MAC control frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RX_CSF_EN ,RX copy short frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RX_CEF_EN ,RX copy error frames enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CTL_EN ,Control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " GIG_FORCE ,Gigabit mode force" "Not forced,Forced"
|
|
bitfld.long 0x00 16. " IFCTL_B ,Interface control B" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IFCTL_A ,Interface control A" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CMD_IDLE ,Command idle" "Not idle,Idle"
|
|
bitfld.long 0x00 10. " TX_SHORT_GAP_EN ,Transmit short gap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GIG ,Gigabit mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TX_PACE ,Transmit pacing" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GMII_EN ,GMII enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TX_FLOW_EN ,Transmit flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RX_FLOW_EN ,Receive flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MTEST ,Manufacturing test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOOPBACK ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FULLDUPLEX ,Full duplex mode" "Disabled,Enabled"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "GMAC0_MACSTATUS,GMAC0 MAC Status Register"
|
|
bitfld.long 0x00 31. " IDLE ,GMAC idle" "Not idle,Idle"
|
|
bitfld.long 0x00 4. " EXT_GIG ,External GIG" "Low,High"
|
|
bitfld.long 0x00 3. " EXT_FULLDUPLEX ,External fullduplex" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FLOW_ACT ,Receive flow control active" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TX_FLOW_ACT ,Transmit flow control active" "Disabled,Enabled"
|
|
group.long 0x8c++0x0b
|
|
line.long 0x00 "GMAC0_SOFT_RESET,GMAC0 Soft Reset Register"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "No reset,Reset"
|
|
line.long 0x04 "GMAC0_RX_MAXLEN,GMAC0 RX Maximum Length Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " RX_MAXLEN ,Receive maximum frame length"
|
|
line.long 0x08 "GMAC0_BOFFTEST,GMAC0 Backoff Test Register"
|
|
bitfld.long 0x08 26.--30. " PACEVAL ,Pacing register current value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x08 16.--25. 1. " RNDNUM ,Backoff random number generator"
|
|
bitfld.long 0x08 12.--15. " COLL_COUNT ,Collision count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--9. 1. " TX_BACKOFF ,Backoff count"
|
|
group.long 0xa0++0x07
|
|
line.long 0x00 "GMAC0_EMCONTROL,GMAC0 Emulation Control Register"
|
|
bitfld.long 0x00 1. " SOFT ,Emulation soft bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FREE ,Emulation free bit" "Disabled,Enabled"
|
|
line.long 0x04 "GMAC0_RX_PRI_MAP,GMAC0 Rx Packet Priority to Header Priority Mapping Register"
|
|
bitfld.long 0x04 28.--30. " PRI7 ,Priority 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 24.--26. " PRI6 ,Priority 6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 20.--22. " PRI5 ,Priority 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " PRI4 ,Priority 4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " PRI3 ,Priority 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. " PRI2 ,Priority 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " PRI1 ,Priority 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " PRI0 ,Priority 0" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x100++0x03 "CPDMA Registers"
|
|
line.long 0x00 "TX_IDVER,TX Identification and Version Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TX_IDENT ,TX Identification value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TX_MAJOR_VER ,TX major version value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_MINOR_VER ,TX minor version value"
|
|
group.long 0x104++0x07
|
|
line.long 0x00 "TX_CONTROL,TX Control Register"
|
|
bitfld.long 0x00 0. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
line.long 0x04 "TX_TEARDOWN,TX Teardown Register"
|
|
bitfld.long 0x04 31. " TX_TDN_READY ,TX teardown ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0.--2. " TX_TDN_CH ,TX teardown channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "RX_IDVER,RX Identification and Version Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RX_IDENT ,RX Identification value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_MAJOR_VER ,RX major version value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_MINOR_VER ,RX minor version value"
|
|
group.long 0x114++0x0f
|
|
line.long 0x00 "RX_CONTROL,RX Control Register"
|
|
bitfld.long 0x00 0. " RX_EN ,Transmit enable" "Disabled,Enabled"
|
|
line.long 0x04 "RX_TEARDOWN,RX Teardown Register"
|
|
bitfld.long 0x04 31. " RX_TDN_READY ,RX teardown ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0.--2. " RX_TDN_CH ,RX teardown channel" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "SOFT_RESET,Soft Reset Register"
|
|
bitfld.long 0x08 0. " SOFT_RESET ,Software reset" "No reset,Reset"
|
|
line.long 0x0c "DMACONTROL,CPDMA Control Register"
|
|
bitfld.long 0x0c 4. " RX_CEF ,RX copy error frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 3. " CMD_IDLE ,Command idle" "Not idle,Idle"
|
|
bitfld.long 0x0c 2. " RX_OFFLEN_BLOCK ,Receive Offset/Length word write block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " RX_OWNERSHIP ,Receive ownership write bit value" "Not received,Received"
|
|
bitfld.long 0x0c 0. " TX_PTYPE ,Transmit queue priority type" "Round robin,Fixed"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "DMASTATUS,CPDMA Status Register"
|
|
bitfld.long 0x00 31. " IDLE ,Idle Status" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TX_HOST_ERR_CODE ,TX host error code" "No error,SOP error,Ownership,Zero next buffer without EOP,Zero buffer pointer,Zero buffer length,Packet length error,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_ERR_CH ,TX host error channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " RX_HOST_ERR_CODE ,RX host error code" "No error,Reserved,Ownership,Reserved,Zero Buffer Pointer,Zero buffer length (Non-SOP),SOP buffer length <= Offset,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " RX_ERROR_CH ,RX host error channel" "0,1,2,3,4,5,6,7"
|
|
group.long 0x128++0x07
|
|
line.long 0x00 "RX_BUFFER_OFFSET,Receive Buffer Offset Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RX_BUFFER_OFFSET ,Receive buffer offset value"
|
|
line.long 0x04 "EMCONTROL,Emulation Control Register"
|
|
bitfld.long 0x04 1. " SOFT ,Emulation soft bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " FREE ,Emulation free bit" "Disabled,Enabled"
|
|
width 19.
|
|
rgroup.long 0x180++0x07 "CPDMA Interrupts"
|
|
line.long 0x00 "TX_INTSTAT_RAW,TX Interrupt Status Register (Raw Value)"
|
|
bitfld.long 0x00 15. " TX7_THRESH_PEND ,TX7_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " TX6_THRESH_PEND ,TX6_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TX5_THRESH_PEND ,TX5_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " TX4_THRESH_PEND ,TX4_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX3_THRESH_PEND ,TX3_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " TX2_THRESH_PEND ,TX2_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TX1_THRESH_PEND ,TX1_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " TX0_THRESH_PEND ,TX0_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TX7_PEND ,TX7_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " TX6_PEND ,TX6_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TX5_PEND ,TX5_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " TX4_PEND ,TX4_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TX3_PEND ,TX3_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " TX2_PEND ,TX2_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX1_PEND ,TX1_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " TX0_PEND ,TX0_PEND raw interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "TX_INTSTAT_MASKED,TX Interrupt Status Register"
|
|
bitfld.long 0x04 15. " TX7_THRESH_PEND ,TX7_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " TX6_THRESH_PEND ,TX6_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TX5_THRESH_PEND ,TX5_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " TX4_THRESH_PEND ,TX4_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " TX3_THRESH_PEND ,TX3_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " TX2_THRESH_PEND ,TX2_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " TX1_THRESH_PEND ,TX1_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " TX0_THRESH_PEND ,TX0_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " TX7_PEND ,TX7_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " TX6_PEND ,TX6_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX5_PEND ,TX5_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " TX4_PEND ,TX4_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TX3_PEND ,TX3_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " TX2_PEND ,TX2_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX1_PEND ,TX1_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " TX0_PEND ,TX0_PEND interrupt" "No interrupt,Interrupt"
|
|
wgroup.long 0x188++0x07
|
|
line.long 0x00 "TX_INTMASK_SET,TX Interrupt Mask Set Register"
|
|
bitfld.long 0x00 15. " TX7_THRESH_PEND_MASK ,TX Channel 7 threshold pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 14. " TX6_THRESH_PEND_MASK ,TX Channel 6 threshold pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TX5_THRESH_PEND_MASK ,TX Channel 5 threshold pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 12. " TX4_THRESH_PEND_MASK ,TX Channel 4 threshold pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX3_THRESH_PEND_MASK ,TX Channel 3 threshold pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 10. " TX2_THRESH_PEND_MASK ,TX Channel 2 threshold pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TX1_THRESH_PEND_MASK ,TX Channel 1 threshold pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 8. " TX0_THRESH_PEND_MASK ,TX Channel 0 threshold pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TX7_PEND_MASK ,TX Channel 7 pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 6. " TX6_PEND_MASK ,TX Channel 6 pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TX5_PEND_MASK ,TX Channel 5 pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 4. " TX4_PEND_MASK ,TX Channel 4 pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TX3_PEND_MASK ,TX Channel 3 pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 2. " TX2_PEND_MASK ,TX Channel 2 pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX1_PEND_MASK ,TX Channel 1 pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 0. " TX0_PEND_MASK ,TX Channel 0 pending interrupt mask" "No effect,Set"
|
|
line.long 0x04 "TX_INTMASK_CLEAR,TX Interrupt Mask Clear Register"
|
|
bitfld.long 0x04 15. " TX7_THRESH_PEND_MASK ,TX Channel 7 threshold pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 14. " TX6_THRESH_PEND_MASK ,TX Channel 6 threshold pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TX5_THRESH_PEND_MASK ,TX Channel 5 threshold pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 12. " TX4_THRESH_PEND_MASK ,TX Channel 4 threshold pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " TX3_THRESH_PEND_MASK ,TX Channel 3 threshold pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 10. " TX2_THRESH_PEND_MASK ,TX Channel 2 threshold pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 9. " TX1_THRESH_PEND_MASK ,TX Channel 1 threshold pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 8. " TX0_THRESH_PEND_MASK ,TX Channel 0 threshold pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " TX7_PEND_MASK ,TX Channel 7 pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 6. " TX6_PEND_MASK ,TX Channel 6 pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX5_PEND_MASK ,TX Channel 5 pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 4. " TX4_PEND_MASK ,TX Channel 4 pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TX3_PEND_MASK ,TX Channel 3 pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 2. " TX2_PEND_MASK ,TX Channel 2 pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX1_PEND_MASK ,TX Channel 1 pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 0. " TX0_PEND_MASK ,TX Channel 0 pending interrupt mask" "No effect,Clear"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "CPDMA_IN_VECTOR,Input Vector Register"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "CPDMA_EOI_VECTOR,End Of Interrupt Vector Register"
|
|
bitfld.long 0x00 0.--4. " DMA_EOI_VECTOR ,DMA end of interrupt vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x1a0++0x07
|
|
line.long 0x00 "RX_INTSTAT_RAW,RX Interrupt Status Register (Raw Value)"
|
|
bitfld.long 0x00 15. " RX7_THRESH_PEND ,RX7_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " RX6_THRESH_PEND ,RX6_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RX5_THRESH_PEND ,RX5_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " RX4_THRESH_PEND ,RX4_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RX3_THRESH_PEND ,RX3_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " RX2_THRESH_PEND ,RX2_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX1_THRESH_PEND ,RX1_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RX0_THRESH_PEND ,RX0_THRESH_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RX7_PEND ,RX7_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RX6_PEND ,RX6_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RX5_PEND ,RX5_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RX4_PEND ,RX4_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX3_PEND ,RX3_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RX2_PEND ,RX2_PEND raw interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX1_PEND ,RX1_PEND raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RX0_PEND ,RX0_PEND raw interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "RX_INTSTAT_MASKED,RX Interrupt Status Register"
|
|
bitfld.long 0x04 15. " RX7_THRESH_PEND ,RX7_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " RX6_THRESH_PEND ,RX6_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RX5_THRESH_PEND ,RX5_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " RX4_THRESH_PEND ,RX4_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RX3_THRESH_PEND ,RX3_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " RX2_THRESH_PEND ,RX2_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX1_THRESH_PEND ,RX1_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RX0_THRESH_PEND ,RX0_THRESH_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RX7_PEND ,RX7_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " RX6_PEND ,RX6_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RX5_PEND ,RX5_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RX4_PEND ,RX4_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX3_PEND ,RX3_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RX2_PEND ,RX2_PEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RX1_PEND ,RX1_PEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RX0_PEND ,RX0_PEND interrupt" "No interrupt,Interrupt"
|
|
wgroup.long 0x1a8++0x07
|
|
line.long 0x00 "RX_INTMASK_SET,RX Interrupt Mask Set Register"
|
|
bitfld.long 0x00 15. " RX7_THRESH_PEND_MASK ,RX Channel 7 threshold pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 14. " RX6_THRESH_PEND_MASK ,RX Channel 6 threshold pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RX5_THRESH_PEND_MASK ,RX Channel 5 threshold pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 12. " RX4_THRESH_PEND_MASK ,RX Channel 4 threshold pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RX3_THRESH_PEND_MASK ,RX Channel 3 threshold pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 10. " RX2_THRESH_PEND_MASK ,RX Channel 2 threshold pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX1_THRESH_PEND_MASK ,RX Channel 1 threshold pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 8. " RX0_THRESH_PEND_MASK ,RX Channel 0 threshold pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RX7_PEND_MASK ,RX Channel 7 pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 6. " RX6_PEND_MASK ,RX Channel 6 pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RX5_PEND_MASK ,RX Channel 5 pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 4. " RX4_PEND_MASK ,RX Channel 4 pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX3_PEND_MASK ,RX Channel 3 pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 2. " RX2_PEND_MASK ,RX Channel 2 pending interrupt mask" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX1_PEND_MASK ,RX Channel 1 pending interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 0. " RX0_PEND_MASK ,RX Channel 0 pending interrupt mask" "No effect,Set"
|
|
line.long 0x04 "RX_INTMASK_CLEAR,RX Interrupt Mask Clear Register"
|
|
bitfld.long 0x04 15. " RX7_THRESH_PEND_MASK ,RX Channel 7 threshold pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 14. " RX6_THRESH_PEND_MASK ,RX Channel 6 threshold pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RX5_THRESH_PEND_MASK ,RX Channel 5 threshold pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 12. " RX4_THRESH_PEND_MASK ,RX Channel 4 threshold pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RX3_THRESH_PEND_MASK ,RX Channel 3 threshold pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 10. " RX2_THRESH_PEND_MASK ,RX Channel 2 threshold pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX1_THRESH_PEND_MASK ,RX Channel 1 threshold pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 8. " RX0_THRESH_PEND_MASK ,RX Channel 0 threshold pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RX7_PEND_MASK ,RX Channel 7 pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 6. " RX6_PEND_MASK ,RX Channel 6 pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RX5_PEND_MASK ,RX Channel 5 pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 4. " RX4_PEND_MASK ,RX Channel 4 pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX3_PEND_MASK ,RX Channel 3 pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 2. " RX2_PEND_MASK ,RX Channel 2 pending interrupt mask" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RX1_PEND_MASK ,RX Channel 1 pending interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 0. " RX0_PEND_MASK ,RX Channel 0 pending interrupt mask" "No effect,Clear"
|
|
rgroup.long 0x1b0++0x07
|
|
line.long 0x00 "DMA_INTSTAT_RAW,DMA Interrupt Status Register (Raw Value)"
|
|
bitfld.long 0x00 1. " HOST_PEND ,Host pending raw interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " STAT_PEND ,Statistics pending raw interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "DMA_INTSTAT_MASKED,DMA Interrupt Status Register"
|
|
bitfld.long 0x04 1. " HOST_PEND ,Host pending interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " STAT_PEND ,Statistics pending interrupt" "No interrupt,Interrupt"
|
|
wgroup.long 0x1b8++0x07
|
|
line.long 0x00 "DMA_INTMASK_SET,DMA Interrupt Mask Set Register"
|
|
bitfld.long 0x00 1. " HOST_ERR_INT_MASK ,Host error interrupt mask" "No effect,Set"
|
|
bitfld.long 0x00 0. " STAT_INT_MASK ,Statistics interrupt mask" "No effect,Set"
|
|
line.long 0x04 "DMA_INTMASK_CLEAR,DMA Interrupt Mask Clear Register"
|
|
bitfld.long 0x04 1. " DMA1_PEND_MASK ,Host error interrupt mask" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DMA0_PEND_MASK ,Statistics interrupt mask" "No effect,Clear"
|
|
group.long 0x1c0++0x1f
|
|
line.long 0x0 "RX0_PENDTHRESH,Receive Threshold Pending Register Channel 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " RX0_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0x4 "RX1_PENDTHRESH,Receive Threshold Pending Register Channel 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " RX1_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0x8 "RX2_PENDTHRESH,Receive Threshold Pending Register Channel 2"
|
|
hexmask.long.byte 0x8 0.--7. 1. " RX2_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0xC "RX3_PENDTHRESH,Receive Threshold Pending Register Channel 3"
|
|
hexmask.long.byte 0xC 0.--7. 1. " RX3_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0x10 "RX4_PENDTHRESH,Receive Threshold Pending Register Channel 4"
|
|
hexmask.long.byte 0x10 0.--7. 1. " RX4_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0x14 "RX5_PENDTHRESH,Receive Threshold Pending Register Channel 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. " RX5_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0x18 "RX6_PENDTHRESH,Receive Threshold Pending Register Channel 6"
|
|
hexmask.long.byte 0x18 0.--7. 1. " RX6_PENDTHRESH ,Receive flow threshold"
|
|
line.long 0x1C "RX7_PENDTHRESH,Receive Threshold Pending Register Channel 7"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " RX7_PENDTHRESH ,Receive flow threshold"
|
|
wgroup.long 0x1e0++0x1f
|
|
line.long 0x0 "RX0_FREEBUFFER,Receive Free Buffer Register Channel 0"
|
|
hexmask.long.word 0x0 0.--15. 1. " RX0_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0x4 "RX1_FREEBUFFER,Receive Free Buffer Register Channel 1"
|
|
hexmask.long.word 0x4 0.--15. 1. " RX1_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0x8 "RX2_FREEBUFFER,Receive Free Buffer Register Channel 2"
|
|
hexmask.long.word 0x8 0.--15. 1. " RX2_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0xC "RX3_FREEBUFFER,Receive Free Buffer Register Channel 3"
|
|
hexmask.long.word 0xC 0.--15. 1. " RX3_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0x10 "RX4_FREEBUFFER,Receive Free Buffer Register Channel 4"
|
|
hexmask.long.word 0x10 0.--15. 1. " RX4_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0x14 "RX5_FREEBUFFER,Receive Free Buffer Register Channel 5"
|
|
hexmask.long.word 0x14 0.--15. 1. " RX5_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0x18 "RX6_FREEBUFFER,Receive Free Buffer Register Channel 6"
|
|
hexmask.long.word 0x18 0.--15. 1. " RX6_FREEBUFFER ,Receive free buffer count"
|
|
line.long 0x1C "RX7_FREEBUFFER,Receive Free Buffer Register Channel 7"
|
|
hexmask.long.word 0x1C 0.--15. 1. " RX7_FREEBUFFER ,Receive free buffer count"
|
|
width 9.
|
|
group.long 0x200++0x7f
|
|
line.long 0x0 "TX0_HDP,TX Channel 0 Head Descriptor Pointer Register"
|
|
line.long 0x4 "TX1_HDP,TX Channel 1 Head Descriptor Pointer Register"
|
|
line.long 0x8 "TX2_HDP,TX Channel 2 Head Descriptor Pointer Register"
|
|
line.long 0xC "TX3_HDP,TX Channel 3 Head Descriptor Pointer Register"
|
|
line.long 0x10 "TX4_HDP,TX Channel 4 Head Descriptor Pointer Register"
|
|
line.long 0x14 "TX5_HDP,TX Channel 5 Head Descriptor Pointer Register"
|
|
line.long 0x18 "TX6_HDP,TX Channel 6 Head Descriptor Pointer Register"
|
|
line.long 0x1C "TX7_HDP,TX Channel 7 Head Descriptor Pointer Register"
|
|
line.long 0x20 "RX0_HDP,RX Channel 0 Head Descriptor Pointer Register"
|
|
line.long 0x24 "RX1_HDP,RX Channel 1 Head Descriptor Pointer Register"
|
|
line.long 0x28 "RX2_HDP,RX Channel 2 Head Descriptor Pointer Register"
|
|
line.long 0x2C "RX3_HDP,RX Channel 3 Head Descriptor Pointer Register"
|
|
line.long 0x30 "RX4_HDP,RX Channel 4 Head Descriptor Pointer Register"
|
|
line.long 0x34 "RX5_HDP,RX Channel 5 Head Descriptor Pointer Register"
|
|
line.long 0x38 "RX6_HDP,RX Channel 6 Head Descriptor Pointer Register"
|
|
line.long 0x3C "RX7_HDP,RX Channel 7 Head Descriptor Pointer Register"
|
|
line.long 0x40 "TX0_CP,TX Channel 0 Completion Pointer Register"
|
|
line.long 0x44 "TX1_CP,TX Channel 1 Completion Pointer Register"
|
|
line.long 0x48 "TX2_CP,TX Channel 2 Completion Pointer Register"
|
|
line.long 0x4C "TX3_CP,TX Channel 3 Completion Pointer Register"
|
|
line.long 0x50 "TX4_CP,TX Channel 4 Completion Pointer Register"
|
|
line.long 0x54 "TX5_CP,TX Channel 5 Completion Pointer Register"
|
|
line.long 0x58 "TX6_CP,TX Channel 6 Completion Pointer Register"
|
|
line.long 0x5C "TX7_CP,TX Channel 7 Completion Pointer Register"
|
|
line.long 0x60 "RX0_CP,RX Channel 0 Completion Pointer Register"
|
|
line.long 0x64 "RX1_CP,RX Channel 1 Completion Pointer Register"
|
|
line.long 0x68 "RX2_CP,RX Channel 2 Completion Pointer Register"
|
|
line.long 0x6C "RX3_CP,RX Channel 3 Completion Pointer Register"
|
|
line.long 0x70 "RX4_CP,RX Channel 4 Completion Pointer Register"
|
|
line.long 0x74 "RX5_CP,RX Channel 5 Completion Pointer Register"
|
|
line.long 0x78 "RX6_CP,RX Channel 6 Completion Pointer Register"
|
|
line.long 0x7C "RX7_CP,RX Channel 7 Completion Pointer Register"
|
|
width 22.
|
|
group.long 0x400++0x27 "Statistics Interface Registers"
|
|
line.long 0x00 "RXGOODFRAMES,Total Number of Good Frames Received Register"
|
|
line.long 0x04 "RXBROADCASTFRAMES,Total Number of Good Broadcast Frames Received Register"
|
|
line.long 0x08 "RXMULTICASTFRAMES,Total Number of Good Multicast Frames Received Register"
|
|
line.long 0x0c "RXPAUSEFRAMES,PauseRxFrames Register"
|
|
line.long 0x10 "RXCRCERRORS,Total Number of CRC Errors Frames Received Register"
|
|
line.long 0x14 "RXALIGNCODEERRORS,Total Number of Alignment/Code Errors Received Register"
|
|
line.long 0x18 "RXOVERSIZEDFRAMES,Total Number of Oversized Frames Received Register"
|
|
line.long 0x1c "RXJABBERFRAMES,Total Number of Jabber Frames Received Register"
|
|
line.long 0x20 "RXUNDERSIZEDFRAMES,Total Number of Undersized Frames Received Register"
|
|
line.long 0x24 "RXFRAGMENTS,RxFragments Received Register"
|
|
group.long 0x430++0x5f
|
|
line.long 0x00 "RXOCTETS,Total Number of Received Bytes in Good Frames Register"
|
|
line.long 0x04 "TXGOODFRAMES,GoodTXFrames Register"
|
|
line.long 0x08 "TXBROADCASTFRAMES,BroadcastTXFrames Register Register"
|
|
line.long 0x0c "TXMULTICASTFRAMES,MulticastTXFrames Register"
|
|
line.long 0x10 "TXPAUSEFRAMES,PauseTXFrames Register"
|
|
line.long 0x14 "TXDEFERREDFRAMES,Deferred Frames Register"
|
|
line.long 0x18 "TXCOLLISIONFRAMES,Collisions Register"
|
|
line.long 0x1c "TXSINGLECOLLFRAMES,Single CollisionTXFrames Register"
|
|
line.long 0x20 "TXMULTCOLLFRAMES,Multiple CollisionTXFrames Register"
|
|
line.long 0x24 "TXEXCESSIVECOLLISIONS,Excessive Collisions Register"
|
|
line.long 0x28 "TXLATECOLLISIONS,Late Collisions Register"
|
|
line.long 0x2c "TXUNDERRUN,Transmit Underrun Error Register"
|
|
line.long 0x30 "TXCARRIERSENSEERRORS,Carrier Sense Errors Register"
|
|
line.long 0x34 "TXOCTETS,TXOctets Register"
|
|
line.long 0x38 "OCTETFRAMES64,64OctetFrames Register"
|
|
line.long 0x3c "OCTETFRAMES65T127,65-127OctetFrames Register"
|
|
line.long 0x40 "OCTETFRAMES128T255,128-255OctetFrames Register"
|
|
line.long 0x44 "OCTETFRAMES256T511,256-511OctetFrames Register"
|
|
line.long 0x48 "OCTETFRAMES512T1023,512-1023OctetFrames Register"
|
|
line.long 0x4c "OCTETFRAMES1024TUP,1023-1518OctetFrames Register"
|
|
line.long 0x50 "NETOCTETS,NetOctets Register"
|
|
line.long 0x54 "RXSOFOVERRUNS,Receive FIFO or DMA Start of Frame Overruns Register"
|
|
line.long 0x58 "RXMOFOVERRUNS,Receive FIFO or DMA Mid of Frame Overruns Register"
|
|
line.long 0x5c "RXDMAOVERRUNS,Receive DMA Start of Frame and Middle of Frame Overruns Register"
|
|
width 12.
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "RTC (Real Time Clock)"
|
|
base ad:0x480C0000
|
|
width 0x14
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "SECOND,Seconds Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x00 04.--07. " SEC ,Second" "0,1,2,3,4,5,-,-,-,-,-,-,-,?..."
|
|
else
|
|
bitfld.long 0x00 04.--06. " SEC ,Second" "0,1,2,3,4,5,-,-"
|
|
endif
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.long 0x0004++0x03
|
|
line.long 0x00 "MINUTE,Minutes Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x00 04.--07. " MIN ,Minute" "0,1,2,3,4,5,-,-,-,-,-,-,-,?..."
|
|
else
|
|
bitfld.long 0x00 04.--06. " MIN ,Minute" "0,1,2,3,4,5,-,-"
|
|
endif
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
if ((data.long(ad:0x480C0000+0x40)&0x08)==0x08)&&((data.long(ad:0x480C0000+0x08)&0x30)==0x10)
|
|
group.long 0x0008++0x03
|
|
line.long 0x00 "HOUR,Hours Register"
|
|
bitfld.long 0x00 04.--05. " HOUR ,Hour" "0,1,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
|
|
elif ((data.long(ad:0x480C0000+0x40)&0x08)==0x08)&&((data.long(ad:0x480C0000+0x08)&0x30)!=0x10)
|
|
group.long 0x0008++0x03
|
|
line.long 0x00 "HOUR,Hours Register"
|
|
bitfld.long 0x00 04.--05. " HOUR ,Hour" "0,1,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
|
|
elif ((data.long(ad:0x480C0000+0x40)&0x08)==0x00)&&((data.long(ad:0x480C0000+0x08)&0x30)==0x20)
|
|
group.long 0x0008++0x03
|
|
line.long 0x00 "HOUR,Hours Register"
|
|
bitfld.long 0x00 04.--05. " HOUR ,Hour" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x0008++0x03
|
|
line.long 0x00 "HOUR,Hours Register"
|
|
bitfld.long 0x00 04.--05. " HOUR ,Hour" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
if (((data.long(ad:0x480C0000+0x10)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(ad:0x480C0000+0x0c))&0x30)==0x30)
|
|
group.long 0x000C++0x03
|
|
line.long 0x00 "DAY,Days Register"
|
|
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(ad:0x480C0000+0x10)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(ad:0x480C0000+0x0c))&0x30)!=0x30)
|
|
group.long 0x000C++0x03
|
|
line.long 0x00 "DAY,Days Register"
|
|
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0x480C0000+0x10)&0x1f)==0x02))
|
|
group.long 0x000C++0x03
|
|
line.long 0x00 "DAY,Days Register"
|
|
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0x480C0000+0x10)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12)))&&(((data.long(ad:0x480C0000+0x0c))&0x30)==0x30)
|
|
group.long 0x000C++0x03
|
|
line.long 0x00 "DAY,Days Register"
|
|
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x000C++0x03
|
|
line.long 0x00 "DAY,Days Register"
|
|
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
if (((data.long(ad:0x480C0000+0x10)&0x10)==0x10))
|
|
//MONTH->MONTH[4.]=='1'
|
|
group.long 0x0010++0x03
|
|
line.long 0x00 "MONTH,Months Register"
|
|
bitfld.long 0x00 04. " MONTH ,Month" "0,1"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x0010++0x03
|
|
line.long 0x00 "MONTH,Months Register"
|
|
bitfld.long 0x00 04. " MONTH ,Month" "0,1"
|
|
bitfld.long 0x00 00.--03. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
group.long 0x0014++0x03
|
|
line.long 0x00 "YEAR,Years Register"
|
|
bitfld.long 0x00 04.--07. " YEAR ,Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.long 0x0018++0x03
|
|
line.long 0x00 "DOTW,Day of the Week Register"
|
|
bitfld.long 0x00 00.--02. " DOTW ,Day of the week" "Sun,Mon,Tue,Wed,Thu,Fri,Sat,-"
|
|
group.long 0x0020++0x03
|
|
line.long 0x00 "ALARMSECOND,Alarm Seconds Register"
|
|
bitfld.long 0x00 04.--06. " AL_SEC ,Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.long 0x0024++0x03
|
|
line.long 0x00 "ALARMMINUTE,Alarm Minutes Register"
|
|
bitfld.long 0x00 04.--06. " AL_MIN ,Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
if ((data.long(ad:0x480C0000+0x40)&0x08)==0x08)&&((data.long(ad:0x480C0000+0x28)&0x30)==0x10)
|
|
group.long 0x0028++0x03
|
|
line.long 0x00 "ALARMHOUR,Alarm Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
|
|
elif ((data.long(ad:0x480C0000+0x40)&0x08)==0x08)&&((data.long(ad:0x480C0000+0x28)&0x30)!=0x10)
|
|
group.long 0x0028++0x03
|
|
line.long 0x00 "ALARMHOUR,Alarm Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
|
|
elif ((data.long(ad:0x480C0000+0x40)&0x08)==0x00)&&((data.long(ad:0x480C0000+0x28)&0x30)==0x20)
|
|
group.long 0x0028++0x03
|
|
line.long 0x00 "ALARMHOUR,Alarm Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x0028++0x03
|
|
line.long 0x00 "ALARMHOUR,Alarm Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
if (((data.long(ad:0x480C0000+0x30)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(ad:0x480C0000+0x2c))&0x30)==0x30)
|
|
group.long 0x002C++0x03
|
|
line.long 0x00 "ALARMDAY,Alarm Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(ad:0x480C0000+0x30)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(ad:0x480C0000+0x2c))&0x30)!=0x30)
|
|
group.long 0x002C++0x03
|
|
line.long 0x00 "ALARMDAY,Alarm Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0x480C0000+0x30)&0x1f)==0x02))
|
|
group.long 0x002C++0x03
|
|
line.long 0x00 "ALARMDAY,Alarm Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((data.long(ad:0x480C0000+0x30)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12)))&&(((data.long(ad:0x480C0000+0x2c))&0x30)==0x30)
|
|
group.long 0x002C++0x03
|
|
line.long 0x00 "ALARMDAY,Alarm Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x002C++0x03
|
|
line.long 0x00 "ALARMDAY,Alarm Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
if (((data.long(ad:0x480C0000+0x30))&0x10)==0x10)
|
|
group.long 0x0030++0x03
|
|
line.long 0x00 "ALARMMONTH,Alarm Months Register"
|
|
bitfld.long 0x00 04. " AL_MONTH ,Month" "0,1"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(ad:0x480C0000+0x30))&0x10)==0x00)
|
|
group.long 0x0030++0x03
|
|
line.long 0x00 "ALARMMONTH,Alarm Months Register"
|
|
bitfld.long 0x00 04. " AL_MONTH ,Month" "0,1"
|
|
bitfld.long 0x00 00.--03. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
group.long 0x0034++0x03
|
|
line.long 0x00 "ALARMYEAR,Alarm Years Register"
|
|
bitfld.long 0x00 04.--07. " AL_YEAR ,Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.long 0x0040++0x13
|
|
line.long 0x00 "CTRL,RTC Control Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(cpu()!="AM3872")&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
bitfld.long 0x00 07. " SPLITPOWER ,Enable split power" "Disabled,Enabled"
|
|
bitfld.long 0x00 06. " RTCDISABLE ,Disable RTC" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 06. " RTCDISABLE ,Disable RTC" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET32COUNTER ,Set the 32-kHz counter" "No action,Set"
|
|
sif ((cpuis("AM389*"))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 04. " TESTMODE ,Test mode" "Functional,Test"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " HOURMODE ,Mode 12-hours or 24-hours" "24-hour,12-hour"
|
|
bitfld.long 0x00 02. " AUTOCOMP ,Enable autocompensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 01. " ROUNDMIN ,Round time to the closest minute" "Not rounded,Rounded"
|
|
bitfld.long 0x00 00. " RUN ,Stop RTC" "Stopped,Running"
|
|
line.long 0x04 "STATUS,RTC Status Register"
|
|
sif (cpuis("DRA62*"))
|
|
eventfld.long 0x04 07. " ALARM2 ,Alarm2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x04 06. " ALARM ,Alarm interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 05. " DAYEVT ,One day has occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 04. " HREVT ,One hour has occurred" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 03. " MINEVT ,One minute has occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 02. " SECEVT ,One second has occurred" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 01. " RUN ,RTC run" "Stopped,Running"
|
|
bitfld.long 0x04 00. " BUSY ,Updating event in more than 15 us" "Not busy,Busy"
|
|
line.long 0x08 "INTERRUPT,RTC Interrupt Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x08 04. " ALARM2 ,Enable one interrupt when the alarm2 value is reached" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 03. " ALARM ,Enable one interrupt when the alarm value is reached" "Disabled,Enabled"
|
|
bitfld.long 0x08 02. " TIMER ,Enable periodic interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 00.--01. " EVERY ,Interrupt period" "Every second,Every minute,Every hour,Every day"
|
|
line.long 0x0c "COMPLSB,RTC Compensation LSB Register"
|
|
hexmask.long.byte 0x0c 00.--07. 1. " COMPLSB ,Lower bits of the 16-bit compensation value"
|
|
line.long 0x10 "COMPMSB,RTC Compensation MSB Register"
|
|
hexmask.long.byte 0x10 00.--07. 1. " COMPMSB ,Higher bits of the 16-bit compensation value"
|
|
sif ((cpuis("AM389*"))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
group.long 0x0054++0x03
|
|
else
|
|
wgroup.long 0x0054++0x03
|
|
endif
|
|
line.long 0x00 "OSC,RTC Oscillator Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 6. " 32KCLK_EN ,32-kHz clock enable post clock mux of rtc_32k_clk_rtc_32k_aux_clk and rtc_32k_clk_rtc_32k_clk" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " OSC32K_GZ ,Disable the oscillator and apply high impedance to the output" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " 32KCLK_SEL ,32-kHz clock source select" "rtc_32k_clk_rtc_32k_aux_clk,rtc_32k_clk_rtc_32k_clk"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RES_SELECT ,External feedback resistor" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SW2 ,Inverter size adjustment" "Low,High"
|
|
bitfld.long 0x00 0. " SW1 ,Inverter size adjustment" "Low,High"
|
|
else
|
|
bitfld.long 0x00 05. " SWRESET ,Software reset" "No effect,Reset"
|
|
sif ((cpuis("AM389*"))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 04. " OSC32KPWRDNR ,Control of 32 kHz Oscillator powerdown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 00.--03. " SWRESPROG ,Value of the oscillator resistance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x0060++0x013
|
|
line.long 0x00 "SCRATCH0,Scratch Register 0"
|
|
line.long 0x04 "SCRATCH1,Scratch Register 1"
|
|
line.long 0x08 "SCRATCH2,Scratch Register 2"
|
|
line.long 0x0c "KICK0R,Kick 0 Register"
|
|
line.long 0x10 "KICK1R,Kick 1 Register"
|
|
sif ((cpuis("AM389*"))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
rgroup.long 0x0074++0x03
|
|
line.long 0x00 "REVISION,RTC Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Indicates a software compatible module family"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
group.long 0x0078++0x07
|
|
line.long 0x00 "SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 0.--1. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,Smart-idle/wakeup-capable"
|
|
line.long 0x04 "IRQWAKEEN,Wakeup Enable Register"
|
|
bitfld.long 0x04 1. " ALARM_WAKEEN ,Wakeup generation for event Alarm" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TIMER_WAKEEN ,Wakeup generation for event Timer" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("DRA62*"))
|
|
group.long 0x0080++0x03
|
|
line.long 0x00 "ALARM2SECOND,Alarm2 Seconds Register"
|
|
bitfld.long 0x00 04.--06. " AL_SEC ,Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.long 0x0084++0x03
|
|
line.long 0x00 "ALARM2MINUTE,Alarm2 Minutes Register"
|
|
bitfld.long 0x00 04.--06. " AL_MIN ,Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
if ((data.long(ad:0x480C0000+0x40)&0x08)==0x08)&&((data.long(ad:0x480C0000+0x88)&0x30)==0x10)
|
|
group.long 0x0088++0x03
|
|
line.long 0x00 "ALARM2HOUR,Alarm2 Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
|
|
elif ((data.long(ad:0x480C0000+0x40)&0x08)==0x08)&&((data.long(ad:0x480C0000+0x88)&0x30)!=0x10)
|
|
group.long 0x0088++0x03
|
|
line.long 0x00 "ALARM2HOUR,Alarm2 Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
|
|
elif ((data.long(ad:0x480C0000+0x40)&0x08)==0x00)&&((data.long(ad:0x480C0000+0x88)&0x30)==0x20)
|
|
group.long 0x0088++0x03
|
|
line.long 0x00 "ALARM2HOUR,Alarm2 Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x0088++0x03
|
|
line.long 0x00 "ALARM2HOUR,Alarm2 Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
if (((data.long(ad:0x480C0000+0x90)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(ad:0x480C0000+0x8c))&0x30)==0x30)
|
|
group.long 0x008C++0x03
|
|
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(ad:0x480C0000+0x90)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(ad:0x480C0000+0x8c))&0x30)!=0x30)
|
|
group.long 0x008C++0x03
|
|
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0x480C0000+0x90)&0x1f)==0x02))
|
|
group.long 0x008C++0x03
|
|
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((data.long(ad:0x480C0000+0x90)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12)))&&(((data.long(ad:0x480C0000+0x8c))&0x30)==0x30)
|
|
group.long 0x008C++0x03
|
|
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x008C++0x03
|
|
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
if (((data.long(ad:0x480C0000+0x90))&0x10)==0x10)
|
|
group.long 0x0090++0x03
|
|
line.long 0x00 "ALARM2MONTH,Alarm2 Months Register"
|
|
bitfld.long 0x00 04. " AL_MONTH ,Month" "0,1"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(ad:0x480C0000+0x90))&0x10)==0x00)
|
|
group.long 0x0090++0x03
|
|
line.long 0x00 "ALARM2MONTH,Alarm2 Months Register"
|
|
bitfld.long 0x00 04. " AL_MONTH ,Month" "0,1"
|
|
bitfld.long 0x00 00.--03. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
group.long 0x0094++0x0B
|
|
line.long 0x00 "ALARM2YEAR,Alarm2 Years Register"
|
|
bitfld.long 0x00 04.--07. " AL_YEAR ,Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
line.long 0x04 "RTC_PMIC,RTC PMIC Register"
|
|
bitfld.long 0x04 17.--18. " PWR_ENABL_SM ,Power state machine state" "Idle,Shutdown,Time-based wakeup,External-event-based wakeup"
|
|
bitfld.long 0x04 16. " PWR_ENABLE_EN ,PWR_enable enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x04 15. " EXT_WAKEUP_STATUS[3] ,External wakeup status 3" "Not occurred,Occurred"
|
|
eventfld.long 0x04 14. " EXT_WAKEUP_STATUS[2] ,External wakeup status 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 13. " EXT_WAKEUP_STATUS[1] ,External wakeup status 1" "Not occurred,Occurred"
|
|
eventfld.long 0x04 12. " EXT_WAKEUP_STATUS[0] ,External wakeup status 0" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EXT_WAKEUP_DB_EN[3] ,External wakeup debounce enabled 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " EXT_WAKEUP_DB_EN[2] ,External wakeup debounce enabled 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EXT_WAKEUP_DB_EN[1] ,External wakeup debounce enabled 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EXT_WAKEUP_DB_EN[0] ,External wakeup debounce enabled 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EXT_WAKEUP_POL[3] ,External wakeup inputs polarity 3" "Active high,Active low"
|
|
bitfld.long 0x04 6. " EXT_WAKEUP_POL[2] ,External wakeup inputs polarity 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EXT_WAKEUP_POL[1] ,External wakeup inputs polarity 1" "Active high,Active low"
|
|
bitfld.long 0x04 4. " EXT_WAKEUP_POL[0] ,External wakeup inputs polarity 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EXT_WAKEUP_EN[3] ,Enable external wakeup inputs 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " EXT_WAKEUP_EN[2] ,Enable external wakeup inputs 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EXT_WAKEUP_EN[1] ,Enable external wakeup inputs 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EXT_WAKEUP_EN[0] ,Enable external wakeup inputs 0" "Disabled,Enabled"
|
|
line.long 0x08 "RTC_DEBOUNCE,RTC Debounce Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " XX ,xx"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DEBOUNCE_REG ,Debounce time"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.open "GPIO (General Purpose Input/Output)"
|
|
tree "GPIO 0"
|
|
base ad:0x48032000
|
|
width 25.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPIO_REVISION,GPIO Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Old/current scheme " "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL version"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major Revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Special version for a particular device"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO System Configuration Register"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle"
|
|
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x00 "GPIO_EOI,GPIO End Of Interrupt Control Register"
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt Control" "Line #1,Line #2"
|
|
width 25.
|
|
group.long 0x24++0x7
|
|
line.long 0x00 "GPIO_IRQSTATUS_RAW_0,GPIO Status/Set Raw Register for Interrupt 1"
|
|
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQSTATUS_RAW_1,GPIO Status/Set Raw Register for Interrupt 2"
|
|
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
|
|
width 25.
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "GPIO_IRQSTATUS_0_set/clr,GPIO Status Register for Interrupt 1"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "GPIO_IRQSTATUS_1_set/clr,GPIO Status Register for Interrupt 2"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
|
|
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
|
|
width 25.
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "GPIO_IRQWAKEN_0,Wakeup Enable Register for Interrupt 1"
|
|
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPIO_IRQWAKEN_1,Wakeup Enable Register for Interrupt 2"
|
|
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
|
|
endif
|
|
width 25.
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO System Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed"
|
|
group.long 0x130++0x7
|
|
line.long 0x00 "GPIO_CTRL,GPIO Module Control Register"
|
|
bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x04 "GPIO_OE,Output Enable Register"
|
|
bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
|
bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
|
|
bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
|
bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
|
bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
|
|
bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
|
bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
|
|
bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
|
|
width 25.
|
|
rgroup.long 0x138++0x3
|
|
line.long 0x00 "GPIO_DATAIN,Sampled Input Data Register"
|
|
sif (cpuis("AM387*")||cpuis("DRA62*"))
|
|
bitfld.long 0x00 31. " DATAIN[31] ,Sampled Input 31" "Low,High"
|
|
bitfld.long 0x00 30. " DATAIN[30] ,Sampled Input 30" "Low,High"
|
|
bitfld.long 0x00 29. " DATAIN[29] ,Sampled Input 29" "Low,High"
|
|
bitfld.long 0x00 28. " DATAIN[28] ,Sampled Input 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DATAIN[27] ,Sampled Input 27" "Low,High"
|
|
bitfld.long 0x00 26. " DATAIN[26] ,Sampled Input 26" "Low,High"
|
|
bitfld.long 0x00 25. " DATAIN[25] ,Sampled Input 25" "Low,High"
|
|
bitfld.long 0x00 24. " DATAIN[24] ,Sampled Input 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DATAIN[23] ,Sampled Input 23" "Low,High"
|
|
bitfld.long 0x00 22. " DATAIN[22] ,Sampled Input 22" "Low,High"
|
|
bitfld.long 0x00 21. " DATAIN[21] ,Sampled Input 21" "Low,High"
|
|
bitfld.long 0x00 20. " DATAIN[20] ,Sampled Input 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DATAIN[19] ,Sampled Input 19" "Low,High"
|
|
bitfld.long 0x00 18. " DATAIN[18] ,Sampled Input 18" "Low,High"
|
|
bitfld.long 0x00 17. " DATAIN[17] ,Sampled Input 17" "Low,High"
|
|
bitfld.long 0x00 16. " DATAIN[16] ,Sampled Input 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DATAIN[15] ,Sampled Input 15" "Low,High"
|
|
bitfld.long 0x00 14. " DATAIN[14] ,Sampled Input 14" "Low,High"
|
|
bitfld.long 0x00 13. " DATAIN[13] ,Sampled Input 13" "Low,High"
|
|
bitfld.long 0x00 12. " DATAIN[12] ,Sampled Input 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DATAIN[11] ,Sampled Input 11" "Low,High"
|
|
bitfld.long 0x00 10. " DATAIN[10] ,Sampled Input 10" "Low,High"
|
|
bitfld.long 0x00 9. " DATAIN[9] ,Sampled Input 9" "Low,High"
|
|
bitfld.long 0x00 8. " DATAIN[8] ,Sampled Input 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DATAIN[7] ,Sampled Input 7" "Low,High"
|
|
bitfld.long 0x00 6. " DATAIN[6] ,Sampled Input 6" "Low,High"
|
|
bitfld.long 0x00 5. " DATAIN[5] ,Sampled Input 5" "Low,High"
|
|
bitfld.long 0x00 4. " DATAIN[4] ,Sampled Input 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATAIN[3] ,Sampled Input 3" "Low,High"
|
|
bitfld.long 0x00 2. " DATAIN[2] ,Sampled Input 2" "Low,High"
|
|
bitfld.long 0x00 1. " DATAIN[1] ,Sampled Input 1" "Low,High"
|
|
bitfld.long 0x00 0. " DATAIN[0] ,Sampled Input 0" "Low,High"
|
|
endif
|
|
width 25.
|
|
group.long 0x13c++0x3
|
|
line.long 0x00 "GPIO_DATAOUT,Output Data Register"
|
|
setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
|
|
setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
|
|
setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
|
|
setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
|
|
setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
|
|
setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
|
|
setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
|
|
setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
|
|
setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
|
|
setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
|
|
setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
|
|
setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
|
|
setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
|
|
setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
|
|
setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
|
|
setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
|
|
setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
|
setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
|
setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
|
setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
|
setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
|
setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
|
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
|
|
setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
|
|
setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
|
|
width 25.
|
|
group.long 0x140++0x17
|
|
line.long 0x00 "GPIO_LEVELDETECT0,Low-level Detection Enable Register"
|
|
bitfld.long 0x00 31. " LEVELDETECT0[31] ,Low Level Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LEVELDETECT0[30] ,Low Level Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LEVELDETECT0[29] ,Low Level Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " LEVELDETECT0[28] ,Low Level Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LEVELDETECT0[27] ,Low Level Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " LEVELDETECT0[26] ,Low Level Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEVELDETECT0[25] ,Low Level Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEVELDETECT0[24] ,Low Level Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LEVELDETECT0[23] ,Low Level Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " LEVELDETECT0[22] ,Low Level Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " LEVELDETECT0[21] ,Low Level Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LEVELDETECT0[20] ,Low Level Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LEVELDETECT0[19] ,Low Level Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " LEVELDETECT0[18] ,Low Level Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LEVELDETECT0[17] ,Low Level Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LEVELDETECT0[16] ,Low Level Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LEVELDETECT0[15] ,Low Level Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LEVELDETECT0[14] ,Low Level Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LEVELDETECT0[13] ,Low Level Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LEVELDETECT0[12] ,Low Level Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LEVELDETECT0[11] ,Low Level Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LEVELDETECT0[10] ,Low Level Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LEVELDETECT0[9] ,Low Level Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LEVELDETECT0[8] ,Low Level Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LEVELDETECT0[7] ,Low Level Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LEVELDETECT0[6] ,Low Level Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LEVELDETECT0[5] ,Low Level Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LEVELDETECT0[4] ,Low Level Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LEVELDETECT0[3] ,Low Level Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LEVELDETECT0[2] ,Low Level Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LEVELDETECT0[1] ,Low Level Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LEVELDETECT0[0] ,Low Level Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPIO_LEVELDETECT1,High-level Detection Enable Register"
|
|
bitfld.long 0x04 31. " LEVELDETECT1[31] ,High Level Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " LEVELDETECT1[30] ,High Level Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " LEVELDETECT1[29] ,High Level Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " LEVELDETECT1[28] ,High Level Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " LEVELDETECT1[27] ,High Level Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " LEVELDETECT1[26] ,High Level Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " LEVELDETECT1[25] ,High Level Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " LEVELDETECT1[24] ,High Level Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " LEVELDETECT1[23] ,High Level Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LEVELDETECT1[22] ,High Level Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " LEVELDETECT1[21] ,High Level Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LEVELDETECT1[20] ,High Level Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LEVELDETECT1[19] ,High Level Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LEVELDETECT1[18] ,High Level Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " LEVELDETECT1[17] ,High Level Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " LEVELDETECT1[16] ,High Level Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LEVELDETECT1[15] ,High Level Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LEVELDETECT1[14] ,High Level Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " LEVELDETECT1[13] ,High Level Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LEVELDETECT1[12] ,High Level Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LEVELDETECT1[11] ,High Level Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LEVELDETECT1[10] ,High Level Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " LEVELDETECT1[9] ,High Level Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LEVELDETECT1[8] ,High Level Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LEVELDETECT1[7] ,High Level Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LEVELDETECT1[6] ,High Level Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " LEVELDETECT1[5] ,High Level Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LEVELDETECT1[4] ,High Level Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LEVELDETECT1[3] ,High Level Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LEVELDETECT1[2] ,High Level Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " LEVELDETECT1[1] ,High Level Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LEVELDETECT1[0] ,High Level Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_RISINGDETECT,Rising-edge Detection Enable Register"
|
|
bitfld.long 0x08 31. " RISINGDETECT[31] ,Rising Edge Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " RISINGDETECT[30] ,Rising Edge Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " RISINGDETECT[29] ,Rising Edge Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " RISINGDETECT[28] ,Rising Edge Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " RISINGDETECT[27] ,Rising Edge Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " RISINGDETECT[26] ,Rising Edge Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " RISINGDETECT[25] ,Rising Edge Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " RISINGDETECT[24] ,Rising Edge Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " RISINGDETECT[23] ,Rising Edge Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " RISINGDETECT[22] ,Rising Edge Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " RISINGDETECT[21] ,Rising Edge Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " RISINGDETECT[20] ,Rising Edge Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " RISINGDETECT[19] ,Rising Edge Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " RISINGDETECT[18] ,Rising Edge Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " RISINGDETECT[17] ,Rising Edge Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " RISINGDETECT[16] ,Rising Edge Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " RISINGDETECT[15] ,Rising Edge Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " RISINGDETECT[14] ,Rising Edge Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " RISINGDETECT[13] ,Rising Edge Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " RISINGDETECT[12] ,Rising Edge Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " RISINGDETECT[11] ,Rising Edge Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " RISINGDETECT[10] ,Rising Edge Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " RISINGDETECT[9] ,Rising Edge Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RISINGDETECT[8] ,Rising Edge Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " RISINGDETECT[7] ,Rising Edge Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RISINGDETECT[6] ,Rising Edge Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " RISINGDETECT[5] ,Rising Edge Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RISINGDETECT[4] ,Rising Edge Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RISINGDETECT[3] ,Rising Edge Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RISINGDETECT[2] ,Rising Edge Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RISINGDETECT[1] ,Rising Edge Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " RISINGDETECT[0] ,Rising Edge Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_FALLINGDETECT,Falling-edge Detection Enable Register"
|
|
bitfld.long 0x0c 31. " FALLINGDETECT[31] ,Falling Edge Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " FALLINGDETECT[30] ,Falling Edge Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 29. " FALLINGDETECT[29] ,Falling Edge Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " FALLINGDETECT[28] ,Falling Edge Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " FALLINGDETECT[27] ,Falling Edge Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " FALLINGDETECT[26] ,Falling Edge Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 25. " FALLINGDETECT[25] ,Falling Edge Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " FALLINGDETECT[24] ,Falling Edge Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " FALLINGDETECT[23] ,Falling Edge Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " FALLINGDETECT[22] ,Falling Edge Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 21. " FALLINGDETECT[21] ,Falling Edge Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " FALLINGDETECT[20] ,Falling Edge Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " FALLINGDETECT[19] ,Falling Edge Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " FALLINGDETECT[18] ,Falling Edge Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 17. " FALLINGDETECT[17] ,Falling Edge Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " FALLINGDETECT[16] ,Falling Edge Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " FALLINGDETECT[15] ,Falling Edge Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " FALLINGDETECT[14] ,Falling Edge Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 13. " FALLINGDETECT[13] ,Falling Edge Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " FALLINGDETECT[12] ,Falling Edge Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " FALLINGDETECT[11] ,Falling Edge Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " FALLINGDETECT[10] ,Falling Edge Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " FALLINGDETECT[9] ,Falling Edge Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " FALLINGDETECT[8] ,Falling Edge Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " FALLINGDETECT[7] ,Falling Edge Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " FALLINGDETECT[6] ,Falling Edge Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " FALLINGDETECT[5] ,Falling Edge Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " FALLINGDETECT[4] ,Falling Edge Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " FALLINGDETECT[3] ,Falling Edge Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " FALLINGDETECT[2] ,Falling Edge Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 1. " FALLINGDETECT[1] ,Falling Edge Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " FALLINGDETECT[0] ,Falling Edge Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_DEBOUNCENABLE,Debounce Enable Register"
|
|
bitfld.long 0x10 31. " DEBOUNCEENABLE[31] ,Input Debounce 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " DEBOUNCEENABLE[30] ,Input Debounce 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " DEBOUNCEENABLE[29] ,Input Debounce 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " DEBOUNCEENABLE[28] ,Input Debounce 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " DEBOUNCEENABLE[27] ,Input Debounce 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " DEBOUNCEENABLE[26] ,Input Debounce 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " DEBOUNCEENABLE[25] ,Input Debounce 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " DEBOUNCEENABLE[24] ,Input Debounce 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " DEBOUNCEENABLE[23] ,Input Debounce 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DEBOUNCEENABLE[22] ,Input Debounce 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DEBOUNCEENABLE[21] ,Input Debounce 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DEBOUNCEENABLE[20] ,Input Debounce 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DEBOUNCEENABLE[19] ,Input Debounce 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DEBOUNCEENABLE[18] ,Input Debounce 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DEBOUNCEENABLE[17] ,Input Debounce 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DEBOUNCEENABLE[16] ,Input Debounce 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DEBOUNCEENABLE[15] ,Input Debounce 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DEBOUNCEENABLE[14] ,Input Debounce 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DEBOUNCEENABLE[13] ,Input Debounce 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DEBOUNCEENABLE[12] ,Input Debounce 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DEBOUNCEENABLE[11] ,Input Debounce 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DEBOUNCEENABLE[10] ,Input Debounce 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DEBOUNCEENABLE[9] ,Input Debounce 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DEBOUNCEENABLE[8] ,Input Debounce 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DEBOUNCEENABLE[7] ,Input Debounce 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DEBOUNCEENABLE[6] ,Input Debounce 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DEBOUNCEENABLE[5] ,Input Debounce 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DEBOUNCEENABLE[4] ,Input Debounce 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DEBOUNCEENABLE[3] ,Input Debounce 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DEBOUNCEENABLE[2] ,Input Debounce 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DEBOUNCEENABLE[1] ,Input Debounce 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DEBOUNCEENABLE[0] ,Input Debounce 0 Enable" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCINGTIME,Debounce Time Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DEBOUNCETIME ,Input Debouncing Value (in 31 ms steps)"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO 1"
|
|
base ad:0x4804c000
|
|
width 25.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPIO_REVISION,GPIO Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Old/current scheme " "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL version"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major Revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Special version for a particular device"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO System Configuration Register"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle"
|
|
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x00 "GPIO_EOI,GPIO End Of Interrupt Control Register"
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt Control" "Line #1,Line #2"
|
|
width 25.
|
|
group.long 0x24++0x7
|
|
line.long 0x00 "GPIO_IRQSTATUS_RAW_0,GPIO Status/Set Raw Register for Interrupt 1"
|
|
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQSTATUS_RAW_1,GPIO Status/Set Raw Register for Interrupt 2"
|
|
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
|
|
width 25.
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "GPIO_IRQSTATUS_0_set/clr,GPIO Status Register for Interrupt 1"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "GPIO_IRQSTATUS_1_set/clr,GPIO Status Register for Interrupt 2"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
|
|
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
|
|
width 25.
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "GPIO_IRQWAKEN_0,Wakeup Enable Register for Interrupt 1"
|
|
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPIO_IRQWAKEN_1,Wakeup Enable Register for Interrupt 2"
|
|
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
|
|
endif
|
|
width 25.
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO System Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed"
|
|
group.long 0x130++0x7
|
|
line.long 0x00 "GPIO_CTRL,GPIO Module Control Register"
|
|
bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x04 "GPIO_OE,Output Enable Register"
|
|
bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
|
bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
|
|
bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
|
bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
|
bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
|
|
bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
|
bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
|
|
bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
|
|
width 25.
|
|
rgroup.long 0x138++0x3
|
|
line.long 0x00 "GPIO_DATAIN,Sampled Input Data Register"
|
|
sif (cpuis("AM387*")||cpuis("DRA62*"))
|
|
bitfld.long 0x00 31. " DATAIN[31] ,Sampled Input 31" "Low,High"
|
|
bitfld.long 0x00 30. " DATAIN[30] ,Sampled Input 30" "Low,High"
|
|
bitfld.long 0x00 29. " DATAIN[29] ,Sampled Input 29" "Low,High"
|
|
bitfld.long 0x00 28. " DATAIN[28] ,Sampled Input 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DATAIN[27] ,Sampled Input 27" "Low,High"
|
|
bitfld.long 0x00 26. " DATAIN[26] ,Sampled Input 26" "Low,High"
|
|
bitfld.long 0x00 25. " DATAIN[25] ,Sampled Input 25" "Low,High"
|
|
bitfld.long 0x00 24. " DATAIN[24] ,Sampled Input 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DATAIN[23] ,Sampled Input 23" "Low,High"
|
|
bitfld.long 0x00 22. " DATAIN[22] ,Sampled Input 22" "Low,High"
|
|
bitfld.long 0x00 21. " DATAIN[21] ,Sampled Input 21" "Low,High"
|
|
bitfld.long 0x00 20. " DATAIN[20] ,Sampled Input 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DATAIN[19] ,Sampled Input 19" "Low,High"
|
|
bitfld.long 0x00 18. " DATAIN[18] ,Sampled Input 18" "Low,High"
|
|
bitfld.long 0x00 17. " DATAIN[17] ,Sampled Input 17" "Low,High"
|
|
bitfld.long 0x00 16. " DATAIN[16] ,Sampled Input 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DATAIN[15] ,Sampled Input 15" "Low,High"
|
|
bitfld.long 0x00 14. " DATAIN[14] ,Sampled Input 14" "Low,High"
|
|
bitfld.long 0x00 13. " DATAIN[13] ,Sampled Input 13" "Low,High"
|
|
bitfld.long 0x00 12. " DATAIN[12] ,Sampled Input 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DATAIN[11] ,Sampled Input 11" "Low,High"
|
|
bitfld.long 0x00 10. " DATAIN[10] ,Sampled Input 10" "Low,High"
|
|
bitfld.long 0x00 9. " DATAIN[9] ,Sampled Input 9" "Low,High"
|
|
bitfld.long 0x00 8. " DATAIN[8] ,Sampled Input 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DATAIN[7] ,Sampled Input 7" "Low,High"
|
|
bitfld.long 0x00 6. " DATAIN[6] ,Sampled Input 6" "Low,High"
|
|
bitfld.long 0x00 5. " DATAIN[5] ,Sampled Input 5" "Low,High"
|
|
bitfld.long 0x00 4. " DATAIN[4] ,Sampled Input 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATAIN[3] ,Sampled Input 3" "Low,High"
|
|
bitfld.long 0x00 2. " DATAIN[2] ,Sampled Input 2" "Low,High"
|
|
bitfld.long 0x00 1. " DATAIN[1] ,Sampled Input 1" "Low,High"
|
|
bitfld.long 0x00 0. " DATAIN[0] ,Sampled Input 0" "Low,High"
|
|
endif
|
|
width 25.
|
|
group.long 0x13c++0x3
|
|
line.long 0x00 "GPIO_DATAOUT,Output Data Register"
|
|
setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
|
|
setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
|
|
setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
|
|
setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
|
|
setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
|
|
setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
|
|
setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
|
|
setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
|
|
setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
|
|
setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
|
|
setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
|
|
setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
|
|
setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
|
|
setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
|
|
setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
|
|
setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
|
|
setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
|
setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
|
setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
|
setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
|
setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
|
setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
|
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
|
|
setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
|
|
setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
|
|
width 25.
|
|
group.long 0x140++0x17
|
|
line.long 0x00 "GPIO_LEVELDETECT0,Low-level Detection Enable Register"
|
|
bitfld.long 0x00 31. " LEVELDETECT0[31] ,Low Level Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LEVELDETECT0[30] ,Low Level Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LEVELDETECT0[29] ,Low Level Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " LEVELDETECT0[28] ,Low Level Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LEVELDETECT0[27] ,Low Level Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " LEVELDETECT0[26] ,Low Level Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEVELDETECT0[25] ,Low Level Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEVELDETECT0[24] ,Low Level Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LEVELDETECT0[23] ,Low Level Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " LEVELDETECT0[22] ,Low Level Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " LEVELDETECT0[21] ,Low Level Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LEVELDETECT0[20] ,Low Level Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LEVELDETECT0[19] ,Low Level Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " LEVELDETECT0[18] ,Low Level Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LEVELDETECT0[17] ,Low Level Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LEVELDETECT0[16] ,Low Level Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LEVELDETECT0[15] ,Low Level Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LEVELDETECT0[14] ,Low Level Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LEVELDETECT0[13] ,Low Level Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LEVELDETECT0[12] ,Low Level Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LEVELDETECT0[11] ,Low Level Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LEVELDETECT0[10] ,Low Level Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LEVELDETECT0[9] ,Low Level Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LEVELDETECT0[8] ,Low Level Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LEVELDETECT0[7] ,Low Level Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LEVELDETECT0[6] ,Low Level Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LEVELDETECT0[5] ,Low Level Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LEVELDETECT0[4] ,Low Level Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LEVELDETECT0[3] ,Low Level Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LEVELDETECT0[2] ,Low Level Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LEVELDETECT0[1] ,Low Level Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LEVELDETECT0[0] ,Low Level Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPIO_LEVELDETECT1,High-level Detection Enable Register"
|
|
bitfld.long 0x04 31. " LEVELDETECT1[31] ,High Level Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " LEVELDETECT1[30] ,High Level Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " LEVELDETECT1[29] ,High Level Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " LEVELDETECT1[28] ,High Level Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " LEVELDETECT1[27] ,High Level Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " LEVELDETECT1[26] ,High Level Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " LEVELDETECT1[25] ,High Level Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " LEVELDETECT1[24] ,High Level Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " LEVELDETECT1[23] ,High Level Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LEVELDETECT1[22] ,High Level Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " LEVELDETECT1[21] ,High Level Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LEVELDETECT1[20] ,High Level Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LEVELDETECT1[19] ,High Level Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LEVELDETECT1[18] ,High Level Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " LEVELDETECT1[17] ,High Level Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " LEVELDETECT1[16] ,High Level Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LEVELDETECT1[15] ,High Level Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LEVELDETECT1[14] ,High Level Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " LEVELDETECT1[13] ,High Level Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LEVELDETECT1[12] ,High Level Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LEVELDETECT1[11] ,High Level Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LEVELDETECT1[10] ,High Level Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " LEVELDETECT1[9] ,High Level Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LEVELDETECT1[8] ,High Level Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LEVELDETECT1[7] ,High Level Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LEVELDETECT1[6] ,High Level Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " LEVELDETECT1[5] ,High Level Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LEVELDETECT1[4] ,High Level Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LEVELDETECT1[3] ,High Level Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LEVELDETECT1[2] ,High Level Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " LEVELDETECT1[1] ,High Level Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LEVELDETECT1[0] ,High Level Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_RISINGDETECT,Rising-edge Detection Enable Register"
|
|
bitfld.long 0x08 31. " RISINGDETECT[31] ,Rising Edge Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " RISINGDETECT[30] ,Rising Edge Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " RISINGDETECT[29] ,Rising Edge Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " RISINGDETECT[28] ,Rising Edge Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " RISINGDETECT[27] ,Rising Edge Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " RISINGDETECT[26] ,Rising Edge Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " RISINGDETECT[25] ,Rising Edge Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " RISINGDETECT[24] ,Rising Edge Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " RISINGDETECT[23] ,Rising Edge Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " RISINGDETECT[22] ,Rising Edge Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " RISINGDETECT[21] ,Rising Edge Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " RISINGDETECT[20] ,Rising Edge Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " RISINGDETECT[19] ,Rising Edge Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " RISINGDETECT[18] ,Rising Edge Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " RISINGDETECT[17] ,Rising Edge Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " RISINGDETECT[16] ,Rising Edge Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " RISINGDETECT[15] ,Rising Edge Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " RISINGDETECT[14] ,Rising Edge Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " RISINGDETECT[13] ,Rising Edge Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " RISINGDETECT[12] ,Rising Edge Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " RISINGDETECT[11] ,Rising Edge Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " RISINGDETECT[10] ,Rising Edge Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " RISINGDETECT[9] ,Rising Edge Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RISINGDETECT[8] ,Rising Edge Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " RISINGDETECT[7] ,Rising Edge Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RISINGDETECT[6] ,Rising Edge Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " RISINGDETECT[5] ,Rising Edge Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RISINGDETECT[4] ,Rising Edge Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RISINGDETECT[3] ,Rising Edge Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RISINGDETECT[2] ,Rising Edge Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RISINGDETECT[1] ,Rising Edge Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " RISINGDETECT[0] ,Rising Edge Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_FALLINGDETECT,Falling-edge Detection Enable Register"
|
|
bitfld.long 0x0c 31. " FALLINGDETECT[31] ,Falling Edge Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " FALLINGDETECT[30] ,Falling Edge Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 29. " FALLINGDETECT[29] ,Falling Edge Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " FALLINGDETECT[28] ,Falling Edge Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " FALLINGDETECT[27] ,Falling Edge Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " FALLINGDETECT[26] ,Falling Edge Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 25. " FALLINGDETECT[25] ,Falling Edge Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " FALLINGDETECT[24] ,Falling Edge Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " FALLINGDETECT[23] ,Falling Edge Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " FALLINGDETECT[22] ,Falling Edge Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 21. " FALLINGDETECT[21] ,Falling Edge Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " FALLINGDETECT[20] ,Falling Edge Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " FALLINGDETECT[19] ,Falling Edge Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " FALLINGDETECT[18] ,Falling Edge Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 17. " FALLINGDETECT[17] ,Falling Edge Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " FALLINGDETECT[16] ,Falling Edge Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " FALLINGDETECT[15] ,Falling Edge Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " FALLINGDETECT[14] ,Falling Edge Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 13. " FALLINGDETECT[13] ,Falling Edge Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " FALLINGDETECT[12] ,Falling Edge Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " FALLINGDETECT[11] ,Falling Edge Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " FALLINGDETECT[10] ,Falling Edge Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " FALLINGDETECT[9] ,Falling Edge Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " FALLINGDETECT[8] ,Falling Edge Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " FALLINGDETECT[7] ,Falling Edge Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " FALLINGDETECT[6] ,Falling Edge Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " FALLINGDETECT[5] ,Falling Edge Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " FALLINGDETECT[4] ,Falling Edge Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " FALLINGDETECT[3] ,Falling Edge Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " FALLINGDETECT[2] ,Falling Edge Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 1. " FALLINGDETECT[1] ,Falling Edge Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " FALLINGDETECT[0] ,Falling Edge Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_DEBOUNCENABLE,Debounce Enable Register"
|
|
bitfld.long 0x10 31. " DEBOUNCEENABLE[31] ,Input Debounce 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " DEBOUNCEENABLE[30] ,Input Debounce 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " DEBOUNCEENABLE[29] ,Input Debounce 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " DEBOUNCEENABLE[28] ,Input Debounce 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " DEBOUNCEENABLE[27] ,Input Debounce 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " DEBOUNCEENABLE[26] ,Input Debounce 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " DEBOUNCEENABLE[25] ,Input Debounce 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " DEBOUNCEENABLE[24] ,Input Debounce 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " DEBOUNCEENABLE[23] ,Input Debounce 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DEBOUNCEENABLE[22] ,Input Debounce 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DEBOUNCEENABLE[21] ,Input Debounce 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DEBOUNCEENABLE[20] ,Input Debounce 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DEBOUNCEENABLE[19] ,Input Debounce 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DEBOUNCEENABLE[18] ,Input Debounce 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DEBOUNCEENABLE[17] ,Input Debounce 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DEBOUNCEENABLE[16] ,Input Debounce 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DEBOUNCEENABLE[15] ,Input Debounce 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DEBOUNCEENABLE[14] ,Input Debounce 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DEBOUNCEENABLE[13] ,Input Debounce 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DEBOUNCEENABLE[12] ,Input Debounce 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DEBOUNCEENABLE[11] ,Input Debounce 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DEBOUNCEENABLE[10] ,Input Debounce 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DEBOUNCEENABLE[9] ,Input Debounce 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DEBOUNCEENABLE[8] ,Input Debounce 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DEBOUNCEENABLE[7] ,Input Debounce 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DEBOUNCEENABLE[6] ,Input Debounce 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DEBOUNCEENABLE[5] ,Input Debounce 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DEBOUNCEENABLE[4] ,Input Debounce 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DEBOUNCEENABLE[3] ,Input Debounce 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DEBOUNCEENABLE[2] ,Input Debounce 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DEBOUNCEENABLE[1] ,Input Debounce 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DEBOUNCEENABLE[0] ,Input Debounce 0 Enable" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCINGTIME,Debounce Time Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DEBOUNCETIME ,Input Debouncing Value (in 31 ms steps)"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO 2"
|
|
base ad:0x481ac000
|
|
width 25.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPIO_REVISION,GPIO Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Old/current scheme " "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL version"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major Revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Special version for a particular device"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO System Configuration Register"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle"
|
|
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x00 "GPIO_EOI,GPIO End Of Interrupt Control Register"
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt Control" "Line #1,Line #2"
|
|
width 25.
|
|
group.long 0x24++0x7
|
|
line.long 0x00 "GPIO_IRQSTATUS_RAW_0,GPIO Status/Set Raw Register for Interrupt 1"
|
|
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQSTATUS_RAW_1,GPIO Status/Set Raw Register for Interrupt 2"
|
|
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
|
|
width 25.
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "GPIO_IRQSTATUS_0_set/clr,GPIO Status Register for Interrupt 1"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "GPIO_IRQSTATUS_1_set/clr,GPIO Status Register for Interrupt 2"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
|
|
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
|
|
width 25.
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "GPIO_IRQWAKEN_0,Wakeup Enable Register for Interrupt 1"
|
|
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPIO_IRQWAKEN_1,Wakeup Enable Register for Interrupt 2"
|
|
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
|
|
endif
|
|
width 25.
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO System Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed"
|
|
group.long 0x130++0x7
|
|
line.long 0x00 "GPIO_CTRL,GPIO Module Control Register"
|
|
bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x04 "GPIO_OE,Output Enable Register"
|
|
bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
|
bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
|
|
bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
|
bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
|
bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
|
|
bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
|
bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
|
|
bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
|
|
width 25.
|
|
rgroup.long 0x138++0x3
|
|
line.long 0x00 "GPIO_DATAIN,Sampled Input Data Register"
|
|
sif (cpuis("AM387*")||cpuis("DRA62*"))
|
|
bitfld.long 0x00 31. " DATAIN[31] ,Sampled Input 31" "Low,High"
|
|
bitfld.long 0x00 30. " DATAIN[30] ,Sampled Input 30" "Low,High"
|
|
bitfld.long 0x00 29. " DATAIN[29] ,Sampled Input 29" "Low,High"
|
|
bitfld.long 0x00 28. " DATAIN[28] ,Sampled Input 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DATAIN[27] ,Sampled Input 27" "Low,High"
|
|
bitfld.long 0x00 26. " DATAIN[26] ,Sampled Input 26" "Low,High"
|
|
bitfld.long 0x00 25. " DATAIN[25] ,Sampled Input 25" "Low,High"
|
|
bitfld.long 0x00 24. " DATAIN[24] ,Sampled Input 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DATAIN[23] ,Sampled Input 23" "Low,High"
|
|
bitfld.long 0x00 22. " DATAIN[22] ,Sampled Input 22" "Low,High"
|
|
bitfld.long 0x00 21. " DATAIN[21] ,Sampled Input 21" "Low,High"
|
|
bitfld.long 0x00 20. " DATAIN[20] ,Sampled Input 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DATAIN[19] ,Sampled Input 19" "Low,High"
|
|
bitfld.long 0x00 18. " DATAIN[18] ,Sampled Input 18" "Low,High"
|
|
bitfld.long 0x00 17. " DATAIN[17] ,Sampled Input 17" "Low,High"
|
|
bitfld.long 0x00 16. " DATAIN[16] ,Sampled Input 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DATAIN[15] ,Sampled Input 15" "Low,High"
|
|
bitfld.long 0x00 14. " DATAIN[14] ,Sampled Input 14" "Low,High"
|
|
bitfld.long 0x00 13. " DATAIN[13] ,Sampled Input 13" "Low,High"
|
|
bitfld.long 0x00 12. " DATAIN[12] ,Sampled Input 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DATAIN[11] ,Sampled Input 11" "Low,High"
|
|
bitfld.long 0x00 10. " DATAIN[10] ,Sampled Input 10" "Low,High"
|
|
bitfld.long 0x00 9. " DATAIN[9] ,Sampled Input 9" "Low,High"
|
|
bitfld.long 0x00 8. " DATAIN[8] ,Sampled Input 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DATAIN[7] ,Sampled Input 7" "Low,High"
|
|
bitfld.long 0x00 6. " DATAIN[6] ,Sampled Input 6" "Low,High"
|
|
bitfld.long 0x00 5. " DATAIN[5] ,Sampled Input 5" "Low,High"
|
|
bitfld.long 0x00 4. " DATAIN[4] ,Sampled Input 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATAIN[3] ,Sampled Input 3" "Low,High"
|
|
bitfld.long 0x00 2. " DATAIN[2] ,Sampled Input 2" "Low,High"
|
|
bitfld.long 0x00 1. " DATAIN[1] ,Sampled Input 1" "Low,High"
|
|
bitfld.long 0x00 0. " DATAIN[0] ,Sampled Input 0" "Low,High"
|
|
endif
|
|
width 25.
|
|
group.long 0x13c++0x3
|
|
line.long 0x00 "GPIO_DATAOUT,Output Data Register"
|
|
setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
|
|
setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
|
|
setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
|
|
setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
|
|
setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
|
|
setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
|
|
setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
|
|
setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
|
|
setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
|
|
setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
|
|
setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
|
|
setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
|
|
setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
|
|
setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
|
|
setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
|
|
setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
|
|
setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
|
setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
|
setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
|
setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
|
setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
|
setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
|
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
|
|
setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
|
|
setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
|
|
width 25.
|
|
group.long 0x140++0x17
|
|
line.long 0x00 "GPIO_LEVELDETECT0,Low-level Detection Enable Register"
|
|
bitfld.long 0x00 31. " LEVELDETECT0[31] ,Low Level Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LEVELDETECT0[30] ,Low Level Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LEVELDETECT0[29] ,Low Level Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " LEVELDETECT0[28] ,Low Level Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LEVELDETECT0[27] ,Low Level Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " LEVELDETECT0[26] ,Low Level Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEVELDETECT0[25] ,Low Level Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEVELDETECT0[24] ,Low Level Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LEVELDETECT0[23] ,Low Level Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " LEVELDETECT0[22] ,Low Level Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " LEVELDETECT0[21] ,Low Level Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LEVELDETECT0[20] ,Low Level Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LEVELDETECT0[19] ,Low Level Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " LEVELDETECT0[18] ,Low Level Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LEVELDETECT0[17] ,Low Level Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LEVELDETECT0[16] ,Low Level Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LEVELDETECT0[15] ,Low Level Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LEVELDETECT0[14] ,Low Level Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LEVELDETECT0[13] ,Low Level Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LEVELDETECT0[12] ,Low Level Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LEVELDETECT0[11] ,Low Level Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LEVELDETECT0[10] ,Low Level Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LEVELDETECT0[9] ,Low Level Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LEVELDETECT0[8] ,Low Level Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LEVELDETECT0[7] ,Low Level Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LEVELDETECT0[6] ,Low Level Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LEVELDETECT0[5] ,Low Level Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LEVELDETECT0[4] ,Low Level Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LEVELDETECT0[3] ,Low Level Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LEVELDETECT0[2] ,Low Level Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LEVELDETECT0[1] ,Low Level Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LEVELDETECT0[0] ,Low Level Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPIO_LEVELDETECT1,High-level Detection Enable Register"
|
|
bitfld.long 0x04 31. " LEVELDETECT1[31] ,High Level Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " LEVELDETECT1[30] ,High Level Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " LEVELDETECT1[29] ,High Level Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " LEVELDETECT1[28] ,High Level Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " LEVELDETECT1[27] ,High Level Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " LEVELDETECT1[26] ,High Level Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " LEVELDETECT1[25] ,High Level Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " LEVELDETECT1[24] ,High Level Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " LEVELDETECT1[23] ,High Level Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LEVELDETECT1[22] ,High Level Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " LEVELDETECT1[21] ,High Level Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LEVELDETECT1[20] ,High Level Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LEVELDETECT1[19] ,High Level Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LEVELDETECT1[18] ,High Level Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " LEVELDETECT1[17] ,High Level Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " LEVELDETECT1[16] ,High Level Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LEVELDETECT1[15] ,High Level Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LEVELDETECT1[14] ,High Level Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " LEVELDETECT1[13] ,High Level Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LEVELDETECT1[12] ,High Level Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LEVELDETECT1[11] ,High Level Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LEVELDETECT1[10] ,High Level Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " LEVELDETECT1[9] ,High Level Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LEVELDETECT1[8] ,High Level Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LEVELDETECT1[7] ,High Level Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LEVELDETECT1[6] ,High Level Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " LEVELDETECT1[5] ,High Level Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LEVELDETECT1[4] ,High Level Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LEVELDETECT1[3] ,High Level Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LEVELDETECT1[2] ,High Level Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " LEVELDETECT1[1] ,High Level Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LEVELDETECT1[0] ,High Level Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_RISINGDETECT,Rising-edge Detection Enable Register"
|
|
bitfld.long 0x08 31. " RISINGDETECT[31] ,Rising Edge Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " RISINGDETECT[30] ,Rising Edge Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " RISINGDETECT[29] ,Rising Edge Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " RISINGDETECT[28] ,Rising Edge Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " RISINGDETECT[27] ,Rising Edge Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " RISINGDETECT[26] ,Rising Edge Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " RISINGDETECT[25] ,Rising Edge Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " RISINGDETECT[24] ,Rising Edge Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " RISINGDETECT[23] ,Rising Edge Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " RISINGDETECT[22] ,Rising Edge Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " RISINGDETECT[21] ,Rising Edge Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " RISINGDETECT[20] ,Rising Edge Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " RISINGDETECT[19] ,Rising Edge Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " RISINGDETECT[18] ,Rising Edge Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " RISINGDETECT[17] ,Rising Edge Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " RISINGDETECT[16] ,Rising Edge Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " RISINGDETECT[15] ,Rising Edge Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " RISINGDETECT[14] ,Rising Edge Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " RISINGDETECT[13] ,Rising Edge Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " RISINGDETECT[12] ,Rising Edge Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " RISINGDETECT[11] ,Rising Edge Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " RISINGDETECT[10] ,Rising Edge Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " RISINGDETECT[9] ,Rising Edge Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RISINGDETECT[8] ,Rising Edge Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " RISINGDETECT[7] ,Rising Edge Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RISINGDETECT[6] ,Rising Edge Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " RISINGDETECT[5] ,Rising Edge Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RISINGDETECT[4] ,Rising Edge Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RISINGDETECT[3] ,Rising Edge Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RISINGDETECT[2] ,Rising Edge Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RISINGDETECT[1] ,Rising Edge Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " RISINGDETECT[0] ,Rising Edge Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_FALLINGDETECT,Falling-edge Detection Enable Register"
|
|
bitfld.long 0x0c 31. " FALLINGDETECT[31] ,Falling Edge Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " FALLINGDETECT[30] ,Falling Edge Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 29. " FALLINGDETECT[29] ,Falling Edge Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " FALLINGDETECT[28] ,Falling Edge Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " FALLINGDETECT[27] ,Falling Edge Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " FALLINGDETECT[26] ,Falling Edge Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 25. " FALLINGDETECT[25] ,Falling Edge Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " FALLINGDETECT[24] ,Falling Edge Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " FALLINGDETECT[23] ,Falling Edge Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " FALLINGDETECT[22] ,Falling Edge Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 21. " FALLINGDETECT[21] ,Falling Edge Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " FALLINGDETECT[20] ,Falling Edge Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " FALLINGDETECT[19] ,Falling Edge Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " FALLINGDETECT[18] ,Falling Edge Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 17. " FALLINGDETECT[17] ,Falling Edge Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " FALLINGDETECT[16] ,Falling Edge Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " FALLINGDETECT[15] ,Falling Edge Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " FALLINGDETECT[14] ,Falling Edge Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 13. " FALLINGDETECT[13] ,Falling Edge Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " FALLINGDETECT[12] ,Falling Edge Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " FALLINGDETECT[11] ,Falling Edge Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " FALLINGDETECT[10] ,Falling Edge Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " FALLINGDETECT[9] ,Falling Edge Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " FALLINGDETECT[8] ,Falling Edge Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " FALLINGDETECT[7] ,Falling Edge Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " FALLINGDETECT[6] ,Falling Edge Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " FALLINGDETECT[5] ,Falling Edge Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " FALLINGDETECT[4] ,Falling Edge Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " FALLINGDETECT[3] ,Falling Edge Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " FALLINGDETECT[2] ,Falling Edge Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 1. " FALLINGDETECT[1] ,Falling Edge Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " FALLINGDETECT[0] ,Falling Edge Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_DEBOUNCENABLE,Debounce Enable Register"
|
|
bitfld.long 0x10 31. " DEBOUNCEENABLE[31] ,Input Debounce 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " DEBOUNCEENABLE[30] ,Input Debounce 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " DEBOUNCEENABLE[29] ,Input Debounce 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " DEBOUNCEENABLE[28] ,Input Debounce 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " DEBOUNCEENABLE[27] ,Input Debounce 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " DEBOUNCEENABLE[26] ,Input Debounce 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " DEBOUNCEENABLE[25] ,Input Debounce 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " DEBOUNCEENABLE[24] ,Input Debounce 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " DEBOUNCEENABLE[23] ,Input Debounce 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DEBOUNCEENABLE[22] ,Input Debounce 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DEBOUNCEENABLE[21] ,Input Debounce 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DEBOUNCEENABLE[20] ,Input Debounce 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DEBOUNCEENABLE[19] ,Input Debounce 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DEBOUNCEENABLE[18] ,Input Debounce 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DEBOUNCEENABLE[17] ,Input Debounce 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DEBOUNCEENABLE[16] ,Input Debounce 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DEBOUNCEENABLE[15] ,Input Debounce 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DEBOUNCEENABLE[14] ,Input Debounce 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DEBOUNCEENABLE[13] ,Input Debounce 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DEBOUNCEENABLE[12] ,Input Debounce 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DEBOUNCEENABLE[11] ,Input Debounce 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DEBOUNCEENABLE[10] ,Input Debounce 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DEBOUNCEENABLE[9] ,Input Debounce 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DEBOUNCEENABLE[8] ,Input Debounce 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DEBOUNCEENABLE[7] ,Input Debounce 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DEBOUNCEENABLE[6] ,Input Debounce 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DEBOUNCEENABLE[5] ,Input Debounce 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DEBOUNCEENABLE[4] ,Input Debounce 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DEBOUNCEENABLE[3] ,Input Debounce 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DEBOUNCEENABLE[2] ,Input Debounce 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DEBOUNCEENABLE[1] ,Input Debounce 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DEBOUNCEENABLE[0] ,Input Debounce 0 Enable" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCINGTIME,Debounce Time Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DEBOUNCETIME ,Input Debouncing Value (in 31 ms steps)"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO 3"
|
|
base ad:0x481ae000
|
|
width 25.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPIO_REVISION,GPIO Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Old/current scheme " "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL version"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major Revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Special version for a particular device"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO System Configuration Register"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle"
|
|
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x00 "GPIO_EOI,GPIO End Of Interrupt Control Register"
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt Control" "Line #1,Line #2"
|
|
width 25.
|
|
group.long 0x24++0x7
|
|
line.long 0x00 "GPIO_IRQSTATUS_RAW_0,GPIO Status/Set Raw Register for Interrupt 1"
|
|
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQSTATUS_RAW_1,GPIO Status/Set Raw Register for Interrupt 2"
|
|
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
|
|
width 25.
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "GPIO_IRQSTATUS_0_set/clr,GPIO Status Register for Interrupt 1"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "GPIO_IRQSTATUS_1_set/clr,GPIO Status Register for Interrupt 2"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
|
|
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
|
|
width 25.
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "GPIO_IRQWAKEN_0,Wakeup Enable Register for Interrupt 1"
|
|
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPIO_IRQWAKEN_1,Wakeup Enable Register for Interrupt 2"
|
|
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
|
|
endif
|
|
width 25.
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO System Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed"
|
|
group.long 0x130++0x7
|
|
line.long 0x00 "GPIO_CTRL,GPIO Module Control Register"
|
|
bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x04 "GPIO_OE,Output Enable Register"
|
|
bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
|
bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
|
|
bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
|
bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
|
bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
|
|
bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
|
bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
|
|
bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
|
|
width 25.
|
|
rgroup.long 0x138++0x3
|
|
line.long 0x00 "GPIO_DATAIN,Sampled Input Data Register"
|
|
sif (cpuis("AM387*")||cpuis("DRA62*"))
|
|
bitfld.long 0x00 31. " DATAIN[31] ,Sampled Input 31" "Low,High"
|
|
bitfld.long 0x00 30. " DATAIN[30] ,Sampled Input 30" "Low,High"
|
|
bitfld.long 0x00 29. " DATAIN[29] ,Sampled Input 29" "Low,High"
|
|
bitfld.long 0x00 28. " DATAIN[28] ,Sampled Input 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DATAIN[27] ,Sampled Input 27" "Low,High"
|
|
bitfld.long 0x00 26. " DATAIN[26] ,Sampled Input 26" "Low,High"
|
|
bitfld.long 0x00 25. " DATAIN[25] ,Sampled Input 25" "Low,High"
|
|
bitfld.long 0x00 24. " DATAIN[24] ,Sampled Input 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DATAIN[23] ,Sampled Input 23" "Low,High"
|
|
bitfld.long 0x00 22. " DATAIN[22] ,Sampled Input 22" "Low,High"
|
|
bitfld.long 0x00 21. " DATAIN[21] ,Sampled Input 21" "Low,High"
|
|
bitfld.long 0x00 20. " DATAIN[20] ,Sampled Input 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DATAIN[19] ,Sampled Input 19" "Low,High"
|
|
bitfld.long 0x00 18. " DATAIN[18] ,Sampled Input 18" "Low,High"
|
|
bitfld.long 0x00 17. " DATAIN[17] ,Sampled Input 17" "Low,High"
|
|
bitfld.long 0x00 16. " DATAIN[16] ,Sampled Input 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DATAIN[15] ,Sampled Input 15" "Low,High"
|
|
bitfld.long 0x00 14. " DATAIN[14] ,Sampled Input 14" "Low,High"
|
|
bitfld.long 0x00 13. " DATAIN[13] ,Sampled Input 13" "Low,High"
|
|
bitfld.long 0x00 12. " DATAIN[12] ,Sampled Input 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DATAIN[11] ,Sampled Input 11" "Low,High"
|
|
bitfld.long 0x00 10. " DATAIN[10] ,Sampled Input 10" "Low,High"
|
|
bitfld.long 0x00 9. " DATAIN[9] ,Sampled Input 9" "Low,High"
|
|
bitfld.long 0x00 8. " DATAIN[8] ,Sampled Input 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DATAIN[7] ,Sampled Input 7" "Low,High"
|
|
bitfld.long 0x00 6. " DATAIN[6] ,Sampled Input 6" "Low,High"
|
|
bitfld.long 0x00 5. " DATAIN[5] ,Sampled Input 5" "Low,High"
|
|
bitfld.long 0x00 4. " DATAIN[4] ,Sampled Input 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATAIN[3] ,Sampled Input 3" "Low,High"
|
|
bitfld.long 0x00 2. " DATAIN[2] ,Sampled Input 2" "Low,High"
|
|
bitfld.long 0x00 1. " DATAIN[1] ,Sampled Input 1" "Low,High"
|
|
bitfld.long 0x00 0. " DATAIN[0] ,Sampled Input 0" "Low,High"
|
|
endif
|
|
width 25.
|
|
group.long 0x13c++0x3
|
|
line.long 0x00 "GPIO_DATAOUT,Output Data Register"
|
|
setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
|
|
setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
|
|
setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
|
|
setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
|
|
setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
|
|
setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
|
|
setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
|
|
setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
|
|
setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
|
|
setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
|
|
setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
|
|
setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
|
|
setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
|
|
setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
|
|
setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
|
|
setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
|
|
setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
|
setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
|
setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
|
setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
|
setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
|
setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
|
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
|
|
setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
|
|
setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
|
|
width 25.
|
|
group.long 0x140++0x17
|
|
line.long 0x00 "GPIO_LEVELDETECT0,Low-level Detection Enable Register"
|
|
bitfld.long 0x00 31. " LEVELDETECT0[31] ,Low Level Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LEVELDETECT0[30] ,Low Level Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LEVELDETECT0[29] ,Low Level Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " LEVELDETECT0[28] ,Low Level Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LEVELDETECT0[27] ,Low Level Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " LEVELDETECT0[26] ,Low Level Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEVELDETECT0[25] ,Low Level Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEVELDETECT0[24] ,Low Level Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LEVELDETECT0[23] ,Low Level Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " LEVELDETECT0[22] ,Low Level Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " LEVELDETECT0[21] ,Low Level Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LEVELDETECT0[20] ,Low Level Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LEVELDETECT0[19] ,Low Level Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " LEVELDETECT0[18] ,Low Level Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LEVELDETECT0[17] ,Low Level Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LEVELDETECT0[16] ,Low Level Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LEVELDETECT0[15] ,Low Level Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LEVELDETECT0[14] ,Low Level Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LEVELDETECT0[13] ,Low Level Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LEVELDETECT0[12] ,Low Level Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LEVELDETECT0[11] ,Low Level Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LEVELDETECT0[10] ,Low Level Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LEVELDETECT0[9] ,Low Level Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LEVELDETECT0[8] ,Low Level Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LEVELDETECT0[7] ,Low Level Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LEVELDETECT0[6] ,Low Level Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LEVELDETECT0[5] ,Low Level Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LEVELDETECT0[4] ,Low Level Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LEVELDETECT0[3] ,Low Level Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LEVELDETECT0[2] ,Low Level Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LEVELDETECT0[1] ,Low Level Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LEVELDETECT0[0] ,Low Level Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPIO_LEVELDETECT1,High-level Detection Enable Register"
|
|
bitfld.long 0x04 31. " LEVELDETECT1[31] ,High Level Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " LEVELDETECT1[30] ,High Level Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " LEVELDETECT1[29] ,High Level Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " LEVELDETECT1[28] ,High Level Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " LEVELDETECT1[27] ,High Level Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " LEVELDETECT1[26] ,High Level Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " LEVELDETECT1[25] ,High Level Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " LEVELDETECT1[24] ,High Level Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " LEVELDETECT1[23] ,High Level Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LEVELDETECT1[22] ,High Level Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " LEVELDETECT1[21] ,High Level Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LEVELDETECT1[20] ,High Level Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LEVELDETECT1[19] ,High Level Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LEVELDETECT1[18] ,High Level Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " LEVELDETECT1[17] ,High Level Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " LEVELDETECT1[16] ,High Level Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LEVELDETECT1[15] ,High Level Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LEVELDETECT1[14] ,High Level Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " LEVELDETECT1[13] ,High Level Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LEVELDETECT1[12] ,High Level Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LEVELDETECT1[11] ,High Level Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LEVELDETECT1[10] ,High Level Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " LEVELDETECT1[9] ,High Level Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LEVELDETECT1[8] ,High Level Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LEVELDETECT1[7] ,High Level Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LEVELDETECT1[6] ,High Level Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " LEVELDETECT1[5] ,High Level Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LEVELDETECT1[4] ,High Level Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LEVELDETECT1[3] ,High Level Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LEVELDETECT1[2] ,High Level Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " LEVELDETECT1[1] ,High Level Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LEVELDETECT1[0] ,High Level Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_RISINGDETECT,Rising-edge Detection Enable Register"
|
|
bitfld.long 0x08 31. " RISINGDETECT[31] ,Rising Edge Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " RISINGDETECT[30] ,Rising Edge Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " RISINGDETECT[29] ,Rising Edge Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " RISINGDETECT[28] ,Rising Edge Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " RISINGDETECT[27] ,Rising Edge Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " RISINGDETECT[26] ,Rising Edge Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " RISINGDETECT[25] ,Rising Edge Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " RISINGDETECT[24] ,Rising Edge Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " RISINGDETECT[23] ,Rising Edge Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " RISINGDETECT[22] ,Rising Edge Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " RISINGDETECT[21] ,Rising Edge Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " RISINGDETECT[20] ,Rising Edge Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " RISINGDETECT[19] ,Rising Edge Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " RISINGDETECT[18] ,Rising Edge Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " RISINGDETECT[17] ,Rising Edge Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " RISINGDETECT[16] ,Rising Edge Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " RISINGDETECT[15] ,Rising Edge Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " RISINGDETECT[14] ,Rising Edge Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " RISINGDETECT[13] ,Rising Edge Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " RISINGDETECT[12] ,Rising Edge Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " RISINGDETECT[11] ,Rising Edge Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " RISINGDETECT[10] ,Rising Edge Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " RISINGDETECT[9] ,Rising Edge Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RISINGDETECT[8] ,Rising Edge Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " RISINGDETECT[7] ,Rising Edge Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RISINGDETECT[6] ,Rising Edge Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " RISINGDETECT[5] ,Rising Edge Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RISINGDETECT[4] ,Rising Edge Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RISINGDETECT[3] ,Rising Edge Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RISINGDETECT[2] ,Rising Edge Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RISINGDETECT[1] ,Rising Edge Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " RISINGDETECT[0] ,Rising Edge Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_FALLINGDETECT,Falling-edge Detection Enable Register"
|
|
bitfld.long 0x0c 31. " FALLINGDETECT[31] ,Falling Edge Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " FALLINGDETECT[30] ,Falling Edge Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 29. " FALLINGDETECT[29] ,Falling Edge Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " FALLINGDETECT[28] ,Falling Edge Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " FALLINGDETECT[27] ,Falling Edge Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " FALLINGDETECT[26] ,Falling Edge Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 25. " FALLINGDETECT[25] ,Falling Edge Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " FALLINGDETECT[24] ,Falling Edge Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " FALLINGDETECT[23] ,Falling Edge Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " FALLINGDETECT[22] ,Falling Edge Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 21. " FALLINGDETECT[21] ,Falling Edge Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " FALLINGDETECT[20] ,Falling Edge Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " FALLINGDETECT[19] ,Falling Edge Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " FALLINGDETECT[18] ,Falling Edge Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 17. " FALLINGDETECT[17] ,Falling Edge Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " FALLINGDETECT[16] ,Falling Edge Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " FALLINGDETECT[15] ,Falling Edge Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " FALLINGDETECT[14] ,Falling Edge Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 13. " FALLINGDETECT[13] ,Falling Edge Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " FALLINGDETECT[12] ,Falling Edge Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " FALLINGDETECT[11] ,Falling Edge Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " FALLINGDETECT[10] ,Falling Edge Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " FALLINGDETECT[9] ,Falling Edge Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " FALLINGDETECT[8] ,Falling Edge Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " FALLINGDETECT[7] ,Falling Edge Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " FALLINGDETECT[6] ,Falling Edge Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " FALLINGDETECT[5] ,Falling Edge Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " FALLINGDETECT[4] ,Falling Edge Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " FALLINGDETECT[3] ,Falling Edge Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " FALLINGDETECT[2] ,Falling Edge Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 1. " FALLINGDETECT[1] ,Falling Edge Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " FALLINGDETECT[0] ,Falling Edge Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_DEBOUNCENABLE,Debounce Enable Register"
|
|
bitfld.long 0x10 31. " DEBOUNCEENABLE[31] ,Input Debounce 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " DEBOUNCEENABLE[30] ,Input Debounce 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " DEBOUNCEENABLE[29] ,Input Debounce 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " DEBOUNCEENABLE[28] ,Input Debounce 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " DEBOUNCEENABLE[27] ,Input Debounce 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " DEBOUNCEENABLE[26] ,Input Debounce 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " DEBOUNCEENABLE[25] ,Input Debounce 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " DEBOUNCEENABLE[24] ,Input Debounce 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " DEBOUNCEENABLE[23] ,Input Debounce 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DEBOUNCEENABLE[22] ,Input Debounce 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DEBOUNCEENABLE[21] ,Input Debounce 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DEBOUNCEENABLE[20] ,Input Debounce 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DEBOUNCEENABLE[19] ,Input Debounce 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DEBOUNCEENABLE[18] ,Input Debounce 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DEBOUNCEENABLE[17] ,Input Debounce 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DEBOUNCEENABLE[16] ,Input Debounce 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DEBOUNCEENABLE[15] ,Input Debounce 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DEBOUNCEENABLE[14] ,Input Debounce 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DEBOUNCEENABLE[13] ,Input Debounce 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DEBOUNCEENABLE[12] ,Input Debounce 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DEBOUNCEENABLE[11] ,Input Debounce 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DEBOUNCEENABLE[10] ,Input Debounce 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DEBOUNCEENABLE[9] ,Input Debounce 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DEBOUNCEENABLE[8] ,Input Debounce 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DEBOUNCEENABLE[7] ,Input Debounce 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DEBOUNCEENABLE[6] ,Input Debounce 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DEBOUNCEENABLE[5] ,Input Debounce 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DEBOUNCEENABLE[4] ,Input Debounce 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DEBOUNCEENABLE[3] ,Input Debounce 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DEBOUNCEENABLE[2] ,Input Debounce 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DEBOUNCEENABLE[1] ,Input Debounce 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DEBOUNCEENABLE[0] ,Input Debounce 0 Enable" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCINGTIME,Debounce Time Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DEBOUNCETIME ,Input Debouncing Value (in 31 ms steps)"
|
|
width 11.
|
|
tree.end
|
|
sif (cpuis("DRA62*"))
|
|
tree "GPIO 4"
|
|
base ad:0x48420000
|
|
width 25.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPIO_REVISION,GPIO Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Old/current scheme " "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL version"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major Revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Special version for a particular device"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO System Configuration Register"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle"
|
|
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x00 "GPIO_EOI,GPIO End Of Interrupt Control Register"
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt Control" "Line #1,Line #2"
|
|
width 25.
|
|
group.long 0x24++0x7
|
|
line.long 0x00 "GPIO_IRQSTATUS_RAW_0,GPIO Status/Set Raw Register for Interrupt 1"
|
|
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQSTATUS_RAW_1,GPIO Status/Set Raw Register for Interrupt 2"
|
|
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
|
|
width 25.
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "GPIO_IRQSTATUS_0_set/clr,GPIO Status Register for Interrupt 1"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "GPIO_IRQSTATUS_1_set/clr,GPIO Status Register for Interrupt 2"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
|
|
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
|
|
width 25.
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "GPIO_IRQWAKEN_0,Wakeup Enable Register for Interrupt 1"
|
|
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPIO_IRQWAKEN_1,Wakeup Enable Register for Interrupt 2"
|
|
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
|
|
endif
|
|
width 25.
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO System Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed"
|
|
group.long 0x130++0x7
|
|
line.long 0x00 "GPIO_CTRL,GPIO Module Control Register"
|
|
bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x04 "GPIO_OE,Output Enable Register"
|
|
bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
|
bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
|
|
bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
|
bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
|
bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
|
|
bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
|
bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
|
|
bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
|
|
width 25.
|
|
rgroup.long 0x138++0x3
|
|
line.long 0x00 "GPIO_DATAIN,Sampled Input Data Register"
|
|
sif (cpuis("AM387*")||cpuis("DRA62*"))
|
|
bitfld.long 0x00 31. " DATAIN[31] ,Sampled Input 31" "Low,High"
|
|
bitfld.long 0x00 30. " DATAIN[30] ,Sampled Input 30" "Low,High"
|
|
bitfld.long 0x00 29. " DATAIN[29] ,Sampled Input 29" "Low,High"
|
|
bitfld.long 0x00 28. " DATAIN[28] ,Sampled Input 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DATAIN[27] ,Sampled Input 27" "Low,High"
|
|
bitfld.long 0x00 26. " DATAIN[26] ,Sampled Input 26" "Low,High"
|
|
bitfld.long 0x00 25. " DATAIN[25] ,Sampled Input 25" "Low,High"
|
|
bitfld.long 0x00 24. " DATAIN[24] ,Sampled Input 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DATAIN[23] ,Sampled Input 23" "Low,High"
|
|
bitfld.long 0x00 22. " DATAIN[22] ,Sampled Input 22" "Low,High"
|
|
bitfld.long 0x00 21. " DATAIN[21] ,Sampled Input 21" "Low,High"
|
|
bitfld.long 0x00 20. " DATAIN[20] ,Sampled Input 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DATAIN[19] ,Sampled Input 19" "Low,High"
|
|
bitfld.long 0x00 18. " DATAIN[18] ,Sampled Input 18" "Low,High"
|
|
bitfld.long 0x00 17. " DATAIN[17] ,Sampled Input 17" "Low,High"
|
|
bitfld.long 0x00 16. " DATAIN[16] ,Sampled Input 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DATAIN[15] ,Sampled Input 15" "Low,High"
|
|
bitfld.long 0x00 14. " DATAIN[14] ,Sampled Input 14" "Low,High"
|
|
bitfld.long 0x00 13. " DATAIN[13] ,Sampled Input 13" "Low,High"
|
|
bitfld.long 0x00 12. " DATAIN[12] ,Sampled Input 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DATAIN[11] ,Sampled Input 11" "Low,High"
|
|
bitfld.long 0x00 10. " DATAIN[10] ,Sampled Input 10" "Low,High"
|
|
bitfld.long 0x00 9. " DATAIN[9] ,Sampled Input 9" "Low,High"
|
|
bitfld.long 0x00 8. " DATAIN[8] ,Sampled Input 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DATAIN[7] ,Sampled Input 7" "Low,High"
|
|
bitfld.long 0x00 6. " DATAIN[6] ,Sampled Input 6" "Low,High"
|
|
bitfld.long 0x00 5. " DATAIN[5] ,Sampled Input 5" "Low,High"
|
|
bitfld.long 0x00 4. " DATAIN[4] ,Sampled Input 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATAIN[3] ,Sampled Input 3" "Low,High"
|
|
bitfld.long 0x00 2. " DATAIN[2] ,Sampled Input 2" "Low,High"
|
|
bitfld.long 0x00 1. " DATAIN[1] ,Sampled Input 1" "Low,High"
|
|
bitfld.long 0x00 0. " DATAIN[0] ,Sampled Input 0" "Low,High"
|
|
endif
|
|
width 25.
|
|
group.long 0x13c++0x3
|
|
line.long 0x00 "GPIO_DATAOUT,Output Data Register"
|
|
setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
|
|
setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
|
|
setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
|
|
setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
|
|
setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
|
|
setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
|
|
setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
|
|
setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
|
|
setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
|
|
setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
|
|
setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
|
|
setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
|
|
setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
|
|
setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
|
|
setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
|
|
setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
|
|
setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
|
setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
|
setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
|
setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
|
setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
|
setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
|
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
|
|
setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
|
|
setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
|
|
width 25.
|
|
group.long 0x140++0x17
|
|
line.long 0x00 "GPIO_LEVELDETECT0,Low-level Detection Enable Register"
|
|
bitfld.long 0x00 31. " LEVELDETECT0[31] ,Low Level Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LEVELDETECT0[30] ,Low Level Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LEVELDETECT0[29] ,Low Level Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " LEVELDETECT0[28] ,Low Level Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LEVELDETECT0[27] ,Low Level Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " LEVELDETECT0[26] ,Low Level Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEVELDETECT0[25] ,Low Level Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEVELDETECT0[24] ,Low Level Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LEVELDETECT0[23] ,Low Level Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " LEVELDETECT0[22] ,Low Level Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " LEVELDETECT0[21] ,Low Level Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LEVELDETECT0[20] ,Low Level Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LEVELDETECT0[19] ,Low Level Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " LEVELDETECT0[18] ,Low Level Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LEVELDETECT0[17] ,Low Level Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LEVELDETECT0[16] ,Low Level Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LEVELDETECT0[15] ,Low Level Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LEVELDETECT0[14] ,Low Level Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LEVELDETECT0[13] ,Low Level Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LEVELDETECT0[12] ,Low Level Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LEVELDETECT0[11] ,Low Level Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LEVELDETECT0[10] ,Low Level Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LEVELDETECT0[9] ,Low Level Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LEVELDETECT0[8] ,Low Level Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LEVELDETECT0[7] ,Low Level Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LEVELDETECT0[6] ,Low Level Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LEVELDETECT0[5] ,Low Level Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LEVELDETECT0[4] ,Low Level Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LEVELDETECT0[3] ,Low Level Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LEVELDETECT0[2] ,Low Level Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LEVELDETECT0[1] ,Low Level Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LEVELDETECT0[0] ,Low Level Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPIO_LEVELDETECT1,High-level Detection Enable Register"
|
|
bitfld.long 0x04 31. " LEVELDETECT1[31] ,High Level Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " LEVELDETECT1[30] ,High Level Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " LEVELDETECT1[29] ,High Level Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " LEVELDETECT1[28] ,High Level Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " LEVELDETECT1[27] ,High Level Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " LEVELDETECT1[26] ,High Level Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " LEVELDETECT1[25] ,High Level Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " LEVELDETECT1[24] ,High Level Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " LEVELDETECT1[23] ,High Level Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LEVELDETECT1[22] ,High Level Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " LEVELDETECT1[21] ,High Level Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LEVELDETECT1[20] ,High Level Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LEVELDETECT1[19] ,High Level Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LEVELDETECT1[18] ,High Level Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " LEVELDETECT1[17] ,High Level Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " LEVELDETECT1[16] ,High Level Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LEVELDETECT1[15] ,High Level Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LEVELDETECT1[14] ,High Level Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " LEVELDETECT1[13] ,High Level Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LEVELDETECT1[12] ,High Level Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LEVELDETECT1[11] ,High Level Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LEVELDETECT1[10] ,High Level Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " LEVELDETECT1[9] ,High Level Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LEVELDETECT1[8] ,High Level Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LEVELDETECT1[7] ,High Level Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LEVELDETECT1[6] ,High Level Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " LEVELDETECT1[5] ,High Level Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LEVELDETECT1[4] ,High Level Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LEVELDETECT1[3] ,High Level Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LEVELDETECT1[2] ,High Level Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " LEVELDETECT1[1] ,High Level Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LEVELDETECT1[0] ,High Level Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_RISINGDETECT,Rising-edge Detection Enable Register"
|
|
bitfld.long 0x08 31. " RISINGDETECT[31] ,Rising Edge Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " RISINGDETECT[30] ,Rising Edge Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " RISINGDETECT[29] ,Rising Edge Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " RISINGDETECT[28] ,Rising Edge Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " RISINGDETECT[27] ,Rising Edge Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " RISINGDETECT[26] ,Rising Edge Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " RISINGDETECT[25] ,Rising Edge Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " RISINGDETECT[24] ,Rising Edge Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " RISINGDETECT[23] ,Rising Edge Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " RISINGDETECT[22] ,Rising Edge Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " RISINGDETECT[21] ,Rising Edge Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " RISINGDETECT[20] ,Rising Edge Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " RISINGDETECT[19] ,Rising Edge Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " RISINGDETECT[18] ,Rising Edge Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " RISINGDETECT[17] ,Rising Edge Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " RISINGDETECT[16] ,Rising Edge Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " RISINGDETECT[15] ,Rising Edge Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " RISINGDETECT[14] ,Rising Edge Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " RISINGDETECT[13] ,Rising Edge Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " RISINGDETECT[12] ,Rising Edge Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " RISINGDETECT[11] ,Rising Edge Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " RISINGDETECT[10] ,Rising Edge Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " RISINGDETECT[9] ,Rising Edge Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RISINGDETECT[8] ,Rising Edge Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " RISINGDETECT[7] ,Rising Edge Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RISINGDETECT[6] ,Rising Edge Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " RISINGDETECT[5] ,Rising Edge Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RISINGDETECT[4] ,Rising Edge Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RISINGDETECT[3] ,Rising Edge Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RISINGDETECT[2] ,Rising Edge Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RISINGDETECT[1] ,Rising Edge Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " RISINGDETECT[0] ,Rising Edge Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_FALLINGDETECT,Falling-edge Detection Enable Register"
|
|
bitfld.long 0x0c 31. " FALLINGDETECT[31] ,Falling Edge Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " FALLINGDETECT[30] ,Falling Edge Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 29. " FALLINGDETECT[29] ,Falling Edge Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " FALLINGDETECT[28] ,Falling Edge Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " FALLINGDETECT[27] ,Falling Edge Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " FALLINGDETECT[26] ,Falling Edge Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 25. " FALLINGDETECT[25] ,Falling Edge Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " FALLINGDETECT[24] ,Falling Edge Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " FALLINGDETECT[23] ,Falling Edge Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " FALLINGDETECT[22] ,Falling Edge Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 21. " FALLINGDETECT[21] ,Falling Edge Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " FALLINGDETECT[20] ,Falling Edge Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " FALLINGDETECT[19] ,Falling Edge Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " FALLINGDETECT[18] ,Falling Edge Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 17. " FALLINGDETECT[17] ,Falling Edge Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " FALLINGDETECT[16] ,Falling Edge Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " FALLINGDETECT[15] ,Falling Edge Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " FALLINGDETECT[14] ,Falling Edge Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 13. " FALLINGDETECT[13] ,Falling Edge Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " FALLINGDETECT[12] ,Falling Edge Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " FALLINGDETECT[11] ,Falling Edge Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " FALLINGDETECT[10] ,Falling Edge Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " FALLINGDETECT[9] ,Falling Edge Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " FALLINGDETECT[8] ,Falling Edge Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " FALLINGDETECT[7] ,Falling Edge Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " FALLINGDETECT[6] ,Falling Edge Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " FALLINGDETECT[5] ,Falling Edge Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " FALLINGDETECT[4] ,Falling Edge Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " FALLINGDETECT[3] ,Falling Edge Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " FALLINGDETECT[2] ,Falling Edge Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 1. " FALLINGDETECT[1] ,Falling Edge Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " FALLINGDETECT[0] ,Falling Edge Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_DEBOUNCENABLE,Debounce Enable Register"
|
|
bitfld.long 0x10 31. " DEBOUNCEENABLE[31] ,Input Debounce 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " DEBOUNCEENABLE[30] ,Input Debounce 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " DEBOUNCEENABLE[29] ,Input Debounce 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " DEBOUNCEENABLE[28] ,Input Debounce 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " DEBOUNCEENABLE[27] ,Input Debounce 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " DEBOUNCEENABLE[26] ,Input Debounce 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " DEBOUNCEENABLE[25] ,Input Debounce 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " DEBOUNCEENABLE[24] ,Input Debounce 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " DEBOUNCEENABLE[23] ,Input Debounce 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DEBOUNCEENABLE[22] ,Input Debounce 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DEBOUNCEENABLE[21] ,Input Debounce 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DEBOUNCEENABLE[20] ,Input Debounce 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DEBOUNCEENABLE[19] ,Input Debounce 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DEBOUNCEENABLE[18] ,Input Debounce 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DEBOUNCEENABLE[17] ,Input Debounce 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DEBOUNCEENABLE[16] ,Input Debounce 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DEBOUNCEENABLE[15] ,Input Debounce 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DEBOUNCEENABLE[14] ,Input Debounce 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DEBOUNCEENABLE[13] ,Input Debounce 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DEBOUNCEENABLE[12] ,Input Debounce 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DEBOUNCEENABLE[11] ,Input Debounce 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DEBOUNCEENABLE[10] ,Input Debounce 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DEBOUNCEENABLE[9] ,Input Debounce 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DEBOUNCEENABLE[8] ,Input Debounce 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DEBOUNCEENABLE[7] ,Input Debounce 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DEBOUNCEENABLE[6] ,Input Debounce 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DEBOUNCEENABLE[5] ,Input Debounce 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DEBOUNCEENABLE[4] ,Input Debounce 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DEBOUNCEENABLE[3] ,Input Debounce 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DEBOUNCEENABLE[2] ,Input Debounce 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DEBOUNCEENABLE[1] ,Input Debounce 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DEBOUNCEENABLE[0] ,Input Debounce 0 Enable" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCINGTIME,Debounce Time Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DEBOUNCETIME ,Input Debouncing Value (in 31 ms steps)"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO 5"
|
|
base ad:0x48422000
|
|
width 25.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPIO_REVISION,GPIO Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Old/current scheme " "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL version"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major Revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Special version for a particular device"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO System Configuration Register"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle"
|
|
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x00 "GPIO_EOI,GPIO End Of Interrupt Control Register"
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt Control" "Line #1,Line #2"
|
|
width 25.
|
|
group.long 0x24++0x7
|
|
line.long 0x00 "GPIO_IRQSTATUS_RAW_0,GPIO Status/Set Raw Register for Interrupt 1"
|
|
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQSTATUS_RAW_1,GPIO Status/Set Raw Register for Interrupt 2"
|
|
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
|
|
width 25.
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "GPIO_IRQSTATUS_0_set/clr,GPIO Status Register for Interrupt 1"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "GPIO_IRQSTATUS_1_set/clr,GPIO Status Register for Interrupt 2"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
|
|
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
|
|
width 25.
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "GPIO_IRQWAKEN_0,Wakeup Enable Register for Interrupt 1"
|
|
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPIO_IRQWAKEN_1,Wakeup Enable Register for Interrupt 2"
|
|
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
|
|
endif
|
|
width 25.
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO System Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed"
|
|
group.long 0x130++0x7
|
|
line.long 0x00 "GPIO_CTRL,GPIO Module Control Register"
|
|
bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x04 "GPIO_OE,Output Enable Register"
|
|
bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
|
bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
|
|
bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
|
bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
|
bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
|
|
bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
|
bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
|
|
bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
|
|
width 25.
|
|
rgroup.long 0x138++0x3
|
|
line.long 0x00 "GPIO_DATAIN,Sampled Input Data Register"
|
|
sif (cpuis("AM387*")||cpuis("DRA62*"))
|
|
bitfld.long 0x00 31. " DATAIN[31] ,Sampled Input 31" "Low,High"
|
|
bitfld.long 0x00 30. " DATAIN[30] ,Sampled Input 30" "Low,High"
|
|
bitfld.long 0x00 29. " DATAIN[29] ,Sampled Input 29" "Low,High"
|
|
bitfld.long 0x00 28. " DATAIN[28] ,Sampled Input 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DATAIN[27] ,Sampled Input 27" "Low,High"
|
|
bitfld.long 0x00 26. " DATAIN[26] ,Sampled Input 26" "Low,High"
|
|
bitfld.long 0x00 25. " DATAIN[25] ,Sampled Input 25" "Low,High"
|
|
bitfld.long 0x00 24. " DATAIN[24] ,Sampled Input 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DATAIN[23] ,Sampled Input 23" "Low,High"
|
|
bitfld.long 0x00 22. " DATAIN[22] ,Sampled Input 22" "Low,High"
|
|
bitfld.long 0x00 21. " DATAIN[21] ,Sampled Input 21" "Low,High"
|
|
bitfld.long 0x00 20. " DATAIN[20] ,Sampled Input 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DATAIN[19] ,Sampled Input 19" "Low,High"
|
|
bitfld.long 0x00 18. " DATAIN[18] ,Sampled Input 18" "Low,High"
|
|
bitfld.long 0x00 17. " DATAIN[17] ,Sampled Input 17" "Low,High"
|
|
bitfld.long 0x00 16. " DATAIN[16] ,Sampled Input 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DATAIN[15] ,Sampled Input 15" "Low,High"
|
|
bitfld.long 0x00 14. " DATAIN[14] ,Sampled Input 14" "Low,High"
|
|
bitfld.long 0x00 13. " DATAIN[13] ,Sampled Input 13" "Low,High"
|
|
bitfld.long 0x00 12. " DATAIN[12] ,Sampled Input 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DATAIN[11] ,Sampled Input 11" "Low,High"
|
|
bitfld.long 0x00 10. " DATAIN[10] ,Sampled Input 10" "Low,High"
|
|
bitfld.long 0x00 9. " DATAIN[9] ,Sampled Input 9" "Low,High"
|
|
bitfld.long 0x00 8. " DATAIN[8] ,Sampled Input 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DATAIN[7] ,Sampled Input 7" "Low,High"
|
|
bitfld.long 0x00 6. " DATAIN[6] ,Sampled Input 6" "Low,High"
|
|
bitfld.long 0x00 5. " DATAIN[5] ,Sampled Input 5" "Low,High"
|
|
bitfld.long 0x00 4. " DATAIN[4] ,Sampled Input 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATAIN[3] ,Sampled Input 3" "Low,High"
|
|
bitfld.long 0x00 2. " DATAIN[2] ,Sampled Input 2" "Low,High"
|
|
bitfld.long 0x00 1. " DATAIN[1] ,Sampled Input 1" "Low,High"
|
|
bitfld.long 0x00 0. " DATAIN[0] ,Sampled Input 0" "Low,High"
|
|
endif
|
|
width 25.
|
|
group.long 0x13c++0x3
|
|
line.long 0x00 "GPIO_DATAOUT,Output Data Register"
|
|
setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
|
|
setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
|
|
setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
|
|
setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
|
|
setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
|
|
setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
|
|
setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
|
|
setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
|
|
setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
|
|
setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
|
|
setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
|
|
setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
|
|
setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
|
|
setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
|
|
setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
|
|
setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
|
|
setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
|
setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
|
setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
|
setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
|
setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
|
setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
|
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
|
|
setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
|
|
setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
|
|
width 25.
|
|
group.long 0x140++0x17
|
|
line.long 0x00 "GPIO_LEVELDETECT0,Low-level Detection Enable Register"
|
|
bitfld.long 0x00 31. " LEVELDETECT0[31] ,Low Level Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LEVELDETECT0[30] ,Low Level Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LEVELDETECT0[29] ,Low Level Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " LEVELDETECT0[28] ,Low Level Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LEVELDETECT0[27] ,Low Level Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " LEVELDETECT0[26] ,Low Level Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEVELDETECT0[25] ,Low Level Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEVELDETECT0[24] ,Low Level Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LEVELDETECT0[23] ,Low Level Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " LEVELDETECT0[22] ,Low Level Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " LEVELDETECT0[21] ,Low Level Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LEVELDETECT0[20] ,Low Level Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LEVELDETECT0[19] ,Low Level Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " LEVELDETECT0[18] ,Low Level Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LEVELDETECT0[17] ,Low Level Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LEVELDETECT0[16] ,Low Level Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LEVELDETECT0[15] ,Low Level Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LEVELDETECT0[14] ,Low Level Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LEVELDETECT0[13] ,Low Level Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LEVELDETECT0[12] ,Low Level Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LEVELDETECT0[11] ,Low Level Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LEVELDETECT0[10] ,Low Level Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LEVELDETECT0[9] ,Low Level Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LEVELDETECT0[8] ,Low Level Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LEVELDETECT0[7] ,Low Level Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LEVELDETECT0[6] ,Low Level Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LEVELDETECT0[5] ,Low Level Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LEVELDETECT0[4] ,Low Level Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LEVELDETECT0[3] ,Low Level Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LEVELDETECT0[2] ,Low Level Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LEVELDETECT0[1] ,Low Level Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LEVELDETECT0[0] ,Low Level Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPIO_LEVELDETECT1,High-level Detection Enable Register"
|
|
bitfld.long 0x04 31. " LEVELDETECT1[31] ,High Level Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " LEVELDETECT1[30] ,High Level Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " LEVELDETECT1[29] ,High Level Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " LEVELDETECT1[28] ,High Level Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " LEVELDETECT1[27] ,High Level Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " LEVELDETECT1[26] ,High Level Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " LEVELDETECT1[25] ,High Level Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " LEVELDETECT1[24] ,High Level Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " LEVELDETECT1[23] ,High Level Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LEVELDETECT1[22] ,High Level Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " LEVELDETECT1[21] ,High Level Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LEVELDETECT1[20] ,High Level Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LEVELDETECT1[19] ,High Level Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LEVELDETECT1[18] ,High Level Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " LEVELDETECT1[17] ,High Level Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " LEVELDETECT1[16] ,High Level Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LEVELDETECT1[15] ,High Level Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LEVELDETECT1[14] ,High Level Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " LEVELDETECT1[13] ,High Level Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LEVELDETECT1[12] ,High Level Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LEVELDETECT1[11] ,High Level Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LEVELDETECT1[10] ,High Level Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " LEVELDETECT1[9] ,High Level Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LEVELDETECT1[8] ,High Level Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LEVELDETECT1[7] ,High Level Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LEVELDETECT1[6] ,High Level Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " LEVELDETECT1[5] ,High Level Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LEVELDETECT1[4] ,High Level Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LEVELDETECT1[3] ,High Level Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LEVELDETECT1[2] ,High Level Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " LEVELDETECT1[1] ,High Level Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LEVELDETECT1[0] ,High Level Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_RISINGDETECT,Rising-edge Detection Enable Register"
|
|
bitfld.long 0x08 31. " RISINGDETECT[31] ,Rising Edge Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " RISINGDETECT[30] ,Rising Edge Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " RISINGDETECT[29] ,Rising Edge Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " RISINGDETECT[28] ,Rising Edge Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " RISINGDETECT[27] ,Rising Edge Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " RISINGDETECT[26] ,Rising Edge Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " RISINGDETECT[25] ,Rising Edge Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " RISINGDETECT[24] ,Rising Edge Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " RISINGDETECT[23] ,Rising Edge Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " RISINGDETECT[22] ,Rising Edge Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " RISINGDETECT[21] ,Rising Edge Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " RISINGDETECT[20] ,Rising Edge Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " RISINGDETECT[19] ,Rising Edge Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " RISINGDETECT[18] ,Rising Edge Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " RISINGDETECT[17] ,Rising Edge Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " RISINGDETECT[16] ,Rising Edge Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " RISINGDETECT[15] ,Rising Edge Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " RISINGDETECT[14] ,Rising Edge Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " RISINGDETECT[13] ,Rising Edge Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " RISINGDETECT[12] ,Rising Edge Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " RISINGDETECT[11] ,Rising Edge Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " RISINGDETECT[10] ,Rising Edge Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " RISINGDETECT[9] ,Rising Edge Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RISINGDETECT[8] ,Rising Edge Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " RISINGDETECT[7] ,Rising Edge Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RISINGDETECT[6] ,Rising Edge Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " RISINGDETECT[5] ,Rising Edge Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RISINGDETECT[4] ,Rising Edge Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RISINGDETECT[3] ,Rising Edge Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RISINGDETECT[2] ,Rising Edge Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RISINGDETECT[1] ,Rising Edge Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " RISINGDETECT[0] ,Rising Edge Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_FALLINGDETECT,Falling-edge Detection Enable Register"
|
|
bitfld.long 0x0c 31. " FALLINGDETECT[31] ,Falling Edge Interrupt 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " FALLINGDETECT[30] ,Falling Edge Interrupt 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 29. " FALLINGDETECT[29] ,Falling Edge Interrupt 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " FALLINGDETECT[28] ,Falling Edge Interrupt 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " FALLINGDETECT[27] ,Falling Edge Interrupt 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " FALLINGDETECT[26] ,Falling Edge Interrupt 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 25. " FALLINGDETECT[25] ,Falling Edge Interrupt 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " FALLINGDETECT[24] ,Falling Edge Interrupt 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " FALLINGDETECT[23] ,Falling Edge Interrupt 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " FALLINGDETECT[22] ,Falling Edge Interrupt 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 21. " FALLINGDETECT[21] ,Falling Edge Interrupt 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " FALLINGDETECT[20] ,Falling Edge Interrupt 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " FALLINGDETECT[19] ,Falling Edge Interrupt 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " FALLINGDETECT[18] ,Falling Edge Interrupt 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 17. " FALLINGDETECT[17] ,Falling Edge Interrupt 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " FALLINGDETECT[16] ,Falling Edge Interrupt 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " FALLINGDETECT[15] ,Falling Edge Interrupt 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " FALLINGDETECT[14] ,Falling Edge Interrupt 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 13. " FALLINGDETECT[13] ,Falling Edge Interrupt 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " FALLINGDETECT[12] ,Falling Edge Interrupt 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " FALLINGDETECT[11] ,Falling Edge Interrupt 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " FALLINGDETECT[10] ,Falling Edge Interrupt 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " FALLINGDETECT[9] ,Falling Edge Interrupt 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " FALLINGDETECT[8] ,Falling Edge Interrupt 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " FALLINGDETECT[7] ,Falling Edge Interrupt 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " FALLINGDETECT[6] ,Falling Edge Interrupt 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " FALLINGDETECT[5] ,Falling Edge Interrupt 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " FALLINGDETECT[4] ,Falling Edge Interrupt 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " FALLINGDETECT[3] ,Falling Edge Interrupt 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " FALLINGDETECT[2] ,Falling Edge Interrupt 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 1. " FALLINGDETECT[1] ,Falling Edge Interrupt 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " FALLINGDETECT[0] ,Falling Edge Interrupt 0 Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_DEBOUNCENABLE,Debounce Enable Register"
|
|
bitfld.long 0x10 31. " DEBOUNCEENABLE[31] ,Input Debounce 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " DEBOUNCEENABLE[30] ,Input Debounce 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " DEBOUNCEENABLE[29] ,Input Debounce 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " DEBOUNCEENABLE[28] ,Input Debounce 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " DEBOUNCEENABLE[27] ,Input Debounce 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " DEBOUNCEENABLE[26] ,Input Debounce 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " DEBOUNCEENABLE[25] ,Input Debounce 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " DEBOUNCEENABLE[24] ,Input Debounce 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " DEBOUNCEENABLE[23] ,Input Debounce 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DEBOUNCEENABLE[22] ,Input Debounce 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DEBOUNCEENABLE[21] ,Input Debounce 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DEBOUNCEENABLE[20] ,Input Debounce 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DEBOUNCEENABLE[19] ,Input Debounce 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DEBOUNCEENABLE[18] ,Input Debounce 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DEBOUNCEENABLE[17] ,Input Debounce 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DEBOUNCEENABLE[16] ,Input Debounce 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DEBOUNCEENABLE[15] ,Input Debounce 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DEBOUNCEENABLE[14] ,Input Debounce 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DEBOUNCEENABLE[13] ,Input Debounce 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DEBOUNCEENABLE[12] ,Input Debounce 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DEBOUNCEENABLE[11] ,Input Debounce 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DEBOUNCEENABLE[10] ,Input Debounce 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DEBOUNCEENABLE[9] ,Input Debounce 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DEBOUNCEENABLE[8] ,Input Debounce 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DEBOUNCEENABLE[7] ,Input Debounce 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DEBOUNCEENABLE[6] ,Input Debounce 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DEBOUNCEENABLE[5] ,Input Debounce 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DEBOUNCEENABLE[4] ,Input Debounce 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DEBOUNCEENABLE[3] ,Input Debounce 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DEBOUNCEENABLE[2] ,Input Debounce 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DEBOUNCEENABLE[1] ,Input Debounce 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DEBOUNCEENABLE[0] ,Input Debounce 0 Enable" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCINGTIME,Debounce Time Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DEBOUNCETIME ,Input Debouncing Value (in 31 ms steps)"
|
|
width 11.
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "GPMC (General Purpose Memory Controller)"
|
|
base ad:0x50000000
|
|
sif cpuis("AM387*")
|
|
width 23.
|
|
tree "Miscellaneous Registers"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPMC_REVISION,IP Revision Code"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP revision"
|
|
group.long 0x10++0x3
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||cpuis("AM389*")||cpuis("AM335*")||cpuis("C6A816*")||cpuis("AM387*")||cpuis("DRA6*")||cpu()=="DM8148"||cpu()=="DM8147"||cpu()=="C6A8148"||cpu()=="C6A8147"||cpu()=="C6A8143"||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
|
|
line.long 0x00 "GPMC_SYSCONFIG,Various Parameters Of The OCP Interface"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
else
|
|
line.long 0x00 "GPMC_SYSCONFIG,Various Parameters Of The Interconnect Control"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPMC_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "GPMC_IRQSTATUS,Interrupt Status Register"
|
|
sif (((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&(!(cpuis("AM389*")))&&(!(cpuis("AM335*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(!(cpuis("DRA6*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143"))
|
|
eventfld.long 0x00 11. " WAIT3EDGEDETECTIONSTATUS ,Status of the Wait3 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT2EDGEDETECTIONSTATUS ,Status of the Wait2 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 9. " WAIT1EDGEDETECTIONSTATUS ,Status of the Wait1 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 8. " WAIT0EDGEDETECTIONSTATUS ,Status of the Wait0 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TERMINALCOUNTSTATUS ,Status of the TerminalCountEvent interrupt (COUNTVALUE)" ">0,=0"
|
|
textline " "
|
|
eventfld.long 0x00 0. " FIFOEVENTSTATUS ,Status of the FIFOEvent interrupt" "<FIFOTHRESHOLD,=FIFOTHRESHOLD"
|
|
line.long 0x04 "GPMC_IRQENABLE,Interrupt Enable Register"
|
|
sif (((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&(!(cpuis("AM389*")))&&(!(cpuis("AM335*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(!(cpuis("DRA6*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143"))
|
|
bitfld.long 0x04 11. " WAIT3EDGEDETECTIONENABLE ,Enables the Wait3 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " WAIT2EDGEDETECTIONENABLE ,Enables the Wait2 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 9. " WAIT1EDGEDETECTIONENABLE ,Enables the Wait1 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT0EDGEDETECTIONENABLE ,Enables the Wait0 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TERMINALCOUNTEVENTENABLE ,Enables TerminalCountEvent interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FIFOEVENTENABLE ,Enables the FIFOEvent interrupt" "Masked,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "GPMC_TIMEOUT_CONTROL,Start Value Of The Timeout Counter Set Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " TIMEOUTSTARTVALUE ,Start value of the time-out counter"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIMEOUTENABLE ,Enable bit of the TimeOut feature" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "GPMC_ERR_ADDRESS,Stores The Address Of The Illegal Access"
|
|
hexmask.long 0x00 0.--30. 1. " ILLEGALADD ,Address of illegal access"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GPMC_ERR_TYPE,Stores The Type Of Error"
|
|
bitfld.long 0x00 8.--10. " ILLEGALMCMD ,System Command of the transaction that caused the error" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERRORNOTSUPPADD ,Not supported Address error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERRORNOTSUPPMCMD ,Not supported Command error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ERRORTIMEOUT ,Time-out error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ERRORVALID ,Error validity status" "Not valid,Valid"
|
|
group.long 0x50++0x7
|
|
line.long 0x00 "GPMC_CONFIG,Global Configuration Of The GPMC Module"
|
|
sif (((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&(!(cpuis("AM389*")))&&(!(cpuis("AM335*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(!(cpuis("DRA6*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143"))
|
|
bitfld.long 0x00 11. " WAIT3PINPOLARITY ,Selects the polarity of input pin WAIT3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WAIT2PINPOLARITY ,Selects the polarity of input pin WAIT2" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " WAIT1PINPOLARITY ,Selects the polarity of input pin WAIT1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WAIT0PINPOLARITY ,Selects the polarity of input pin WAIT0" "Low,High"
|
|
textline " "
|
|
sif (!(cpuis("AM387*")))
|
|
bitfld.long 0x00 4. " WRITEPROTECT ,Controls the /WP output pin level" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 1. " LIMITEDADDRESS ,Limited Address device support" "Not supported,Supported"
|
|
else
|
|
bitfld.long 0x00 1. " LIMITEDADDRESS ,Limited Address device support" "No effect,A26-A11 not modified"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " NANDFORCEPOSTEDWRITE ,Enables the Force Posted Write feature to NAND Cmd/Add/Data location" "Disabled,Enabled"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "GPMC_STATUS,Global Status Bits Of The GPMC Module"
|
|
sif (((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&(!(cpuis("AM389*")))&&(!(cpuis("AM335*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(!(cpuis("DRA6*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143"))
|
|
bitfld.long 0x00 11. " WAIT3STATUS ,Copy of input pin WAIT3" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WAIT2STATUS ,Copy of input pin WAIT2" "Asserted,De-asserted"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " WAIT1STATUS ,Copy of input pin WAIT1" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WAIT0STATUS ,Copy of input pin WAIT0" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EMPTYWRITEBUFFERSTATUS ,Stores the empty status of the write buffer" "Not empty,Empty"
|
|
group.long 0x1E0++0x7
|
|
line.long 0x00 "GPMC_PREFETCH_CONFIG1,Prefetch Engine Configuration 1"
|
|
bitfld.long 0x00 28.--30. " CYCLEOPTIMIZATION ,Defines the number of GPMC_FCLK cycles to be subtracted" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENABLEOPTIMIZEDACCESS ,Enables access cycle optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ENGINECSSELECTOR ,/CS where Prefetch Postwrite engine is active" "/CS0,/CS1,/CS2,/CS3,/CS4,/CS5,/CS6,/CS7"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFPWENROUNDROBIN ,PFPW RoundRobin arbitration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PFPWWEIGHTEDPRIO ,Arbitration between a direct memory access and a PFPW engine access (next access is granted to the PFPW engine)" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " FIFOTHRESHOLD ,Maximum number of bytes read/write from the FIFO"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLEENGINE ,Prefetch Postwite engine enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--5. " WAITPINSELECTOR ,Selects which wait pin edge detector should start the engine in synchronized mode" "Wait0EdgeDetection,Wait1EdgeDetection,?..."
|
|
else
|
|
bitfld.long 0x00 4.--5. " WAITPINSELECTOR ,Selects which wait pin edge detector should start the engine in synchronized mode" "Wait0EdgeDetection,Wait1EdgeDetection,Wait2EdgeDetection,Wait3EdgeDetection"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHROMODE ,Selects when the engine starts the access to CS" "StartEngine set,StartEngine set/wait to nonwait edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMAMODE ,Selects interrupt synchronization or DMA request synchronization" "Interrupt,DMA request"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACCESSMODE ,Selects prefetch read or write-posting accesses" "Prefetch read,Write-posting"
|
|
line.long 0x04 "GPMC_PREFETCH_CONFIG2,Prefetch Engine Configuration 2"
|
|
hexmask.long.word 0x04 0.--13. 1. " TRANSFERCOUNT ,Number of bytes to be read/write by the engine to the selected CS"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "GPMC_PREFETCH_CONTROL,Prefetch Engine Control"
|
|
bitfld.long 0x00 0. " STARTENGINE ,Reset FIFO pointer and start the engine" "Stopped,Running"
|
|
rgroup.long 0x1f0++0x03
|
|
line.long 0x00 "GPMC_PREFETCH_STATUS,Prefetch Engine Status"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FIFOPOINTER ,Number of available bytes to be read/write"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FIFOTHRESHOLDSTATUS ,Set when FIFOPOINTER exceeds FIFOTHRESHOLD value" "<=FIFOTHRESHOLD,>FIFOTHRESHOLD"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--13. 1. " COUNTVALUE ,Number of remaining bytes to be read/write"
|
|
group.long 0x1f4++0x0b
|
|
line.long 0x00 "GPMC_ECC_CONFIG,ECC Configuration"
|
|
bitfld.long 0x00 16. " ECCALGORITHM ,ECC algorithm used" "Hamming,BCH"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*")||(cpuis("AM335*"))||cpuis("C6A816*"))||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 12.--13. " ECCBCHTSEL ,Error correction capability used for BCH" "t=4,t=8,t=16,?..."
|
|
else
|
|
bitfld.long 0x00 12. " ECCBCHT8 ,Error correction capability used for BCH" "t=4,t=8"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " ECCWRAPMODE ,Spare area organization definition for the BCH algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ECC16B ,Selects an ECC calculated on 16 columns" "8 columns,16 columns"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " ECCTOPSECTOR ,Number of sectors to process with the BCH algorithm" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM335*"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143"))
|
|
bitfld.long 0x00 1.--3. " ECCCS ,Selects the CS where ECC is computed" "Chip-select 0,Chip-select 1,Chip-select 2,Chip-select 3,Chip-select 4,Chip-select 5,?..."
|
|
else
|
|
bitfld.long 0x00 1.--3. " ECCCS ,Selects the CS where ECC is computed" "Chip-select 0,Chip-select 1,Chip-select 2,Chip-select 3,Chip-select 4,Chip-select 5,Chip-select 6,Chip-select 7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " ECCENABLE ,Enables the ECC feature" "Disabled,Enabled"
|
|
line.long 0x04 "GPMC_ECC_CONTROL,ECC Control"
|
|
eventfld.long 0x04 8. " ECCCLEAR ,Clear all ECC result registers" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " ECCPOINTER ,ECC result register" "ECC engine disabled,ECC result register 1,ECC result register 2,ECC result register 3,ECC result register 4,ECC result register 5,ECC result register 6,ECC result register 7,ECC result register 8,ECC result register 9,?..."
|
|
line.long 0x08 "GPMC_ECC_SIZE_CONFIG,ECC Size"
|
|
hexmask.long.byte 0x08 22.--29. 1. " ECCSIZE1 ,Defines ECC size 1"
|
|
hexmask.long.byte 0x08 12.--19. 1. " ECCSIZE0 ,Defines ECC size 0"
|
|
textline " "
|
|
bitfld.long 0x08 8. " ECC9RESULTSIZE ,Selects ECC size for ECC 9 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x08 7. " ECC8RESULTSIZE ,Selects ECC size for ECC 8 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x08 6. " ECC7RESULTSIZE ,Selects ECC size for ECC 7 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x08 5. " ECC6RESULTSIZE ,Selects ECC size for ECC 6 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x08 4. " ECC5RESULTSIZE ,Selects ECC size for ECC 5 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x08 3. " ECC4RESULTSIZE ,Selects ECC size for ECC 4 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ECC3RESULTSIZE ,Selects ECC size for ECC 3 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x08 1. " ECC2RESULTSIZE ,Selects ECC size for ECC 2 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ECC1RESULTSIZE ,Selects ECC size for ECC 1 result register" "ECCSize0,ECCSize1"
|
|
group.long 0x2D0++0x3
|
|
line.long 0x00 "GPMC_BCH_SWDATA,Pass Data To The BCH ECC Calculator"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCH_DATA ,Data to be included in the BCH calculation"
|
|
tree.end
|
|
tree "Chip Select #0"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS0,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0x60+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS0,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,0CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,0CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,0CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,0CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS0,0ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,0ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,0ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,0ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,0ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,0ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,0ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,0ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS0,0WE and 0OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,0WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,0WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,0WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,0OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,0OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,0OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,0OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,0OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS0,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x60+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS0,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS0,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0x60+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS0,Address Location"
|
|
wgroup.long (0x60+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS0,Address Location"
|
|
group.long (0x60+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS0,Address Location"
|
|
tree.end
|
|
tree "Chip Select #1"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS1,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0x90+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS1,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,1CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,1CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,1CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,1CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS1,1ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,1ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,1ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,1ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,1ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,1ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,1ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,1ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS1,1WE and 1OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,1WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,1WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,1WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,1OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,1OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,1OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,1OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,1OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS1,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x90+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS1,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS1,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0x90+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS1,Address Location"
|
|
wgroup.long (0x90+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS1,Address Location"
|
|
group.long (0x90+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS1,Address Location"
|
|
tree.end
|
|
tree "Chip Select #2"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS2,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0xC0+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS2,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,2CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,2CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,2CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,2CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS2,2ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,2ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,2ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,2ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,2ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,2ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,2ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,2ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS2,2WE and 2OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,2WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,2WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,2WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,2OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,2OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,2OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,2OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,2OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS2,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xC0+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS2,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS2,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0xC0+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS2,Address Location"
|
|
wgroup.long (0xC0+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS2,Address Location"
|
|
group.long (0xC0+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS2,Address Location"
|
|
tree.end
|
|
tree "Chip Select #3"
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS3,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0xF0+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS3,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,3CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,3CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,3CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,3CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS3,3ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,3ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,3ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,3ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,3ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,3ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,3ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,3ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS3,3WE and 3OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,3WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,3WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,3WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,3OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,3OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,3OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,3OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,3OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS3,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xF0+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS3,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS3,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0xF0+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS3,Address Location"
|
|
wgroup.long (0xF0+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS3,Address Location"
|
|
group.long (0xF0+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS3,Address Location"
|
|
tree.end
|
|
tree "Chip Select #4"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS4,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0x120+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS4,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,4CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,4CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,4CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,4CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS4,4ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,4ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,4ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,4ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,4ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,4ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,4ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,4ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS4,4WE and 4OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,4WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,4WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,4WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,4OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,4OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,4OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,4OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,4OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS4,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x120+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS4,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS4,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0x120+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS4,Address Location"
|
|
wgroup.long (0x120+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS4,Address Location"
|
|
group.long (0x120+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS4,Address Location"
|
|
tree.end
|
|
tree "Chip Select #5"
|
|
group.long 0x150++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS5,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0x150+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS5,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,5CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,5CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,5CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,5CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS5,5ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,5ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,5ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,5ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,5ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,5ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,5ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,5ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS5,5WE and 5OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,5WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,5WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,5WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,5OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,5OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,5OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,5OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,5OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS5,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x150+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS5,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS5,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0x150+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS5,Address Location"
|
|
wgroup.long (0x150+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS5,Address Location"
|
|
group.long (0x150+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS5,Address Location"
|
|
tree.end
|
|
tree "Result Registers"
|
|
width 19.
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rgroup.long 0x200++0x23
|
|
line.long 0x0 "GPMC_ECC1_RESULT,ECC1 Result Register"
|
|
bitfld.long 0x0 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x0 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x0 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x0 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x0 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x0 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x0 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x0 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x0 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x0 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x0 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x0 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x0 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x0 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x0 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x0 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x4 "GPMC_ECC2_RESULT,ECC2 Result Register"
|
|
bitfld.long 0x4 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x4 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x4 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x4 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x4 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x4 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x4 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x4 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x4 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x4 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x4 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x4 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x4 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x4 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x4 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x4 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x4 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x4 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x4 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x8 "GPMC_ECC3_RESULT,ECC3 Result Register"
|
|
bitfld.long 0x8 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x8 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x8 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x8 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x8 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x8 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x8 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x8 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x8 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x8 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x8 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x8 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x8 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x8 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x8 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x8 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x8 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x8 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x8 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0xC "GPMC_ECC4_RESULT,ECC4 Result Register"
|
|
bitfld.long 0xC 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0xC 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0xC 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0xC 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0xC 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0xC 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0xC 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0xC 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0xC 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0xC 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0xC 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0xC 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0xC 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0xC 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0xC 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0xC 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0xC 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0xC 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0xC 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x10 "GPMC_ECC5_RESULT,ECC5 Result Register"
|
|
bitfld.long 0x10 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x10 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x10 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x10 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x10 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x10 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x10 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x10 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x10 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x10 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x10 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x10 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x10 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x10 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x10 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x10 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x10 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x10 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x10 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x14 "GPMC_ECC6_RESULT,ECC6 Result Register"
|
|
bitfld.long 0x14 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x14 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x14 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x14 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x14 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x14 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x14 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x14 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x14 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x14 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x14 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x14 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x14 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x14 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x14 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x14 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x14 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x14 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x14 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x18 "GPMC_ECC7_RESULT,ECC7 Result Register"
|
|
bitfld.long 0x18 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x18 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x18 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x18 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x18 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x18 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x18 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x18 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x18 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x18 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x18 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x18 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x18 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x18 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x18 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x18 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x18 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x18 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x18 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x1C "GPMC_ECC8_RESULT,ECC8 Result Register"
|
|
bitfld.long 0x1C 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x1C 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x1C 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x1C 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x1C 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x1C 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x1C 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x1C 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x1C 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x1C 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x1C 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x1C 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x1C 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x1C 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x1C 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x1C 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x1C 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x1C 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x1C 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x20 "GPMC_ECC9_RESULT,ECC9 Result Register"
|
|
bitfld.long 0x20 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x20 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x20 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x20 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x20 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x20 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x20 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x20 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x20 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x20 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x20 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x20 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x20 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x20 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x20 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x20 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x20 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x20 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x20 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
else
|
|
group.long 0x200++0x23
|
|
line.long 0x0 "GPMC_ECC1_RESULT,ECC1 Result Register"
|
|
bitfld.long 0x0 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x0 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x0 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x0 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x0 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x0 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x0 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x0 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x0 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x0 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x0 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x0 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x0 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x0 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x0 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x0 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x4 "GPMC_ECC2_RESULT,ECC2 Result Register"
|
|
bitfld.long 0x4 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x4 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x4 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x4 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x4 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x4 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x4 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x4 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x4 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x4 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x4 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x4 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x4 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x4 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x4 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x4 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x4 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x4 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x4 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x8 "GPMC_ECC3_RESULT,ECC3 Result Register"
|
|
bitfld.long 0x8 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x8 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x8 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x8 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x8 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x8 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x8 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x8 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x8 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x8 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x8 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x8 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x8 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x8 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x8 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x8 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x8 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x8 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x8 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0xC "GPMC_ECC4_RESULT,ECC4 Result Register"
|
|
bitfld.long 0xC 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0xC 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0xC 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0xC 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0xC 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0xC 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0xC 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0xC 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0xC 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0xC 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0xC 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0xC 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0xC 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0xC 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0xC 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0xC 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0xC 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0xC 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0xC 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x10 "GPMC_ECC5_RESULT,ECC5 Result Register"
|
|
bitfld.long 0x10 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x10 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x10 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x10 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x10 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x10 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x10 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x10 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x10 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x10 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x10 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x10 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x10 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x10 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x10 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x10 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x10 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x10 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x10 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x14 "GPMC_ECC6_RESULT,ECC6 Result Register"
|
|
bitfld.long 0x14 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x14 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x14 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x14 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x14 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x14 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x14 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x14 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x14 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x14 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x14 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x14 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x14 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x14 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x14 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x14 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x14 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x14 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x14 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x18 "GPMC_ECC7_RESULT,ECC7 Result Register"
|
|
bitfld.long 0x18 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x18 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x18 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x18 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x18 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x18 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x18 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x18 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x18 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x18 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x18 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x18 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x18 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x18 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x18 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x18 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x18 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x18 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x18 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x1C "GPMC_ECC8_RESULT,ECC8 Result Register"
|
|
bitfld.long 0x1C 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x1C 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x1C 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x1C 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x1C 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x1C 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x1C 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x1C 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x1C 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x1C 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x1C 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x1C 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x1C 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x1C 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x1C 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x1C 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x1C 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x1C 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x1C 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x20 "GPMC_ECC9_RESULT,ECC9 Result Register"
|
|
bitfld.long 0x20 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x20 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x20 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x20 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x20 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x20 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x20 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x20 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x20 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x20 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x20 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x20 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x20 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x20 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x20 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x20 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x20 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x20 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x20 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
endif
|
|
group.long 0x240++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_0,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_0,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_0,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_0,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_0,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x240+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_0,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_0,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_0,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_0 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
group.long 0x250++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_1,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_1,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_1,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_1,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_1,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x250+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_1,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_1,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_1,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_1 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
group.long 0x260++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_2,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_2,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_2,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_2,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_2,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x260+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_2,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_2,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_2,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_2 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
group.long 0x270++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_3,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_3,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_3,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_3,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_3,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x270+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_3,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_3,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_3,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_3 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
group.long 0x280++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_4,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_4,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_4,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_4,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_4,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x280+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_4,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_4,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_4,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_4 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
group.long 0x290++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_5,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_5,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_5,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_5,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_5,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x290+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_5,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_5,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_5,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_5 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 0xb
|
|
else
|
|
width 23.
|
|
tree "Miscellaneous Registers"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPMC_REVISION,IP Revision Code"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP revision"
|
|
group.long 0x10++0x3
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||cpuis("AM389*")||cpuis("AM335*")||cpuis("C6A816*")||cpuis("AM387*")||cpuis("DRA6*")||cpu()=="DM8148"||cpu()=="DM8147"||cpu()=="C6A8148"||cpu()=="C6A8147"||cpu()=="C6A8143"||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
|
|
line.long 0x00 "GPMC_SYSCONFIG,Various Parameters Of The OCP Interface"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
else
|
|
line.long 0x00 "GPMC_SYSCONFIG,Various Parameters Of The Interconnect Control"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPMC_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "GPMC_IRQSTATUS,Interrupt Status Register"
|
|
sif (((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&(!(cpuis("AM389*")))&&(!(cpuis("AM335*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(!(cpuis("DRA6*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143"))
|
|
eventfld.long 0x00 11. " WAIT3EDGEDETECTIONSTATUS ,Status of the Wait3 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT2EDGEDETECTIONSTATUS ,Status of the Wait2 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 9. " WAIT1EDGEDETECTIONSTATUS ,Status of the Wait1 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 8. " WAIT0EDGEDETECTIONSTATUS ,Status of the Wait0 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TERMINALCOUNTSTATUS ,Status of the TerminalCountEvent interrupt (COUNTVALUE)" ">0,=0"
|
|
textline " "
|
|
eventfld.long 0x00 0. " FIFOEVENTSTATUS ,Status of the FIFOEvent interrupt" "<FIFOTHRESHOLD,=FIFOTHRESHOLD"
|
|
line.long 0x04 "GPMC_IRQENABLE,Interrupt Enable Register"
|
|
sif (((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&(!(cpuis("AM389*")))&&(!(cpuis("AM335*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(!(cpuis("DRA6*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143"))
|
|
bitfld.long 0x04 11. " WAIT3EDGEDETECTIONENABLE ,Enables the Wait3 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " WAIT2EDGEDETECTIONENABLE ,Enables the Wait2 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 9. " WAIT1EDGEDETECTIONENABLE ,Enables the Wait1 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT0EDGEDETECTIONENABLE ,Enables the Wait0 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TERMINALCOUNTEVENTENABLE ,Enables TerminalCountEvent interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FIFOEVENTENABLE ,Enables the FIFOEvent interrupt" "Masked,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "GPMC_TIMEOUT_CONTROL,Start Value Of The Timeout Counter Set Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " TIMEOUTSTARTVALUE ,Start value of the time-out counter"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIMEOUTENABLE ,Enable bit of the TimeOut feature" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "GPMC_ERR_ADDRESS,Stores The Address Of The Illegal Access"
|
|
hexmask.long 0x00 0.--30. 1. " ILLEGALADD ,Address of illegal access"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GPMC_ERR_TYPE,Stores The Type Of Error"
|
|
bitfld.long 0x00 8.--10. " ILLEGALMCMD ,System Command of the transaction that caused the error" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERRORNOTSUPPADD ,Not supported Address error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERRORNOTSUPPMCMD ,Not supported Command error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ERRORTIMEOUT ,Time-out error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ERRORVALID ,Error validity status" "Not valid,Valid"
|
|
group.long 0x50++0x7
|
|
line.long 0x00 "GPMC_CONFIG,Global Configuration Of The GPMC Module"
|
|
sif (((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&(!(cpuis("AM389*")))&&(!(cpuis("AM335*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(!(cpuis("DRA6*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143"))
|
|
bitfld.long 0x00 11. " WAIT3PINPOLARITY ,Selects the polarity of input pin WAIT3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WAIT2PINPOLARITY ,Selects the polarity of input pin WAIT2" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " WAIT1PINPOLARITY ,Selects the polarity of input pin WAIT1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WAIT0PINPOLARITY ,Selects the polarity of input pin WAIT0" "Low,High"
|
|
textline " "
|
|
sif (!(cpuis("AM387*")))
|
|
bitfld.long 0x00 4. " WRITEPROTECT ,Controls the /WP output pin level" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 1. " LIMITEDADDRESS ,Limited Address device support" "Not supported,Supported"
|
|
else
|
|
bitfld.long 0x00 1. " LIMITEDADDRESS ,Limited Address device support" "No effect,A26-A11 not modified"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " NANDFORCEPOSTEDWRITE ,Enables the Force Posted Write feature to NAND Cmd/Add/Data location" "Disabled,Enabled"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "GPMC_STATUS,Global Status Bits Of The GPMC Module"
|
|
sif (((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&(!(cpuis("AM389*")))&&(!(cpuis("AM335*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(!(cpuis("DRA6*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143"))
|
|
bitfld.long 0x00 11. " WAIT3STATUS ,Copy of input pin WAIT3" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WAIT2STATUS ,Copy of input pin WAIT2" "Asserted,De-asserted"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " WAIT1STATUS ,Copy of input pin WAIT1" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WAIT0STATUS ,Copy of input pin WAIT0" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EMPTYWRITEBUFFERSTATUS ,Stores the empty status of the write buffer" "Not empty,Empty"
|
|
group.long 0x1E0++0x7
|
|
line.long 0x00 "GPMC_PREFETCH_CONFIG1,Prefetch Engine Configuration 1"
|
|
bitfld.long 0x00 28.--30. " CYCLEOPTIMIZATION ,Defines the number of GPMC_FCLK cycles to be subtracted" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENABLEOPTIMIZEDACCESS ,Enables access cycle optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ENGINECSSELECTOR ,/CS where Prefetch Postwrite engine is active" "/CS0,/CS1,/CS2,/CS3,/CS4,/CS5,/CS6,/CS7"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFPWENROUNDROBIN ,PFPW RoundRobin arbitration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PFPWWEIGHTEDPRIO ,Arbitration between a direct memory access and a PFPW engine access (next access is granted to the PFPW engine)" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " FIFOTHRESHOLD ,Maximum number of bytes read/write from the FIFO"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLEENGINE ,Prefetch Postwite engine enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--5. " WAITPINSELECTOR ,Selects which wait pin edge detector should start the engine in synchronized mode" "Wait0EdgeDetection,Wait1EdgeDetection,?..."
|
|
else
|
|
bitfld.long 0x00 4.--5. " WAITPINSELECTOR ,Selects which wait pin edge detector should start the engine in synchronized mode" "Wait0EdgeDetection,Wait1EdgeDetection,Wait2EdgeDetection,Wait3EdgeDetection"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHROMODE ,Selects when the engine starts the access to CS" "StartEngine set,StartEngine set/wait to nonwait edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMAMODE ,Selects interrupt synchronization or DMA request synchronization" "Interrupt,DMA request"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACCESSMODE ,Selects prefetch read or write-posting accesses" "Prefetch read,Write-posting"
|
|
line.long 0x04 "GPMC_PREFETCH_CONFIG2,Prefetch Engine Configuration 2"
|
|
hexmask.long.word 0x04 0.--13. 1. " TRANSFERCOUNT ,Number of bytes to be read/write by the engine to the selected CS"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "GPMC_PREFETCH_CONTROL,Prefetch Engine Control"
|
|
bitfld.long 0x00 0. " STARTENGINE ,Reset FIFO pointer and start the engine" "Stopped,Running"
|
|
rgroup.long 0x1f0++0x03
|
|
line.long 0x00 "GPMC_PREFETCH_STATUS,Prefetch Engine Status"
|
|
hexmask.long.byte 0x00 24.--30. 1. " FIFOPOINTER ,Number of available bytes to be read/write"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FIFOTHRESHOLDSTATUS ,Set when FIFOPOINTER exceeds FIFOTHRESHOLD value" "<=FIFOTHRESHOLD,>FIFOTHRESHOLD"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--13. 1. " COUNTVALUE ,Number of remaining bytes to be read/write"
|
|
group.long 0x1f4++0x0b
|
|
line.long 0x00 "GPMC_ECC_CONFIG,ECC Configuration"
|
|
bitfld.long 0x00 16. " ECCALGORITHM ,ECC algorithm used" "Hamming,BCH"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*")||(cpuis("AM335*"))||cpuis("C6A816*"))||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 12.--13. " ECCBCHTSEL ,Error correction capability used for BCH" "t=4,t=8,t=16,?..."
|
|
else
|
|
bitfld.long 0x00 12. " ECCBCHT8 ,Error correction capability used for BCH" "t=4,t=8"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " ECCWRAPMODE ,Spare area organization definition for the BCH algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ECC16B ,Selects an ECC calculated on 16 columns" "8 columns,16 columns"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " ECCTOPSECTOR ,Number of sectors to process with the BCH algorithm" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM335*"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143"))
|
|
bitfld.long 0x00 1.--3. " ECCCS ,Selects the CS where ECC is computed" "Chip-select 0,Chip-select 1,Chip-select 2,Chip-select 3,Chip-select 4,Chip-select 5,?..."
|
|
else
|
|
bitfld.long 0x00 1.--3. " ECCCS ,Selects the CS where ECC is computed" "Chip-select 0,Chip-select 1,Chip-select 2,Chip-select 3,Chip-select 4,Chip-select 5,Chip-select 6,Chip-select 7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " ECCENABLE ,Enables the ECC feature" "Disabled,Enabled"
|
|
line.long 0x04 "GPMC_ECC_CONTROL,ECC Control"
|
|
eventfld.long 0x04 8. " ECCCLEAR ,Clear all ECC result registers" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " ECCPOINTER ,ECC result register" "ECC engine disabled,ECC result register 1,ECC result register 2,ECC result register 3,ECC result register 4,ECC result register 5,ECC result register 6,ECC result register 7,ECC result register 8,ECC result register 9,?..."
|
|
line.long 0x08 "GPMC_ECC_SIZE_CONFIG,ECC Size"
|
|
hexmask.long.byte 0x08 22.--29. 1. " ECCSIZE1 ,Defines ECC size 1"
|
|
hexmask.long.byte 0x08 12.--19. 1. " ECCSIZE0 ,Defines ECC size 0"
|
|
textline " "
|
|
bitfld.long 0x08 8. " ECC9RESULTSIZE ,Selects ECC size for ECC 9 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x08 7. " ECC8RESULTSIZE ,Selects ECC size for ECC 8 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x08 6. " ECC7RESULTSIZE ,Selects ECC size for ECC 7 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x08 5. " ECC6RESULTSIZE ,Selects ECC size for ECC 6 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x08 4. " ECC5RESULTSIZE ,Selects ECC size for ECC 5 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x08 3. " ECC4RESULTSIZE ,Selects ECC size for ECC 4 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ECC3RESULTSIZE ,Selects ECC size for ECC 3 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x08 1. " ECC2RESULTSIZE ,Selects ECC size for ECC 2 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ECC1RESULTSIZE ,Selects ECC size for ECC 1 result register" "ECCSize0,ECCSize1"
|
|
group.long 0x2D0++0x3
|
|
line.long 0x00 "GPMC_BCH_SWDATA,Pass Data To The BCH ECC Calculator"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCH_DATA ,Data to be included in the BCH calculation"
|
|
tree.end
|
|
tree "Chip Select #0"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS0,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0x60+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS0,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,0CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,0CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,0CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,0CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS0,0ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,0ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,0ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,0ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,0ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,0ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,0ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,0ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS0,0WE and 0OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,0WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,0WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,0WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,0OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,0OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,0OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,0OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,0OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS0,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x60+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS0,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS0,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0x60+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS0,Address Location"
|
|
wgroup.long (0x60+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS0,Address Location"
|
|
group.long (0x60+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS0,Address Location"
|
|
tree.end
|
|
tree "Chip Select #1"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS1,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0x90+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS1,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,1CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,1CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,1CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,1CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS1,1ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,1ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,1ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,1ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,1ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,1ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,1ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,1ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS1,1WE and 1OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,1WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,1WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,1WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,1OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,1OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,1OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,1OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,1OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS1,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x90+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS1,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS1,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0x90+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS1,Address Location"
|
|
wgroup.long (0x90+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS1,Address Location"
|
|
group.long (0x90+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS1,Address Location"
|
|
tree.end
|
|
tree "Chip Select #2"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS2,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0xC0+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS2,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,2CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,2CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,2CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,2CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS2,2ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,2ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,2ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,2ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,2ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,2ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,2ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,2ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS2,2WE and 2OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,2WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,2WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,2WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,2OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,2OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,2OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,2OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,2OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS2,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xC0+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS2,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS2,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0xC0+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS2,Address Location"
|
|
wgroup.long (0xC0+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS2,Address Location"
|
|
group.long (0xC0+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS2,Address Location"
|
|
tree.end
|
|
tree "Chip Select #3"
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS3,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0xF0+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS3,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,3CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,3CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,3CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,3CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS3,3ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,3ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,3ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,3ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,3ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,3ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,3ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,3ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS3,3WE and 3OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,3WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,3WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,3WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,3OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,3OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,3OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,3OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,3OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS3,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xF0+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS3,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS3,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0xF0+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS3,Address Location"
|
|
wgroup.long (0xF0+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS3,Address Location"
|
|
group.long (0xF0+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS3,Address Location"
|
|
tree.end
|
|
tree "Chip Select #4"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS4,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0x120+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS4,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,4CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,4CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,4CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,4CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS4,4ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,4ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,4ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,4ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,4ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,4ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,4ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,4ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS4,4WE and 4OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,4WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,4WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,4WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,4OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,4OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,4OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,4OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,4OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS4,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x120+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS4,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS4,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0x120+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS4,Address Location"
|
|
wgroup.long (0x120+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS4,Address Location"
|
|
group.long (0x120+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS4,Address Location"
|
|
tree.end
|
|
tree "Chip Select #5"
|
|
group.long 0x150++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS5,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0x150+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS5,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,5CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,5CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,5CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,5CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS5,5ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,5ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,5ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,5ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,5ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,5ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,5ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,5ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS5,5WE and 5OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,5WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,5WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,5WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,5OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,5OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,5OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,5OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,5OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS5,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x150+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS5,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS5,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0x150+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS5,Address Location"
|
|
wgroup.long (0x150+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS5,Address Location"
|
|
group.long (0x150+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS5,Address Location"
|
|
tree.end
|
|
tree "Chip Select #6"
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS6,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0x180+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS6,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,6CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,6CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,6CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,6CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x180+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS6,6ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,6ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,6ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,6ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,6ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,6ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,6ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,6ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x180+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS6,6WE and 6OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,6WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,6WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,6WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,6OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,6OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,6OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,6OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,6OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x180+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS6,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x180+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS6,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x180+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS6,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0x180+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS6,Address Location"
|
|
wgroup.long (0x180+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS6,Address Location"
|
|
group.long (0x180+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS6,Address Location"
|
|
tree.end
|
|
tree "Chip Select #7"
|
|
group.long 0x1B0++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_CS7,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
|
|
else
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
else
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
|
|
endif
|
|
group.long (0x1B0+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_CS7,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,7CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,7CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,7CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,7CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x1B0+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_CS7,7ADV Signal Timing Parameter Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,7ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,7ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,7ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,7ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,7ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,7ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,7ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x1B0+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_CS7,7WE and 7OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,7WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,7WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,7WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,7OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,7OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,7OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,7OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,7OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x1B0+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_CS7,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x1B0+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_CS7,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x1B0+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_CS7,Chip-select Address Mapping Configuration"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
else
|
|
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
wgroup.long (0x1B0+0x1C)++0x3
|
|
line.long 0x00 "GPMC_NAND_COMMAND_CS7,Address Location"
|
|
wgroup.long (0x1B0+0x20)++0x3
|
|
line.long 0x00 "GPMC_NAND_ADDRESS_CS7,Address Location"
|
|
group.long (0x1B0+0x24)++0x3
|
|
line.long 0x00 "GPMC_NAND_DATA_CS7,Address Location"
|
|
tree.end
|
|
tree "Result Registers"
|
|
width 19.
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rgroup.long 0x200++0x23
|
|
line.long 0x0 "GPMC_ECC1_RESULT,ECC1 Result Register"
|
|
bitfld.long 0x0 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x0 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x0 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x0 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x0 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x0 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x0 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x0 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x0 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x0 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x0 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x0 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x0 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x0 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x0 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x0 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x4 "GPMC_ECC2_RESULT,ECC2 Result Register"
|
|
bitfld.long 0x4 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x4 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x4 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x4 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x4 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x4 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x4 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x4 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x4 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x4 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x4 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x4 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x4 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x4 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x4 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x4 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x4 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x4 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x4 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x8 "GPMC_ECC3_RESULT,ECC3 Result Register"
|
|
bitfld.long 0x8 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x8 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x8 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x8 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x8 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x8 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x8 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x8 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x8 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x8 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x8 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x8 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x8 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x8 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x8 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x8 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x8 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x8 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x8 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0xC "GPMC_ECC4_RESULT,ECC4 Result Register"
|
|
bitfld.long 0xC 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0xC 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0xC 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0xC 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0xC 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0xC 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0xC 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0xC 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0xC 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0xC 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0xC 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0xC 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0xC 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0xC 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0xC 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0xC 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0xC 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0xC 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0xC 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x10 "GPMC_ECC5_RESULT,ECC5 Result Register"
|
|
bitfld.long 0x10 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x10 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x10 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x10 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x10 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x10 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x10 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x10 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x10 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x10 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x10 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x10 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x10 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x10 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x10 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x10 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x10 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x10 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x10 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x14 "GPMC_ECC6_RESULT,ECC6 Result Register"
|
|
bitfld.long 0x14 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x14 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x14 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x14 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x14 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x14 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x14 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x14 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x14 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x14 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x14 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x14 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x14 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x14 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x14 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x14 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x14 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x14 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x14 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x18 "GPMC_ECC7_RESULT,ECC7 Result Register"
|
|
bitfld.long 0x18 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x18 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x18 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x18 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x18 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x18 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x18 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x18 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x18 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x18 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x18 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x18 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x18 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x18 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x18 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x18 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x18 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x18 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x18 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x1C "GPMC_ECC8_RESULT,ECC8 Result Register"
|
|
bitfld.long 0x1C 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x1C 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x1C 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x1C 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x1C 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x1C 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x1C 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x1C 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x1C 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x1C 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x1C 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x1C 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x1C 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x1C 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x1C 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x1C 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x1C 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x1C 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x1C 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x20 "GPMC_ECC9_RESULT,ECC9 Result Register"
|
|
bitfld.long 0x20 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x20 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x20 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x20 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x20 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x20 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x20 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x20 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x20 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x20 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x20 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x20 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x20 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x20 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x20 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x20 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x20 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x20 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x20 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
else
|
|
group.long 0x200++0x23
|
|
line.long 0x0 "GPMC_ECC1_RESULT,ECC1 Result Register"
|
|
bitfld.long 0x0 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x0 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x0 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x0 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x0 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x0 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x0 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x0 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x0 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x0 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x0 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x0 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x0 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x0 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x0 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x0 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x4 "GPMC_ECC2_RESULT,ECC2 Result Register"
|
|
bitfld.long 0x4 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x4 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x4 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x4 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x4 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x4 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x4 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x4 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x4 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x4 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x4 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x4 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x4 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x4 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x4 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x4 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x4 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x4 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x4 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x8 "GPMC_ECC3_RESULT,ECC3 Result Register"
|
|
bitfld.long 0x8 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x8 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x8 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x8 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x8 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x8 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x8 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x8 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x8 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x8 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x8 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x8 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x8 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x8 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x8 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x8 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x8 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x8 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x8 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0xC "GPMC_ECC4_RESULT,ECC4 Result Register"
|
|
bitfld.long 0xC 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0xC 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0xC 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0xC 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0xC 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0xC 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0xC 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0xC 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0xC 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0xC 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0xC 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0xC 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0xC 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0xC 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0xC 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0xC 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0xC 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0xC 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0xC 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x10 "GPMC_ECC5_RESULT,ECC5 Result Register"
|
|
bitfld.long 0x10 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x10 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x10 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x10 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x10 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x10 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x10 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x10 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x10 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x10 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x10 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x10 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x10 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x10 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x10 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x10 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x10 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x10 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x10 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x14 "GPMC_ECC6_RESULT,ECC6 Result Register"
|
|
bitfld.long 0x14 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x14 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x14 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x14 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x14 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x14 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x14 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x14 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x14 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x14 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x14 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x14 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x14 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x14 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x14 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x14 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x14 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x14 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x14 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x18 "GPMC_ECC7_RESULT,ECC7 Result Register"
|
|
bitfld.long 0x18 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x18 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x18 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x18 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x18 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x18 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x18 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x18 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x18 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x18 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x18 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x18 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x18 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x18 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x18 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x18 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x18 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x18 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x18 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x1C "GPMC_ECC8_RESULT,ECC8 Result Register"
|
|
bitfld.long 0x1C 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x1C 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x1C 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x1C 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x1C 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x1C 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x1C 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x1C 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x1C 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x1C 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x1C 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x1C 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x1C 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x1C 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x1C 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x1C 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x1C 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x1C 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x1C 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x20 "GPMC_ECC9_RESULT,ECC9 Result Register"
|
|
bitfld.long 0x20 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x20 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x20 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x20 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x20 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x20 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x20 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x20 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x20 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x20 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x20 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x20 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x20 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x20 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x20 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x20 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x20 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x20 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x20 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
endif
|
|
group.long 0x240++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_0,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_0,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_0,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_0,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_0,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x240+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_0,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_0,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_0,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_0 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
group.long 0x250++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_1,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_1,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_1,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_1,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_1,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x250+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_1,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_1,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_1,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_1 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
group.long 0x260++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_2,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_2,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_2,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_2,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_2,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x260+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_2,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_2,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_2,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_2 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
group.long 0x270++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_3,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_3,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_3,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_3,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_3,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x270+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_3,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_3,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_3,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_3 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
group.long 0x280++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_4,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_4,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_4,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_4,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_4,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x280+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_4,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_4,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_4,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_4 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
group.long 0x290++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_5,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_5,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_5,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_5,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_5,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x290+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_5,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_5,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_5,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_5 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
group.long 0x2A0++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_6,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_6,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_6,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_6,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_6,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x2A0+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_6,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_6,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_6,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_6 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
group.long 0x2B0++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_7,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_7,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_7,BCH ECC result (bits 64 to 95)"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
line.long 0x0C "GPMC_BCH_RESULT3_7,BCH ECC result (bits 96 to 127)"
|
|
else
|
|
line.long 0x0C "GPMC_BCH_RESULT3_7,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
endif
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long (0x2B0+0xc0)++0xb
|
|
line.long 0x00 "GPMC_BCH_RESULT4_7,BCH ECC result (bits 128 to 159)"
|
|
line.long 0x04 "GPMC_BCH_RESULT5_7,BCH ECC result (bits 160 to 191)"
|
|
line.long 0x08 "GPMC_BCH_RESULT6_7,BCH ECC result (bits 192 to 207)"
|
|
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
|
|
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_7 ,BCH ECC result (bits 192 to 207)"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="AM3871"&&!cpuis("DRA62*"))
|
|
tree.open "HDVPSS (HD Video Processing Subsystem)"
|
|
tree "INTC"
|
|
base ad:0x48100000
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "HDVPSS_PID,HDVPSS Peripheral Identification Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme of the register used" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function of the module being used"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL Release Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major Release Number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom IP" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "HDVPSS_SYSCONFIG,HDVPSS Sysytem Configuration Register"
|
|
bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby,Smart-standby wakeup-capable"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
|
|
group.long 0xa0++0x3
|
|
line.long 0x00 "EOI,INTC EOI Vector Register"
|
|
width 20.
|
|
tree "INTR0"
|
|
group.long 0x20++0x1f
|
|
line.long 0x00 "INTR0_RAW0,INTC INTR0 Interrupt Status Raw/Set Register 0"
|
|
bitfld.long 0x00 31. " SDVENC_INT_RAW ,SDVENC Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 30. " VOUT0_INT2_RAW ,VOUT0 Frame Start Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 29. " VOUT0_INT1_RAW ,VOUT0 VBI End Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 28. " VOUT0_INT0_RAW ,VOUT0 VBI Start Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x00 24. " VOUT1_INT2_RAW ,HDMI/VOUT1 Frame Start Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 23. " VOUT1_INT1_RAW ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VOUT1_INT0_RAW ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 21. " VIN1_PARSER_INT_RAW ,Video Input Port 2 Parser Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " VIN0_PARSER_INT_RAW ,Video Input Port 1 Parser Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " DEI_FMD_INT_RAW ,DEI (M) Film Mode Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VPDMA_INT0_DESCRIPTOR_RAW ,VPDMA INT0 Descriptor Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 15. " VPDMA_INT0_LIST7_NOTIFY_RAW ,VPDMA INT0 List7 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 14. " VPDMA_INT0_LIST7_COMPLETE_RAW ,VPDMA INT0 List7 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 13. " VPDMA_INT0_LIST6_NOTIFY_RAW ,VPDMA INT0 List6 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " VPDMA_INT0_LIST6_COMPLETE_RAW ,VPDMA INT0 List6 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 11. " VPDMA_INT0_LIST5_NOTIFY_RAW ,VPDMA INT0 List5 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VPDMA_INT0_LIST5_COMPLETE_RAW ,VPDMA INT0 List5 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 9. " VPDMA_INT0_LIST4_NOTIFY_RAW ,VPDMA INT0 List4 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VPDMA_INT0_LIST4_COMPLETE_RAW ,VPDMA INT0 List4 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 7. " VPDMA_INT0_LIST3_NOTIFY_RAW ,VPDMA INT0 List3 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VPDMA_INT0_LIST3_COMPLETE_RAW ,VPDMA INT0 List3 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 5. " VPDMA_INT0_LIST2_NOTIFY_RAW ,VPDMA INT0 List2 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VPDMA_INT0_LIST2_COMPLETE_RAW ,VPDMA INT0 List2 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 3. " VPDMA_INT0_LIST1_NOTIFY_RAW ,VPDMA INT0 List1 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VPDMA_INT0_LIST1_COMPLETE_RAW ,VPDMA INT0 List1 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 1. " VPDMA_INT0_LIST0_NOTIFY_RAW ,VPDMA INT0 List0 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VPDMA_INT0_LIST0_COMPLETE_RAW ,VPDMA INT0 List0 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
line.long 0x04 "INTR0_RAW1,INTC INTR0 Interrupt Status Raw/Set Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x04 25. " VIN1_CHR_DS_2_UV_ERROR_INT_RAW ,VIN1 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 24. " VIN1_CHR_DS_1_UV_ERROR_INT_RAW ,VIN1 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 23. " VIN0_CHR_DS_2_UV_ERROR_INT_RAW ,VIN0 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 22. " VIN0_CHR_DS_1_UV_ERROR_INT_RAW ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 21. " NF_CHR_DS_UV_ERROR_INT_RAW ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 20. " COMP_ERROR_INT_RAW ,Compositor Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 19. " GRPX3_ERROR_INT_RAW ,GRPX3 Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 18. " GRPX2_ERROR_INT_RAW ,GRPX2 Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GRPX1_ERROR_INT_RAW ,GRPX1 Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 16. " DEI_ERROR_INT_RAW ,DEI (M) Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " VPDMA_INT0_CLIENT_RAW ,VPDMA INT0 Client Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 5. " VPDMA_INT0_CHANNEL_GROUP5_RAW ,VPDMA INT0 Channel Group5 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 4. " VPDMA_INT0_CHANNEL_GROUP4_RAW ,VPDMA INT0 Channel Group4 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 3. " VPDMA_INT0_CHANNEL_GROUP3_RAW ,VPDMA INT0 Channel Group3 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VPDMA_INT0_CHANNEL_GROUP2_RAW ,VPDMA INT0 Channel Group2 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 1. " VPDMA_INT0_CHANNEL_GROUP1_RAW ,VPDMA INT0 Channel Group1 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VPDMA_INT0_CHANNEL_GROUP0_RAW ,VPDMA INT0 Channel Group0 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
line.long 0x08 "INTR0_STAT_EN_CLR0,INTC INTR0 Interrupt Status Enabled/Clear Register 0"
|
|
bitfld.long 0x08 31. " SDVENC_INT_ENA ,SDVENC Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 30. " VOUT0_INT2_ENA ,VOUT0 Frame Start Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 29. " VOUT0_INT1_ENA ,VOUT0 VBI End Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 28. " VOUT0_INT0_ENA ,VOUT0 VBI Start Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x08 24. " VOUT1_INT2_ENA ,HDMI/VOUT1 Frame Start Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 23. " VOUT1_INT1_ENA ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 22. " VOUT1_INT0_ENA ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 21. " VIN1_PARSER_INT_ENA ,Video Input Port 2 Parser Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 20. " VIN0_PARSER_INT_ENA ,Video Input Port 1 Parser Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 18. " DEI_FMD_INT_ENA ,DEI (M) Film Mode Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 16. " VPDMA_INT0_DESCRIPTOR_ENA ,VPDMA INT0 Descriptor Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 15. " VPDMA_INT0_LIST7_NOTIFY_ENA ,VPDMA INT0 List7 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 14. " VPDMA_INT0_LIST7_COMPLETE_ENA ,VPDMA INT0 List7 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 13. " VPDMA_INT0_LIST6_NOTIFY_ENA ,VPDMA INT0 List6 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 12. " VPDMA_INT0_LIST6_COMPLETE_ENA ,VPDMA INT0 List6 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 11. " VPDMA_INT0_LIST5_NOTIFY_ENA ,VPDMA INT0 List5 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 10. " VPDMA_INT0_LIST5_COMPLETE_ENA ,VPDMA INT0 List5 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 9. " VPDMA_INT0_LIST4_NOTIFY_ENA ,VPDMA INT0 List4 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 8. " VPDMA_INT0_LIST4_COMPLETE_ENA ,VPDMA INT0 List4 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 7. " VPDMA_INT0_LIST3_NOTIFY_ENA ,VPDMA INT0 List3 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 6. " VPDMA_INT0_LIST3_COMPLETE_ENA ,VPDMA INT0 List3 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 5. " VPDMA_INT0_LIST2_NOTIFY_ENA ,VPDMA INT0 List2 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 4. " VPDMA_INT0_LIST2_COMPLETE_ENA ,VPDMA INT0 List2 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 3. " VPDMA_INT0_LIST1_NOTIFY_ENA ,VPDMA INT0 List1 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VPDMA_INT0_LIST1_COMPLETE_ENA ,VPDMA INT0 List1 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 1. " VPDMA_INT0_LIST0_NOTIFY_ENA ,VPDMA INT0 List0 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 0. " VPDMA_INT0_LIST0_COMPLETE_ENA ,VPDMA INT0 List0 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
line.long 0x0c "INTR0_STAT_EN_CLR1,INTC INTR0 Interrupt Status Enabled/Clear Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x0c 25. " VIN1_CHR_DS_2_UV_ERROR_INT_ENA ,VIN1 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 24. " VIN1_CHR_DS_1_UV_ERROR_INT_ENA ,VIN1 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " VIN0_CHR_DS_2_UV_ERROR_INT_ENA ,VIN0 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 22. " VIN0_CHR_DS_1_UV_ERROR_INT_ENA ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " NF_CHR_DS_UV_ERROR_INT_ENA ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 20. " COMP_ERROR_INT_ENA ,Compositor Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " GRPX3_ERROR_INT_ENA ,GRPX3 Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 18. " GRPX2_ERROR_INT_ENA ,GRPX2 Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " GRPX1_ERROR_INT_ENA ,GRPX1 Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 16. " DEI_ERROR_INT_ENA ,DEI (M) Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " VPDMA_INT0_CLIENT_ENA ,VPDMA INT0 Client Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA ,VPDMA INT0 Channel Group5 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA ,VPDMA INT0 Channel Group4 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA ,VPDMA INT0 Channel Group3 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA ,VPDMA INT0 Channel Group2 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA ,VPDMA INT0 Channel Group1 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA ,VPDMA INT0 Channel Group0 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
line.long 0x10 "INTR0_EN_SET0,INTC INTR0 Interrupt Enable/Set Register 0"
|
|
bitfld.long 0x10 31. " SDVENC_INT_ENA_SET ,SDVENC Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 30. " VOUT0_INT2_ENA_SET ,VOUT0 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 29. " VOUT0_INT1_ENA_SET ,VOUT0 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 28. " VOUT0_INT0_ENA_SET ,VOUT0 VBI Start Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x10 24. " VOUT1_INT2_ENA_SET ,HDMI/VOUT1 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 23. " VOUT1_INT1_ENA_SET ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 22. " VOUT1_INT0_ENA_SET ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 21. " VIN1_PARSER_INT_ENA_SET ,Video Input Port 2 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 20. " VIN0_PARSER_INT_ENA_SET ,Video Input Port 1 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 18. " DEI_FMD_INT_ENA_SET ,DEI (M) Film Mode Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 16. " VPDMA_INT0_DESCRIPTOR_ENA_SET ,VPDMA INT0 Descriptor Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_SET ,VPDMA INT0 List7 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_SET ,VPDMA INT0 List7 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_SET ,VPDMA INT0 List6 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_SET ,VPDMA INT0 List6 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_SET ,VPDMA INT0 List5 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_SET ,VPDMA INT0 List5 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_SET ,VPDMA INT0 List4 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_SET ,VPDMA INT0 List4 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_SET ,VPDMA INT0 List3 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_SET ,VPDMA INT0 List3 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_SET ,VPDMA INT0 List2 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_SET ,VPDMA INT0 List2 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_SET ,VPDMA INT0 List1 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_SET ,VPDMA INT0 List1 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_SET ,VPDMA INT0 List0 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_SET ,VPDMA INT0 List0 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
line.long 0x14 "INTR0_EN_SET1,INTC INTR0 Interrupt Enable/Set Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x14 25. " VIN1_CHR_DS_2_UV_ERROR_INT_ENA_SET ,VIN1 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 24. " VIN1_CHR_DS_1_UV_ERROR_INT_ENA_SET ,VIN1 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 23. " VIN0_CHR_DS_2_UV_ERROR_INT_ENA_SET ,VIN0 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 22. " VIN0_CHR_DS_1_UV_ERROR_INT_ENA_SET ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 21. " NF_CHR_DS_UV_ERROR_INT_ENA_SET ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 20. " COMP_ERROR_INT_ENA_SET ,Compositor Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 19. " GRPX3_ERROR_INT_ENA_SET ,GRPX3 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 18. " GRPX2_ERROR_INT_ENA_SET ,GRPX2 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 17. " GRPX1_ERROR_INT_ENA_SET ,GRPX1 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 16. " DEI_ERROR_INT_ENA_SET ,DEI (M) Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 7. " VPDMA_INT0_CLIENT_ENA_SET ,VPDMA INT0 Client Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_SET ,VPDMA INT0 Channel Group5 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_SET ,VPDMA INT0 Channel Group4 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_SET ,VPDMA INT0 Channel Group3 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_SET ,VPDMA INT0 Channel Group2 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_SET ,VPDMA INT0 Channel Group1 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_SET ,VPDMA INT0 Channel Group0 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
line.long 0x18 "INTR0_EN_CLR0,INTC INTR0 Interrupt Enable/Clear Register 0"
|
|
bitfld.long 0x18 31. " SDVENC_INT_ENA_CLR ,SDVENC Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 30. " VOUT0_INT2_ENA_CLR ,VOUT0 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 29. " VOUT0_INT1_ENA_CLR ,VOUT0 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 28. " VOUT0_INT0_ENA_CLR ,VOUT0 VBI Start Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x18 24. " VOUT1_INT2_ENA_CLR ,HDMI/VOUT1 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 23. " VOUT1_INT1_ENA_CLR ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 22. " VOUT1_INT0_ENA_CLR ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 21. " VIN1_PARSER_INT_ENA_CLR ,Video Input Port 2 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 20. " VIN0_PARSER_INT_ENA_CLR ,Video Input Port 1 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 18. " DEI_FMD_INT_ENA_CLR ,DEI (M) Film Mode Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 16. " VPDMA_INT0_DESCRIPTOR_ENA_CLR ,VPDMA INT0 Descriptor Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_CLR ,VPDMA INT0 List7 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_CLR ,VPDMA INT0 List7 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_CLR ,VPDMA INT0 List6 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_CLR ,VPDMA INT0 List6 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_CLR ,VPDMA INT0 List5 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_CLR ,VPDMA INT0 List5 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_CLR ,VPDMA INT0 List4 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_CLR ,VPDMA INT0 List4 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_CLR ,VPDMA INT0 List3 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_CLR ,VPDMA INT0 List3 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_CLR ,VPDMA INT0 List2 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_CLR ,VPDMA INT0 List2 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_CLR ,VPDMA INT0 List1 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_CLR ,VPDMA INT0 List1 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_CLR ,VPDMA INT0 List0 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_CLR ,VPDMA INT0 List0 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
line.long 0x1c "INTR0_EN_CLR1,INTC INTR0 Interrupt Enable/Clear Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x1c 25. " VIN1_CHR_DS_2_UV_ERROR_INT_ENA_CLR ,VIN1 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 24. " VIN1_CHR_DS_1_UV_ERROR_INT_ENA_CLR ,VIN1 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 23. " VIN0_CHR_DS_2_UV_ERROR_INT_ENA_CLR ,VIN0 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 22. " VIN0_CHR_DS_1_UV_ERROR_INT_ENA_CLR ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 21. " NF_CHR_DS_UV_ERROR_INT_ENA_CLR ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1c 20. " COMP_ERROR_INT_ENA_CLR ,Compositor Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 19. " GRPX3_ERROR_INT_ENA_CLR ,GRPX3 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 18. " GRPX2_ERROR_INT_ENA_CLR ,GRPX2 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 17. " GRPX1_ERROR_INT_ENA_CLR ,GRPX1 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 16. " DEI_ERROR_INT_ENA_CLR ,DEI (M) Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 7. " VPDMA_INT0_CLIENT_ENA_CLR ,VPDMA INT0 Client Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR ,VPDMA INT0 Channel Group5 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR ,VPDMA INT0 Channel Group4 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR ,VPDMA INT0 Channel Group3 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR ,VPDMA INT0 Channel Group2 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR ,VPDMA INT0 Channel Group1 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR ,VPDMA INT0 Channel Group0 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
tree.end
|
|
tree "INTR1"
|
|
group.long 0x40++0x1f
|
|
line.long 0x00 "INTR1_RAW0,INTC INTR1 Interrupt Status Raw/Set Register 0"
|
|
bitfld.long 0x00 31. " SDVENC_INT_RAW ,SDVENC Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 30. " VOUT0_INT2_RAW ,VOUT0 Frame Start Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 29. " VOUT0_INT1_RAW ,VOUT0 VBI End Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 28. " VOUT0_INT0_RAW ,VOUT0 VBI Start Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x00 24. " VOUT1_INT2_RAW ,HDMI/VOUT1 Frame Start Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 23. " VOUT1_INT1_RAW ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VOUT1_INT0_RAW ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 21. " VIN1_PARSER_INT_RAW ,Video Input Port 2 Parser Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " VIN0_PARSER_INT_RAW ,Video Input Port 1 Parser Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " DEI_FMD_INT_RAW ,DEI (M) Film Mode Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VPDMA_INT0_DESCRIPTOR_RAW ,VPDMA INT0 Descriptor Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 15. " VPDMA_INT0_LIST7_NOTIFY_RAW ,VPDMA INT0 List7 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 14. " VPDMA_INT0_LIST7_COMPLETE_RAW ,VPDMA INT0 List7 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 13. " VPDMA_INT0_LIST6_NOTIFY_RAW ,VPDMA INT0 List6 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " VPDMA_INT0_LIST6_COMPLETE_RAW ,VPDMA INT0 List6 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 11. " VPDMA_INT0_LIST5_NOTIFY_RAW ,VPDMA INT0 List5 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VPDMA_INT0_LIST5_COMPLETE_RAW ,VPDMA INT0 List5 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 9. " VPDMA_INT0_LIST4_NOTIFY_RAW ,VPDMA INT0 List4 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VPDMA_INT0_LIST4_COMPLETE_RAW ,VPDMA INT0 List4 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 7. " VPDMA_INT0_LIST3_NOTIFY_RAW ,VPDMA INT0 List3 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VPDMA_INT0_LIST3_COMPLETE_RAW ,VPDMA INT0 List3 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 5. " VPDMA_INT0_LIST2_NOTIFY_RAW ,VPDMA INT0 List2 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VPDMA_INT0_LIST2_COMPLETE_RAW ,VPDMA INT0 List2 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 3. " VPDMA_INT0_LIST1_NOTIFY_RAW ,VPDMA INT0 List1 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VPDMA_INT0_LIST1_COMPLETE_RAW ,VPDMA INT0 List1 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 1. " VPDMA_INT0_LIST0_NOTIFY_RAW ,VPDMA INT0 List0 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VPDMA_INT0_LIST0_COMPLETE_RAW ,VPDMA INT0 List0 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
line.long 0x04 "INTR1_RAW1,INTC INTR1 Interrupt Status Raw/Set Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x04 25. " VIN1_CHR_DS_2_UV_ERROR_INT_RAW ,VIN1 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 24. " VIN1_CHR_DS_1_UV_ERROR_INT_RAW ,VIN1 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 23. " VIN0_CHR_DS_2_UV_ERROR_INT_RAW ,VIN0 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 22. " VIN0_CHR_DS_1_UV_ERROR_INT_RAW ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 21. " NF_CHR_DS_UV_ERROR_INT_RAW ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 20. " COMP_ERROR_INT_RAW ,Compositor Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 19. " GRPX3_ERROR_INT_RAW ,GRPX3 Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 18. " GRPX2_ERROR_INT_RAW ,GRPX2 Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GRPX1_ERROR_INT_RAW ,GRPX1 Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 16. " DEI_ERROR_INT_RAW ,DEI (M) Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " VPDMA_INT0_CLIENT_RAW ,VPDMA INT0 Client Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 5. " VPDMA_INT0_CHANNEL_GROUP5_RAW ,VPDMA INT0 Channel Group5 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 4. " VPDMA_INT0_CHANNEL_GROUP4_RAW ,VPDMA INT0 Channel Group4 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 3. " VPDMA_INT0_CHANNEL_GROUP3_RAW ,VPDMA INT0 Channel Group3 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VPDMA_INT0_CHANNEL_GROUP2_RAW ,VPDMA INT0 Channel Group2 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 1. " VPDMA_INT0_CHANNEL_GROUP1_RAW ,VPDMA INT0 Channel Group1 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VPDMA_INT0_CHANNEL_GROUP0_RAW ,VPDMA INT0 Channel Group0 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
line.long 0x08 "INTR1_STAT_EN_CLR0,INTC INTR1 Interrupt Status Enabled/Clear Register 0"
|
|
bitfld.long 0x08 31. " SDVENC_INT_ENA ,SDVENC Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 30. " VOUT0_INT2_ENA ,VOUT0 Frame Start Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 29. " VOUT0_INT1_ENA ,VOUT0 VBI End Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 28. " VOUT0_INT0_ENA ,VOUT0 VBI Start Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x08 24. " VOUT1_INT2_ENA ,HDMI/VOUT1 Frame Start Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 23. " VOUT1_INT1_ENA ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 22. " VOUT1_INT0_ENA ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 21. " VIN1_PARSER_INT_ENA ,Video Input Port 2 Parser Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 20. " VIN0_PARSER_INT_ENA ,Video Input Port 1 Parser Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 18. " DEI_FMD_INT_ENA ,DEI (M) Film Mode Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 16. " VPDMA_INT0_DESCRIPTOR_ENA ,VPDMA INT0 Descriptor Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 15. " VPDMA_INT0_LIST7_NOTIFY_ENA ,VPDMA INT0 List7 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 14. " VPDMA_INT0_LIST7_COMPLETE_ENA ,VPDMA INT0 List7 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 13. " VPDMA_INT0_LIST6_NOTIFY_ENA ,VPDMA INT0 List6 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 12. " VPDMA_INT0_LIST6_COMPLETE_ENA ,VPDMA INT0 List6 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 11. " VPDMA_INT0_LIST5_NOTIFY_ENA ,VPDMA INT0 List5 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 10. " VPDMA_INT0_LIST5_COMPLETE_ENA ,VPDMA INT0 List5 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 9. " VPDMA_INT0_LIST4_NOTIFY_ENA ,VPDMA INT0 List4 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 8. " VPDMA_INT0_LIST4_COMPLETE_ENA ,VPDMA INT0 List4 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 7. " VPDMA_INT0_LIST3_NOTIFY_ENA ,VPDMA INT0 List3 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 6. " VPDMA_INT0_LIST3_COMPLETE_ENA ,VPDMA INT0 List3 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 5. " VPDMA_INT0_LIST2_NOTIFY_ENA ,VPDMA INT0 List2 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 4. " VPDMA_INT0_LIST2_COMPLETE_ENA ,VPDMA INT0 List2 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 3. " VPDMA_INT0_LIST1_NOTIFY_ENA ,VPDMA INT0 List1 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VPDMA_INT0_LIST1_COMPLETE_ENA ,VPDMA INT0 List1 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 1. " VPDMA_INT0_LIST0_NOTIFY_ENA ,VPDMA INT0 List0 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 0. " VPDMA_INT0_LIST0_COMPLETE_ENA ,VPDMA INT0 List0 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
line.long 0x0c "INTR1_STAT_EN_CLR1,INTC INTR1 Interrupt Status Enabled/Clear Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x0c 25. " VIN1_CHR_DS_2_UV_ERROR_INT_ENA ,VIN1 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 24. " VIN1_CHR_DS_1_UV_ERROR_INT_ENA ,VIN1 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " VIN0_CHR_DS_2_UV_ERROR_INT_ENA ,VIN0 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 22. " VIN0_CHR_DS_1_UV_ERROR_INT_ENA ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " NF_CHR_DS_UV_ERROR_INT_ENA ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 20. " COMP_ERROR_INT_ENA ,Compositor Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " GRPX3_ERROR_INT_ENA ,GRPX3 Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 18. " GRPX2_ERROR_INT_ENA ,GRPX2 Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " GRPX1_ERROR_INT_ENA ,GRPX1 Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 16. " DEI_ERROR_INT_ENA ,DEI (M) Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " VPDMA_INT0_CLIENT_ENA ,VPDMA INT0 Client Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA ,VPDMA INT0 Channel Group5 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA ,VPDMA INT0 Channel Group4 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA ,VPDMA INT0 Channel Group3 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA ,VPDMA INT0 Channel Group2 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA ,VPDMA INT0 Channel Group1 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA ,VPDMA INT0 Channel Group0 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
line.long 0x10 "INTR1_EN_SET0,INTC INTR1 Interrupt Enable/Set Register 0"
|
|
bitfld.long 0x10 31. " SDVENC_INT_ENA_SET ,SDVENC Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 30. " VOUT0_INT2_ENA_SET ,VOUT0 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 29. " VOUT0_INT1_ENA_SET ,VOUT0 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 28. " VOUT0_INT0_ENA_SET ,VOUT0 VBI Start Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x10 24. " VOUT1_INT2_ENA_SET ,HDMI/VOUT1 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 23. " VOUT1_INT1_ENA_SET ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 22. " VOUT1_INT0_ENA_SET ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 21. " VIN1_PARSER_INT_ENA_SET ,Video Input Port 2 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 20. " VIN0_PARSER_INT_ENA_SET ,Video Input Port 1 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 18. " DEI_FMD_INT_ENA_SET ,DEI (M) Film Mode Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 16. " VPDMA_INT0_DESCRIPTOR_ENA_SET ,VPDMA INT0 Descriptor Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_SET ,VPDMA INT0 List7 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_SET ,VPDMA INT0 List7 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_SET ,VPDMA INT0 List6 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_SET ,VPDMA INT0 List6 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_SET ,VPDMA INT0 List5 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_SET ,VPDMA INT0 List5 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_SET ,VPDMA INT0 List4 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_SET ,VPDMA INT0 List4 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_SET ,VPDMA INT0 List3 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_SET ,VPDMA INT0 List3 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_SET ,VPDMA INT0 List2 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_SET ,VPDMA INT0 List2 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_SET ,VPDMA INT0 List1 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_SET ,VPDMA INT0 List1 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_SET ,VPDMA INT0 List0 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_SET ,VPDMA INT0 List0 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
line.long 0x14 "INTR1_EN_SET1,INTC INTR1 Interrupt Enable/Set Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x14 25. " VIN1_CHR_DS_2_UV_ERROR_INT_ENA_SET ,VIN1 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 24. " VIN1_CHR_DS_1_UV_ERROR_INT_ENA_SET ,VIN1 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 23. " VIN0_CHR_DS_2_UV_ERROR_INT_ENA_SET ,VIN0 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 22. " VIN0_CHR_DS_1_UV_ERROR_INT_ENA_SET ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 21. " NF_CHR_DS_UV_ERROR_INT_ENA_SET ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 20. " COMP_ERROR_INT_ENA_SET ,Compositor Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 19. " GRPX3_ERROR_INT_ENA_SET ,GRPX3 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 18. " GRPX2_ERROR_INT_ENA_SET ,GRPX2 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 17. " GRPX1_ERROR_INT_ENA_SET ,GRPX1 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 16. " DEI_ERROR_INT_ENA_SET ,DEI (M) Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 7. " VPDMA_INT0_CLIENT_ENA_SET ,VPDMA INT0 Client Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_SET ,VPDMA INT0 Channel Group5 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_SET ,VPDMA INT0 Channel Group4 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_SET ,VPDMA INT0 Channel Group3 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_SET ,VPDMA INT0 Channel Group2 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_SET ,VPDMA INT0 Channel Group1 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_SET ,VPDMA INT0 Channel Group0 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
line.long 0x18 "INTR1_EN_CLR0,INTC INTR1 Interrupt Enable/Clear Register 0"
|
|
bitfld.long 0x18 31. " SDVENC_INT_ENA_CLR ,SDVENC Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 30. " VOUT0_INT2_ENA_CLR ,VOUT0 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 29. " VOUT0_INT1_ENA_CLR ,VOUT0 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 28. " VOUT0_INT0_ENA_CLR ,VOUT0 VBI Start Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x18 24. " VOUT1_INT2_ENA_CLR ,HDMI/VOUT1 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 23. " VOUT1_INT1_ENA_CLR ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 22. " VOUT1_INT0_ENA_CLR ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 21. " VIN1_PARSER_INT_ENA_CLR ,Video Input Port 2 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 20. " VIN0_PARSER_INT_ENA_CLR ,Video Input Port 1 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 18. " DEI_FMD_INT_ENA_CLR ,DEI (M) Film Mode Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 16. " VPDMA_INT0_DESCRIPTOR_ENA_CLR ,VPDMA INT0 Descriptor Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_CLR ,VPDMA INT0 List7 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_CLR ,VPDMA INT0 List7 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_CLR ,VPDMA INT0 List6 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_CLR ,VPDMA INT0 List6 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_CLR ,VPDMA INT0 List5 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_CLR ,VPDMA INT0 List5 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_CLR ,VPDMA INT0 List4 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_CLR ,VPDMA INT0 List4 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_CLR ,VPDMA INT0 List3 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_CLR ,VPDMA INT0 List3 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_CLR ,VPDMA INT0 List2 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_CLR ,VPDMA INT0 List2 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_CLR ,VPDMA INT0 List1 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_CLR ,VPDMA INT0 List1 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_CLR ,VPDMA INT0 List0 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_CLR ,VPDMA INT0 List0 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
line.long 0x1c "INTR1_EN_CLR1,INTC INTR1 Interrupt Enable/Clear Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x1c 25. " VIN1_CHR_DS_2_UV_ERROR_INT_ENA_CLR ,VIN1 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 24. " VIN1_CHR_DS_1_UV_ERROR_INT_ENA_CLR ,VIN1 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 23. " VIN0_CHR_DS_2_UV_ERROR_INT_ENA_CLR ,VIN0 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 22. " VIN0_CHR_DS_1_UV_ERROR_INT_ENA_CLR ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 21. " NF_CHR_DS_UV_ERROR_INT_ENA_CLR ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1c 20. " COMP_ERROR_INT_ENA_CLR ,Compositor Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 19. " GRPX3_ERROR_INT_ENA_CLR ,GRPX3 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 18. " GRPX2_ERROR_INT_ENA_CLR ,GRPX2 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 17. " GRPX1_ERROR_INT_ENA_CLR ,GRPX1 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 16. " DEI_ERROR_INT_ENA_CLR ,DEI (M) Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 7. " VPDMA_INT0_CLIENT_ENA_CLR ,VPDMA INT0 Client Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR ,VPDMA INT0 Channel Group5 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR ,VPDMA INT0 Channel Group4 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR ,VPDMA INT0 Channel Group3 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR ,VPDMA INT0 Channel Group2 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR ,VPDMA INT0 Channel Group1 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR ,VPDMA INT0 Channel Group0 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
tree.end
|
|
tree "INTR2"
|
|
group.long 0x60++0x1f
|
|
line.long 0x00 "INTR2_RAW0,INTC INTR2 Interrupt Status Raw/Set Register 0"
|
|
bitfld.long 0x00 31. " SDVENC_INT_RAW ,SDVENC Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 30. " VOUT0_INT2_RAW ,VOUT0 Frame Start Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 29. " VOUT0_INT1_RAW ,VOUT0 VBI End Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 28. " VOUT0_INT0_RAW ,VOUT0 VBI Start Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x00 24. " VOUT1_INT2_RAW ,HDMI/VOUT1 Frame Start Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 23. " VOUT1_INT1_RAW ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VOUT1_INT0_RAW ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 21. " VIN1_PARSER_INT_RAW ,Video Input Port 2 Parser Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " VIN0_PARSER_INT_RAW ,Video Input Port 1 Parser Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " DEI_FMD_INT_RAW ,DEI (M) Film Mode Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VPDMA_INT0_DESCRIPTOR_RAW ,VPDMA INT0 Descriptor Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 15. " VPDMA_INT0_LIST7_NOTIFY_RAW ,VPDMA INT0 List7 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 14. " VPDMA_INT0_LIST7_COMPLETE_RAW ,VPDMA INT0 List7 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 13. " VPDMA_INT0_LIST6_NOTIFY_RAW ,VPDMA INT0 List6 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " VPDMA_INT0_LIST6_COMPLETE_RAW ,VPDMA INT0 List6 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 11. " VPDMA_INT0_LIST5_NOTIFY_RAW ,VPDMA INT0 List5 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VPDMA_INT0_LIST5_COMPLETE_RAW ,VPDMA INT0 List5 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 9. " VPDMA_INT0_LIST4_NOTIFY_RAW ,VPDMA INT0 List4 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VPDMA_INT0_LIST4_COMPLETE_RAW ,VPDMA INT0 List4 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 7. " VPDMA_INT0_LIST3_NOTIFY_RAW ,VPDMA INT0 List3 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VPDMA_INT0_LIST3_COMPLETE_RAW ,VPDMA INT0 List3 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 5. " VPDMA_INT0_LIST2_NOTIFY_RAW ,VPDMA INT0 List2 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VPDMA_INT0_LIST2_COMPLETE_RAW ,VPDMA INT0 List2 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 3. " VPDMA_INT0_LIST1_NOTIFY_RAW ,VPDMA INT0 List1 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VPDMA_INT0_LIST1_COMPLETE_RAW ,VPDMA INT0 List1 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 1. " VPDMA_INT0_LIST0_NOTIFY_RAW ,VPDMA INT0 List0 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VPDMA_INT0_LIST0_COMPLETE_RAW ,VPDMA INT0 List0 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
line.long 0x04 "INTR2_RAW1,INTC INTR2 Interrupt Status Raw/Set Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x04 25. " VIN1_CHR_DS_2_UV_ERROR_INT_RAW ,VIN1 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 24. " VIN1_CHR_DS_1_UV_ERROR_INT_RAW ,VIN1 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 23. " VIN0_CHR_DS_2_UV_ERROR_INT_RAW ,VIN0 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 22. " VIN0_CHR_DS_1_UV_ERROR_INT_RAW ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 21. " NF_CHR_DS_UV_ERROR_INT_RAW ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 20. " COMP_ERROR_INT_RAW ,Compositor Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 19. " GRPX3_ERROR_INT_RAW ,GRPX3 Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 18. " GRPX2_ERROR_INT_RAW ,GRPX2 Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GRPX1_ERROR_INT_RAW ,GRPX1 Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 16. " DEI_ERROR_INT_RAW ,DEI (M) Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " VPDMA_INT0_CLIENT_RAW ,VPDMA INT0 Client Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 5. " VPDMA_INT0_CHANNEL_GROUP5_RAW ,VPDMA INT0 Channel Group5 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 4. " VPDMA_INT0_CHANNEL_GROUP4_RAW ,VPDMA INT0 Channel Group4 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 3. " VPDMA_INT0_CHANNEL_GROUP3_RAW ,VPDMA INT0 Channel Group3 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VPDMA_INT0_CHANNEL_GROUP2_RAW ,VPDMA INT0 Channel Group2 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 1. " VPDMA_INT0_CHANNEL_GROUP1_RAW ,VPDMA INT0 Channel Group1 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VPDMA_INT0_CHANNEL_GROUP0_RAW ,VPDMA INT0 Channel Group0 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
line.long 0x08 "INTR2_STAT_EN_CLR0,INTC INTR2 Interrupt Status Enabled/Clear Register 0"
|
|
bitfld.long 0x08 31. " SDVENC_INT_ENA ,SDVENC Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 30. " VOUT0_INT2_ENA ,VOUT0 Frame Start Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 29. " VOUT0_INT1_ENA ,VOUT0 VBI End Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 28. " VOUT0_INT0_ENA ,VOUT0 VBI Start Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x08 24. " VOUT1_INT2_ENA ,HDMI/VOUT1 Frame Start Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 23. " VOUT1_INT1_ENA ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 22. " VOUT1_INT0_ENA ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 21. " VIN1_PARSER_INT_ENA ,Video Input Port 2 Parser Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 20. " VIN0_PARSER_INT_ENA ,Video Input Port 1 Parser Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 18. " DEI_FMD_INT_ENA ,DEI (M) Film Mode Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 16. " VPDMA_INT0_DESCRIPTOR_ENA ,VPDMA INT0 Descriptor Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 15. " VPDMA_INT0_LIST7_NOTIFY_ENA ,VPDMA INT0 List7 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 14. " VPDMA_INT0_LIST7_COMPLETE_ENA ,VPDMA INT0 List7 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 13. " VPDMA_INT0_LIST6_NOTIFY_ENA ,VPDMA INT0 List6 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 12. " VPDMA_INT0_LIST6_COMPLETE_ENA ,VPDMA INT0 List6 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 11. " VPDMA_INT0_LIST5_NOTIFY_ENA ,VPDMA INT0 List5 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 10. " VPDMA_INT0_LIST5_COMPLETE_ENA ,VPDMA INT0 List5 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 9. " VPDMA_INT0_LIST4_NOTIFY_ENA ,VPDMA INT0 List4 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 8. " VPDMA_INT0_LIST4_COMPLETE_ENA ,VPDMA INT0 List4 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 7. " VPDMA_INT0_LIST3_NOTIFY_ENA ,VPDMA INT0 List3 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 6. " VPDMA_INT0_LIST3_COMPLETE_ENA ,VPDMA INT0 List3 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 5. " VPDMA_INT0_LIST2_NOTIFY_ENA ,VPDMA INT0 List2 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 4. " VPDMA_INT0_LIST2_COMPLETE_ENA ,VPDMA INT0 List2 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 3. " VPDMA_INT0_LIST1_NOTIFY_ENA ,VPDMA INT0 List1 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VPDMA_INT0_LIST1_COMPLETE_ENA ,VPDMA INT0 List1 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 1. " VPDMA_INT0_LIST0_NOTIFY_ENA ,VPDMA INT0 List0 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 0. " VPDMA_INT0_LIST0_COMPLETE_ENA ,VPDMA INT0 List0 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
line.long 0x0c "INTR2_STAT_EN_CLR1,INTC INTR2 Interrupt Status Enabled/Clear Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x0c 25. " VIN1_CHR_DS_2_UV_ERROR_INT_ENA ,VIN1 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 24. " VIN1_CHR_DS_1_UV_ERROR_INT_ENA ,VIN1 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " VIN0_CHR_DS_2_UV_ERROR_INT_ENA ,VIN0 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 22. " VIN0_CHR_DS_1_UV_ERROR_INT_ENA ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " NF_CHR_DS_UV_ERROR_INT_ENA ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 20. " COMP_ERROR_INT_ENA ,Compositor Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " GRPX3_ERROR_INT_ENA ,GRPX3 Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 18. " GRPX2_ERROR_INT_ENA ,GRPX2 Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " GRPX1_ERROR_INT_ENA ,GRPX1 Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 16. " DEI_ERROR_INT_ENA ,DEI (M) Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " VPDMA_INT0_CLIENT_ENA ,VPDMA INT0 Client Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA ,VPDMA INT0 Channel Group5 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA ,VPDMA INT0 Channel Group4 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA ,VPDMA INT0 Channel Group3 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA ,VPDMA INT0 Channel Group2 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA ,VPDMA INT0 Channel Group1 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA ,VPDMA INT0 Channel Group0 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
line.long 0x10 "INTR2_EN_SET0,INTC INTR2 Interrupt Enable/Set Register 0"
|
|
bitfld.long 0x10 31. " SDVENC_INT_ENA_SET ,SDVENC Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 30. " VOUT0_INT2_ENA_SET ,VOUT0 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 29. " VOUT0_INT1_ENA_SET ,VOUT0 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 28. " VOUT0_INT0_ENA_SET ,VOUT0 VBI Start Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x10 24. " VOUT1_INT2_ENA_SET ,HDMI/VOUT1 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 23. " VOUT1_INT1_ENA_SET ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 22. " VOUT1_INT0_ENA_SET ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 21. " VIN1_PARSER_INT_ENA_SET ,Video Input Port 2 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 20. " VIN0_PARSER_INT_ENA_SET ,Video Input Port 1 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 18. " DEI_FMD_INT_ENA_SET ,DEI (M) Film Mode Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 16. " VPDMA_INT0_DESCRIPTOR_ENA_SET ,VPDMA INT0 Descriptor Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_SET ,VPDMA INT0 List7 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_SET ,VPDMA INT0 List7 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_SET ,VPDMA INT0 List6 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_SET ,VPDMA INT0 List6 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_SET ,VPDMA INT0 List5 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_SET ,VPDMA INT0 List5 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_SET ,VPDMA INT0 List4 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_SET ,VPDMA INT0 List4 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_SET ,VPDMA INT0 List3 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_SET ,VPDMA INT0 List3 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_SET ,VPDMA INT0 List2 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_SET ,VPDMA INT0 List2 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_SET ,VPDMA INT0 List1 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_SET ,VPDMA INT0 List1 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_SET ,VPDMA INT0 List0 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_SET ,VPDMA INT0 List0 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
line.long 0x14 "INTR2_EN_SET1,INTC INTR2 Interrupt Enable/Set Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x14 25. " VIN1_CHR_DS_2_UV_ERROR_INT_ENA_SET ,VIN1 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 24. " VIN1_CHR_DS_1_UV_ERROR_INT_ENA_SET ,VIN1 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 23. " VIN0_CHR_DS_2_UV_ERROR_INT_ENA_SET ,VIN0 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 22. " VIN0_CHR_DS_1_UV_ERROR_INT_ENA_SET ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 21. " NF_CHR_DS_UV_ERROR_INT_ENA_SET ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 20. " COMP_ERROR_INT_ENA_SET ,Compositor Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 19. " GRPX3_ERROR_INT_ENA_SET ,GRPX3 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 18. " GRPX2_ERROR_INT_ENA_SET ,GRPX2 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 17. " GRPX1_ERROR_INT_ENA_SET ,GRPX1 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 16. " DEI_ERROR_INT_ENA_SET ,DEI (M) Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 7. " VPDMA_INT0_CLIENT_ENA_SET ,VPDMA INT0 Client Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_SET ,VPDMA INT0 Channel Group5 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_SET ,VPDMA INT0 Channel Group4 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_SET ,VPDMA INT0 Channel Group3 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_SET ,VPDMA INT0 Channel Group2 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_SET ,VPDMA INT0 Channel Group1 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_SET ,VPDMA INT0 Channel Group0 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
line.long 0x18 "INTR2_EN_CLR0,INTC INTR2 Interrupt Enable/Clear Register 0"
|
|
bitfld.long 0x18 31. " SDVENC_INT_ENA_CLR ,SDVENC Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 30. " VOUT0_INT2_ENA_CLR ,VOUT0 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 29. " VOUT0_INT1_ENA_CLR ,VOUT0 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 28. " VOUT0_INT0_ENA_CLR ,VOUT0 VBI Start Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x18 24. " VOUT1_INT2_ENA_CLR ,HDMI/VOUT1 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 23. " VOUT1_INT1_ENA_CLR ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 22. " VOUT1_INT0_ENA_CLR ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 21. " VIN1_PARSER_INT_ENA_CLR ,Video Input Port 2 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 20. " VIN0_PARSER_INT_ENA_CLR ,Video Input Port 1 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 18. " DEI_FMD_INT_ENA_CLR ,DEI (M) Film Mode Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 16. " VPDMA_INT0_DESCRIPTOR_ENA_CLR ,VPDMA INT0 Descriptor Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_CLR ,VPDMA INT0 List7 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_CLR ,VPDMA INT0 List7 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_CLR ,VPDMA INT0 List6 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_CLR ,VPDMA INT0 List6 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_CLR ,VPDMA INT0 List5 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_CLR ,VPDMA INT0 List5 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_CLR ,VPDMA INT0 List4 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_CLR ,VPDMA INT0 List4 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_CLR ,VPDMA INT0 List3 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_CLR ,VPDMA INT0 List3 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_CLR ,VPDMA INT0 List2 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_CLR ,VPDMA INT0 List2 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_CLR ,VPDMA INT0 List1 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_CLR ,VPDMA INT0 List1 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_CLR ,VPDMA INT0 List0 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_CLR ,VPDMA INT0 List0 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
line.long 0x1c "INTR2_EN_CLR1,INTC INTR2 Interrupt Enable/Clear Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x1c 25. " VIN1_CHR_DS_2_UV_ERROR_INT_ENA_CLR ,VIN1 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 24. " VIN1_CHR_DS_1_UV_ERROR_INT_ENA_CLR ,VIN1 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 23. " VIN0_CHR_DS_2_UV_ERROR_INT_ENA_CLR ,VIN0 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 22. " VIN0_CHR_DS_1_UV_ERROR_INT_ENA_CLR ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 21. " NF_CHR_DS_UV_ERROR_INT_ENA_CLR ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1c 20. " COMP_ERROR_INT_ENA_CLR ,Compositor Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 19. " GRPX3_ERROR_INT_ENA_CLR ,GRPX3 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 18. " GRPX2_ERROR_INT_ENA_CLR ,GRPX2 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 17. " GRPX1_ERROR_INT_ENA_CLR ,GRPX1 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 16. " DEI_ERROR_INT_ENA_CLR ,DEI (M) Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 7. " VPDMA_INT0_CLIENT_ENA_CLR ,VPDMA INT0 Client Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR ,VPDMA INT0 Channel Group5 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR ,VPDMA INT0 Channel Group4 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR ,VPDMA INT0 Channel Group3 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR ,VPDMA INT0 Channel Group2 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR ,VPDMA INT0 Channel Group1 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR ,VPDMA INT0 Channel Group0 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
tree.end
|
|
tree "INTR3"
|
|
group.long 0x80++0x1f
|
|
line.long 0x00 "INTR3_RAW0,INTC INTR3 Interrupt Status Raw/Set Register 0"
|
|
bitfld.long 0x00 31. " SDVENC_INT_RAW ,SDVENC Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 30. " VOUT0_INT2_RAW ,VOUT0 Frame Start Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 29. " VOUT0_INT1_RAW ,VOUT0 VBI End Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 28. " VOUT0_INT0_RAW ,VOUT0 VBI Start Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x00 24. " VOUT1_INT2_RAW ,HDMI/VOUT1 Frame Start Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 23. " VOUT1_INT1_RAW ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VOUT1_INT0_RAW ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 21. " VIN1_PARSER_INT_RAW ,Video Input Port 2 Parser Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " VIN0_PARSER_INT_RAW ,Video Input Port 1 Parser Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " DEI_FMD_INT_RAW ,DEI (M) Film Mode Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VPDMA_INT0_DESCRIPTOR_RAW ,VPDMA INT0 Descriptor Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 15. " VPDMA_INT0_LIST7_NOTIFY_RAW ,VPDMA INT0 List7 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 14. " VPDMA_INT0_LIST7_COMPLETE_RAW ,VPDMA INT0 List7 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 13. " VPDMA_INT0_LIST6_NOTIFY_RAW ,VPDMA INT0 List6 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " VPDMA_INT0_LIST6_COMPLETE_RAW ,VPDMA INT0 List6 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 11. " VPDMA_INT0_LIST5_NOTIFY_RAW ,VPDMA INT0 List5 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VPDMA_INT0_LIST5_COMPLETE_RAW ,VPDMA INT0 List5 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 9. " VPDMA_INT0_LIST4_NOTIFY_RAW ,VPDMA INT0 List4 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VPDMA_INT0_LIST4_COMPLETE_RAW ,VPDMA INT0 List4 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 7. " VPDMA_INT0_LIST3_NOTIFY_RAW ,VPDMA INT0 List3 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VPDMA_INT0_LIST3_COMPLETE_RAW ,VPDMA INT0 List3 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 5. " VPDMA_INT0_LIST2_NOTIFY_RAW ,VPDMA INT0 List2 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VPDMA_INT0_LIST2_COMPLETE_RAW ,VPDMA INT0 List2 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 3. " VPDMA_INT0_LIST1_NOTIFY_RAW ,VPDMA INT0 List1 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VPDMA_INT0_LIST1_COMPLETE_RAW ,VPDMA INT0 List1 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x00 1. " VPDMA_INT0_LIST0_NOTIFY_RAW ,VPDMA INT0 List0 Notify Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VPDMA_INT0_LIST0_COMPLETE_RAW ,VPDMA INT0 List0 Complete Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
line.long 0x04 "INTR3_RAW1,INTC INTR3 Interrupt Status Raw/Set Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x04 25. " VIN1_CHR_DS_2_UV_ERROR_INT_RAW ,VIN1 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 24. " VIN1_CHR_DS_1_UV_ERROR_INT_RAW ,VIN1 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 23. " VIN0_CHR_DS_2_UV_ERROR_INT_RAW ,VIN0 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 22. " VIN0_CHR_DS_1_UV_ERROR_INT_RAW ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 21. " NF_CHR_DS_UV_ERROR_INT_RAW ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 20. " COMP_ERROR_INT_RAW ,Compositor Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 19. " GRPX3_ERROR_INT_RAW ,GRPX3 Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 18. " GRPX2_ERROR_INT_RAW ,GRPX2 Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GRPX1_ERROR_INT_RAW ,GRPX1 Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 16. " DEI_ERROR_INT_RAW ,DEI (M) Error Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " VPDMA_INT0_CLIENT_RAW ,VPDMA INT0 Client Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 5. " VPDMA_INT0_CHANNEL_GROUP5_RAW ,VPDMA INT0 Channel Group5 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 4. " VPDMA_INT0_CHANNEL_GROUP4_RAW ,VPDMA INT0 Channel Group4 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 3. " VPDMA_INT0_CHANNEL_GROUP3_RAW ,VPDMA INT0 Channel Group3 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VPDMA_INT0_CHANNEL_GROUP2_RAW ,VPDMA INT0 Channel Group2 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
bitfld.long 0x04 1. " VPDMA_INT0_CHANNEL_GROUP1_RAW ,VPDMA INT0 Channel Group1 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VPDMA_INT0_CHANNEL_GROUP0_RAW ,VPDMA INT0 Channel Group0 Interrupt Status (R/W)" "No interrupt/No effect,Interrupt/Set"
|
|
line.long 0x08 "INTR3_STAT_EN_CLR0,INTC INTR3 Interrupt Status Enabled/Clear Register 0"
|
|
bitfld.long 0x08 31. " SDVENC_INT_ENA ,SDVENC Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 30. " VOUT0_INT2_ENA ,VOUT0 Frame Start Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 29. " VOUT0_INT1_ENA ,VOUT0 VBI End Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 28. " VOUT0_INT0_ENA ,VOUT0 VBI Start Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x08 24. " VOUT1_INT2_ENA ,HDMI/VOUT1 Frame Start Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 23. " VOUT1_INT1_ENA ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 22. " VOUT1_INT0_ENA ,HDMI/VOUT1 VBI End Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 21. " VIN1_PARSER_INT_ENA ,Video Input Port 2 Parser Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 20. " VIN0_PARSER_INT_ENA ,Video Input Port 1 Parser Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 18. " DEI_FMD_INT_ENA ,DEI (M) Film Mode Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 16. " VPDMA_INT0_DESCRIPTOR_ENA ,VPDMA INT0 Descriptor Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 15. " VPDMA_INT0_LIST7_NOTIFY_ENA ,VPDMA INT0 List7 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 14. " VPDMA_INT0_LIST7_COMPLETE_ENA ,VPDMA INT0 List7 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 13. " VPDMA_INT0_LIST6_NOTIFY_ENA ,VPDMA INT0 List6 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 12. " VPDMA_INT0_LIST6_COMPLETE_ENA ,VPDMA INT0 List6 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 11. " VPDMA_INT0_LIST5_NOTIFY_ENA ,VPDMA INT0 List5 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 10. " VPDMA_INT0_LIST5_COMPLETE_ENA ,VPDMA INT0 List5 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 9. " VPDMA_INT0_LIST4_NOTIFY_ENA ,VPDMA INT0 List4 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 8. " VPDMA_INT0_LIST4_COMPLETE_ENA ,VPDMA INT0 List4 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 7. " VPDMA_INT0_LIST3_NOTIFY_ENA ,VPDMA INT0 List3 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 6. " VPDMA_INT0_LIST3_COMPLETE_ENA ,VPDMA INT0 List3 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 5. " VPDMA_INT0_LIST2_NOTIFY_ENA ,VPDMA INT0 List2 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 4. " VPDMA_INT0_LIST2_COMPLETE_ENA ,VPDMA INT0 List2 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 3. " VPDMA_INT0_LIST1_NOTIFY_ENA ,VPDMA INT0 List1 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VPDMA_INT0_LIST1_COMPLETE_ENA ,VPDMA INT0 List1 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x08 1. " VPDMA_INT0_LIST0_NOTIFY_ENA ,VPDMA INT0 List0 Notify Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 0. " VPDMA_INT0_LIST0_COMPLETE_ENA ,VPDMA INT0 List0 Complete Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
line.long 0x0c "INTR3_STAT_EN_CLR1,INTC INTR3 Interrupt Status Enabled/Clear Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x0c 25. " VIN1_CHR_DS_2_UV_ERROR_INT_ENA ,VIN1 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 24. " VIN1_CHR_DS_1_UV_ERROR_INT_ENA ,VIN1 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " VIN0_CHR_DS_2_UV_ERROR_INT_ENA ,VIN0 Chroma Downsampler 2 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 22. " VIN0_CHR_DS_1_UV_ERROR_INT_ENA ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " NF_CHR_DS_UV_ERROR_INT_ENA ,VIN0 Chroma Downsampler 1 UV Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 20. " COMP_ERROR_INT_ENA ,Compositor Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " GRPX3_ERROR_INT_ENA ,GRPX3 Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 18. " GRPX2_ERROR_INT_ENA ,GRPX2 Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " GRPX1_ERROR_INT_ENA ,GRPX1 Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 16. " DEI_ERROR_INT_ENA ,DEI (M) Error Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " VPDMA_INT0_CLIENT_ENA ,VPDMA INT0 Client Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA ,VPDMA INT0 Channel Group5 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA ,VPDMA INT0 Channel Group4 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA ,VPDMA INT0 Channel Group3 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA ,VPDMA INT0 Channel Group2 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x0c 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA ,VPDMA INT0 Channel Group1 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA ,VPDMA INT0 Channel Group0 Interrupt Status (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
line.long 0x10 "INTR3_EN_SET0,INTC INTR3 Interrupt Enable/Set Register 0"
|
|
bitfld.long 0x10 31. " SDVENC_INT_ENA_SET ,SDVENC Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 30. " VOUT0_INT2_ENA_SET ,VOUT0 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 29. " VOUT0_INT1_ENA_SET ,VOUT0 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 28. " VOUT0_INT0_ENA_SET ,VOUT0 VBI Start Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x10 24. " VOUT1_INT2_ENA_SET ,HDMI/VOUT1 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 23. " VOUT1_INT1_ENA_SET ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 22. " VOUT1_INT0_ENA_SET ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 21. " VIN1_PARSER_INT_ENA_SET ,Video Input Port 2 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 20. " VIN0_PARSER_INT_ENA_SET ,Video Input Port 1 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 18. " DEI_FMD_INT_ENA_SET ,DEI (M) Film Mode Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 16. " VPDMA_INT0_DESCRIPTOR_ENA_SET ,VPDMA INT0 Descriptor Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_SET ,VPDMA INT0 List7 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_SET ,VPDMA INT0 List7 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_SET ,VPDMA INT0 List6 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_SET ,VPDMA INT0 List6 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_SET ,VPDMA INT0 List5 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_SET ,VPDMA INT0 List5 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_SET ,VPDMA INT0 List4 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_SET ,VPDMA INT0 List4 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_SET ,VPDMA INT0 List3 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_SET ,VPDMA INT0 List3 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_SET ,VPDMA INT0 List2 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_SET ,VPDMA INT0 List2 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_SET ,VPDMA INT0 List1 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_SET ,VPDMA INT0 List1 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x10 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_SET ,VPDMA INT0 List0 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x10 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_SET ,VPDMA INT0 List0 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
line.long 0x14 "INTR3_EN_SET1,INTC INTR3 Interrupt Enable/Set Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x14 25. " VIN1_CHR_DS_2_UV_ERROR_INT_ENA_SET ,VIN1 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 24. " VIN1_CHR_DS_1_UV_ERROR_INT_ENA_SET ,VIN1 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 23. " VIN0_CHR_DS_2_UV_ERROR_INT_ENA_SET ,VIN0 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 22. " VIN0_CHR_DS_1_UV_ERROR_INT_ENA_SET ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 21. " NF_CHR_DS_UV_ERROR_INT_ENA_SET ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 20. " COMP_ERROR_INT_ENA_SET ,Compositor Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 19. " GRPX3_ERROR_INT_ENA_SET ,GRPX3 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 18. " GRPX2_ERROR_INT_ENA_SET ,GRPX2 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 17. " GRPX1_ERROR_INT_ENA_SET ,GRPX1 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 16. " DEI_ERROR_INT_ENA_SET ,DEI (M) Error Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 7. " VPDMA_INT0_CLIENT_ENA_SET ,VPDMA INT0 Client Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_SET ,VPDMA INT0 Channel Group5 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_SET ,VPDMA INT0 Channel Group4 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_SET ,VPDMA INT0 Channel Group3 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_SET ,VPDMA INT0 Channel Group2 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x14 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_SET ,VPDMA INT0 Channel Group1 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
textline " "
|
|
bitfld.long 0x14 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_SET ,VPDMA INT0 Channel Group0 Interrupt (R/W)" "Disabled/No effect,Enabled/Set"
|
|
line.long 0x18 "INTR3_EN_CLR0,INTC INTR3 Interrupt Enable/Clear Register 0"
|
|
bitfld.long 0x18 31. " SDVENC_INT_ENA_CLR ,SDVENC Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 30. " VOUT0_INT2_ENA_CLR ,VOUT0 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 29. " VOUT0_INT1_ENA_CLR ,VOUT0 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 28. " VOUT0_INT0_ENA_CLR ,VOUT0 VBI Start Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x18 24. " VOUT1_INT2_ENA_CLR ,HDMI/VOUT1 Frame Start Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 23. " VOUT1_INT1_ENA_CLR ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 22. " VOUT1_INT0_ENA_CLR ,HDMI/VOUT1 VBI End Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 21. " VIN1_PARSER_INT_ENA_CLR ,Video Input Port 2 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 20. " VIN0_PARSER_INT_ENA_CLR ,Video Input Port 1 Parser Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 18. " DEI_FMD_INT_ENA_CLR ,DEI (M) Film Mode Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 16. " VPDMA_INT0_DESCRIPTOR_ENA_CLR ,VPDMA INT0 Descriptor Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_CLR ,VPDMA INT0 List7 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_CLR ,VPDMA INT0 List7 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_CLR ,VPDMA INT0 List6 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_CLR ,VPDMA INT0 List6 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_CLR ,VPDMA INT0 List5 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_CLR ,VPDMA INT0 List5 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_CLR ,VPDMA INT0 List4 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_CLR ,VPDMA INT0 List4 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_CLR ,VPDMA INT0 List3 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_CLR ,VPDMA INT0 List3 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_CLR ,VPDMA INT0 List2 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_CLR ,VPDMA INT0 List2 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_CLR ,VPDMA INT0 List1 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_CLR ,VPDMA INT0 List1 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x18 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_CLR ,VPDMA INT0 List0 Notify Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x18 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_CLR ,VPDMA INT0 List0 Complete Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
line.long 0x1c "INTR3_EN_CLR1,INTC INTR3 Interrupt Enable/Clear Register 1"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x1c 25. " VIN1_CHR_DS_2_UV_ERROR_INT_ENA_CLR ,VIN1 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 24. " VIN1_CHR_DS_1_UV_ERROR_INT_ENA_CLR ,VIN1 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 23. " VIN0_CHR_DS_2_UV_ERROR_INT_ENA_CLR ,VIN0 Chroma Downsampler 2 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 22. " VIN0_CHR_DS_1_UV_ERROR_INT_ENA_CLR ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 21. " NF_CHR_DS_UV_ERROR_INT_ENA_CLR ,VIN0 Chroma Downsampler 1 UV Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1c 20. " COMP_ERROR_INT_ENA_CLR ,Compositor Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 19. " GRPX3_ERROR_INT_ENA_CLR ,GRPX3 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 18. " GRPX2_ERROR_INT_ENA_CLR ,GRPX2 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 17. " GRPX1_ERROR_INT_ENA_CLR ,GRPX1 Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 16. " DEI_ERROR_INT_ENA_CLR ,DEI (M) Error Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 7. " VPDMA_INT0_CLIENT_ENA_CLR ,VPDMA INT0 Client Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR ,VPDMA INT0 Channel Group5 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR ,VPDMA INT0 Channel Group4 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR ,VPDMA INT0 Channel Group3 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR ,VPDMA INT0 Channel Group2 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
bitfld.long 0x1c 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR ,VPDMA INT0 Channel Group1 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
textline " "
|
|
bitfld.long 0x1c 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR ,VPDMA INT0 Channel Group0 Interrupt (R/W)" "Disabled/No effect,Enabled/Clear"
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
tree "CLKC"
|
|
base ad:0x48100100
|
|
width 19.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "CLK_EN,CLKC Module Clock Enable Register"
|
|
bitfld.long 0x00 24. " NF_DP_EN ,Noise Filter Data Path Clock Enable" "Disabled,Enabled"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x00 17. " VIN1_DP_EN ,Video Input Port 2 Data Path Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " VIN0_DP_EN ,Video Input Port 1 Data Path Clock Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " SDVENC_EN ,SD VENC Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VOUT0_EN ,VOUT0 VENC Clock Enable" "Disabled,Enabled"
|
|
sif (cpu()!="C6A8143")
|
|
textline " "
|
|
bitfld.long 0x00 9. " HDMI_VOUT1_EN ,HDMI/VOUT1 VENC Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IND_TRANS2_DP_EN ,Independent Transcode 2 (to VIN1) Data Path Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " IND_TRANS1_DP_EN ,Independent Transcode 1 (to VIN0) Data Path Clock Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " COMP_DP_EN ,Compositor Data Path Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GRPX3_DP_EN ,Graphics 3 Data Path Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " GRPX2_DP_EN ,Graphics 2 Data Path Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GRPX1_DP_EN ,Graphics 1 Data Path Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AUX_DP_EN ,Auxiliary Video Data Path Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PRIM_DP_EN ,Primary Video Data Path Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VPDMA_EN ,VPDMA Clock Enable" "Disabled,Enabled"
|
|
line.long 0x04 "RESET,CLKC Module Reset Register"
|
|
bitfld.long 0x04 31. " MAIN_RST ,Reset for all modules in HDVPSS Main Data Path" "No reset,Reset"
|
|
bitfld.long 0x04 24. " NF_DP_RST ,Noise Filter Data Path Reset" "No reset,Reset"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x04 17. " VIN1_DP_RST ,Video Input Port 2 Data Path Reset" "No reset,Reset"
|
|
bitfld.long 0x04 16. " VIN0_DP_RST ,Video Input Port 1 Data Path Reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 12. " SDVENC_RST ,SD VENC Reset" "No reset,Reset"
|
|
bitfld.long 0x04 11. " VOUT0_RST ,VOUT0 VENC Reset" "No reset,Reset"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x04 9. " HDMI_VOUT1_RST ,HDMI/VOUT1 VENC Reset" "No reset,Reset"
|
|
bitfld.long 0x04 8. " IND_TRANS2_DP_RST ,Independent Transcode 2 (to VIN1) Data Path Reset" "No reset,Reset"
|
|
bitfld.long 0x04 7. " IND_TRANS1_DP_RST ,Independent Transcode 1 (to VIN0) Data Path Reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " COMP_DP_RST ,Compositor Data Path Reset" "No reset,Reset"
|
|
bitfld.long 0x04 5. " GRPX3_DP_RST ,Graphics 3 Data Path Reset" "No reset,Reset"
|
|
bitfld.long 0x04 4. " GRPX2_DP_RST ,Graphics 2 Data Path Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 3. " GRPX1_DP_RST ,Graphics 1 Data Path Reset" "No reset,Reset"
|
|
bitfld.long 0x04 2. " AUX_DP_RST ,Auxiliary Video Data Path Reset" "No reset,Reset"
|
|
bitfld.long 0x04 1. " PRIM_DP_RST ,Primary Video Data Path Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VPDMA_RST ,VPDMA Reset" "No reset,Reset"
|
|
width 19.
|
|
line.long 0x08 "DATAPATH,CLKC Main Data Path Select Register"
|
|
bitfld.long 0x08 28.--31. " MAIN_DATAPATH_SELECT ,Main Datapath Register Field Enable" "All fields,VCOMP_PIP_SELECT,VCOMP_MAIN_DISABLE,HDCOMP_VOUT0_SELECT,SDVENC_SELECT,SC_WRBK_SELECT,IND_TRANS1_SELECT,IND_TRANS2_SELECT,Reserved,Reserved,NF_BYPASS_SELECT,?..."
|
|
bitfld.long 0x08 17. " NF_BYPASS_SELECT ,Noise Filter Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x08 14. " IND_TRANS2_SELECT ,Independent Transcode 2 Path Select" "DEI_H,Independent"
|
|
bitfld.long 0x08 13. " IND_TRANS1_SELECT ,Independent Transcode 1 Path Select" "DEI,Independent"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 9.--11. " SC_WRBK_SELECT ,SC_WRBK Path Select" "Disabled,HDMI (COMP),Reserved,VCOMP,Auxiliary Memory (VPDMA),Primary Memory (VPDMA),Independent Transcode Path1,?..."
|
|
bitfld.long 0x08 6.--8. " SDVENC_SELECT ,SD VENC Path Select" "Disabled,Auxiliary (SC),Auxiliary Memory (VPDMA),Primary Memory (VPDMA),Independent Transcode,?..."
|
|
textline " "
|
|
bitfld.long 0x08 3.--5. " HDCOMP_VOUT0_SELECT ,HDCOMP/VOUT0 Path Input Select" "Disabled,Auxiliary (SC),Auxiliary Memory (VPDMA),Primary Memory (VPDMA),?..."
|
|
bitfld.long 0x08 2. " VCOMP_MAIN_DISABLE ,VCOMP Main Input Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " VCOMP_PIP_SELECT ,VCOMP PIP Input Select" "Disabled,Auxiliary (SC),Auxiliary Memory (VPDMA),Primary Memory (VPDMA)"
|
|
sif (cpu()!="C6A8143")
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "VINP1_DATAPATH,CLKC Video Input Port 1 Data Path Select Register"
|
|
bitfld.long 0x00 28.--31. " VIN0_DATAPATH_SELECT ,VIN0 Datapath Register Field Enable" "All fields,VIN0_CSC_SRC_SELECT,VIN0_SC_SRC_SELECT,VIN0_RGB_SRC_SELECT,VIN0_RGB_OUT_LO_SELECT,VIN0_RGB_OUT_HI_SELECT,VIN0_CHR_DS_1_SRC_SELECT,VIN0_CHR_DS_2_SRC_SELECT,VIN0_MULTI_CHANNEL_SELECT,VIN0_CHR_DS_1_BYPASS,VIN0_CHR_DS_2_BYPASS,?..."
|
|
bitfld.long 0x00 17. " VIN0_CHR_DS_2_BYPASS ,Video Input Port 1 Chroma Downsampler 2 Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VIN0_CHR_DS_1_BYPASS ,Video Input Port 1 Chroma Downsampler 1 Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 15. " VIN0_MULTI_CHANNEL_SELECT ,Video Input Port 1 Multi Channel Select" "Single,Multi"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " VIN0_CHR_DS_2_SRC_SELECT ,Video Input Port 1 Chroma Downsampler 2 Source Select" "Disabled,Scaler,Color Space Converter,VIN_PARSER A,VIN_PARSER B,Transcode (422),?..."
|
|
bitfld.long 0x00 9.--11. " VIN0_CHR_DS_1_SRC_SELECT ,Video Input Port 1 Chroma Downsampler 1 Source Select" "Disabled,Scaler,Color Space Converter,VIN_PARSER A,VIN_PARSER B,Transcode (422),?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " VIN0_RGB_OUT_HI_SELECT ,Video Input Port 1 HI RGB Output Select" "420/422,RGB"
|
|
bitfld.long 0x00 7. " VIN0_RGB_OUT_LO_SELECT ,Video Input Port 1 LO RGB Output Select" "420/422,RGB"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VIN0_RGB_SRC_SELECT ,Video Input Port 1 RGB Output Path Select" "Compositor RGB,CSC"
|
|
bitfld.long 0x00 3.--5. " VIN0_SC_SRC_SELECT ,Video Input Port 1 SC Source Select" "Disabled,Color Space Converter,VIN_PARSER A,VIN_PARSER B,Transcode (422),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " VIN0_CSC_SRC_SELECT ,Video Input Port 1 CSC Source Select" "Disabled,VIN_PARSER A (422),VIN_PARSER B,Transcode (422),VIN_PARSER A (RGB),Compositor (RGB),?..."
|
|
line.long 0x04 "VINP2_DATAPATH,CLKC Video Input Port 2 Data Path Select Register"
|
|
bitfld.long 0x04 28.--31. " VIN1_DATAPATH_SELECT ,VIN1 Datapath Register Field Enable" "All fields,VIN1_CSC_SRC_SELECT,VIN1_SC_SRC_SELECT,VIN1_RGB_SRC_SELECT,VIN1_RGB_OUT_LO_SELECT,VIN1_RGB_OUT_HI_SELECT,VIN1_CHR_DS_1_SRC_SELECT,VIN1_CHR_DS_2_SRC_SELECT,VIN1_MULTI_CHANNEL_SELECT,VIN1_CHR_DS_1_BYPASS,VIN1_CHR_DS_2_BYPASS,?..."
|
|
bitfld.long 0x04 17. " VIN1_CHR_DS_2_BYPASS ,Video Input Port 2 Chroma Downsampler 2 Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x04 16. " VIN1_CHR_DS_1_BYPASS ,Video Input Port 2 Chroma Downsampler 1 Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x04 15. " VIN1_MULTI_CHANNEL_SELECT ,Video Input Port 2 Multi Channel Select" "Single,Multi"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " VIN1_CHR_DS_2_SRC_SELECT ,Video Input Port 2 Chroma Downsampler 2 Source Select" "Disabled,Scaler,Color Space Converter,VIN_PARSER A,VIN_PARSER B,Transcode (422),?..."
|
|
bitfld.long 0x04 9.--11. " VIN1_CHR_DS_1_SRC_SELECT ,Video Input Port 2 Chroma Downsampler 1 Source Select" "Disabled,Scaler,Color Space Converter,VIN_PARSER A,VIN_PARSER B,Transcode (422),?..."
|
|
textline " "
|
|
bitfld.long 0x04 8. " VIN1_RGB_OUT_HI_SELECT ,Video Input Port 2 HI RGB Output Select" "420/422,RGB"
|
|
bitfld.long 0x04 7. " VIN1_RGB_OUT_LO_SELECT ,Video Input Port 2 LO RGB Output Select" "420/422,RGB"
|
|
textline " "
|
|
bitfld.long 0x04 6. " VIN1_RGB_SRC_SELECT ,Video Input Port 2 RGB Output Path Select" "Compositor RGB,CSC"
|
|
bitfld.long 0x04 3.--5. " VIN1_SC_SRC_SELECT ,Video Input Port 2 SC Source Select" "Disabled,Color Space Converter,VIN_PARSER A,VIN_PARSER B,Transcode (422),?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " VIN1_CSC_SRC_SELECT ,Video Input Port 2 CSC Source Select" "Disabled,VIN_PARSER A (422),VIN_PARSER B,Transcode (422),VIN_PARSER A (RGB),Compositor (RGB),?..."
|
|
endif
|
|
width 19.
|
|
group.long 0x14++0x0F
|
|
line.long 0x00 "VENC_CLKSEL,CLKC Video Encoder Clock Select"
|
|
bitfld.long 0x00 19. " VOUT0_CLK_ON ,Digital Video Output 2 output clock on" "OFF,ON"
|
|
bitfld.long 0x00 18. " VOUT0_CLK_SELECT ,Digital Video Output 2 output clock" "Hd_venc_g_clk,Hd_venc_g_clk/2"
|
|
bitfld.long 0x00 16. " HD_VENC_G_CLK1X_SELECT ,HD_VENC_G (VOUT0) clk1x source clock" "Hd_venc_g_clk/2,Hd_venc_g_clk"
|
|
sif (cpu()!="C6A8143")
|
|
textline " "
|
|
bitfld.long 0x00 3. " HDMI_CLK_ON ,HDMI output clock on" "OFF,ON"
|
|
bitfld.long 0x00 2. " VOUT1_CLK_ON ,Digital Video Output 1 output clock on" "OFF,ON"
|
|
bitfld.long 0x00 1. " VOUT1_CLK_SELECT ,Digital Video Output 1 output clock" "Hd_venc_d_clk,Hd_venc_d_clk/2"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HD_VENC_D_CLK1X_SELECT ,HD_VENC_D_VOUT1 clk1x source clock" "Hd_venc_d_clk/2,Hd_venc_d_clk"
|
|
endif
|
|
line.long 0x04 "VENC_EN,CLKC Video Encoder Enable"
|
|
bitfld.long 0x04 3. " SDVENC_ENABLE ,SD VENC Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " VOUT0_ENABLE ,Digital Video Output 2 VENC Enable" "Disabled,Enabled"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x04 0. " HDMI_VOUT1_ENABLE ,HDMI/Digital Video Output 1 VENC Enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x08 "VC1_RANGE,CLKC VC-1 Range Map/Range Reduction Register"
|
|
bitfld.long 0x08 31. " RANGE_REDUCTION_IND2_ON ,Range Reduction ON for IND2 transcode input" "OFF,ON"
|
|
bitfld.long 0x08 30. " RANGE_REDUCTION_IND1_ON ,Range Reduction ON for IND1 transcode input" "OFF,ON"
|
|
bitfld.long 0x08 29. " RANGE_REDUCTION_AUX_ON ,Range Reduction ON for Auxiliary input" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x08 28. " RANGE_REDUCTION_PRIM_ON ,Range Reduction ON for Primary input" "OFF,ON"
|
|
bitfld.long 0x08 27. " RANGE_MAP_IND2_ON ,Range Mapping ON for IND2 transcode input" "OFF,ON"
|
|
bitfld.long 0x08 24.--26. " RANGE_MAPUV_IND2 ,Range Map UV for IND2 transcode input" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 21.--23. " RANGE_MAPY_IND2 ,Range Map Y for IND2 transcode input" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 20. " RANGE_MAP_IND1_ON ,Range Mapping ON for IND1 transcode input" "OFF,ON"
|
|
bitfld.long 0x08 17.--19. " RANGE_MAPUV_IND1 ,Range Map UV for IND1 transcode input" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 14.--16. " RANGE_MAPY_IND1 ,Range Map Y for IND1 transcode input" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 13. " RANGE_MAP_AUX_ON ,Range Mapping ON for Auxiliary input" "OFF,ON"
|
|
bitfld.long 0x08 10.--12. " RANGE_MAPUV_AUX ,Range Map UV for Auxiliary input" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 7.--9. " RANGE_MAPY_AUX ,Range Map Y for Auxiliary input" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 6. " RANGE_MAP_PRIM_ON ,Range Mapping ON for Primary input" "OFF,ON"
|
|
bitfld.long 0x08 3.--5. " RANGE_MAPUV_PRIM ,Range Map UV for Primary input" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " RANGE_MAPY_PRIM ,Range Map Y for Primary input" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "VENC_UNDERFLOW_ST,CLKC Video Encoder Underflow Status Register"
|
|
eventfld.long 0x0C 3. " SD_UNDERFLOW_STAT ,Underflow on SD output" "No underflow,Underflow"
|
|
eventfld.long 0x0C 2. " VOUT0_UNDERFLOW_STAT ,Underflow on VOUT0 output" "No underflow,Underflow"
|
|
sif (cpu()!="C6A8143")
|
|
eventfld.long 0x0C 0. " HDMI_UNDERFLOW_STAT ,Underflow on HDMI/VOUT1 output" "No underflow,Underflow"
|
|
endif
|
|
width 11.
|
|
tree.end
|
|
tree "DFT_CONTROL"
|
|
base ad:0x48100200
|
|
width 20.
|
|
sif (cpu()!="C6A8143")
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "VOUT1_INCTRL,DFT_CONTROL VOUT1 Input Control (External Loopback) Register"
|
|
bitfld.long 0x00 2. " VOUT1_OE_N ,VOUT1 Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " VOUT1_MISR_CONTROL ,VOUT1 MISR Control" "Hold content,Load with seed,Run 1 frame,Continuous run"
|
|
line.long 0x04 "VOUT1_INMISR_SEED,DFT_CONTROL VOUT1 Input MISR Seed (External Loopback) Register"
|
|
line.long 0x08 "VOUT1_INMISR_SIGN,DFT_CONTROL VOUT1 Input MISR Signature (External Loopback) Register"
|
|
endif
|
|
group.long 0x0C++0xB
|
|
line.long 0x00 "VOUT0_INCTRL,DFT_CONTROL VOUT0 Input Control (External Loopback) Register"
|
|
bitfld.long 0x00 2. " VOUT0_OE_N ,VOUT0 Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " VOUT0_MISR_CONTROL ,VOUT0 MISR Control" "Hold content,Load with seed,Run 1 frame,Continuous run"
|
|
line.long 0x04 "VOUT0_INMISR_SEED,DFT_CONTROL VOUT0 Input MISR Seed (External Loopback) Register"
|
|
line.long 0x08 "VOUT0_INMISR_SIGN,DFT_CONTROL VOUT0 Input MISR Signature (External Loopback) Register"
|
|
sif (cpu()!="C6A8143")
|
|
group.long 0x18++0xB
|
|
line.long 0x00 "VOUT1_OUTCTRL,DFT_CONTROL VOUT1 Output Control (Internal Loopback) Register"
|
|
bitfld.long 0x00 0.--1. " VOUT1_MISR_CONTROL ,VOUT1 MISR Control" "Hold content,Load with seed,Run 1 frame,Continuous run"
|
|
line.long 0x04 "VOUT1_OUTMISR_SEED,DFT_CONTROL VOUT1 Output MISR Seed (Internal Loopback) Register"
|
|
line.long 0x08 "VOUT1_OUTMISR_SIGN,DFT_CONTROL VOUT1 Output MISR Signature (Internal Loopback) Register"
|
|
endif
|
|
group.long 0x24++0xB
|
|
line.long 0x00 "VOUT0_OUTCTRL,DFT_CONTROL VOUT0 Output Control (Internal Loopback) Register"
|
|
bitfld.long 0x00 0.--1. " VOUT0_MISR_CONTROL ,VOUT0 MISR Control" "Hold content,Load with seed,Run 1 frame,Continuous run"
|
|
line.long 0x04 "VOUT0_OUTMISR_SEED,DFT_CONTROL VOUT0 Output MISR Seed (Internal Loopback) Register"
|
|
line.long 0x08 "VOUT0_OUTMISR_SIGN,DFT_CONTROL VOUT0 Output MISR Signature (Internal Loopback) Register"
|
|
group.long 0x3c++0xb
|
|
line.long 0x00 "SDDAC_MISR_CTRL,DFT_CONTROL SDDAC MISR Control Register"
|
|
bitfld.long 0x00 0.--1. " SDDAC_MISR_CONTROL ,SDDAC MISR Control" "Hold content,Load with seed,Run 1 frame,Continuous run"
|
|
line.long 0x04 "SDDAC_MISR_SEED,DFT_CONTROL SDDAC MISR Seed Register"
|
|
line.long 0x08 "SDDAC_MISR_SIGN,DFT_CONTROL SDDAC MISR Signature Register"
|
|
width 11.
|
|
tree.end
|
|
tree "CHR_US_P1"
|
|
base ad:0x48100300
|
|
width 6.
|
|
group.long 0x04++0x1f
|
|
line.long 0x00 "REG0,CHR_US_P1 REG0 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " ANCHOR_FID0_C0 ,C0 coefficient for Anchor Pixel"
|
|
bitfld.long 0x00 16.--17. " CFG_MODE ,Configuration Mode" "Mode A,Mode B,Mode C,Mode D"
|
|
hexmask.long.word 0x00 2.--15. 1. " ANCHOR_FID0_C1 ,C1 coefficient for Anchor Pixel"
|
|
line.long 0x04 "REG1,CHR_US_P1 REG1 Register"
|
|
hexmask.long.word 0x04 18.--31. 1. " ANCHOR_FID0_C2 ,C2 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x04 2.--15. 1. " ANCHOR_FID0_C3 ,C3 coefficient for Anchor Pixel"
|
|
line.long 0x08 "REG2,CHR_US_P1 REG2 Register"
|
|
hexmask.long.word 0x08 18.--31. 1. " INTERP_FID0_C0 ,C0 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x08 2.--15. 1. " INTERP_FID0_C1 ,C1 coefficient for Interpolated Pixel"
|
|
line.long 0x0c "REG3,CHR_US_P1 REG3 Register"
|
|
hexmask.long.word 0x0c 18.--31. 1. " INTERP_FID0_C2 ,C2 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x0c 2.--15. 1. " INTERP_FID0_C3 ,C3 coefficient for Interpolated Pixel"
|
|
line.long 0x10 "REG4,CHR_US_P1 REG4 Register"
|
|
hexmask.long.word 0x10 18.--31. 1. " ANCHOR_FID1_C0 ,C0 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x10 2.--15. 1. " ANCHOR_FID1_C1 ,C1 coefficient for Anchor Pixel"
|
|
line.long 0x14 "REG5,CHR_US_P1 REG5 Register"
|
|
hexmask.long.word 0x14 18.--31. 1. " ANCHOR_FID1_C2 ,C2 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x14 2.--15. 1. " ANCHOR_FID1_C3 ,C3 coefficient for Anchor Pixel"
|
|
line.long 0x18 "REG6,CHR_US_P1 REG6 Register"
|
|
hexmask.long.word 0x18 18.--31. 1. " INTERP_FID1_C0 ,C0 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x18 2.--15. 1. " INTERP_FID1_C1 ,C1 coefficient for Interpolated Pixel"
|
|
line.long 0x1c "REG7,CHR_US_P1 REG7 Register"
|
|
hexmask.long.word 0x1c 18.--31. 1. " INTERP_FID1_C2 ,C2 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x1c 2.--15. 1. " INTERP_FID1_C3 ,C3 coefficient for Interpolated Pixel"
|
|
width 11.
|
|
tree.end
|
|
tree "CHR_US_P2"
|
|
base ad:0x48100400
|
|
width 6.
|
|
group.long 0x04++0x1f
|
|
line.long 0x00 "REG0,CHR_US_P2 REG0 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " ANCHOR_FID0_C0 ,C0 coefficient for Anchor Pixel"
|
|
bitfld.long 0x00 16.--17. " CFG_MODE ,Configuration Mode" "Mode A,Mode B,Mode C,Mode D"
|
|
hexmask.long.word 0x00 2.--15. 1. " ANCHOR_FID0_C1 ,C1 coefficient for Anchor Pixel"
|
|
line.long 0x04 "REG1,CHR_US_P2 REG1 Register"
|
|
hexmask.long.word 0x04 18.--31. 1. " ANCHOR_FID0_C2 ,C2 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x04 2.--15. 1. " ANCHOR_FID0_C3 ,C3 coefficient for Anchor Pixel"
|
|
line.long 0x08 "REG2,CHR_US_P2 REG2 Register"
|
|
hexmask.long.word 0x08 18.--31. 1. " INTERP_FID0_C0 ,C0 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x08 2.--15. 1. " INTERP_FID0_C1 ,C1 coefficient for Interpolated Pixel"
|
|
line.long 0x0c "REG3,CHR_US_P2 REG3 Register"
|
|
hexmask.long.word 0x0c 18.--31. 1. " INTERP_FID0_C2 ,C2 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x0c 2.--15. 1. " INTERP_FID0_C3 ,C3 coefficient for Interpolated Pixel"
|
|
line.long 0x10 "REG4,CHR_US_P2 REG4 Register"
|
|
hexmask.long.word 0x10 18.--31. 1. " ANCHOR_FID1_C0 ,C0 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x10 2.--15. 1. " ANCHOR_FID1_C1 ,C1 coefficient for Anchor Pixel"
|
|
line.long 0x14 "REG5,CHR_US_P2 REG5 Register"
|
|
hexmask.long.word 0x14 18.--31. 1. " ANCHOR_FID1_C2 ,C2 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x14 2.--15. 1. " ANCHOR_FID1_C3 ,C3 coefficient for Anchor Pixel"
|
|
line.long 0x18 "REG6,CHR_US_P2 REG6 Register"
|
|
hexmask.long.word 0x18 18.--31. 1. " INTERP_FID1_C0 ,C0 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x18 2.--15. 1. " INTERP_FID1_C1 ,C1 coefficient for Interpolated Pixel"
|
|
line.long 0x1c "REG7,CHR_US_P2 REG7 Register"
|
|
hexmask.long.word 0x1c 18.--31. 1. " INTERP_FID1_C2 ,C2 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x1c 2.--15. 1. " INTERP_FID1_C3 ,C3 coefficient for Interpolated Pixel"
|
|
width 11.
|
|
tree.end
|
|
tree "CHR_US_P3"
|
|
base ad:0x48100500
|
|
width 6.
|
|
group.long 0x04++0x1f
|
|
line.long 0x00 "REG0,CHR_US_P3 REG0 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " ANCHOR_FID0_C0 ,C0 coefficient for Anchor Pixel"
|
|
bitfld.long 0x00 16.--17. " CFG_MODE ,Configuration Mode" "Mode A,Mode B,Mode C,Mode D"
|
|
hexmask.long.word 0x00 2.--15. 1. " ANCHOR_FID0_C1 ,C1 coefficient for Anchor Pixel"
|
|
line.long 0x04 "REG1,CHR_US_P3 REG1 Register"
|
|
hexmask.long.word 0x04 18.--31. 1. " ANCHOR_FID0_C2 ,C2 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x04 2.--15. 1. " ANCHOR_FID0_C3 ,C3 coefficient for Anchor Pixel"
|
|
line.long 0x08 "REG2,CHR_US_P3 REG2 Register"
|
|
hexmask.long.word 0x08 18.--31. 1. " INTERP_FID0_C0 ,C0 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x08 2.--15. 1. " INTERP_FID0_C1 ,C1 coefficient for Interpolated Pixel"
|
|
line.long 0x0c "REG3,CHR_US_P3 REG3 Register"
|
|
hexmask.long.word 0x0c 18.--31. 1. " INTERP_FID0_C2 ,C2 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x0c 2.--15. 1. " INTERP_FID0_C3 ,C3 coefficient for Interpolated Pixel"
|
|
line.long 0x10 "REG4,CHR_US_P3 REG4 Register"
|
|
hexmask.long.word 0x10 18.--31. 1. " ANCHOR_FID1_C0 ,C0 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x10 2.--15. 1. " ANCHOR_FID1_C1 ,C1 coefficient for Anchor Pixel"
|
|
line.long 0x14 "REG5,CHR_US_P3 REG5 Register"
|
|
hexmask.long.word 0x14 18.--31. 1. " ANCHOR_FID1_C2 ,C2 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x14 2.--15. 1. " ANCHOR_FID1_C3 ,C3 coefficient for Anchor Pixel"
|
|
line.long 0x18 "REG6,CHR_US_P3 REG6 Register"
|
|
hexmask.long.word 0x18 18.--31. 1. " INTERP_FID1_C0 ,C0 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x18 2.--15. 1. " INTERP_FID1_C1 ,C1 coefficient for Interpolated Pixel"
|
|
line.long 0x1c "REG7,CHR_US_P3 REG7 Register"
|
|
hexmask.long.word 0x1c 18.--31. 1. " INTERP_FID1_C2 ,C2 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x1c 2.--15. 1. " INTERP_FID1_C3 ,C3 coefficient for Interpolated Pixel"
|
|
width 11.
|
|
tree.end
|
|
tree "DEI"
|
|
base ad:0x48100600
|
|
width 18.
|
|
group.long 0x00++0x2f
|
|
line.long 0x00 "FRAME_SZ,DEI Frame Size Register"
|
|
bitfld.long 0x00 31. " PROGRESSIVE ,Progressive Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " FIELD_FLUSH ,Field Flush Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INTERLACE_BYPASS ,Interlace Bypass Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--26. 1. " HEIGHT ,Frame Height"
|
|
hexmask.long.word 0x00 0.--10. 1. " WIDTH ,Frame Width"
|
|
line.long 0x04 "MDT_BYP,DEI MDT Bypass Register"
|
|
bitfld.long 0x04 1. " MDT_SPATMAX_BYPASS ,MDT Spatmax Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x04 0. " MDT_TEMPMAX_BYPASS ,MDT Tempmax Bypass" "Not bypassed,Bypassed"
|
|
line.long 0x08 "MDT_SPATFREQ_THR,DEI MDT Spatial Frequency Threshold Register"
|
|
bitfld.long 0x08 28.--31. " MDT_MVSTMAX_COR_THR ,Threshold for coring for spatial-maximum output of motion values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " MDT_MV_COR_THR ,Threshold for coring for motion value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x08 16.--23. 1. " MDT_SF_SC_THR3 ,Spatial frequency threshold 3"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " MDT_SF_SC_THR2 ,Spatial frequency threshold 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " MDT_SF_SC_THR1 ,Spatial frequency threshold 1"
|
|
line.long 0x0c "EDI_CTRL,DEI EDI Configuration Control Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " EDI_COR_SCALE_FACTOR ,Scaling factor for correlation along detected edge"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " EDI_DIR_COR_LOWER_THR ,Lower threshold used for correlation along detected edge"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " EDI_CHROMA3D_COR_THR ,Correlation threshold used in 3D processing for chroma"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " EDI_CHROMA_3D_ENABLE ,3D Chroma Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " EDI_ENABLE_3D ,3D Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " EDI_INP_MODE ,Interpolation mode" "Line average,Field average,Edge-directed (luma),Edge-directed (luma/chroma)"
|
|
width 18.
|
|
line.long 0x10 "EDI_LUT0,DEI EDI Lookup Table Register 0"
|
|
bitfld.long 0x10 24.--28. " EDI_LUT3 ,EDI Lookup Table 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 16.--20. " EDI_LUT2 ,EDI Lookup Table 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 8.--12. " EDI_LUT1 ,EDI Lookup Table 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 0.--4. " EDI_LUT0 ,EDI Lookup Table 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "EDI_LUT1,DEI EDI Lookup Table Register 1"
|
|
bitfld.long 0x14 24.--28. " EDI_LUT7 ,EDI Lookup Table 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x14 16.--20. " EDI_LUT6 ,EDI Lookup Table 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x14 8.--12. " EDI_LUT5 ,EDI Lookup Table 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x14 0.--4. " EDI_LUT4 ,EDI Lookup Table 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "EDI_LUT2,DEI EDI Lookup Table Register 2"
|
|
bitfld.long 0x18 24.--28. " EDI_LUT11 ,EDI Lookup Table 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 16.--20. " EDI_LUT10 ,EDI Lookup Table 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 8.--12. " EDI_LUT9 ,EDI Lookup Table 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 0.--4. " EDI_LUT8 ,EDI Lookup Table 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1c "EDI_LUT3,DEI EDI Lookup Table Register 3"
|
|
bitfld.long 0x1c 24.--28. " EDI_LUT15 ,EDI Lookup Table 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x1c 16.--20. " EDI_LUT14 ,EDI Lookup Table 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x1c 8.--12. " EDI_LUT13 ,EDI Lookup Table 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x1c 0.--4. " EDI_LUT12 ,EDI Lookup Table 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 18.
|
|
line.long 0x20 "FMD_WINDOW0,DEI FMD Window Register 0"
|
|
bitfld.long 0x20 31. " FMD_WINDOW_ENABLE ,Enable FMD operation window" "Disabled,Enabled"
|
|
hexmask.long.word 0x20 16.--26. 1. " FMD_WINDOW_MAXX ,Right boundary of FMD operation window"
|
|
hexmask.long.word 0x20 0.--10. 1. " FMD_WINDOW_MINX ,Left boundary of FMD operation window"
|
|
line.long 0x24 "FMD_WINDOW1,DEI FMD Window Register 1"
|
|
hexmask.long.word 0x24 16.--26. 1. " FMD_WINDOW_MAXY ,Bottom boundary of FMD operation window"
|
|
hexmask.long.word 0x24 0.--10. 1. " FMD_WINDOW_MINY ,Top boundary of FMD operation window"
|
|
line.long 0x28 "FMD_CTRL0,DEI FMD Control Register 0"
|
|
hexmask.long.byte 0x28 24.--31. 1. " FMD_CAF_LINE_THR ,CAF threshold for pixels from two lines in one field"
|
|
hexmask.long.byte 0x28 16.--23. 1. " FMD_CAF_FIELD_THR ,CAF threshold for pixels from two lines"
|
|
bitfld.long 0x28 3. " FMD_BED_ENABLE ,Film Mode Bad Edit Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 2. " FMD_JAM_DIR ,Film Mode Field Jamming Direction" "Previous,Next"
|
|
bitfld.long 0x28 1. " FMD_LOCK ,Lock Deinterlacer to film mode" "Standard,Film Mode"
|
|
bitfld.long 0x28 0. " FMD_ENABLE ,Enable film mode processing" "Disabled,Enabled"
|
|
line.long 0x2c "FMD_CTRL1,DEI FMD Control Register 1"
|
|
hexmask.long.byte 0x2c 0.--19. 1. " FMD_CAF_THR ,CAF threshold for leaving film mode"
|
|
rgroup.long 0x30++0xb
|
|
line.long 0x00 "FMD_STS0,DEI FMD Status Register 0"
|
|
bitfld.long 0x00 24. " FMD_RESET ,Film mode detection module reset" "No reset,Reset"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " FMD_CAF ,Detected combing artifacts"
|
|
line.long 0x04 "FMD_STS1,DEI FMD Status Register 1"
|
|
hexmask.long 0x04 0.--27. 1. " FMD_FIELD_DIFF ,Field difference"
|
|
line.long 0x08 "FMD_STS2,DEI FMD Status Register 2"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " FMD_FRAME_DIFF ,Frame difference"
|
|
width 11.
|
|
tree.end
|
|
tree "SC_P"
|
|
base ad:0x48100700
|
|
width 10.
|
|
group.long 0x00++0x1b
|
|
line.long 0x00 "CFG_SC0,SC_P CFG_SC0 Register"
|
|
bitfld.long 0x00 16. " CFG_SELFGEN_FID ,Self Generate FID Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CFG_TRIM ,Trimming enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CFG_Y_PK_EN ,Luma peaking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CFG_ENABLE_SIN2_VER_INTP ,Bilinear interpolation select" "Original,Modified"
|
|
bitfld.long 0x00 10. " CFG_INTERLACE_I ,Input video format" "Progressive,Interlace"
|
|
bitfld.long 0x00 9. " CFG_HP_BYPASS ,Polyphase scaler bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CFG_DCM_4X ,4X decimation filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CFG_DCM_2X ,2X decimation filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CFG_AUTO_HS ,Hardware autoselect scalling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CFG_ENABLE_EV ,Edge-detection block output" "Forced to 0,Normal"
|
|
bitfld.long 0x00 4. " CFG_USE_RAV ,Vertical scaling filter select" "Poly-phase,Running average"
|
|
bitfld.long 0x00 3. " CFG_INVT_FID ,Field ID inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CFG_SC_BYPASS ,Scaling module bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 1. " CFG_LINEAR ,Scaling" "Anamorphic,Linear"
|
|
bitfld.long 0x00 0. " CFG_INTERLACE_O ,Output format of SC" "Progressive,Interlace"
|
|
line.long 0x04 "CFG_SC1,SC_P CFG_SC1 Register"
|
|
hexmask.long 0x04 0.--26. 1. " CFG_ROW_ACC_INC ,Increment of row accumulator in vertical poly-phase filter"
|
|
line.long 0x08 "CFG_SC2,SC_P CFG_SC2 Register"
|
|
hexmask.long 0x08 0.--27. 1. " CFG_ROW_ACC_OFFSET ,Vertical offset during vertical scaling"
|
|
line.long 0x0c "CFG_SC3,SC_P CFG_SC3 Register"
|
|
hexmask.long 0x0c 0.--27. 1. " CFG_ROW_ACC_OFFSET_B ,Vertical offset during vertical scaling"
|
|
line.long 0x10 "CFG_SC4,SC_P CFG_SC4 Register"
|
|
bitfld.long 0x10 28.--30. " CFG_NLIN_ACC_INIT_U ,3 MSBs of nlin_acc_init" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x10 24.--26. " CFG_LIN_ACC_INC_U ,3 MSBs of lin_acc_inc" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
hexmask.long.word 0x10 12.--22. 1. " CFG_TAR_W ,Scaled target picture width (in pixels)"
|
|
hexmask.long.word 0x10 0.--10. 1. " CFG_TAR_H ,Scaled target picture height (in lines)"
|
|
line.long 0x14 "CFG_SC5,SC_P CFG_SC5 Register"
|
|
bitfld.long 0x14 24.--26. " CFG_NLIN_ACC_INC_U ,3 MSBs of nlin_acc_inc" "000,001,010,011,100,101,110,111"
|
|
hexmask.long.word 0x14 12.--22. 1. " CFG_SRC_W ,Source image width"
|
|
hexmask.long.word 0x14 0.--10. 1. " CFG_SRC_H ,Source image height"
|
|
line.long 0x18 "CFG_SC6,SC_P CFG_SC6 Register"
|
|
hexmask.long.word 0x18 10.--19. 1. " CFG_ROW_ACC_INIT_RAV ,Running average filter row accumulator init value (bottom field of interlace format)"
|
|
hexmask.long.word 0x18 0.--9. 1. " CFG_ROW_ACC_INIT_RAV_B ,Running average filter row accumulator init value (progressive format / top field of interlace format)"
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "CFG_SC8,SC_P CFG_SC8 Register"
|
|
hexmask.long.word 0x00 12.--22. 1. " CFG_NLIN_RIGHT ,Strip on right-hand side width (in anamorphic mode)"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFG_NLIN_LEFT ,Strip on left-hand side width (in anamorphic mode)"
|
|
line.long 0x04 "CFG_SC9,SC_P CFG_SC9 Register"
|
|
line.long 0x08 "CFG_SC10,SC_P CFG_SC10 Register"
|
|
line.long 0x0c "CFG_SC11,SC_P CFG_SC11 Register"
|
|
line.long 0x10 "CFG_SC12,SC_P CFG_SC12 Register"
|
|
hexmask.long 0x10 0.--24. 1. " CFG_COL_ACC_OFFSET ,Luma accumulators offset"
|
|
line.long 0x14 "CFG_SC13,SC_P CFG_SC13 Register"
|
|
bitfld.long 0x14 24.--27. " CFG_DELTA_CHROMA_THR ,Range for chroma soft switch based on pixel differences" "0,1,2,3,4,5,6,7,8,?..."
|
|
hexmask.long.word 0x14 12.--21. 1. " CFG_CHROMA_INTP_THR ,Difference-threshold between chroma pixels"
|
|
hexmask.long.word 0x14 0.--9. 1. " CFG_SC_FACTOR_RAV ,Vertical scaling factor (1024*tarH/srcH)"
|
|
group.long 0x44++0x23
|
|
line.long 0x00 "CFG_SC17,SC_P CFG_SC17 Register"
|
|
bitfld.long 0x00 28.--31. " CFG_DELTA_EV_THR ,Range of luma soft switch based on edge vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " CFG_DELTA_LUMA_THR ,Range for luma soft switch based on pixel differences" "0,1,2,3,4,5,6,7,8,?..."
|
|
hexmask.long.word 0x00 12.--21. 1. " CFG_EV_THR ,Edge vector threshold (8.2)"
|
|
line.long 0x04 "CFG_SC18,SC_P CFG_SC18 Register"
|
|
hexmask.long.word 0x04 16.--24. 1. " CFG_CONF_DEFAULT ,Confidence factor when edge detection is disabled"
|
|
hexmask.long.word 0x04 0.--9. 1. " CFG_HS_FACTOR ,Horizontal scaling factor (tarWi/srcWi)(6.4)"
|
|
line.long 0x08 "CFG_SC19,SC_P CFG_SC19 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " CFG_HPF_COEF3 ,Coefficient 3 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFG_HPF_COEF2 ,Coefficient 2 of HPF used in peaking filter"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " CFG_HPF_COEF1 ,Coefficient 1 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFG_HPF_COEF0 ,Coefficient 0 of HPF used in peaking filter"
|
|
line.long 0x0c "CFG_SC20,SC_P CFG_SC20 Register"
|
|
hexmask.long.word 0x0C 20.--28. 1. " CFG_NL_LIMIT ,Maximum of clipping"
|
|
bitfld.long 0x0C 16.--18. " CFG_HPF_NORM_SHIFT ,Decimal point of hpf coefficient" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 8.--15. 1. " CFG_HPF_COEF5 ,Coefficient 5 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CFG_HPF_COEF4 ,Coefficient 4 of HPF used in peaking filter"
|
|
line.long 0x10 "CFG_SC21,SC_P CFG_SC21 Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. " CFG_NL_LO_SLOPE ,Slope of nonlinear peaking function"
|
|
hexmask.long.word 0x10 0.--8. 1. " CFG_NL_LO_THR ,Threshold for nonlinear peaking function"
|
|
line.long 0x14 "CFG_SC22,SC_P CFG_SC22 Register"
|
|
bitfld.long 0x14 16.--18. " CFG_NL_HI_SLOPE_SHIFT ,Slope of nonlinear peaking function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x14 0.--8. 1. " CFG_NL_HI_THR ,Threshold for nonlinear peaking function"
|
|
line.long 0x18 "CFG_SC23,SC_P CFG_SC23 Register"
|
|
bitfld.long 0x18 28.--31. " CFG_MIN_GY_THR_RANGE ,Soft switch range of small Gy decay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x18 16.--25. 1. " CFG_MIN_GY_THR ,Threshold for soft switch of decay for small Gy"
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " CFG_GRADIENT_THR_RANGE ,Soft switch range of edge strength test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x18 0.--10. 1. " CFG_GRADIENT_THR ,Threshold for gradient for edge strength test"
|
|
line.long 0x1c "CFG_SC24,SC_P CFG_SC24 Register"
|
|
hexmask.long.word 0x1C 16.--26. 1. " CFG_ORG_W ,Width of original input image"
|
|
hexmask.long.word 0x1C 0.--10. 1. " CFG_ORG_H ,Height of original input image"
|
|
line.long 0x20 "CFG_SC25,SC_P CFG_SC25 Register"
|
|
hexmask.long.word 0x20 16.--26. 1. " CFG_OFF_W ,Horizontal offset from left of original input image"
|
|
hexmask.long.word 0x20 0.--10. 1. " CFG_OFF_H ,Vertical offset from top of original input image"
|
|
width 11.
|
|
tree.end
|
|
tree "CHR_US_A"
|
|
base ad:0x48100a00
|
|
width 6.
|
|
group.long 0x04++0x1f
|
|
line.long 0x00 "REG0,CHR_US_A REG0 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " ANCHOR_FID0_C0 ,C0 coefficient for Anchor Pixel"
|
|
bitfld.long 0x00 16.--17. " CFG_MODE ,Configuration Mode" "Mode A,Mode B,Mode C,Mode D"
|
|
hexmask.long.word 0x00 2.--15. 1. " ANCHOR_FID0_C1 ,C1 coefficient for Anchor Pixel"
|
|
line.long 0x04 "REG1,CHR_US_A REG1 Register"
|
|
hexmask.long.word 0x04 18.--31. 1. " ANCHOR_FID0_C2 ,C2 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x04 2.--15. 1. " ANCHOR_FID0_C3 ,C3 coefficient for Anchor Pixel"
|
|
line.long 0x08 "REG2,CHR_US_A REG2 Register"
|
|
hexmask.long.word 0x08 18.--31. 1. " INTERP_FID0_C0 ,C0 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x08 2.--15. 1. " INTERP_FID0_C1 ,C1 coefficient for Interpolated Pixel"
|
|
line.long 0x0c "REG3,CHR_US_A REG3 Register"
|
|
hexmask.long.word 0x0c 18.--31. 1. " INTERP_FID0_C2 ,C2 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x0c 2.--15. 1. " INTERP_FID0_C3 ,C3 coefficient for Interpolated Pixel"
|
|
line.long 0x10 "REG4,CHR_US_A REG4 Register"
|
|
hexmask.long.word 0x10 18.--31. 1. " ANCHOR_FID1_C0 ,C0 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x10 2.--15. 1. " ANCHOR_FID1_C1 ,C1 coefficient for Anchor Pixel"
|
|
line.long 0x14 "REG5,CHR_US_A REG5 Register"
|
|
hexmask.long.word 0x14 18.--31. 1. " ANCHOR_FID1_C2 ,C2 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x14 2.--15. 1. " ANCHOR_FID1_C3 ,C3 coefficient for Anchor Pixel"
|
|
line.long 0x18 "REG6,CHR_US_A REG6 Register"
|
|
hexmask.long.word 0x18 18.--31. 1. " INTERP_FID1_C0 ,C0 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x18 2.--15. 1. " INTERP_FID1_C1 ,C1 coefficient for Interpolated Pixel"
|
|
line.long 0x1c "REG7,CHR_US_A REG7 Register"
|
|
hexmask.long.word 0x1c 18.--31. 1. " INTERP_FID1_C2 ,C2 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x1c 2.--15. 1. " INTERP_FID1_C3 ,C3 coefficient for Interpolated Pixel"
|
|
width 11.
|
|
tree.end
|
|
tree "SC_A"
|
|
base ad:0x48100b00
|
|
width 10.
|
|
group.long 0x00++0x1b
|
|
line.long 0x00 "CFG_SC0,SC_A CFG_SC0 Register"
|
|
bitfld.long 0x00 16. " CFG_SELFGEN_FID ,Self Generate FID Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CFG_TRIM ,Trimming enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CFG_Y_PK_EN ,Luma peaking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CFG_ENABLE_SIN2_VER_INTP ,Bilinear interpolation select" "Original,Modified"
|
|
bitfld.long 0x00 10. " CFG_INTERLACE_I ,Input video format" "Progressive,Interlace"
|
|
bitfld.long 0x00 9. " CFG_HP_BYPASS ,Polyphase scaler bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CFG_DCM_4X ,4X decimation filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CFG_DCM_2X ,2X decimation filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CFG_AUTO_HS ,Hardware autoselect scalling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CFG_ENABLE_EV ,Edge-detection block output" "Forced to 0,Normal"
|
|
bitfld.long 0x00 4. " CFG_USE_RAV ,Vertical scaling filter select" "Poly-phase,Running average"
|
|
bitfld.long 0x00 3. " CFG_INVT_FID ,Field ID inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CFG_SC_BYPASS ,Scaling module bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 1. " CFG_LINEAR ,Scaling" "Anamorphic,Linear"
|
|
bitfld.long 0x00 0. " CFG_INTERLACE_O ,Output format of SC" "Progressive,Interlace"
|
|
line.long 0x04 "CFG_SC1,SC_A CFG_SC1 Register"
|
|
hexmask.long 0x04 0.--26. 1. " CFG_ROW_ACC_INC ,Increment of row accumulator in vertical poly-phase filter"
|
|
line.long 0x08 "CFG_SC2,SC_A CFG_SC2 Register"
|
|
hexmask.long 0x08 0.--27. 1. " CFG_ROW_ACC_OFFSET ,Vertical offset during vertical scaling"
|
|
line.long 0x0c "CFG_SC3,SC_A CFG_SC3 Register"
|
|
hexmask.long 0x0c 0.--27. 1. " CFG_ROW_ACC_OFFSET_B ,Vertical offset during vertical scaling"
|
|
line.long 0x10 "CFG_SC4,SC_A CFG_SC4 Register"
|
|
bitfld.long 0x10 28.--30. " CFG_NLIN_ACC_INIT_U ,3 MSBs of nlin_acc_init" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x10 24.--26. " CFG_LIN_ACC_INC_U ,3 MSBs of lin_acc_inc" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
hexmask.long.word 0x10 12.--22. 1. " CFG_TAR_W ,Scaled target picture width (in pixels)"
|
|
hexmask.long.word 0x10 0.--10. 1. " CFG_TAR_H ,Scaled target picture height (in lines)"
|
|
line.long 0x14 "CFG_SC5,SC_A CFG_SC5 Register"
|
|
bitfld.long 0x14 24.--26. " CFG_NLIN_ACC_INC_U ,3 MSBs of nlin_acc_inc" "000,001,010,011,100,101,110,111"
|
|
hexmask.long.word 0x14 12.--22. 1. " CFG_SRC_W ,Source image width"
|
|
hexmask.long.word 0x14 0.--10. 1. " CFG_SRC_H ,Source image height"
|
|
line.long 0x18 "CFG_SC6,SC_A CFG_SC6 Register"
|
|
hexmask.long.word 0x18 10.--19. 1. " CFG_ROW_ACC_INIT_RAV ,Running average filter row accumulator init value (bottom field of interlace format)"
|
|
hexmask.long.word 0x18 0.--9. 1. " CFG_ROW_ACC_INIT_RAV_B ,Running average filter row accumulator init value (progressive format / top field of interlace format)"
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "CFG_SC8,SC_A CFG_SC8 Register"
|
|
hexmask.long.word 0x00 12.--22. 1. " CFG_NLIN_RIGHT ,Strip on right-hand side width (in anamorphic mode)"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFG_NLIN_LEFT ,Strip on left-hand side width (in anamorphic mode)"
|
|
line.long 0x04 "CFG_SC9,SC_A CFG_SC9 Register"
|
|
line.long 0x08 "CFG_SC10,SC_A CFG_SC10 Register"
|
|
line.long 0x0c "CFG_SC11,SC_A CFG_SC11 Register"
|
|
line.long 0x10 "CFG_SC12,SC_A CFG_SC12 Register"
|
|
hexmask.long 0x10 0.--24. 1. " CFG_COL_ACC_OFFSET ,Luma accumulators offset"
|
|
line.long 0x14 "CFG_SC13,SC_A CFG_SC13 Register"
|
|
bitfld.long 0x14 24.--27. " CFG_DELTA_CHROMA_THR ,Range for chroma soft switch based on pixel differences" "0,1,2,3,4,5,6,7,8,?..."
|
|
hexmask.long.word 0x14 12.--21. 1. " CFG_CHROMA_INTP_THR ,Difference-threshold between chroma pixels"
|
|
hexmask.long.word 0x14 0.--9. 1. " CFG_SC_FACTOR_RAV ,Vertical scaling factor (1024*tarH/srcH)"
|
|
group.long 0x44++0x23
|
|
line.long 0x00 "CFG_SC17,SC_A CFG_SC17 Register"
|
|
bitfld.long 0x00 28.--31. " CFG_DELTA_EV_THR ,Range of luma soft switch based on edge vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " CFG_DELTA_LUMA_THR ,Range for luma soft switch based on pixel differences" "0,1,2,3,4,5,6,7,8,?..."
|
|
hexmask.long.word 0x00 12.--21. 1. " CFG_EV_THR ,Edge vector threshold (8.2)"
|
|
line.long 0x04 "CFG_SC18,SC_A CFG_SC18 Register"
|
|
hexmask.long.word 0x04 16.--24. 1. " CFG_CONF_DEFAULT ,Confidence factor when edge detection is disabled"
|
|
hexmask.long.word 0x04 0.--9. 1. " CFG_HS_FACTOR ,Horizontal scaling factor (tarWi/srcWi)(6.4)"
|
|
line.long 0x08 "CFG_SC19,SC_A CFG_SC19 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " CFG_HPF_COEF3 ,Coefficient 3 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFG_HPF_COEF2 ,Coefficient 2 of HPF used in peaking filter"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " CFG_HPF_COEF1 ,Coefficient 1 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFG_HPF_COEF0 ,Coefficient 0 of HPF used in peaking filter"
|
|
line.long 0x0c "CFG_SC20,SC_A CFG_SC20 Register"
|
|
hexmask.long.word 0x0C 20.--28. 1. " CFG_NL_LIMIT ,Maximum of clipping"
|
|
bitfld.long 0x0C 16.--18. " CFG_HPF_NORM_SHIFT ,Decimal point of hpf coefficient" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 8.--15. 1. " CFG_HPF_COEF5 ,Coefficient 5 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CFG_HPF_COEF4 ,Coefficient 4 of HPF used in peaking filter"
|
|
line.long 0x10 "CFG_SC21,SC_A CFG_SC21 Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. " CFG_NL_LO_SLOPE ,Slope of nonlinear peaking function"
|
|
hexmask.long.word 0x10 0.--8. 1. " CFG_NL_LO_THR ,Threshold for nonlinear peaking function"
|
|
line.long 0x14 "CFG_SC22,SC_A CFG_SC22 Register"
|
|
bitfld.long 0x14 16.--18. " CFG_NL_HI_SLOPE_SHIFT ,Slope of nonlinear peaking function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x14 0.--8. 1. " CFG_NL_HI_THR ,Threshold for nonlinear peaking function"
|
|
line.long 0x18 "CFG_SC23,SC_A CFG_SC23 Register"
|
|
bitfld.long 0x18 28.--31. " CFG_MIN_GY_THR_RANGE ,Soft switch range of small Gy decay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x18 16.--25. 1. " CFG_MIN_GY_THR ,Threshold for soft switch of decay for small Gy"
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " CFG_GRADIENT_THR_RANGE ,Soft switch range of edge strength test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x18 0.--10. 1. " CFG_GRADIENT_THR ,Threshold for gradient for edge strength test"
|
|
line.long 0x1c "CFG_SC24,SC_A CFG_SC24 Register"
|
|
hexmask.long.word 0x1C 16.--26. 1. " CFG_ORG_W ,Width of original input image"
|
|
hexmask.long.word 0x1C 0.--10. 1. " CFG_ORG_H ,Height of original input image"
|
|
line.long 0x20 "CFG_SC25,SC_A CFG_SC25 Register"
|
|
hexmask.long.word 0x20 16.--26. 1. " CFG_OFF_W ,Horizontal offset from left of original input image"
|
|
hexmask.long.word 0x20 0.--10. 1. " CFG_OFF_H ,Vertical offset from top of original input image"
|
|
width 11.
|
|
tree.end
|
|
tree "CSC_Y2R_1"
|
|
base ad:0x48100c00
|
|
width 7.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "CSC00,CSC_Y2R_1 Coefficients of Color Space Converter Register 0"
|
|
hexmask.long.word 0x00 16.--28. 1. " B0 ,B0 coefficient of color space converter"
|
|
hexmask.long.word 0x00 0.--12. 1. " A0 ,A0 coefficient of color space converter"
|
|
line.long 0x04 "CSC01,CSC_Y2R_1 Coefficients of Color Space Converter Register 1"
|
|
hexmask.long.word 0x04 16.--28. 1. " A1 ,A1 coefficient of color space converter"
|
|
hexmask.long.word 0x04 0.--12. 1. " C0 ,C0 coefficient of color space converter"
|
|
line.long 0x08 "CSC02,CSC_Y2R_1 Coefficients of Color Space Converter Register 2"
|
|
hexmask.long.word 0x08 16.--28. 1. " C1 ,C1 coefficient of color space converter"
|
|
hexmask.long.word 0x08 0.--12. 1. " B1 ,B1 coefficient of color space converter"
|
|
line.long 0x0c "CSC03,CSC_Y2R_1 Coefficients of Color Space Converter Register 3"
|
|
hexmask.long.word 0x0c 16.--28. 1. " B2 ,B2 coefficient of color space converter"
|
|
hexmask.long.word 0x0c 0.--12. 1. " A2 ,A2 coefficient of color space converter"
|
|
line.long 0x10 "CSC04,CSC_Y2R_1 Coefficients of Color Space Converter Register 4"
|
|
hexmask.long.word 0x10 16.--27. 1. " D0 ,D0 coefficient of color space converter"
|
|
hexmask.long.word 0x10 0.--12. 1. " C2 ,C2 coefficient of color space converter"
|
|
line.long 0x14 "CSC05,CSC_Y2R_1 Coefficients of Color Space Converter Register 5"
|
|
bitfld.long 0x14 28. " BYPASS ,Full CSC bypass mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x14 16.--27. 1. " D2 ,D2 coefficient of color space converter"
|
|
hexmask.long.word 0x14 0.--11. 1. " D1 ,D1 coefficient of color space converter"
|
|
width 11.
|
|
tree.end
|
|
tree "CSC_Y2R_2"
|
|
base ad:0x48100d00
|
|
width 7.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "CSC00,CSC_Y2R_2 Coefficients of Color Space Converter Register 0"
|
|
hexmask.long.word 0x00 16.--28. 1. " B0 ,B0 coefficient of color space converter"
|
|
hexmask.long.word 0x00 0.--12. 1. " A0 ,A0 coefficient of color space converter"
|
|
line.long 0x04 "CSC01,CSC_Y2R_2 Coefficients of Color Space Converter Register 1"
|
|
hexmask.long.word 0x04 16.--28. 1. " A1 ,A1 coefficient of color space converter"
|
|
hexmask.long.word 0x04 0.--12. 1. " C0 ,C0 coefficient of color space converter"
|
|
line.long 0x08 "CSC02,CSC_Y2R_2 Coefficients of Color Space Converter Register 2"
|
|
hexmask.long.word 0x08 16.--28. 1. " C1 ,C1 coefficient of color space converter"
|
|
hexmask.long.word 0x08 0.--12. 1. " B1 ,B1 coefficient of color space converter"
|
|
line.long 0x0c "CSC03,CSC_Y2R_2 Coefficients of Color Space Converter Register 3"
|
|
hexmask.long.word 0x0c 16.--28. 1. " B2 ,B2 coefficient of color space converter"
|
|
hexmask.long.word 0x0c 0.--12. 1. " A2 ,A2 coefficient of color space converter"
|
|
line.long 0x10 "CSC04,CSC_Y2R_2 Coefficients of Color Space Converter Register 4"
|
|
hexmask.long.word 0x10 16.--27. 1. " D0 ,D0 coefficient of color space converter"
|
|
hexmask.long.word 0x10 0.--12. 1. " C2 ,C2 coefficient of color space converter"
|
|
line.long 0x14 "CSC05,CSC_Y2R_2 Coefficients of Color Space Converter Register 5"
|
|
bitfld.long 0x14 28. " BYPASS ,Full CSC bypass mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x14 16.--27. 1. " D2 ,D2 coefficient of color space converter"
|
|
hexmask.long.word 0x14 0.--11. 1. " D1 ,D1 coefficient of color space converter"
|
|
width 11.
|
|
tree.end
|
|
tree "VCOMP"
|
|
base ad:0x48100e00
|
|
width 7.
|
|
group.long 0x00++0x33
|
|
line.long 0x00 "REG0,VCOMP REG0 Register"
|
|
bitfld.long 0x00 31. " CFG_MAIN_ENABLE ,Main Plane Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CFG_MAIN_FIXED_DATA_SEND ,Main data to be sent" "Source,Fixed"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--27. 1. " CFG_MAIN_NATIVE_NUMLINES ,Number of lines in a field or frame from the incoming main source"
|
|
hexmask.long.word 0x00 0.--11. 1. " CFG_MAIN_NATIVE_NUMPIX_PER_LINE ,Number of pixels per line from the incoming main source"
|
|
line.long 0x04 "REG1,VCOMP REG1 Register"
|
|
bitfld.long 0x04 30. " CFG_MAIN_STARTUP_HANDLING ,Video in/video out operation condition" "Default,Set"
|
|
hexmask.long.word 0x04 16.--27. 1. " CFG_MAIN_SKIP_NUMPIX ,Number of incoming pixels to discard"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--11. 1. " CFG_MAIN_USE_NUMPIX ,Number of pixels to use from each incoming line"
|
|
line.long 0x08 "REG2,VCOMP REG2 Register"
|
|
hexmask.long.word 0x08 16.--27. 1. " CFG_MAIN_SKIP_NUMLINES ,Number of incoming lines to discard"
|
|
hexmask.long.word 0x08 0.--11. 1. " CFG_MAIN_USE_NUMLINES ,Number of lines to use from each incoming field or frame"
|
|
line.long 0x0c "REG3,VCOMP REG3 Register"
|
|
bitfld.long 0x0c 31. " CFG_AUX_ENABLE ,Aux Plane Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " CFG_AUX_FIXED_DATA_SEND ,Aux data to be sent" "Source,Fixed"
|
|
textline " "
|
|
hexmask.long.word 0x0c 16.--27. 1. " CFG_AUX_NATIVE_NUMLINES ,Number of lines in a field or frame from the incoming aux source"
|
|
hexmask.long.word 0x0c 0.--11. 1. " CFG_AUX_NATIVE_NUMPIX_PER_LINE ,Number of pixels per line from the incoming aux source"
|
|
line.long 0x10 "REG4,VCOMP REG4 Register"
|
|
bitfld.long 0x10 30. " CFG_AUX_STARTUP_HANDLING ,Video in/video out operation condition" "Default,Set"
|
|
hexmask.long.word 0x10 16.--27. 1. " CFG_AUX_SKIP_NUMPIX ,Number of incoming pixels to discard"
|
|
textline " "
|
|
hexmask.long.word 0x10 0.--11. 1. " CFG_AUX_USE_NUMPIX ,Number of pixels to use from each incoming line"
|
|
line.long 0x14 "REG5,VCOMP REG5 Register"
|
|
hexmask.long.word 0x14 16.--27. 1. " CFG_AUX_SKIP_NUMLINES ,Number of incoming lines to discard"
|
|
hexmask.long.word 0x14 0.--11. 1. " CFG_AUX_USE_NUMLINES ,Number of lines to use from each incoming field or frame"
|
|
line.long 0x18 "REG6,VCOMP REG6 Register"
|
|
hexmask.long.word 0x18 16.--27. 1. " CFG_DSPLY_NUMPIX_PER_LINE ,Number of lines in a field or frame for the output picture"
|
|
hexmask.long.word 0x18 0.--11. 1. " CFG_DSPLY_NUMLINES ,Number of pixels per line for the output picture"
|
|
line.long 0x1c "REG7,VCOMP REG7 Register"
|
|
hexmask.long.word 0x1c 16.--27. 1. " CFG_DSPLY_MAIN_Y_ORIGIN ,Row origin index for the Main source picture"
|
|
hexmask.long.word 0x1c 0.--11. 1. " CFG_DSPLY_MAIN_X_ORIGIN ,Column origin index for the Main source picture"
|
|
line.long 0x20 "REG8,VCOMP REG8 Register"
|
|
bitfld.long 0x20 30.--31. " CFG_DWNSTRM_SRC_FID_CTRL ,Source FID (bit 0) out of the VCOMP (compared to upstream module respective bit)" "Same,Inversed,Set to '0',Set to '1'"
|
|
hexmask.long.word 0x20 16.--27. 1. " CFG_DSPLY_AUX_Y_ORIGIN ,Row origin index for the Aux source picture"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--11. 1. " CFG_DSPLY_AUX_X_ORIGIN ,Column origin index for the Aux source picture"
|
|
line.long 0x24 "REG9,VCOMP REG9 Register"
|
|
bitfld.long 0x24 31. " CFG_MAIN_AUX_N_OPTOP ,Window presence in display areas where overlap occurs" "Aux over Main,Main over Aux"
|
|
hexmask.long.word 0x24 20.--29. 1. " CFG_DSPLY_BCKGRND_CR_VAL ,Background Cr/Chroma value for the display output"
|
|
textline " "
|
|
hexmask.long.word 0x24 10.--19. 1. " CFG_DSPLY_BCKGRND_CB_VAL ,Background Cb/Chroma value for the display output"
|
|
hexmask.long.word 0x24 0.--9. 1. " CFG_DSPLY_BCKGRND_Y_VA ,Background Y/Luma value for the display output"
|
|
line.long 0x28 "REG10,VCOMP REG10 Register"
|
|
line.long 0x2c "REG11,VCOMP REG11 Register"
|
|
bitfld.long 0x2C 30.--31. " CFG_NF_HANDLING ,NF handling" "First,Reserved,Main,Aux"
|
|
hexmask.long.word 0x2C 20.--29. 1. " CFG_DSPLY_ALT_MAIN_CR_VAL ,Alternate Main Cr/Chroma value for the background display output"
|
|
textline " "
|
|
hexmask.long.word 0x2C 10.--19. 1. " CFG_DSPLY_ALT_MAIN_CB_VAL ,Alternate Main Cb/Chroma value for the background display output"
|
|
hexmask.long.word 0x2C 0.--9. 1. " CFG_DSPLY_ALT_MAIN_Y_VAL ,Alternate Main Y/Luma value for the background display output"
|
|
line.long 0x30 "REG12,VCOMP REG12 Register"
|
|
bitfld.long 0x30 30.--31. " CFG_DWNSTRM_ENC_FID_CTRL ,Encoder FID (bit 1) out of the VCOMP (compared to upstream module respective bit)" "Same,Inversed,Set to '0',Set to '1'"
|
|
hexmask.long.word 0x30 20.--29. 1. " CFG_DSPLY_ALT_AUX_CR_VAL ,Alternate Aux Y/Luma value for the background display output"
|
|
textline " "
|
|
hexmask.long.word 0x30 10.--19. 1. " CFG_DSPLY_ALT_AUX_CB_VAL ,Alternate Aux Cb/Chroma value for the background display output"
|
|
hexmask.long.word 0x30 0.--9. 1. " CFG_DSPLY_ALT_AUX_Y_VAL ,Alternate Aux Y/Luma value for the background display output"
|
|
width 11.
|
|
tree.end
|
|
tree "CSC_Y2R_3"
|
|
base ad:0x48100f00
|
|
width 7.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "CSC00,CSC_Y2R_3 Coefficients of Color Space Converter Register 0"
|
|
hexmask.long.word 0x00 16.--28. 1. " B0 ,B0 coefficient of color space converter"
|
|
hexmask.long.word 0x00 0.--12. 1. " A0 ,A0 coefficient of color space converter"
|
|
line.long 0x04 "CSC01,CSC_Y2R_3 Coefficients of Color Space Converter Register 1"
|
|
hexmask.long.word 0x04 16.--28. 1. " A1 ,A1 coefficient of color space converter"
|
|
hexmask.long.word 0x04 0.--12. 1. " C0 ,C0 coefficient of color space converter"
|
|
line.long 0x08 "CSC02,CSC_Y2R_3 Coefficients of Color Space Converter Register 2"
|
|
hexmask.long.word 0x08 16.--28. 1. " C1 ,C1 coefficient of color space converter"
|
|
hexmask.long.word 0x08 0.--12. 1. " B1 ,B1 coefficient of color space converter"
|
|
line.long 0x0c "CSC03,CSC_Y2R_3 Coefficients of Color Space Converter Register 3"
|
|
hexmask.long.word 0x0c 16.--28. 1. " B2 ,B2 coefficient of color space converter"
|
|
hexmask.long.word 0x0c 0.--12. 1. " A2 ,A2 coefficient of color space converter"
|
|
line.long 0x10 "CSC04,CSC_Y2R_3 Coefficients of Color Space Converter Register 4"
|
|
hexmask.long.word 0x10 16.--27. 1. " D0 ,D0 coefficient of color space converter"
|
|
hexmask.long.word 0x10 0.--12. 1. " C2 ,C2 coefficient of color space converter"
|
|
line.long 0x14 "CSC05,CSC_Y2R_3 Coefficients of Color Space Converter Register 5"
|
|
bitfld.long 0x14 28. " BYPASS ,Full CSC bypass mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x14 16.--27. 1. " D2 ,D2 coefficient of color space converter"
|
|
hexmask.long.word 0x14 0.--11. 1. " D1 ,D1 coefficient of color space converter"
|
|
width 11.
|
|
tree.end
|
|
tree "SC_WRBK"
|
|
base ad:0x48105000
|
|
width 10.
|
|
group.long 0x00++0x1b
|
|
line.long 0x00 "CFG_SC0,SC_WRBK CFG_SC0 Register"
|
|
bitfld.long 0x00 16. " CFG_SELFGEN_FID ,Self Generate FID Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CFG_TRIM ,Trimming enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CFG_Y_PK_EN ,Luma peaking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CFG_ENABLE_SIN2_VER_INTP ,Bilinear interpolation select" "Original,Modified"
|
|
bitfld.long 0x00 10. " CFG_INTERLACE_I ,Input video format" "Progressive,Interlace"
|
|
bitfld.long 0x00 9. " CFG_HP_BYPASS ,Polyphase scaler bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CFG_DCM_4X ,4X decimation filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CFG_DCM_2X ,2X decimation filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CFG_AUTO_HS ,Hardware autoselect scalling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CFG_ENABLE_EV ,Edge-detection block output" "Forced to 0,Normal"
|
|
bitfld.long 0x00 4. " CFG_USE_RAV ,Vertical scaling filter select" "Poly-phase,Running average"
|
|
bitfld.long 0x00 3. " CFG_INVT_FID ,Field ID inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CFG_SC_BYPASS ,Scaling module bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 1. " CFG_LINEAR ,Scaling" "Anamorphic,Linear"
|
|
bitfld.long 0x00 0. " CFG_INTERLACE_O ,Output format of SC" "Progressive,Interlace"
|
|
line.long 0x04 "CFG_SC1,SC_WRBK CFG_SC1 Register"
|
|
hexmask.long 0x04 0.--26. 1. " CFG_ROW_ACC_INC ,Increment of row accumulator in vertical poly-phase filter"
|
|
line.long 0x08 "CFG_SC2,SC_WRBK CFG_SC2 Register"
|
|
hexmask.long 0x08 0.--27. 1. " CFG_ROW_ACC_OFFSET ,Vertical offset during vertical scaling"
|
|
line.long 0x0c "CFG_SC3,SC_WRBK CFG_SC3 Register"
|
|
hexmask.long 0x0c 0.--27. 1. " CFG_ROW_ACC_OFFSET_B ,Vertical offset during vertical scaling"
|
|
line.long 0x10 "CFG_SC4,SC_WRBK CFG_SC4 Register"
|
|
bitfld.long 0x10 28.--30. " CFG_NLIN_ACC_INIT_U ,3 MSBs of nlin_acc_init" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x10 24.--26. " CFG_LIN_ACC_INC_U ,3 MSBs of lin_acc_inc" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
hexmask.long.word 0x10 12.--22. 1. " CFG_TAR_W ,Scaled target picture width (in pixels)"
|
|
hexmask.long.word 0x10 0.--10. 1. " CFG_TAR_H ,Scaled target picture height (in lines)"
|
|
line.long 0x14 "CFG_SC5,SC_WRBK CFG_SC5 Register"
|
|
bitfld.long 0x14 24.--26. " CFG_NLIN_ACC_INC_U ,3 MSBs of nlin_acc_inc" "000,001,010,011,100,101,110,111"
|
|
hexmask.long.word 0x14 12.--22. 1. " CFG_SRC_W ,Source image width"
|
|
hexmask.long.word 0x14 0.--10. 1. " CFG_SRC_H ,Source image height"
|
|
line.long 0x18 "CFG_SC6,SC_WRBK CFG_SC6 Register"
|
|
hexmask.long.word 0x18 10.--19. 1. " CFG_ROW_ACC_INIT_RAV ,Running average filter row accumulator init value (bottom field of interlace format)"
|
|
hexmask.long.word 0x18 0.--9. 1. " CFG_ROW_ACC_INIT_RAV_B ,Running average filter row accumulator init value (progressive format / top field of interlace format)"
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "CFG_SC8,SC_WRBK CFG_SC8 Register"
|
|
hexmask.long.word 0x00 12.--22. 1. " CFG_NLIN_RIGHT ,Strip on right-hand side width (in anamorphic mode)"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFG_NLIN_LEFT ,Strip on left-hand side width (in anamorphic mode)"
|
|
line.long 0x04 "CFG_SC9,SC_WRBK CFG_SC9 Register"
|
|
line.long 0x08 "CFG_SC10,SC_WRBK CFG_SC10 Register"
|
|
line.long 0x0c "CFG_SC11,SC_WRBK CFG_SC11 Register"
|
|
line.long 0x10 "CFG_SC12,SC_WRBK CFG_SC12 Register"
|
|
hexmask.long 0x10 0.--24. 1. " CFG_COL_ACC_OFFSET ,Luma accumulators offset"
|
|
line.long 0x14 "CFG_SC13,SC_WRBK CFG_SC13 Register"
|
|
bitfld.long 0x14 24.--27. " CFG_DELTA_CHROMA_THR ,Range for chroma soft switch based on pixel differences" "0,1,2,3,4,5,6,7,8,?..."
|
|
hexmask.long.word 0x14 12.--21. 1. " CFG_CHROMA_INTP_THR ,Difference-threshold between chroma pixels"
|
|
hexmask.long.word 0x14 0.--9. 1. " CFG_SC_FACTOR_RAV ,Vertical scaling factor (1024*tarH/srcH)"
|
|
group.long 0x44++0x23
|
|
line.long 0x00 "CFG_SC17,SC_WRBK CFG_SC17 Register"
|
|
bitfld.long 0x00 28.--31. " CFG_DELTA_EV_THR ,Range of luma soft switch based on edge vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " CFG_DELTA_LUMA_THR ,Range for luma soft switch based on pixel differences" "0,1,2,3,4,5,6,7,8,?..."
|
|
hexmask.long.word 0x00 12.--21. 1. " CFG_EV_THR ,Edge vector threshold (8.2)"
|
|
line.long 0x04 "CFG_SC18,SC_WRBK CFG_SC18 Register"
|
|
hexmask.long.word 0x04 16.--24. 1. " CFG_CONF_DEFAULT ,Confidence factor when edge detection is disabled"
|
|
hexmask.long.word 0x04 0.--9. 1. " CFG_HS_FACTOR ,Horizontal scaling factor (tarWi/srcWi)(6.4)"
|
|
line.long 0x08 "CFG_SC19,SC_WRBK CFG_SC19 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " CFG_HPF_COEF3 ,Coefficient 3 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFG_HPF_COEF2 ,Coefficient 2 of HPF used in peaking filter"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " CFG_HPF_COEF1 ,Coefficient 1 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFG_HPF_COEF0 ,Coefficient 0 of HPF used in peaking filter"
|
|
line.long 0x0c "CFG_SC20,SC_WRBK CFG_SC20 Register"
|
|
hexmask.long.word 0x0C 20.--28. 1. " CFG_NL_LIMIT ,Maximum of clipping"
|
|
bitfld.long 0x0C 16.--18. " CFG_HPF_NORM_SHIFT ,Decimal point of hpf coefficient" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 8.--15. 1. " CFG_HPF_COEF5 ,Coefficient 5 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CFG_HPF_COEF4 ,Coefficient 4 of HPF used in peaking filter"
|
|
line.long 0x10 "CFG_SC21,SC_WRBK CFG_SC21 Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. " CFG_NL_LO_SLOPE ,Slope of nonlinear peaking function"
|
|
hexmask.long.word 0x10 0.--8. 1. " CFG_NL_LO_THR ,Threshold for nonlinear peaking function"
|
|
line.long 0x14 "CFG_SC22,SC_WRBK CFG_SC22 Register"
|
|
bitfld.long 0x14 16.--18. " CFG_NL_HI_SLOPE_SHIFT ,Slope of nonlinear peaking function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x14 0.--8. 1. " CFG_NL_HI_THR ,Threshold for nonlinear peaking function"
|
|
line.long 0x18 "CFG_SC23,SC_WRBK CFG_SC23 Register"
|
|
bitfld.long 0x18 28.--31. " CFG_MIN_GY_THR_RANGE ,Soft switch range of small Gy decay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x18 16.--25. 1. " CFG_MIN_GY_THR ,Threshold for soft switch of decay for small Gy"
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " CFG_GRADIENT_THR_RANGE ,Soft switch range of edge strength test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x18 0.--10. 1. " CFG_GRADIENT_THR ,Threshold for gradient for edge strength test"
|
|
line.long 0x1c "CFG_SC24,SC_WRBK CFG_SC24 Register"
|
|
hexmask.long.word 0x1C 16.--26. 1. " CFG_ORG_W ,Width of original input image"
|
|
hexmask.long.word 0x1C 0.--10. 1. " CFG_ORG_H ,Height of original input image"
|
|
line.long 0x20 "CFG_SC25,SC_WRBK CFG_SC25 Register"
|
|
hexmask.long.word 0x20 16.--26. 1. " CFG_OFF_W ,Horizontal offset from left of original input image"
|
|
hexmask.long.word 0x20 0.--10. 1. " CFG_OFF_H ,Vertical offset from top of original input image"
|
|
width 11.
|
|
tree.end
|
|
tree "CIG"
|
|
base ad:0x48105100
|
|
width 11.
|
|
group.long 0x00++0x2f
|
|
line.long 0x00 "CIG_REG0,CIG Mode Configuration Register"
|
|
bitfld.long 0x00 7. " PIP_P2I_EN ,Enable Output Interlacing for PIP output" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PIP_FULLSIZE ,CIG PIP window size" "Sub-window,Full-size"
|
|
bitfld.long 0x00 5. " PIP_EN ,CIG PIP path enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CI_FIELD_RPT_EN ,CIG filter field drop/repeat option enable for vertical filtering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CI_VDEC_EN ,CIG filter vertical decimation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CI_P2I_EN ,Enable Output Interlacing for Constrained output" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P2I_EN ,Enable Output Interlacing for Non-constrained output" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CIG_EN ,CIG module enable" "Disabled,Enabled"
|
|
line.long 0x04 "CIG_REG1,CIG Output Display Size Configuration Register"
|
|
hexmask.long.word 0x04 16.--26. 1. " DISP_W ,Output display Width"
|
|
hexmask.long.word 0x04 0.--10. 1. " DISP_H ,Output display Height"
|
|
line.long 0x08 "CIG_REG2,CIG HDMI Output Transparency/Blending Configuration Register"
|
|
hexmask.long.byte 0x08 4.--11. 1. " HDMI_BL_LEVEL ,Blending Value"
|
|
bitfld.long 0x08 3. " HDMI_BL_ENABLE ,Blending Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1.--2. " HDMI_TR_MODE_MASK ,Transparency Color Mask" "No masking,1 LSB,2 LSBs,3 LSBs"
|
|
bitfld.long 0x08 0. " HDMI_TR_ENABLE ,Transparency Enable" "Disabled,Enabled"
|
|
line.long 0x0c "CIG_REG3,CIG HDMI Output Transparency Color Register"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " HDMI_TR_COLOR_R ,Transparency Color R"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " HDMI_TR_COLOR_G ,Transparency Color G"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " HDMI_TR_COLOR_B ,Transparency Color B"
|
|
line.long 0x10 "CIG_REG4,CIG HDCOMP Output Transparency/Blending Configuration Register"
|
|
hexmask.long.byte 0x10 4.--11. 1. " HDCOMP_BL_LEVEL ,Blending Value"
|
|
bitfld.long 0x10 3. " HDCOMP_BL_ENABLE ,Blending Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1.--2. " HDCOMP_TR_MODE_MASK ,Transparency Color Mask" "Not masked,1 LSB,2 LSBs,3 LSBs"
|
|
bitfld.long 0x10 0. " HDCOMP_TR_ENABLE ,Transparency Enable" "Disabled,Enabled"
|
|
line.long 0x14 "CIG_REG5,CIG HDCOMP Output Transparency Color Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. " HDCOMP_TR_COLOR_R ,Transparency Color R"
|
|
hexmask.long.byte 0x14 8.--15. 1. " HDCOMP_TR_COLOR_G ,Transparency Color G"
|
|
hexmask.long.byte 0x14 0.--7. 1. " HDCOMP_TR_COLOR_B ,Transparency Color B"
|
|
line.long 0x18 "CIG_REG6,CIG PIP Output Display Size Configuration Register"
|
|
hexmask.long.word 0x18 16.--26. 1. " PIP_DISP_W ,Pip output display Width"
|
|
hexmask.long.word 0x18 0.--10. 1. " PIP_DISP_H ,Pip output display Height"
|
|
line.long 0x1c "CIG_REG7,CIG PIP Window Position Configuration Register"
|
|
hexmask.long.word 0x1c 16.--26. 1. " PIP_X ,PIP window X position"
|
|
hexmask.long.word 0x1c 0.--10. 1. " PIP_Y ,PIP window Y position"
|
|
line.long 0x20 "CIG_REG8,CIG PIP Window Size Configuration Register"
|
|
hexmask.long.word 0x20 16.--26. 1. " PIP_W ,PIP window Width"
|
|
hexmask.long.word 0x20 0.--10. 1. " PIP_H ,PIP window Height"
|
|
line.long 0x24 "CIG_REG9,CIG PIP Output Transparency/Blending Configuration Register"
|
|
hexmask.long.byte 0x24 4.--11. 1. " PIP_BL_LEVEL ,Blending Value"
|
|
bitfld.long 0x24 3. " PIP_BL_ENABLE ,Blending Enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 1.--2. " PIP_TR_MODE_MASK ,Transparency Color Mask" "Not masked,1 LSB,2 LSBs,3 LSBs"
|
|
bitfld.long 0x24 0. " PIP_TR_ENABLE ,Transparency Enable" "Disabled,Enabled"
|
|
line.long 0x28 "CIG_REG10,CIG PIP Output Transparency Color Register"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PIP_TR_COLOR_R ,Transparency Color R"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PIP_TR_COLOR_G ,Transparency Color G"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PIP_TR_COLOR_B ,Transparency Color B"
|
|
line.long 0x2c "CIG_REG11,CIG Status Register"
|
|
hexmask.long.byte 0x2c 0.--7. 1. " CIG_STATUS ,CIG Status"
|
|
width 11.
|
|
tree.end
|
|
tree "COMP"
|
|
base ad:0x48105200
|
|
width 16.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "COMP_STS,COMP Compositor Status Register"
|
|
bitfld.long 0x00 25. " SD_FMT ,SD format" "Progressive,Interlace"
|
|
bitfld.long 0x00 24. " SD_ENABLE ,SD enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " HD_2_FMT ,HD_2 format" "Progressive,Interlace"
|
|
bitfld.long 0x00 16. " HD_2_ENABLE ,HD_2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HDCOMP_FMT ,HD COMP format" "Progressive,Interlace"
|
|
bitfld.long 0x00 8. " HDCOMP_ENABLE ,HD COMP enable" "Disabled,Enabled"
|
|
sif (cpu()!="C6A8143")
|
|
bitfld.long 0x00 1. " HDMI_FMT ,HD HDMI format" "Progressive,Interlace"
|
|
bitfld.long 0x00 0. " HDMI_ENABLE ,HD HDMI enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="C6A8143")
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x00 "HDMI_VOUT1_SETT,COMP HDMI/VOUT1 Settings Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x08++0x3
|
|
hide.long 0x00 "VOUT0_SETT,COMP VOUT0 Settings Register"
|
|
in
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x00 "SD_SETT,COMP SD Settings Register"
|
|
in
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "BACKGROUND,COMP Background Color Register"
|
|
hexmask.long 0x00 0.--29. 1. " BACKGROUND_COLOR ,Default background color"
|
|
width 11.
|
|
tree.end
|
|
tree "CSC_R2Y"
|
|
base ad:0x48105300
|
|
width 7.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "CSC00,CSC_R2Y Coefficients of Color Space Converter Register 0"
|
|
hexmask.long.word 0x00 16.--28. 1. " B0 ,B0 coefficient of color space converter"
|
|
hexmask.long.word 0x00 0.--12. 1. " A0 ,A0 coefficient of color space converter"
|
|
line.long 0x04 "CSC01,CSC_R2Y Coefficients of Color Space Converter Register 1"
|
|
hexmask.long.word 0x04 16.--28. 1. " A1 ,A1 coefficient of color space converter"
|
|
hexmask.long.word 0x04 0.--12. 1. " C0 ,C0 coefficient of color space converter"
|
|
line.long 0x08 "CSC02,CSC_R2Y Coefficients of Color Space Converter Register 2"
|
|
hexmask.long.word 0x08 16.--28. 1. " C1 ,C1 coefficient of color space converter"
|
|
hexmask.long.word 0x08 0.--12. 1. " B1 ,B1 coefficient of color space converter"
|
|
line.long 0x0c "CSC03,CSC_R2Y Coefficients of Color Space Converter Register 3"
|
|
hexmask.long.word 0x0c 16.--28. 1. " B2 ,B2 coefficient of color space converter"
|
|
hexmask.long.word 0x0c 0.--12. 1. " A2 ,A2 coefficient of color space converter"
|
|
line.long 0x10 "CSC04,CSC_R2Y Coefficients of Color Space Converter Register 4"
|
|
hexmask.long.word 0x10 16.--27. 1. " D0 ,D0 coefficient of color space converter"
|
|
hexmask.long.word 0x10 0.--12. 1. " C2 ,C2 coefficient of color space converter"
|
|
line.long 0x14 "CSC05,CSC_R2Y Coefficients of Color Space Converter Register 5"
|
|
bitfld.long 0x14 28. " BYPASS ,Full CSC bypass mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x14 16.--27. 1. " D2 ,D2 coefficient of color space converter"
|
|
hexmask.long.word 0x14 0.--11. 1. " D1 ,D1 coefficient of color space converter"
|
|
width 11.
|
|
tree.end
|
|
tree "CHR_US_IND1"
|
|
base ad:0x48105400
|
|
width 6.
|
|
group.long 0x04++0x1f
|
|
line.long 0x00 "REG0,CHR_US_IND1 REG0 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " ANCHOR_FID0_C0 ,C0 coefficient for Anchor Pixel"
|
|
bitfld.long 0x00 16.--17. " CFG_MODE ,Configuration Mode" "Mode A,Mode B,Mode C,Mode D"
|
|
hexmask.long.word 0x00 2.--15. 1. " ANCHOR_FID0_C1 ,C1 coefficient for Anchor Pixel"
|
|
line.long 0x04 "REG1,CHR_US_IND1 REG1 Register"
|
|
hexmask.long.word 0x04 18.--31. 1. " ANCHOR_FID0_C2 ,C2 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x04 2.--15. 1. " ANCHOR_FID0_C3 ,C3 coefficient for Anchor Pixel"
|
|
line.long 0x08 "REG2,CHR_US_IND1 REG2 Register"
|
|
hexmask.long.word 0x08 18.--31. 1. " INTERP_FID0_C0 ,C0 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x08 2.--15. 1. " INTERP_FID0_C1 ,C1 coefficient for Interpolated Pixel"
|
|
line.long 0x0c "REG3,CHR_US_IND1 REG3 Register"
|
|
hexmask.long.word 0x0c 18.--31. 1. " INTERP_FID0_C2 ,C2 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x0c 2.--15. 1. " INTERP_FID0_C3 ,C3 coefficient for Interpolated Pixel"
|
|
line.long 0x10 "REG4,CHR_US_IND1 REG4 Register"
|
|
hexmask.long.word 0x10 18.--31. 1. " ANCHOR_FID1_C0 ,C0 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x10 2.--15. 1. " ANCHOR_FID1_C1 ,C1 coefficient for Anchor Pixel"
|
|
line.long 0x14 "REG5,CHR_US_IND1 REG5 Register"
|
|
hexmask.long.word 0x14 18.--31. 1. " ANCHOR_FID1_C2 ,C2 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x14 2.--15. 1. " ANCHOR_FID1_C3 ,C3 coefficient for Anchor Pixel"
|
|
line.long 0x18 "REG6,CHR_US_IND1 REG6 Register"
|
|
hexmask.long.word 0x18 18.--31. 1. " INTERP_FID1_C0 ,C0 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x18 2.--15. 1. " INTERP_FID1_C1 ,C1 coefficient for Interpolated Pixel"
|
|
line.long 0x1c "REG7,CHR_US_IND1 REG7 Register"
|
|
hexmask.long.word 0x1c 18.--31. 1. " INTERP_FID1_C2 ,C2 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x1c 2.--15. 1. " INTERP_FID1_C3 ,C3 coefficient for Interpolated Pixel"
|
|
width 11.
|
|
tree.end
|
|
tree "CHR_US_IND2"
|
|
base ad:0x48105480
|
|
width 6.
|
|
group.long 0x04++0x1f
|
|
line.long 0x00 "REG0,CHR_US_IND2 REG0 Register"
|
|
hexmask.long.word 0x00 18.--31. 1. " ANCHOR_FID0_C0 ,C0 coefficient for Anchor Pixel"
|
|
bitfld.long 0x00 16.--17. " CFG_MODE ,Configuration Mode" "Mode A,Mode B,Mode C,Mode D"
|
|
hexmask.long.word 0x00 2.--15. 1. " ANCHOR_FID0_C1 ,C1 coefficient for Anchor Pixel"
|
|
line.long 0x04 "REG1,CHR_US_IND2 REG1 Register"
|
|
hexmask.long.word 0x04 18.--31. 1. " ANCHOR_FID0_C2 ,C2 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x04 2.--15. 1. " ANCHOR_FID0_C3 ,C3 coefficient for Anchor Pixel"
|
|
line.long 0x08 "REG2,CHR_US_IND2 REG2 Register"
|
|
hexmask.long.word 0x08 18.--31. 1. " INTERP_FID0_C0 ,C0 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x08 2.--15. 1. " INTERP_FID0_C1 ,C1 coefficient for Interpolated Pixel"
|
|
line.long 0x0c "REG3,CHR_US_IND2 REG3 Register"
|
|
hexmask.long.word 0x0c 18.--31. 1. " INTERP_FID0_C2 ,C2 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x0c 2.--15. 1. " INTERP_FID0_C3 ,C3 coefficient for Interpolated Pixel"
|
|
line.long 0x10 "REG4,CHR_US_IND2 REG4 Register"
|
|
hexmask.long.word 0x10 18.--31. 1. " ANCHOR_FID1_C0 ,C0 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x10 2.--15. 1. " ANCHOR_FID1_C1 ,C1 coefficient for Anchor Pixel"
|
|
line.long 0x14 "REG5,CHR_US_IND2 REG5 Register"
|
|
hexmask.long.word 0x14 18.--31. 1. " ANCHOR_FID1_C2 ,C2 coefficient for Anchor Pixel"
|
|
hexmask.long.word 0x14 2.--15. 1. " ANCHOR_FID1_C3 ,C3 coefficient for Anchor Pixel"
|
|
line.long 0x18 "REG6,CHR_US_IND2 REG6 Register"
|
|
hexmask.long.word 0x18 18.--31. 1. " INTERP_FID1_C0 ,C0 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x18 2.--15. 1. " INTERP_FID1_C1 ,C1 coefficient for Interpolated Pixel"
|
|
line.long 0x1c "REG7,CHR_US_IND2 REG7 Register"
|
|
hexmask.long.word 0x1c 18.--31. 1. " INTERP_FID1_C2 ,C2 coefficient for Interpolated Pixel"
|
|
hexmask.long.word 0x1c 2.--15. 1. " INTERP_FID1_C3 ,C3 coefficient for Interpolated Pixel"
|
|
width 11.
|
|
tree.end
|
|
sif (cpu()!="C6A8143")
|
|
tree "VIN0_PARSER"
|
|
base ad:0x48105500
|
|
width 13.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "MAIN_CONFIG,VIN0 Parser Main Configuration Register"
|
|
bitfld.long 0x00 5. " CLIP_ACTIVE ,Clip Active Pixels" "Not clipped,Clipped"
|
|
bitfld.long 0x00 4. " CLIP_BLNK ,Clip Blanking Data" "Not clipped,Clipped"
|
|
bitfld.long 0x00 0.--1. " DATA_INTERFACE_MODE ,Data Interface Mode" "24b,16b,Dual 8b,?..."
|
|
group.long 0x14++0xb
|
|
line.long 0x00 "FIQ_MASK,VIN0_PARSER FIQ Mask Register"
|
|
bitfld.long 0x00 15. " PRTBSRC0SIZE ,Port B Src0 Unexpected Size Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " PRTASRC0SIZE ,Port A Src0 Unexpected Size Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PRTBDISCONN ,Port B Link Disconnnect Srcnum 0 Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " PRTBCONN ,Port B Link Connect Srcnum 0 Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PRTADISCONN ,Port A Link Disconnect Srcnum 0 Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " PRTACONN ,Port A Link Connect Srcnum 0 Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OUTPUT_FIFO_PRTB_ANC_OF ,Output FIFO Port B Ancillary Overflow Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " OUTPUT_FIFO_PRTB_YUV_OF ,Output FIFO Port B Luma Overflow Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OUTPUT_FIFO_PRTA_ANC_OF ,Output FIFO Port A Ancillary Overflow Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " OUTPUT_FIFO_PRTA_YUV_OF ,Output FIFO Port A Luma Overflow Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASYNC_FIFO_PRTB_OF ,Port B Async FIFO Overflow FIQ Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " ASYNC_FIFO_PRTA_OF ,Port A Async FIFO Overflow FIQ Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PRTB_VDET_MASK ,Port B Video Detect FIQ Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " PRTA_VDET_MASK ,Port A Video Detect FIQ Mask" "Not masked,Masked"
|
|
line.long 0x04 "FIQ_CLR,VIN0_PARSER FIQ Clear Register"
|
|
bitfld.long 0x04 15. " PRTBSRC0SIZECLR ,Port B Src0 Unexpected Size Clear" "No effect,Clear"
|
|
bitfld.long 0x04 14. " PRTASRC0SIZECLR ,Port A Src0 Unexpected Size Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PRTBDISCONNCLR ,Port B Link Disconnnect Srcnum 0 Clear" "No effect,Clear"
|
|
bitfld.long 0x04 12. " PRTBCONNCLR ,Port B Link Connect Srcnum 0 Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PRTADISCONNCLR ,Port A Link Disconnect Srcnum 0 Clear" "No effect,Clear"
|
|
bitfld.long 0x04 10. " PRTACONNCLR ,Port A Link Connect Srcnum 0 Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OUTPUT_FIFO_PRTB_ANC_CLR ,Output FIFO Port B Ancillary Overflow Clear" "No effect,Clear"
|
|
bitfld.long 0x04 7. " OUTPUT_FIFO_PRTB_YUV_CLR ,Output FIFO Port B Luma Overflow Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OUTPUT_FIFO_PRTA_ANC_CLR ,Output FIFO Port A Ancillary Overflow Clear" "No effect,Clear"
|
|
bitfld.long 0x04 4. " OUTPUT_FIFO_PRTA_YUV_CLR ,Output FIFO Port A Luma Overflow Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ASYNC_FIFO_PRTB_CLR ,Port B Async FIFO Overflow FIQ Clear" "No effect,Clear"
|
|
bitfld.long 0x04 2. " ASYNC_FIFO_PRTA_CLR ,Port A Async FIFO Overflow FIQ Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PRTB_VDET_CLR ,Port B Video Detect FIQ Clear" "No effect,Clear"
|
|
bitfld.long 0x04 0. " PRTA_VDET_CLR ,Port A Video Detect FIQ Clear" "No effect,Clear"
|
|
line.long 0x08 "FIQ_STS,VIN0_PARSER FIQ Status Register"
|
|
bitfld.long 0x08 15. " PRTBSRC0SIZESTATUS ,Port B Src0 Unexpected Size Status" "Low,High"
|
|
bitfld.long 0x08 14. " PRTASRC0SIZESTATUS ,Port A Src0 Unexpected Size Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 13. " PRTBDISCONNSTATUS ,Port B Link Disconnnect Srcnum 0 Status" "Low,High"
|
|
bitfld.long 0x08 12. " PRTBCONNSTATUS ,Port B Link Connect Srcnum 0 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 11. " PRTADISCONNSTATUS ,Port A Link Disconnect Srcnum 0 Status" "Low,High"
|
|
bitfld.long 0x08 10. " PRTACONNSTATUS ,Port A Link Connect Srcnum 0 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OUTPUT_FIFO_PRTB_ANC_STATUS ,Output FIFO Port B Ancillary Overflow Status" "Low,High"
|
|
bitfld.long 0x08 7. " OUTPUT_FIFO_PRTB_YUV_STATUS ,Output FIFO Port B Luma Overflow Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 6. " OUTPUT_FIFO_PRTA_ANC_STATUS ,Output FIFO Port A Ancillary Overflow Status" "Low,High"
|
|
bitfld.long 0x08 4. " OUTPUT_FIFO_PRTA_YUV_STATUS ,Output FIFO Port A Luma Overflow Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ASYNC_FIFO_PRTB_STATUS ,Port B Async FIFO Overflow FIQ Status" "Low,High"
|
|
bitfld.long 0x08 2. " ASYNC_FIFO_PRTA_STATUS ,Port A Async FIFO Overflow FIQ Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PRTB_VDET_STATUS ,Port B Video Detect FIQ Status" "Low,High"
|
|
bitfld.long 0x08 0. " PRTA_VDET_STATUS ,Port A Video Detect FIQ Status" "Low,High"
|
|
width 16.
|
|
tree "PORT A"
|
|
if ((d.l(ad:0x48105500+0x04)&0xf)==(0x0||0x1||0x2||0x3||0x5||0x6||0x7||0x8))
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "PORTA_CONFIG0,VIN0_PARSER Configuration for Input Port A Register 0"
|
|
bitfld.long 0x00 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Error correction for the fvh control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ANALYZER_2X4X_SRCNUM_POS ,Srcnum position in 2x/4x mux mode (least significant nibble of)" "XV/fvh codeword,Horizontal blanking pixel value"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PIXCLK_EDGE_POLARITY ,PIXCLK edge polarity" "Rising,Falling"
|
|
bitfld.long 0x00 9. " FID_POLARITY ,Invert Determined Value of FID" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE ,Enable the port" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CLR_ASYNC_FIFO_RD ,Clear Async FIFO Read Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLR_ASYNC_FIFO_WR ,Clear Async FIFO Write Logic" "No effect,Clear"
|
|
bitfld.long 0x00 4.--5. " CTRL_CHAN_SEL ,Channel select" "Data[7:0] (8b/16b/24b),Data[15:8] (16b/24b),Data[23:16] (24b),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SYNC_TYPE ,Sync type" "Embedded sync single 4:2:2 YUV stream,Embedded sync 2x multiplexed 4:2:2 YUV stream,Embedded sync 4x multiplexed 4:2:2 YUV stream,Embedded sync line multiplexed 4:2:2 YUV stream,Discrete sync single 4:2:2 YUV stream,Embedded sync single RGB stream or single 444 YUV stream,Embedded sync 2x multiplexed RGB stream,Embedded sync 4x multiplexed RGB stream,Embedded sync line multiplexed RGB stream,Discrete sync single 8b RGB stream,Discrete sync single 24b RGB stream,?..."
|
|
elif ((d.l(ad:0x48105500+0x04)&0xf)==(0x4||0x9||0xa))
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "PORTA_CONFIG0,VIN0_PARSER Configuration for Input Port A Register 0"
|
|
bitfld.long 0x00 24.--29. " FID_SKEW_POSTCOUNT ,Post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 22. " DISCRETE_BASIC_MODE ,Discrete Mode" "Normal,Basic"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " FID_SKEW_PRECOUNT ,Pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15. " USE_ACTVID_HSYNC_N ,Line capture style" "HSYNC,ACTVID"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FID_DETECT_MODE ,FID detection mode" "Pin,VSYNC skew"
|
|
bitfld.long 0x00 13. " ACTVID_POLARITY ,ACTVID polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " VSYNC_POLARITY ,VSYNC polarity" "Low,High"
|
|
bitfld.long 0x00 11. " HSYNC_POLARITY ,HSYNC polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PIXCLK_EDGE_POLARITY ,PIXCLK edge polarity" "Rising,Falling"
|
|
bitfld.long 0x00 9. " FID_POLARITY ,Invert Determined Value of FID" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE ,Enable the port" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CLR_ASYNC_FIFO_RD ,Clear Async FIFO Read Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLR_ASYNC_FIFO_WR ,Clear Async FIFO Write Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SYNC_TYPE ,Sync type" "Embedded sync single 4:2:2 YUV stream,Embedded sync 2x multiplexed 4:2:2 YUV stream,Embedded sync 4x multiplexed 4:2:2 YUV stream,Embedded sync line multiplexed 4:2:2 YUV stream,Discrete sync single 4:2:2 YUV stream,Embedded sync single RGB stream or single 444 YUV stream,Embedded sync 2x multiplexed RGB stream,Embedded sync 4x multiplexed RGB stream,Embedded sync line multiplexed RGB stream,Discrete sync single 8b RGB stream,Discrete sync single 24b RGB stream,?..."
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "PORTA_CONFIG0,VIN0_PARSER Configuration for Input Port A Register 0"
|
|
bitfld.long 0x00 10. " PIXCLK_EDGE_POLARITY ,PIXCLK edge polarity" "Rising,Falling"
|
|
bitfld.long 0x00 9. " FID_POLARITY ,Invert Determined Value of FID" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE ,Enable the port" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CLR_ASYNC_FIFO_RD ,Clear Async FIFO Read Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLR_ASYNC_FIFO_WR ,Clear Async FIFO Write Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SYNC_TYPE ,Sync type" "Embedded sync single 4:2:2 YUV stream,Embedded sync 2x multiplexed 4:2:2 YUV stream,Embedded sync 4x multiplexed 4:2:2 YUV stream,Embedded sync line multiplexed 4:2:2 YUV stream,Discrete sync single 4:2:2 YUV stream,Embedded sync single RGB stream or single 444 YUV stream,Embedded sync 2x multiplexed RGB stream,Embedded sync 4x multiplexed RGB stream,Embedded sync line multiplexed RGB stream,Discrete sync single 8b RGB stream,Discrete sync single 24b RGB stream,?..."
|
|
endif
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "PORTA_CONFIG1,VIN0_PARSER Configuration for Input Port A Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " SRC0_NUMPIX ,Expected number of Pixels per Line for Src0"
|
|
bitfld.long 0x00 13.--14. " ANC_CHAN_SEL_8B ,Vertically Ancillary Data Extraction Source (In 8b mode)" "Luma,Chroma,Both,Both"
|
|
hexmask.long.word 0x00 0.--10. 1. " SRC0_NUMLINES ,Expected number of Lines for Src0"
|
|
width 16.
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x00 "PORTA_SRC,VIN0_PARSER Port A Source FID Register"
|
|
bitfld.long 0x00 31. " PRTA_SRC15_CURR_SOURCE_FID ,Source Field ID 15 for Current Field" "0,1"
|
|
bitfld.long 0x00 30. " PRTA_SRC15_PREV_SOURCE_FID ,Source Field ID 15 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PRTA_SRC14_CURR_SOURCE_FID ,Source Field ID 14 for Current Field" "0,1"
|
|
bitfld.long 0x00 28. " PRTA_SRC14_PREV_SOURCE_FID ,Source Field ID 14 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PRTA_SRC13_CURR_SOURCE_FID ,Source Field ID 13 for Current Field" "0,1"
|
|
bitfld.long 0x00 26. " PRTA_SRC13_PREV_SOURCE_FID ,Source Field ID 13 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PRTA_SRC12_CURR_SOURCE_FID ,Source Field ID 12 for Current Field" "0,1"
|
|
bitfld.long 0x00 24. " PRTA_SRC12_PREV_SOURCE_FID ,Source Field ID 12 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PRTA_SRC11_CURR_SOURCE_FID ,Source Field ID 11 for Current Field" "0,1"
|
|
bitfld.long 0x00 22. " PRTA_SRC11_PREV_SOURCE_FID ,Source Field ID 11 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PRTA_SRC10_CURR_SOURCE_FID ,Source Field ID 10 for Current Field" "0,1"
|
|
bitfld.long 0x00 20. " PRTA_SRC10_PREV_SOURCE_FID ,Source Field ID 10 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PRTA_SRC9_CURR_SOURCE_FID ,Source Field ID 9 for Current Field" "0,1"
|
|
bitfld.long 0x00 18. " PRTA_SRC9_PREV_SOURCE_FID ,Source Field ID 9 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PRTA_SRC8_CURR_SOURCE_FID ,Source Field ID 8 for Current Field" "0,1"
|
|
bitfld.long 0x00 16. " PRTA_SRC8_PREV_SOURCE_FID ,Source Field ID 8 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PRTA_SRC7_CURR_SOURCE_FID ,Source Field ID 7 for Current Field" "0,1"
|
|
bitfld.long 0x00 14. " PRTA_SRC7_PREV_SOURCE_FID ,Source Field ID 7 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PRTA_SRC6_CURR_SOURCE_FID ,Source Field ID 6 for Current Field" "0,1"
|
|
bitfld.long 0x00 12. " PRTA_SRC6_PREV_SOURCE_FID ,Source Field ID 6 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PRTA_SRC5_CURR_SOURCE_FID ,Source Field ID 5 for Current Field" "0,1"
|
|
bitfld.long 0x00 10. " PRTA_SRC5_PREV_SOURCE_FID ,Source Field ID 5 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PRTA_SRC4_CURR_SOURCE_FID ,Source Field ID 4 for Current Field" "0,1"
|
|
bitfld.long 0x00 8. " PRTA_SRC4_PREV_SOURCE_FID ,Source Field ID 4 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PRTA_SRC3_CURR_SOURCE_FID ,Source Field ID 3 for Current Field" "0,1"
|
|
bitfld.long 0x00 6. " PRTA_SRC3_PREV_SOURCE_FID ,Source Field ID 3 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PRTA_SRC2_CURR_SOURCE_FID ,Source Field ID 2 for Current Field" "0,1"
|
|
bitfld.long 0x00 4. " PRTA_SRC2_PREV_SOURCE_FID ,Source Field ID 2 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PRTA_SRC1_CURR_SOURCE_FID ,Source Field ID 1 for Current Field" "0,1"
|
|
bitfld.long 0x00 2. " PRTA_SRC1_PREV_SOURCE_FID ,Source Field ID 1 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PRTA_SRC0_CURR_SOURCE_FID ,Source Field ID 0 for Current Field" "0,1"
|
|
bitfld.long 0x00 0. " PRTA_SRC0_PREV_SOURCE_FID ,Source Field ID 0 for Previous Field" "0,1"
|
|
line.long 0x04 "PORTA_ENC,VIN0_PARSER Port A Encoder FID Register"
|
|
bitfld.long 0x04 31. " PRTA_SRC15_CURR_ENC_FID ,Encoder Field ID 15 for Current Field" "0,1"
|
|
bitfld.long 0x04 30. " PRTA_SRC15_PREV_ENC_FID ,Encoder Field ID 15 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 29. " PRTA_SRC14_CURR_ENC_FID ,Encoder Field ID 14 for Current Field" "0,1"
|
|
bitfld.long 0x04 28. " PRTA_SRC14_PREV_ENC_FID ,Encoder Field ID 14 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PRTA_SRC13_CURR_ENC_FID ,Encoder Field ID 13 for Current Field" "0,1"
|
|
bitfld.long 0x04 26. " PRTA_SRC13_PREV_ENC_FID ,Encoder Field ID 13 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 25. " PRTA_SRC12_CURR_ENC_FID ,Encoder Field ID 12 for Current Field" "0,1"
|
|
bitfld.long 0x04 24. " PRTA_SRC12_PREV_ENC_FID ,Encoder Field ID 12 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PRTA_SRC11_CURR_ENC_FID ,Encoder Field ID 11 for Current Field" "0,1"
|
|
bitfld.long 0x04 22. " PRTA_SRC11_PREV_ENC_FID ,Encoder Field ID 11 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 21. " PRTA_SRC10_CURR_ENC_FID ,Encoder Field ID 10 for Current Field" "0,1"
|
|
bitfld.long 0x04 20. " PRTA_SRC10_PREV_ENC_FID ,Encoder Field ID 10 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PRTA_SRC9_CURR_ENC_FID ,Encoder Field ID 9 for Current Field" "0,1"
|
|
bitfld.long 0x04 18. " PRTA_SRC9_PREV_ENC_FID ,Encoder Field ID 9 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " PRTA_SRC8_CURR_ENC_FID ,Encoder Field ID 8 for Current Field" "0,1"
|
|
bitfld.long 0x04 16. " PRTA_SRC8_PREV_ENC_FID ,Encoder Field ID 8 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 15. " PRTA_SRC7_CURR_ENC_FID ,Encoder Field ID 7 for Current Field" "0,1"
|
|
bitfld.long 0x04 14. " PRTA_SRC7_PREV_ENC_FID ,Encoder Field ID 7 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PRTA_SRC6_CURR_ENC_FID ,Encoder Field ID 6 for Current Field" "0,1"
|
|
bitfld.long 0x04 12. " PRTA_SRC6_PREV_ENC_FID ,Encoder Field ID 6 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PRTA_SRC5_CURR_ENC_FID ,Encoder Field ID 5 for Current Field" "0,1"
|
|
bitfld.long 0x04 10. " PRTA_SRC5_PREV_ENC_FID ,Encoder Field ID 5 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PRTA_SRC4_CURR_ENC_FID ,Encoder Field ID 4 for Current Field" "0,1"
|
|
bitfld.long 0x04 8. " PRTA_SRC4_PREV_ENC_FID ,Encoder Field ID 4 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PRTA_SRC3_CURR_ENC_FID ,Encoder Field ID 3 for Current Field" "0,1"
|
|
bitfld.long 0x04 6. " PRTA_SRC3_PREV_ENC_FID ,Encoder Field ID 3 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PRTA_SRC2_CURR_ENC_FID ,Encoder Field ID 2 for Current Field" "0,1"
|
|
bitfld.long 0x04 4. " PRTA_SRC2_PREV_ENC_FID ,Encoder Field ID 2 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PRTA_SRC1_CURR_ENC_FID ,Encoder Field ID 1 for Current Field" "0,1"
|
|
bitfld.long 0x04 2. " PRTA_SRC1_PREV_ENC_FID ,Encoder Field ID 1 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PRTA_SRC0_CURR_ENC_FID ,Encoder Field ID 0 for Current Field" "0,1"
|
|
bitfld.long 0x04 0. " PRTA_SRC0_PREV_ENC_FID ,Encoder Field ID 0 for Previous Field" "0,1"
|
|
width 16.
|
|
group.long 0x30++0x3f
|
|
line.long 0x0 "PORTA_SRC0_SZ,VIN0_PARSER Output Port A Source 0 Size"
|
|
hexmask.long.word 0x0 16.--26. 1. " WIDTH ,Source 0 width"
|
|
hexmask.long.word 0x0 0.--10. 1. " HEIGHT ,Source 0 height"
|
|
line.long 0x4 "PORTA_SRC1_SZ,VIN0_PARSER Output Port A Source 1 Size"
|
|
hexmask.long.word 0x4 16.--26. 1. " WIDTH ,Source 1 width"
|
|
hexmask.long.word 0x4 0.--10. 1. " HEIGHT ,Source 1 height"
|
|
line.long 0x8 "PORTA_SRC2_SZ,VIN0_PARSER Output Port A Source 2 Size"
|
|
hexmask.long.word 0x8 16.--26. 1. " WIDTH ,Source 2 width"
|
|
hexmask.long.word 0x8 0.--10. 1. " HEIGHT ,Source 2 height"
|
|
line.long 0xC "PORTA_SRC3_SZ,VIN0_PARSER Output Port A Source 3 Size"
|
|
hexmask.long.word 0xC 16.--26. 1. " WIDTH ,Source 3 width"
|
|
hexmask.long.word 0xC 0.--10. 1. " HEIGHT ,Source 3 height"
|
|
line.long 0x10 "PORTA_SRC4_SZ,VIN0_PARSER Output Port A Source 4 Size"
|
|
hexmask.long.word 0x10 16.--26. 1. " WIDTH ,Source 4 width"
|
|
hexmask.long.word 0x10 0.--10. 1. " HEIGHT ,Source 4 height"
|
|
line.long 0x14 "PORTA_SRC5_SZ,VIN0_PARSER Output Port A Source 5 Size"
|
|
hexmask.long.word 0x14 16.--26. 1. " WIDTH ,Source 5 width"
|
|
hexmask.long.word 0x14 0.--10. 1. " HEIGHT ,Source 5 height"
|
|
line.long 0x18 "PORTA_SRC6_SZ,VIN0_PARSER Output Port A Source 6 Size"
|
|
hexmask.long.word 0x18 16.--26. 1. " WIDTH ,Source 6 width"
|
|
hexmask.long.word 0x18 0.--10. 1. " HEIGHT ,Source 6 height"
|
|
line.long 0x1C "PORTA_SRC7_SZ,VIN0_PARSER Output Port A Source 7 Size"
|
|
hexmask.long.word 0x1C 16.--26. 1. " WIDTH ,Source 7 width"
|
|
hexmask.long.word 0x1C 0.--10. 1. " HEIGHT ,Source 7 height"
|
|
line.long 0x20 "PORTA_SRC8_SZ,VIN0_PARSER Output Port A Source 8 Size"
|
|
hexmask.long.word 0x20 16.--26. 1. " WIDTH ,Source 8 width"
|
|
hexmask.long.word 0x20 0.--10. 1. " HEIGHT ,Source 8 height"
|
|
line.long 0x24 "PORTA_SRC9_SZ,VIN0_PARSER Output Port A Source 9 Size"
|
|
hexmask.long.word 0x24 16.--26. 1. " WIDTH ,Source 9 width"
|
|
hexmask.long.word 0x24 0.--10. 1. " HEIGHT ,Source 9 height"
|
|
line.long 0x28 "PORTA_SRC10_SZ,VIN0_PARSER Output Port A Source 10 Size"
|
|
hexmask.long.word 0x28 16.--26. 1. " WIDTH ,Source 10 width"
|
|
hexmask.long.word 0x28 0.--10. 1. " HEIGHT ,Source 10 height"
|
|
line.long 0x2C "PORTA_SRC11_SZ,VIN0_PARSER Output Port A Source 11 Size"
|
|
hexmask.long.word 0x2C 16.--26. 1. " WIDTH ,Source 11 width"
|
|
hexmask.long.word 0x2C 0.--10. 1. " HEIGHT ,Source 11 height"
|
|
line.long 0x30 "PORTA_SRC12_SZ,VIN0_PARSER Output Port A Source 12 Size"
|
|
hexmask.long.word 0x30 16.--26. 1. " WIDTH ,Source 12 width"
|
|
hexmask.long.word 0x30 0.--10. 1. " HEIGHT ,Source 12 height"
|
|
line.long 0x34 "PORTA_SRC13_SZ,VIN0_PARSER Output Port A Source 13 Size"
|
|
hexmask.long.word 0x34 16.--26. 1. " WIDTH ,Source 13 width"
|
|
hexmask.long.word 0x34 0.--10. 1. " HEIGHT ,Source 13 height"
|
|
line.long 0x38 "PORTA_SRC14_SZ,VIN0_PARSER Output Port A Source 14 Size"
|
|
hexmask.long.word 0x38 16.--26. 1. " WIDTH ,Source 14 width"
|
|
hexmask.long.word 0x38 0.--10. 1. " HEIGHT ,Source 14 height"
|
|
line.long 0x3C "PORTA_SRC15_SZ,VIN0_PARSER Output Port A Source 15 Size"
|
|
hexmask.long.word 0x3C 16.--26. 1. " WIDTH ,Source 15 width"
|
|
hexmask.long.word 0x3C 0.--10. 1. " HEIGHT ,Source 15 height"
|
|
if ((d.l(ad:0x48105500+0x04)&0xf)==(0x0||0x1||0x2||0x3||0x5||0x6||0x7||0x8))
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "PORTA_DETVEC,VIN0_PARSER Port A Detector Vector"
|
|
else
|
|
hgroup.long 0xb0++0x3
|
|
hide.long 0x00 "PORTA_DETVEC,VIN0_PARSER Port A Detector Vector"
|
|
endif
|
|
tree.end
|
|
width 16.
|
|
tree "PORT B"
|
|
if ((d.l(ad:0x48105500+0x0c)&0xf)==(0x0||0x1||0x2||0x3||0x5||0x6||0x7||0x8))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "PORTB_CONFIG0,VIN0_PARSER Configuration for Input Port B Register 0"
|
|
bitfld.long 0x00 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Error correction for the fvh control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ANALYZER_2X4X_SRCNUM_POS ,Srcnum position in 2x/4x mux mode (least significant nibble of)" "XV/fvh codeword,Horizontal blanking pixel value"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PIXCLK_EDGE_POLARITY ,PIXCLK edge polarity" "Rising,Falling"
|
|
bitfld.long 0x00 9. " FID_POLARITY ,Invert Determined Value of FID" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE ,Enable the port" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CLR_ASYNC_FIFO_RD ,Clear Async FIFO Read Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLR_ASYNC_FIFO_WR ,Clear Async FIFO Write Logic" "No effect,Clear"
|
|
bitfld.long 0x00 4.--5. " CTRL_CHAN_SEL ,Channel select" "Data[7:0] (8b/16b/24b),Data[15:8] (16b/24b),Data[23:16] (24b),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SYNC_TYPE ,Sync type" "Embedded sync single 4:2:2 YUV stream,Embedded sync 2x multiplexed 4:2:2 YUV stream,Embedded sync 4x multiplexed 4:2:2 YUV stream,Embedded sync line multiplexed 4:2:2 YUV stream,Discrete sync single 4:2:2 YUV stream,Embedded sync single RGB stream or single 444 YUV stream,Embedded sync 2x multiplexed RGB stream,Embedded sync 4x multiplexed RGB stream,Embedded sync line multiplexed RGB stream,Discrete sync single 8b RGB stream,Discrete sync single 24b RGB stream,?..."
|
|
elif ((d.l(ad:0x48105500+0x0c)&0xf)==(0x4||0x9||0xa))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "PORTB_CONFIG0,VIN0_PARSER Configuration for Input Port B Register 0"
|
|
bitfld.long 0x00 24.--29. " FID_SKEW_POSTCOUNT ,Post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 22. " DISCRETE_BASIC_MODE ,Discrete Mode" "Normal,Basic"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " FID_SKEW_PRECOUNT ,Pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15. " USE_ACTVID_HSYNC_N ,Line capture style" "HSYNC,ACTVID"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FID_DETECT_MODE ,FID detection mode" "Pin,VSYNC skew"
|
|
bitfld.long 0x00 13. " ACTVID_POLARITY ,ACTVID polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " VSYNC_POLARITY ,VSYNC polarity" "Low,High"
|
|
bitfld.long 0x00 11. " HSYNC_POLARITY ,HSYNC polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PIXCLK_EDGE_POLARITY ,PIXCLK edge polarity" "Rising,Falling"
|
|
bitfld.long 0x00 9. " FID_POLARITY ,Invert Determined Value of FID" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE ,Enable the port" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CLR_ASYNC_FIFO_RD ,Clear Async FIFO Read Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLR_ASYNC_FIFO_WR ,Clear Async FIFO Write Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SYNC_TYPE ,Sync type" "Embedded sync single 4:2:2 YUV stream,Embedded sync 2x multiplexed 4:2:2 YUV stream,Embedded sync 4x multiplexed 4:2:2 YUV stream,Embedded sync line multiplexed 4:2:2 YUV stream,Discrete sync single 4:2:2 YUV stream,Embedded sync single RGB stream or single 444 YUV stream,Embedded sync 2x multiplexed RGB stream,Embedded sync 4x multiplexed RGB stream,Embedded sync line multiplexed RGB stream,Discrete sync single 8b RGB stream,Discrete sync single 24b RGB stream,?..."
|
|
else
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "PORTB_CONFIG0,VIN0_PARSER Configuration for Input Port B Register 0"
|
|
bitfld.long 0x00 10. " PIXCLK_EDGE_POLARITY ,PIXCLK edge polarity" "Rising,Falling"
|
|
bitfld.long 0x00 9. " FID_POLARITY ,Invert Determined Value of FID" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE ,Enable the port" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CLR_ASYNC_FIFO_RD ,Clear Async FIFO Read Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLR_ASYNC_FIFO_WR ,Clear Async FIFO Write Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SYNC_TYPE ,Sync type" "Embedded sync single 4:2:2 YUV stream,Embedded sync 2x multiplexed 4:2:2 YUV stream,Embedded sync 4x multiplexed 4:2:2 YUV stream,Embedded sync line multiplexed 4:2:2 YUV stream,Discrete sync single 4:2:2 YUV stream,Embedded sync single RGB stream or single 444 YUV stream,Embedded sync 2x multiplexed RGB stream,Embedded sync 4x multiplexed RGB stream,Embedded sync line multiplexed RGB stream,Discrete sync single 8b RGB stream,Discrete sync single 24b RGB stream,?..."
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "PORTB_CONFIG1,VIN0_PARSER Configuration for Input Port B Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " SRC0_NUMPIX ,Expected number of Pixels per Line for Src0"
|
|
bitfld.long 0x00 13.--14. " ANC_CHAN_SEL_8B ,Vertically Ancillary Data Extraction Source (In 8b mode)" "Luma,Chroma,Both,Both"
|
|
hexmask.long.word 0x00 0.--10. 1. " SRC0_NUMLINES ,Expected number of Lines for Src0"
|
|
width 16.
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x00 "PORTB_SRC,VIN0_PARSER Port B Source FID Register"
|
|
bitfld.long 0x00 31. " PRTB_SRC15_CURR_SOURCE_FID ,Source Field ID 15 for Current Field" "0,1"
|
|
bitfld.long 0x00 30. " PRTB_SRC15_PREV_SOURCE_FID ,Source Field ID 15 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PRTB_SRC14_CURR_SOURCE_FID ,Source Field ID 14 for Current Field" "0,1"
|
|
bitfld.long 0x00 28. " PRTB_SRC14_PREV_SOURCE_FID ,Source Field ID 14 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PRTB_SRC13_CURR_SOURCE_FID ,Source Field ID 13 for Current Field" "0,1"
|
|
bitfld.long 0x00 26. " PRTB_SRC13_PREV_SOURCE_FID ,Source Field ID 13 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PRTB_SRC12_CURR_SOURCE_FID ,Source Field ID 12 for Current Field" "0,1"
|
|
bitfld.long 0x00 24. " PRTB_SRC12_PREV_SOURCE_FID ,Source Field ID 12 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PRTB_SRC11_CURR_SOURCE_FID ,Source Field ID 11 for Current Field" "0,1"
|
|
bitfld.long 0x00 22. " PRTB_SRC11_PREV_SOURCE_FID ,Source Field ID 11 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PRTB_SRC10_CURR_SOURCE_FID ,Source Field ID 10 for Current Field" "0,1"
|
|
bitfld.long 0x00 20. " PRTB_SRC10_PREV_SOURCE_FID ,Source Field ID 10 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PRTB_SRC9_CURR_SOURCE_FID ,Source Field ID 9 for Current Field" "0,1"
|
|
bitfld.long 0x00 18. " PRTB_SRC9_PREV_SOURCE_FID ,Source Field ID 9 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PRTB_SRC8_CURR_SOURCE_FID ,Source Field ID 8 for Current Field" "0,1"
|
|
bitfld.long 0x00 16. " PRTB_SRC8_PREV_SOURCE_FID ,Source Field ID 8 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PRTB_SRC7_CURR_SOURCE_FID ,Source Field ID 7 for Current Field" "0,1"
|
|
bitfld.long 0x00 14. " PRTB_SRC7_PREV_SOURCE_FID ,Source Field ID 7 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PRTB_SRC6_CURR_SOURCE_FID ,Source Field ID 6 for Current Field" "0,1"
|
|
bitfld.long 0x00 12. " PRTB_SRC6_PREV_SOURCE_FID ,Source Field ID 6 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PRTB_SRC5_CURR_SOURCE_FID ,Source Field ID 5 for Current Field" "0,1"
|
|
bitfld.long 0x00 10. " PRTB_SRC5_PREV_SOURCE_FID ,Source Field ID 5 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PRTB_SRC4_CURR_SOURCE_FID ,Source Field ID 4 for Current Field" "0,1"
|
|
bitfld.long 0x00 8. " PRTB_SRC4_PREV_SOURCE_FID ,Source Field ID 4 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PRTB_SRC3_CURR_SOURCE_FID ,Source Field ID 3 for Current Field" "0,1"
|
|
bitfld.long 0x00 6. " PRTB_SRC3_PREV_SOURCE_FID ,Source Field ID 3 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PRTB_SRC2_CURR_SOURCE_FID ,Source Field ID 2 for Current Field" "0,1"
|
|
bitfld.long 0x00 4. " PRTB_SRC2_PREV_SOURCE_FID ,Source Field ID 2 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PRTB_SRC1_CURR_SOURCE_FID ,Source Field ID 1 for Current Field" "0,1"
|
|
bitfld.long 0x00 2. " PRTB_SRC1_PREV_SOURCE_FID ,Source Field ID 1 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PRTB_SRC0_CURR_SOURCE_FID ,Source Field ID 0 for Current Field" "0,1"
|
|
bitfld.long 0x00 0. " PRTB_SRC0_PREV_SOURCE_FID ,Source Field ID 0 for Previous Field" "0,1"
|
|
line.long 0x04 "PORTB_ENC,VIN0_PARSER Port B Encoder FID Register"
|
|
bitfld.long 0x04 31. " PRTB_SRC15_CURR_ENC_FID ,Encoder Field ID 15 for Current Field" "0,1"
|
|
bitfld.long 0x04 30. " PRTB_SRC15_PREV_ENC_FID ,Encoder Field ID 15 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 29. " PRTB_SRC14_CURR_ENC_FID ,Encoder Field ID 14 for Current Field" "0,1"
|
|
bitfld.long 0x04 28. " PRTB_SRC14_PREV_ENC_FID ,Encoder Field ID 14 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PRTB_SRC13_CURR_ENC_FID ,Encoder Field ID 13 for Current Field" "0,1"
|
|
bitfld.long 0x04 26. " PRTB_SRC13_PREV_ENC_FID ,Encoder Field ID 13 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 25. " PRTB_SRC12_CURR_ENC_FID ,Encoder Field ID 12 for Current Field" "0,1"
|
|
bitfld.long 0x04 24. " PRTB_SRC12_PREV_ENC_FID ,Encoder Field ID 12 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PRTB_SRC11_CURR_ENC_FID ,Encoder Field ID 11 for Current Field" "0,1"
|
|
bitfld.long 0x04 22. " PRTB_SRC11_PREV_ENC_FID ,Encoder Field ID 11 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 21. " PRTB_SRC10_CURR_ENC_FID ,Encoder Field ID 10 for Current Field" "0,1"
|
|
bitfld.long 0x04 20. " PRTB_SRC10_PREV_ENC_FID ,Encoder Field ID 10 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PRTB_SRC9_CURR_ENC_FID ,Encoder Field ID 9 for Current Field" "0,1"
|
|
bitfld.long 0x04 18. " PRTB_SRC9_PREV_ENC_FID ,Encoder Field ID 9 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " PRTB_SRC8_CURR_ENC_FID ,Encoder Field ID 8 for Current Field" "0,1"
|
|
bitfld.long 0x04 16. " PRTB_SRC8_PREV_ENC_FID ,Encoder Field ID 8 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 15. " PRTB_SRC7_CURR_ENC_FID ,Encoder Field ID 7 for Current Field" "0,1"
|
|
bitfld.long 0x04 14. " PRTB_SRC7_PREV_ENC_FID ,Encoder Field ID 7 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PRTB_SRC6_CURR_ENC_FID ,Encoder Field ID 6 for Current Field" "0,1"
|
|
bitfld.long 0x04 12. " PRTB_SRC6_PREV_ENC_FID ,Encoder Field ID 6 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PRTB_SRC5_CURR_ENC_FID ,Encoder Field ID 5 for Current Field" "0,1"
|
|
bitfld.long 0x04 10. " PRTB_SRC5_PREV_ENC_FID ,Encoder Field ID 5 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PRTB_SRC4_CURR_ENC_FID ,Encoder Field ID 4 for Current Field" "0,1"
|
|
bitfld.long 0x04 8. " PRTB_SRC4_PREV_ENC_FID ,Encoder Field ID 4 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PRTB_SRC3_CURR_ENC_FID ,Encoder Field ID 3 for Current Field" "0,1"
|
|
bitfld.long 0x04 6. " PRTB_SRC3_PREV_ENC_FID ,Encoder Field ID 3 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PRTB_SRC2_CURR_ENC_FID ,Encoder Field ID 2 for Current Field" "0,1"
|
|
bitfld.long 0x04 4. " PRTB_SRC2_PREV_ENC_FID ,Encoder Field ID 2 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PRTB_SRC1_CURR_ENC_FID ,Encoder Field ID 1 for Current Field" "0,1"
|
|
bitfld.long 0x04 2. " PRTB_SRC1_PREV_ENC_FID ,Encoder Field ID 1 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PRTB_SRC0_CURR_ENC_FID ,Encoder Field ID 0 for Current Field" "0,1"
|
|
bitfld.long 0x04 0. " PRTB_SRC0_PREV_ENC_FID ,Encoder Field ID 0 for Previous Field" "0,1"
|
|
width 16.
|
|
group.long 0x70++0x3f
|
|
line.long 0x0 "PORTB_SRC0_SZ,VIN0_PARSER Output Port B Source 0 Size"
|
|
hexmask.long.word 0x0 16.--26. 1. " WIDTH ,Source 0 width"
|
|
hexmask.long.word 0x0 0.--10. 1. " HEIGHT ,Source 0 height"
|
|
line.long 0x4 "PORTB_SRC1_SZ,VIN0_PARSER Output Port B Source 1 Size"
|
|
hexmask.long.word 0x4 16.--26. 1. " WIDTH ,Source 1 width"
|
|
hexmask.long.word 0x4 0.--10. 1. " HEIGHT ,Source 1 height"
|
|
line.long 0x8 "PORTB_SRC2_SZ,VIN0_PARSER Output Port B Source 2 Size"
|
|
hexmask.long.word 0x8 16.--26. 1. " WIDTH ,Source 2 width"
|
|
hexmask.long.word 0x8 0.--10. 1. " HEIGHT ,Source 2 height"
|
|
line.long 0xC "PORTB_SRC3_SZ,VIN0_PARSER Output Port B Source 3 Size"
|
|
hexmask.long.word 0xC 16.--26. 1. " WIDTH ,Source 3 width"
|
|
hexmask.long.word 0xC 0.--10. 1. " HEIGHT ,Source 3 height"
|
|
line.long 0x10 "PORTB_SRC4_SZ,VIN0_PARSER Output Port B Source 4 Size"
|
|
hexmask.long.word 0x10 16.--26. 1. " WIDTH ,Source 4 width"
|
|
hexmask.long.word 0x10 0.--10. 1. " HEIGHT ,Source 4 height"
|
|
line.long 0x14 "PORTB_SRC5_SZ,VIN0_PARSER Output Port B Source 5 Size"
|
|
hexmask.long.word 0x14 16.--26. 1. " WIDTH ,Source 5 width"
|
|
hexmask.long.word 0x14 0.--10. 1. " HEIGHT ,Source 5 height"
|
|
line.long 0x18 "PORTB_SRC6_SZ,VIN0_PARSER Output Port B Source 6 Size"
|
|
hexmask.long.word 0x18 16.--26. 1. " WIDTH ,Source 6 width"
|
|
hexmask.long.word 0x18 0.--10. 1. " HEIGHT ,Source 6 height"
|
|
line.long 0x1C "PORTB_SRC7_SZ,VIN0_PARSER Output Port B Source 7 Size"
|
|
hexmask.long.word 0x1C 16.--26. 1. " WIDTH ,Source 7 width"
|
|
hexmask.long.word 0x1C 0.--10. 1. " HEIGHT ,Source 7 height"
|
|
line.long 0x20 "PORTB_SRC8_SZ,VIN0_PARSER Output Port B Source 8 Size"
|
|
hexmask.long.word 0x20 16.--26. 1. " WIDTH ,Source 8 width"
|
|
hexmask.long.word 0x20 0.--10. 1. " HEIGHT ,Source 8 height"
|
|
line.long 0x24 "PORTB_SRC9_SZ,VIN0_PARSER Output Port B Source 9 Size"
|
|
hexmask.long.word 0x24 16.--26. 1. " WIDTH ,Source 9 width"
|
|
hexmask.long.word 0x24 0.--10. 1. " HEIGHT ,Source 9 height"
|
|
line.long 0x28 "PORTB_SRC10_SZ,VIN0_PARSER Output Port B Source 10 Size"
|
|
hexmask.long.word 0x28 16.--26. 1. " WIDTH ,Source 10 width"
|
|
hexmask.long.word 0x28 0.--10. 1. " HEIGHT ,Source 10 height"
|
|
line.long 0x2C "PORTB_SRC11_SZ,VIN0_PARSER Output Port B Source 11 Size"
|
|
hexmask.long.word 0x2C 16.--26. 1. " WIDTH ,Source 11 width"
|
|
hexmask.long.word 0x2C 0.--10. 1. " HEIGHT ,Source 11 height"
|
|
line.long 0x30 "PORTB_SRC12_SZ,VIN0_PARSER Output Port B Source 12 Size"
|
|
hexmask.long.word 0x30 16.--26. 1. " WIDTH ,Source 12 width"
|
|
hexmask.long.word 0x30 0.--10. 1. " HEIGHT ,Source 12 height"
|
|
line.long 0x34 "PORTB_SRC13_SZ,VIN0_PARSER Output Port B Source 13 Size"
|
|
hexmask.long.word 0x34 16.--26. 1. " WIDTH ,Source 13 width"
|
|
hexmask.long.word 0x34 0.--10. 1. " HEIGHT ,Source 13 height"
|
|
line.long 0x38 "PORTB_SRC14_SZ,VIN0_PARSER Output Port B Source 14 Size"
|
|
hexmask.long.word 0x38 16.--26. 1. " WIDTH ,Source 14 width"
|
|
hexmask.long.word 0x38 0.--10. 1. " HEIGHT ,Source 14 height"
|
|
line.long 0x3C "PORTB_SRC15_SZ,VIN0_PARSER Output Port B Source 15 Size"
|
|
hexmask.long.word 0x3C 16.--26. 1. " WIDTH ,Source 15 width"
|
|
hexmask.long.word 0x3C 0.--10. 1. " HEIGHT ,Source 15 height"
|
|
if ((d.l(ad:0x48105500+0x0c)&0xf)==(0x0||0x1||0x2||0x3||0x5||0x6||0x7||0x8))
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "PORTB_DETVEC,VIN0_PARSER Port B Detector Vector"
|
|
else
|
|
hgroup.long 0xb4++0x3
|
|
hide.long 0x00 "PORTB_DETVEC,VIN0_PARSER Port B Detector Vector"
|
|
endif
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
tree "VIN0_CSC_R2Y"
|
|
base ad:0x48105700
|
|
width 7.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "CSC00,VIN0_CSC_R2Y Coefficients of Color Space Converter Register 0"
|
|
hexmask.long.word 0x00 16.--28. 1. " B0 ,B0 coefficient of color space converter"
|
|
hexmask.long.word 0x00 0.--12. 1. " A0 ,A0 coefficient of color space converter"
|
|
line.long 0x04 "CSC01,VIN0_CSC_R2Y Coefficients of Color Space Converter Register 1"
|
|
hexmask.long.word 0x04 16.--28. 1. " A1 ,A1 coefficient of color space converter"
|
|
hexmask.long.word 0x04 0.--12. 1. " C0 ,C0 coefficient of color space converter"
|
|
line.long 0x08 "CSC02,VIN0_CSC_R2Y Coefficients of Color Space Converter Register 2"
|
|
hexmask.long.word 0x08 16.--28. 1. " C1 ,C1 coefficient of color space converter"
|
|
hexmask.long.word 0x08 0.--12. 1. " B1 ,B1 coefficient of color space converter"
|
|
line.long 0x0c "CSC03,VIN0_CSC_R2Y Coefficients of Color Space Converter Register 3"
|
|
hexmask.long.word 0x0c 16.--28. 1. " B2 ,B2 coefficient of color space converter"
|
|
hexmask.long.word 0x0c 0.--12. 1. " A2 ,A2 coefficient of color space converter"
|
|
line.long 0x10 "CSC04,VIN0_CSC_R2Y Coefficients of Color Space Converter Register 4"
|
|
hexmask.long.word 0x10 16.--27. 1. " D0 ,D0 coefficient of color space converter"
|
|
hexmask.long.word 0x10 0.--12. 1. " C2 ,C2 coefficient of color space converter"
|
|
line.long 0x14 "CSC05,VIN0_CSC_R2Y Coefficients of Color Space Converter Register 5"
|
|
bitfld.long 0x14 28. " BYPASS ,Full CSC bypass mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x14 16.--27. 1. " D2 ,D2 coefficient of color space converter"
|
|
hexmask.long.word 0x14 0.--11. 1. " D1 ,D1 coefficient of color space converter"
|
|
width 11.
|
|
tree.end
|
|
tree "VIN0_SC"
|
|
base ad:0x48105800
|
|
width 10.
|
|
group.long 0x00++0x1b
|
|
line.long 0x00 "CFG_SC0,VIN0_SC CFG_SC0 Register"
|
|
bitfld.long 0x00 16. " CFG_SELFGEN_FID ,Self Generate FID Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CFG_TRIM ,Trimming enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CFG_Y_PK_EN ,Luma peaking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CFG_ENABLE_SIN2_VER_INTP ,Bilinear interpolation select" "Original,Modified"
|
|
bitfld.long 0x00 10. " CFG_INTERLACE_I ,Input video format" "Progressive,Interlace"
|
|
bitfld.long 0x00 9. " CFG_HP_BYPASS ,Polyphase scaler bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CFG_DCM_4X ,4X decimation filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CFG_DCM_2X ,2X decimation filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CFG_AUTO_HS ,Hardware autoselect scalling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CFG_ENABLE_EV ,Edge-detection block output" "Forced to 0,Normal"
|
|
bitfld.long 0x00 4. " CFG_USE_RAV ,Vertical scaling filter select" "Poly-phase,Running average"
|
|
bitfld.long 0x00 3. " CFG_INVT_FID ,Field ID inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CFG_SC_BYPASS ,Scaling module bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 1. " CFG_LINEAR ,Scaling" "Anamorphic,Linear"
|
|
bitfld.long 0x00 0. " CFG_INTERLACE_O ,Output format of SC" "Progressive,Interlace"
|
|
line.long 0x04 "CFG_SC1,VIN0_SC CFG_SC1 Register"
|
|
hexmask.long 0x04 0.--26. 1. " CFG_ROW_ACC_INC ,Increment of row accumulator in vertical poly-phase filter"
|
|
line.long 0x08 "CFG_SC2,VIN0_SC CFG_SC2 Register"
|
|
hexmask.long 0x08 0.--27. 1. " CFG_ROW_ACC_OFFSET ,Vertical offset during vertical scaling"
|
|
line.long 0x0c "CFG_SC3,VIN0_SC CFG_SC3 Register"
|
|
hexmask.long 0x0c 0.--27. 1. " CFG_ROW_ACC_OFFSET_B ,Vertical offset during vertical scaling"
|
|
line.long 0x10 "CFG_SC4,VIN0_SC CFG_SC4 Register"
|
|
bitfld.long 0x10 28.--30. " CFG_NLIN_ACC_INIT_U ,3 MSBs of nlin_acc_init" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x10 24.--26. " CFG_LIN_ACC_INC_U ,3 MSBs of lin_acc_inc" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
hexmask.long.word 0x10 12.--22. 1. " CFG_TAR_W ,Scaled target picture width (in pixels)"
|
|
hexmask.long.word 0x10 0.--10. 1. " CFG_TAR_H ,Scaled target picture height (in lines)"
|
|
line.long 0x14 "CFG_SC5,VIN0_SC CFG_SC5 Register"
|
|
bitfld.long 0x14 24.--26. " CFG_NLIN_ACC_INC_U ,3 MSBs of nlin_acc_inc" "000,001,010,011,100,101,110,111"
|
|
hexmask.long.word 0x14 12.--22. 1. " CFG_SRC_W ,Source image width"
|
|
hexmask.long.word 0x14 0.--10. 1. " CFG_SRC_H ,Source image height"
|
|
line.long 0x18 "CFG_SC6,VIN0_SC CFG_SC6 Register"
|
|
hexmask.long.word 0x18 10.--19. 1. " CFG_ROW_ACC_INIT_RAV ,Running average filter row accumulator init value (bottom field of interlace format)"
|
|
hexmask.long.word 0x18 0.--9. 1. " CFG_ROW_ACC_INIT_RAV_B ,Running average filter row accumulator init value (progressive format / top field of interlace format)"
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "CFG_SC8,VIN0_SC CFG_SC8 Register"
|
|
hexmask.long.word 0x00 12.--22. 1. " CFG_NLIN_RIGHT ,Strip on right-hand side width (in anamorphic mode)"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFG_NLIN_LEFT ,Strip on left-hand side width (in anamorphic mode)"
|
|
line.long 0x04 "CFG_SC9,VIN0_SC CFG_SC9 Register"
|
|
line.long 0x08 "CFG_SC10,VIN0_SC CFG_SC10 Register"
|
|
line.long 0x0c "CFG_SC11,VIN0_SC CFG_SC11 Register"
|
|
line.long 0x10 "CFG_SC12,VIN0_SC CFG_SC12 Register"
|
|
hexmask.long 0x10 0.--24. 1. " CFG_COL_ACC_OFFSET ,Luma accumulators offset"
|
|
line.long 0x14 "CFG_SC13,VIN0_SC CFG_SC13 Register"
|
|
bitfld.long 0x14 24.--27. " CFG_DELTA_CHROMA_THR ,Range for chroma soft switch based on pixel differences" "0,1,2,3,4,5,6,7,8,?..."
|
|
hexmask.long.word 0x14 12.--21. 1. " CFG_CHROMA_INTP_THR ,Difference-threshold between chroma pixels"
|
|
hexmask.long.word 0x14 0.--9. 1. " CFG_SC_FACTOR_RAV ,Vertical scaling factor (1024*tarH/srcH)"
|
|
group.long 0x44++0x23
|
|
line.long 0x00 "CFG_SC17,VIN0_SC CFG_SC17 Register"
|
|
bitfld.long 0x00 28.--31. " CFG_DELTA_EV_THR ,Range of luma soft switch based on edge vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " CFG_DELTA_LUMA_THR ,Range for luma soft switch based on pixel differences" "0,1,2,3,4,5,6,7,8,?..."
|
|
hexmask.long.word 0x00 12.--21. 1. " CFG_EV_THR ,Edge vector threshold (8.2)"
|
|
line.long 0x04 "CFG_SC18,VIN0_SC CFG_SC18 Register"
|
|
hexmask.long.word 0x04 16.--24. 1. " CFG_CONF_DEFAULT ,Confidence factor when edge detection is disabled"
|
|
hexmask.long.word 0x04 0.--9. 1. " CFG_HS_FACTOR ,Horizontal scaling factor (tarWi/srcWi)(6.4)"
|
|
line.long 0x08 "CFG_SC19,VIN0_SC CFG_SC19 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " CFG_HPF_COEF3 ,Coefficient 3 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFG_HPF_COEF2 ,Coefficient 2 of HPF used in peaking filter"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " CFG_HPF_COEF1 ,Coefficient 1 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFG_HPF_COEF0 ,Coefficient 0 of HPF used in peaking filter"
|
|
line.long 0x0c "CFG_SC20,VIN0_SC CFG_SC20 Register"
|
|
hexmask.long.word 0x0C 20.--28. 1. " CFG_NL_LIMIT ,Maximum of clipping"
|
|
bitfld.long 0x0C 16.--18. " CFG_HPF_NORM_SHIFT ,Decimal point of hpf coefficient" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 8.--15. 1. " CFG_HPF_COEF5 ,Coefficient 5 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CFG_HPF_COEF4 ,Coefficient 4 of HPF used in peaking filter"
|
|
line.long 0x10 "CFG_SC21,VIN0_SC CFG_SC21 Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. " CFG_NL_LO_SLOPE ,Slope of nonlinear peaking function"
|
|
hexmask.long.word 0x10 0.--8. 1. " CFG_NL_LO_THR ,Threshold for nonlinear peaking function"
|
|
line.long 0x14 "CFG_SC22,VIN0_SC CFG_SC22 Register"
|
|
bitfld.long 0x14 16.--18. " CFG_NL_HI_SLOPE_SHIFT ,Slope of nonlinear peaking function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x14 0.--8. 1. " CFG_NL_HI_THR ,Threshold for nonlinear peaking function"
|
|
line.long 0x18 "CFG_SC23,VIN0_SC CFG_SC23 Register"
|
|
bitfld.long 0x18 28.--31. " CFG_MIN_GY_THR_RANGE ,Soft switch range of small Gy decay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x18 16.--25. 1. " CFG_MIN_GY_THR ,Threshold for soft switch of decay for small Gy"
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " CFG_GRADIENT_THR_RANGE ,Soft switch range of edge strength test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x18 0.--10. 1. " CFG_GRADIENT_THR ,Threshold for gradient for edge strength test"
|
|
line.long 0x1c "CFG_SC24,VIN0_SC CFG_SC24 Register"
|
|
hexmask.long.word 0x1C 16.--26. 1. " CFG_ORG_W ,Width of original input image"
|
|
hexmask.long.word 0x1C 0.--10. 1. " CFG_ORG_H ,Height of original input image"
|
|
line.long 0x20 "CFG_SC25,VIN0_SC CFG_SC25 Register"
|
|
hexmask.long.word 0x20 16.--26. 1. " CFG_OFF_W ,Horizontal offset from left of original input image"
|
|
hexmask.long.word 0x20 0.--10. 1. " CFG_OFF_H ,Vertical offset from top of original input image"
|
|
width 11.
|
|
tree.end
|
|
tree "VIN1_PARSER"
|
|
base ad:0x48105a00
|
|
width 13.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "MAIN_CONFIG,VIN1 Parser Main Configuration Register"
|
|
bitfld.long 0x00 5. " CLIP_ACTIVE ,Clip Active Pixels" "Not clipped,Clipped"
|
|
bitfld.long 0x00 4. " CLIP_BLNK ,Clip Blanking Data" "Not clipped,Clipped"
|
|
bitfld.long 0x00 0.--1. " DATA_INTERFACE_MODE ,Data Interface Mode" "24b,16b,Dual 8b,?..."
|
|
group.long 0x14++0xb
|
|
line.long 0x00 "FIQ_MASK,VIN1_PARSER FIQ Mask Register"
|
|
bitfld.long 0x00 9. " OUTPUT_FIFO_PRTB_ANC_OF ,Output FIFO Port B Ancillary Overflow Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " OUTPUT_FIFO_PRTB_UV_OF ,Output FIFO Port B Chroma Overflow Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OUTPUT_FIFO_PRTB_YUV_OF ,Output FIFO Port B Luma Overflow Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " OUTPUT_FIFO_PRTA_ANC_OF ,Output FIFO Port A Ancillary Overflow Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OUTPUT_FIFO_PRTA_UV_OF ,Output FIFO Port A Chroma Overflow Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " OUTPUT_FIFO_PRTA_YUV_OF ,Output FIFO Port A Luma Overflow Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASYNC_FIFO_PRTB_OF ,Port B Async FIFO Overflow FIQ Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " ASYNC_FIFO_PRTA_OF ,Port A Async FIFO Overflow FIQ Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PRTB_VDET_MASK ,Port B Video Detect FIQ Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " PRTA_VDET_MASK ,Port A Video Detect FIQ Mask" "Not masked,Masked"
|
|
line.long 0x04 "FIQ_CLR,VIN1_PARSER FIQ Clear Register"
|
|
bitfld.long 0x04 9. " OUTPUT_FIFO_PRTB_ANC_CLR ,Output FIFO Port B Ancillary Overflow Clear" "No effect,Clear"
|
|
bitfld.long 0x04 8. " OUTPUT_FIFO_PRTB_UV_CLR ,Output FIFO Port B Chroma Overflow Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OUTPUT_FIFO_PRTB_YUV_CLR ,Output FIFO Port B Luma Overflow Clear" "No effect,Clear"
|
|
bitfld.long 0x04 6. " OUTPUT_FIFO_PRTA_ANC_CLR ,Output FIFO Port A Ancillary Overflow Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OUTPUT_FIFO_PRTA_UV_CLR ,Output FIFO Port A Chroma Overflow Clear" "No effect,Clear"
|
|
bitfld.long 0x04 4. " OUTPUT_FIFO_PRTA_YUV_CLR ,Output FIFO Port A Luma Overflow Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ASYNC_FIFO_PRTB_CLR ,Port B Async FIFO Overflow FIQ Clear" "No effect,Clear"
|
|
bitfld.long 0x04 2. " ASYNC_FIFO_PRTA_CLR ,Port A Async FIFO Overflow FIQ Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PRTB_VDET_CLR ,Port B Video Detect FIQ Clear" "No effect,Clear"
|
|
bitfld.long 0x04 0. " PRTA_VDET_CLR ,Port A Video Detect FIQ Clear" "No effect,Clear"
|
|
line.long 0x08 "FIQ_STS,VIN1_PARSER FIQ Status Register"
|
|
bitfld.long 0x08 9. " OUTPUT_FIFO_PRTB_ANC_STATUS ,Output FIFO Port B Ancillary Overflow Status" "Low,High"
|
|
bitfld.long 0x08 8. " OUTPUT_FIFO_PRTB_UV_STATUS ,Output FIFO Port B Chroma Overflow Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 7. " OUTPUT_FIFO_PRTB_YUV_STATUS ,Output FIFO Port B Luma Overflow Status" "Low,High"
|
|
bitfld.long 0x08 6. " OUTPUT_FIFO_PRTA_ANC_STATUS ,Output FIFO Port A Ancillary Overflow Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OUTPUT_FIFO_PRTA_UV_STATUS ,Output FIFO Port A Chroma Overflow Status" "Low,High"
|
|
bitfld.long 0x08 4. " OUTPUT_FIFO_PRTA_YUV_STATUS ,Output FIFO Port A Luma Overflow Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ASYNC_FIFO_PRTB_STATUS ,Port B Async FIFO Overflow FIQ Status" "Low,High"
|
|
bitfld.long 0x08 2. " ASYNC_FIFO_PRTA_STATUS ,Port A Async FIFO Overflow FIQ Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PRTB_VDET_STATUS ,Port B Video Detect FIQ Status" "Low,High"
|
|
bitfld.long 0x08 0. " PRTA_VDET_STATUS ,Port A Video Detect FIQ Status" "Low,High"
|
|
width 16.
|
|
tree "PORT A"
|
|
if ((d.l(ad:0x48105a00+0x04)&0xf)==(0x0||0x1||0x2||0x3||0x5||0x6||0x7||0x8))
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "PORTA_CONFIG0,VIN1_PARSER Configuration for Input Port A Register 0"
|
|
bitfld.long 0x00 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Error correction for the fvh control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ANALYZER_2X4X_SRCNUM_POS ,Srcnum position in 2x/4x mux mode (least significant nibble of)" "XV/fvh codeword,Horizontal blanking pixel value"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PIXCLK_EDGE_POLARITY ,PIXCLK edge polarity" "Rising,Falling"
|
|
bitfld.long 0x00 9. " FID_POLARITY ,Invert Determined Value of FID" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE ,Enable the port" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CLR_ASYNC_FIFO_RD ,Clear Async FIFO Read Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLR_ASYNC_FIFO_WR ,Clear Async FIFO Write Logic" "No effect,Clear"
|
|
bitfld.long 0x00 4.--5. " CTRL_CHAN_SEL ,Channel select" "Data[7:0] (8b/16b/24b),Data[15:8] (16b/24b),Data[23:16] (24b),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SYNC_TYPE ,Sync type" "Embedded sync single 4:2:2 YUV stream,Embedded sync 2x multiplexed 4:2:2 YUV stream,Embedded sync 4x multiplexed 4:2:2 YUV stream,Embedded sync line multiplexed 4:2:2 YUV stream,Discrete sync single 4:2:2 YUV stream,Embedded sync single RGB stream or single 444 YUV stream,Embedded sync 2x multiplexed RGB stream,Embedded sync 4x multiplexed RGB stream,Embedded sync line multiplexed RGB stream,Discrete sync single 8b RGB stream,Discrete sync single 24b RGB stream,?..."
|
|
elif ((d.l(ad:0x48105a00+0x04)&0xf)==(0x4||0x9||0xa))
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "PORTA_CONFIG0,VIN1_PARSER Configuration for Input Port A Register 0"
|
|
bitfld.long 0x00 24.--29. " FID_SKEW_POSTCOUNT ,Post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " FID_SKEW_PRECOUNT ,Pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15. " USE_ACTVID_HSYNC_N ,Line capture style" "HSYNC,ACTVID"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FID_DETECT_MODE ,FID detection mode" "Pin,VSYNC skew"
|
|
bitfld.long 0x00 13. " ACTVID_POLARITY ,ACTVID polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " VSYNC_POLARITY ,VSYNC polarity" "Low,High"
|
|
bitfld.long 0x00 11. " HSYNC_POLARITY ,HSYNC polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PIXCLK_EDGE_POLARITY ,PIXCLK edge polarity" "Rising,Falling"
|
|
bitfld.long 0x00 9. " FID_POLARITY ,Invert Determined Value of FID" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE ,Enable the port" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CLR_ASYNC_FIFO_RD ,Clear Async FIFO Read Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLR_ASYNC_FIFO_WR ,Clear Async FIFO Write Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SYNC_TYPE ,Sync type" "Embedded sync single 4:2:2 YUV stream,Embedded sync 2x multiplexed 4:2:2 YUV stream,Embedded sync 4x multiplexed 4:2:2 YUV stream,Embedded sync line multiplexed 4:2:2 YUV stream,Discrete sync single 4:2:2 YUV stream,Embedded sync single RGB stream or single 444 YUV stream,Embedded sync 2x multiplexed RGB stream,Embedded sync 4x multiplexed RGB stream,Embedded sync line multiplexed RGB stream,Discrete sync single 8b RGB stream,Discrete sync single 24b RGB stream,?..."
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "PORTA_CONFIG0,VIN1_PARSER Configuration for Input Port A Register 0"
|
|
bitfld.long 0x00 10. " PIXCLK_EDGE_POLARITY ,PIXCLK edge polarity" "Rising,Falling"
|
|
bitfld.long 0x00 9. " FID_POLARITY ,Invert Determined Value of FID" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE ,Enable the port" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CLR_ASYNC_FIFO_RD ,Clear Async FIFO Read Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLR_ASYNC_FIFO_WR ,Clear Async FIFO Write Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SYNC_TYPE ,Sync type" "Embedded sync single 4:2:2 YUV stream,Embedded sync 2x multiplexed 4:2:2 YUV stream,Embedded sync 4x multiplexed 4:2:2 YUV stream,Embedded sync line multiplexed 4:2:2 YUV stream,Discrete sync single 4:2:2 YUV stream,Embedded sync single RGB stream or single 444 YUV stream,Embedded sync 2x multiplexed RGB stream,Embedded sync 4x multiplexed RGB stream,Embedded sync line multiplexed RGB stream,Discrete sync single 8b RGB stream,Discrete sync single 24b RGB stream,?..."
|
|
endif
|
|
if ((d.l(ad:0x48105a00+0x04)&0xf)==(0x0||0x1||0x2||0x3||0x5||0x6||0x7||0x8))
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "PORTA_CONFIG1,VIN1_PARSER Configuration for Input Port A Register 1"
|
|
bitfld.long 0x00 12. " TVP5158_CHAN_ID_TYPE ,TVP5158 channel ID type" "All bits,Bits 2:0"
|
|
elif ((d.l(ad:0x48105a00+0x04)&0xf)==(0x4||0x9||0xa))
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "PORTA_CONFIG1,VIN1_PARSER Configuration for Input Port A Register 1"
|
|
hexmask.long.word 0x00 0.--10. 1. " ANC_LINES ,Number of Ancillary Lines of data before the ACTIVE video lines start"
|
|
else
|
|
hgroup.long 0x08++0x3
|
|
hide.long 0x00 "PORTA_CONFIG1,VIN1_PARSER Configuration for Input Port A Register 1"
|
|
endif
|
|
width 16.
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x00 "PORTA_SRC,VIN1_PARSER Port A Source FID Register"
|
|
bitfld.long 0x00 31. " PRTA_SRC15_CURR_SOURCE_FID ,Source Field ID 15 for Current Field" "0,1"
|
|
bitfld.long 0x00 30. " PRTA_SRC15_PREV_SOURCE_FID ,Source Field ID 15 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PRTA_SRC14_CURR_SOURCE_FID ,Source Field ID 14 for Current Field" "0,1"
|
|
bitfld.long 0x00 28. " PRTA_SRC14_PREV_SOURCE_FID ,Source Field ID 14 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PRTA_SRC13_CURR_SOURCE_FID ,Source Field ID 13 for Current Field" "0,1"
|
|
bitfld.long 0x00 26. " PRTA_SRC13_PREV_SOURCE_FID ,Source Field ID 13 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PRTA_SRC12_CURR_SOURCE_FID ,Source Field ID 12 for Current Field" "0,1"
|
|
bitfld.long 0x00 24. " PRTA_SRC12_PREV_SOURCE_FID ,Source Field ID 12 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PRTA_SRC11_CURR_SOURCE_FID ,Source Field ID 11 for Current Field" "0,1"
|
|
bitfld.long 0x00 22. " PRTA_SRC11_PREV_SOURCE_FID ,Source Field ID 11 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PRTA_SRC10_CURR_SOURCE_FID ,Source Field ID 10 for Current Field" "0,1"
|
|
bitfld.long 0x00 20. " PRTA_SRC10_PREV_SOURCE_FID ,Source Field ID 10 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PRTA_SRC9_CURR_SOURCE_FID ,Source Field ID 9 for Current Field" "0,1"
|
|
bitfld.long 0x00 18. " PRTA_SRC9_PREV_SOURCE_FID ,Source Field ID 9 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PRTA_SRC8_CURR_SOURCE_FID ,Source Field ID 8 for Current Field" "0,1"
|
|
bitfld.long 0x00 16. " PRTA_SRC8_PREV_SOURCE_FID ,Source Field ID 8 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PRTA_SRC7_CURR_SOURCE_FID ,Source Field ID 7 for Current Field" "0,1"
|
|
bitfld.long 0x00 14. " PRTA_SRC7_PREV_SOURCE_FID ,Source Field ID 7 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PRTA_SRC6_CURR_SOURCE_FID ,Source Field ID 6 for Current Field" "0,1"
|
|
bitfld.long 0x00 12. " PRTA_SRC6_PREV_SOURCE_FID ,Source Field ID 6 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PRTA_SRC5_CURR_SOURCE_FID ,Source Field ID 5 for Current Field" "0,1"
|
|
bitfld.long 0x00 10. " PRTA_SRC5_PREV_SOURCE_FID ,Source Field ID 5 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PRTA_SRC4_CURR_SOURCE_FID ,Source Field ID 4 for Current Field" "0,1"
|
|
bitfld.long 0x00 8. " PRTA_SRC4_PREV_SOURCE_FID ,Source Field ID 4 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PRTA_SRC3_CURR_SOURCE_FID ,Source Field ID 3 for Current Field" "0,1"
|
|
bitfld.long 0x00 6. " PRTA_SRC3_PREV_SOURCE_FID ,Source Field ID 3 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PRTA_SRC2_CURR_SOURCE_FID ,Source Field ID 2 for Current Field" "0,1"
|
|
bitfld.long 0x00 4. " PRTA_SRC2_PREV_SOURCE_FID ,Source Field ID 2 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PRTA_SRC1_CURR_SOURCE_FID ,Source Field ID 1 for Current Field" "0,1"
|
|
bitfld.long 0x00 2. " PRTA_SRC1_PREV_SOURCE_FID ,Source Field ID 1 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PRTA_SRC0_CURR_SOURCE_FID ,Source Field ID 0 for Current Field" "0,1"
|
|
bitfld.long 0x00 0. " PRTA_SRC0_PREV_SOURCE_FID ,Source Field ID 0 for Previous Field" "0,1"
|
|
line.long 0x04 "PORTA_ENC,VIN1_PARSER Port A Encoder FID Register"
|
|
bitfld.long 0x04 31. " PRTA_SRC15_CURR_ENC_FID ,Encoder Field ID 15 for Current Field" "0,1"
|
|
bitfld.long 0x04 30. " PRTA_SRC15_PREV_ENC_FID ,Encoder Field ID 15 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 29. " PRTA_SRC14_CURR_ENC_FID ,Encoder Field ID 14 for Current Field" "0,1"
|
|
bitfld.long 0x04 28. " PRTA_SRC14_PREV_ENC_FID ,Encoder Field ID 14 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PRTA_SRC13_CURR_ENC_FID ,Encoder Field ID 13 for Current Field" "0,1"
|
|
bitfld.long 0x04 26. " PRTA_SRC13_PREV_ENC_FID ,Encoder Field ID 13 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 25. " PRTA_SRC12_CURR_ENC_FID ,Encoder Field ID 12 for Current Field" "0,1"
|
|
bitfld.long 0x04 24. " PRTA_SRC12_PREV_ENC_FID ,Encoder Field ID 12 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PRTA_SRC11_CURR_ENC_FID ,Encoder Field ID 11 for Current Field" "0,1"
|
|
bitfld.long 0x04 22. " PRTA_SRC11_PREV_ENC_FID ,Encoder Field ID 11 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 21. " PRTA_SRC10_CURR_ENC_FID ,Encoder Field ID 10 for Current Field" "0,1"
|
|
bitfld.long 0x04 20. " PRTA_SRC10_PREV_ENC_FID ,Encoder Field ID 10 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PRTA_SRC9_CURR_ENC_FID ,Encoder Field ID 9 for Current Field" "0,1"
|
|
bitfld.long 0x04 18. " PRTA_SRC9_PREV_ENC_FID ,Encoder Field ID 9 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " PRTA_SRC8_CURR_ENC_FID ,Encoder Field ID 8 for Current Field" "0,1"
|
|
bitfld.long 0x04 16. " PRTA_SRC8_PREV_ENC_FID ,Encoder Field ID 8 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 15. " PRTA_SRC7_CURR_ENC_FID ,Encoder Field ID 7 for Current Field" "0,1"
|
|
bitfld.long 0x04 14. " PRTA_SRC7_PREV_ENC_FID ,Encoder Field ID 7 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PRTA_SRC6_CURR_ENC_FID ,Encoder Field ID 6 for Current Field" "0,1"
|
|
bitfld.long 0x04 12. " PRTA_SRC6_PREV_ENC_FID ,Encoder Field ID 6 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PRTA_SRC5_CURR_ENC_FID ,Encoder Field ID 5 for Current Field" "0,1"
|
|
bitfld.long 0x04 10. " PRTA_SRC5_PREV_ENC_FID ,Encoder Field ID 5 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PRTA_SRC4_CURR_ENC_FID ,Encoder Field ID 4 for Current Field" "0,1"
|
|
bitfld.long 0x04 8. " PRTA_SRC4_PREV_ENC_FID ,Encoder Field ID 4 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PRTA_SRC3_CURR_ENC_FID ,Encoder Field ID 3 for Current Field" "0,1"
|
|
bitfld.long 0x04 6. " PRTA_SRC3_PREV_ENC_FID ,Encoder Field ID 3 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PRTA_SRC2_CURR_ENC_FID ,Encoder Field ID 2 for Current Field" "0,1"
|
|
bitfld.long 0x04 4. " PRTA_SRC2_PREV_ENC_FID ,Encoder Field ID 2 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PRTA_SRC1_CURR_ENC_FID ,Encoder Field ID 1 for Current Field" "0,1"
|
|
bitfld.long 0x04 2. " PRTA_SRC1_PREV_ENC_FID ,Encoder Field ID 1 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PRTA_SRC0_CURR_ENC_FID ,Encoder Field ID 0 for Current Field" "0,1"
|
|
bitfld.long 0x04 0. " PRTA_SRC0_PREV_ENC_FID ,Encoder Field ID 0 for Previous Field" "0,1"
|
|
width 16.
|
|
group.long 0x30++0x3f
|
|
line.long 0x0 "PORTA_SRC0_SZ,VIN1_PARSER Output Port A Source 0 Size"
|
|
hexmask.long.word 0x0 16.--26. 1. " WIDTH ,Source 0 width"
|
|
hexmask.long.word 0x0 0.--10. 1. " HEIGHT ,Source 0 height"
|
|
line.long 0x4 "PORTA_SRC1_SZ,VIN1_PARSER Output Port A Source 1 Size"
|
|
hexmask.long.word 0x4 16.--26. 1. " WIDTH ,Source 1 width"
|
|
hexmask.long.word 0x4 0.--10. 1. " HEIGHT ,Source 1 height"
|
|
line.long 0x8 "PORTA_SRC2_SZ,VIN1_PARSER Output Port A Source 2 Size"
|
|
hexmask.long.word 0x8 16.--26. 1. " WIDTH ,Source 2 width"
|
|
hexmask.long.word 0x8 0.--10. 1. " HEIGHT ,Source 2 height"
|
|
line.long 0xC "PORTA_SRC3_SZ,VIN1_PARSER Output Port A Source 3 Size"
|
|
hexmask.long.word 0xC 16.--26. 1. " WIDTH ,Source 3 width"
|
|
hexmask.long.word 0xC 0.--10. 1. " HEIGHT ,Source 3 height"
|
|
line.long 0x10 "PORTA_SRC4_SZ,VIN1_PARSER Output Port A Source 4 Size"
|
|
hexmask.long.word 0x10 16.--26. 1. " WIDTH ,Source 4 width"
|
|
hexmask.long.word 0x10 0.--10. 1. " HEIGHT ,Source 4 height"
|
|
line.long 0x14 "PORTA_SRC5_SZ,VIN1_PARSER Output Port A Source 5 Size"
|
|
hexmask.long.word 0x14 16.--26. 1. " WIDTH ,Source 5 width"
|
|
hexmask.long.word 0x14 0.--10. 1. " HEIGHT ,Source 5 height"
|
|
line.long 0x18 "PORTA_SRC6_SZ,VIN1_PARSER Output Port A Source 6 Size"
|
|
hexmask.long.word 0x18 16.--26. 1. " WIDTH ,Source 6 width"
|
|
hexmask.long.word 0x18 0.--10. 1. " HEIGHT ,Source 6 height"
|
|
line.long 0x1C "PORTA_SRC7_SZ,VIN1_PARSER Output Port A Source 7 Size"
|
|
hexmask.long.word 0x1C 16.--26. 1. " WIDTH ,Source 7 width"
|
|
hexmask.long.word 0x1C 0.--10. 1. " HEIGHT ,Source 7 height"
|
|
line.long 0x20 "PORTA_SRC8_SZ,VIN1_PARSER Output Port A Source 8 Size"
|
|
hexmask.long.word 0x20 16.--26. 1. " WIDTH ,Source 8 width"
|
|
hexmask.long.word 0x20 0.--10. 1. " HEIGHT ,Source 8 height"
|
|
line.long 0x24 "PORTA_SRC9_SZ,VIN1_PARSER Output Port A Source 9 Size"
|
|
hexmask.long.word 0x24 16.--26. 1. " WIDTH ,Source 9 width"
|
|
hexmask.long.word 0x24 0.--10. 1. " HEIGHT ,Source 9 height"
|
|
line.long 0x28 "PORTA_SRC10_SZ,VIN1_PARSER Output Port A Source 10 Size"
|
|
hexmask.long.word 0x28 16.--26. 1. " WIDTH ,Source 10 width"
|
|
hexmask.long.word 0x28 0.--10. 1. " HEIGHT ,Source 10 height"
|
|
line.long 0x2C "PORTA_SRC11_SZ,VIN1_PARSER Output Port A Source 11 Size"
|
|
hexmask.long.word 0x2C 16.--26. 1. " WIDTH ,Source 11 width"
|
|
hexmask.long.word 0x2C 0.--10. 1. " HEIGHT ,Source 11 height"
|
|
line.long 0x30 "PORTA_SRC12_SZ,VIN1_PARSER Output Port A Source 12 Size"
|
|
hexmask.long.word 0x30 16.--26. 1. " WIDTH ,Source 12 width"
|
|
hexmask.long.word 0x30 0.--10. 1. " HEIGHT ,Source 12 height"
|
|
line.long 0x34 "PORTA_SRC13_SZ,VIN1_PARSER Output Port A Source 13 Size"
|
|
hexmask.long.word 0x34 16.--26. 1. " WIDTH ,Source 13 width"
|
|
hexmask.long.word 0x34 0.--10. 1. " HEIGHT ,Source 13 height"
|
|
line.long 0x38 "PORTA_SRC14_SZ,VIN1_PARSER Output Port A Source 14 Size"
|
|
hexmask.long.word 0x38 16.--26. 1. " WIDTH ,Source 14 width"
|
|
hexmask.long.word 0x38 0.--10. 1. " HEIGHT ,Source 14 height"
|
|
line.long 0x3C "PORTA_SRC15_SZ,VIN1_PARSER Output Port A Source 15 Size"
|
|
hexmask.long.word 0x3C 16.--26. 1. " WIDTH ,Source 15 width"
|
|
hexmask.long.word 0x3C 0.--10. 1. " HEIGHT ,Source 15 height"
|
|
if ((d.l(ad:0x48105a00+0x04)&0xf)==(0x0||0x1||0x2||0x3||0x5||0x6||0x7||0x8))
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "PORTA_DETVEC,VIN1_PARSER Port A Detector Vector"
|
|
else
|
|
hgroup.long 0xb0++0x3
|
|
hide.long 0x00 "PORTA_DETVEC,VIN1_PARSER Port A Detector Vector"
|
|
endif
|
|
tree.end
|
|
width 16.
|
|
tree "PORT B"
|
|
if ((d.l(ad:0x48105a00+0x0c)&0xf)==(0x0||0x1||0x2||0x3||0x5||0x6||0x7||0x8))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "PORTB_CONFIG0,VIN1_PARSER Configuration for Input Port B Register 0"
|
|
bitfld.long 0x00 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Error correction for the fvh control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ANALYZER_2X4X_SRCNUM_POS ,Srcnum position in 2x/4x mux mode (least significant nibble of)" "XV/fvh codeword,Horizontal blanking pixel value"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PIXCLK_EDGE_POLARITY ,PIXCLK edge polarity" "Rising,Falling"
|
|
bitfld.long 0x00 9. " FID_POLARITY ,Invert Determined Value of FID" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE ,Enable the port" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CLR_ASYNC_FIFO_RD ,Clear Async FIFO Read Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLR_ASYNC_FIFO_WR ,Clear Async FIFO Write Logic" "No effect,Clear"
|
|
bitfld.long 0x00 4.--5. " CTRL_CHAN_SEL ,Channel select" "Data[7:0] (8b/16b/24b),Data[15:8] (16b/24b),Data[23:16] (24b),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SYNC_TYPE ,Sync type" "Embedded sync single 4:2:2 YUV stream,Embedded sync 2x multiplexed 4:2:2 YUV stream,Embedded sync 4x multiplexed 4:2:2 YUV stream,Embedded sync line multiplexed 4:2:2 YUV stream,Discrete sync single 4:2:2 YUV stream,Embedded sync single RGB stream or single 444 YUV stream,Embedded sync 2x multiplexed RGB stream,Embedded sync 4x multiplexed RGB stream,Embedded sync line multiplexed RGB stream,Discrete sync single 8b RGB stream,Discrete sync single 24b RGB stream,?..."
|
|
elif ((d.l(ad:0x48105a00+0x0c)&0xf)==(0x4||0x9||0xa))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "PORTB_CONFIG0,VIN1_PARSER Configuration for Input Port B Register 0"
|
|
bitfld.long 0x00 24.--29. " FID_SKEW_POSTCOUNT ,Post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " FID_SKEW_PRECOUNT ,Pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15. " USE_ACTVID_HSYNC_N ,Line capture style" "HSYNC,ACTVID"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FID_DETECT_MODE ,FID detection mode" "Pin,VSYNC skew"
|
|
bitfld.long 0x00 13. " ACTVID_POLARITY ,ACTVID polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " VSYNC_POLARITY ,VSYNC polarity" "Low,High"
|
|
bitfld.long 0x00 11. " HSYNC_POLARITY ,HSYNC polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PIXCLK_EDGE_POLARITY ,PIXCLK edge polarity" "Rising,Falling"
|
|
bitfld.long 0x00 9. " FID_POLARITY ,Invert Determined Value of FID" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE ,Enable the port" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CLR_ASYNC_FIFO_RD ,Clear Async FIFO Read Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLR_ASYNC_FIFO_WR ,Clear Async FIFO Write Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SYNC_TYPE ,Sync type" "Embedded sync single 4:2:2 YUV stream,Embedded sync 2x multiplexed 4:2:2 YUV stream,Embedded sync 4x multiplexed 4:2:2 YUV stream,Embedded sync line multiplexed 4:2:2 YUV stream,Discrete sync single 4:2:2 YUV stream,Embedded sync single RGB stream or single 444 YUV stream,Embedded sync 2x multiplexed RGB stream,Embedded sync 4x multiplexed RGB stream,Embedded sync line multiplexed RGB stream,Discrete sync single 8b RGB stream,Discrete sync single 24b RGB stream,?..."
|
|
else
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "PORTB_CONFIG0,VIN1_PARSER Configuration for Input Port B Register 0"
|
|
bitfld.long 0x00 10. " PIXCLK_EDGE_POLARITY ,PIXCLK edge polarity" "Rising,Falling"
|
|
bitfld.long 0x00 9. " FID_POLARITY ,Invert Determined Value of FID" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE ,Enable the port" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CLR_ASYNC_FIFO_RD ,Clear Async FIFO Read Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLR_ASYNC_FIFO_WR ,Clear Async FIFO Write Logic" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SYNC_TYPE ,Sync type" "Embedded sync single 4:2:2 YUV stream,Embedded sync 2x multiplexed 4:2:2 YUV stream,Embedded sync 4x multiplexed 4:2:2 YUV stream,Embedded sync line multiplexed 4:2:2 YUV stream,Discrete sync single 4:2:2 YUV stream,Embedded sync single RGB stream or single 444 YUV stream,Embedded sync 2x multiplexed RGB stream,Embedded sync 4x multiplexed RGB stream,Embedded sync line multiplexed RGB stream,Discrete sync single 8b RGB stream,Discrete sync single 24b RGB stream,?..."
|
|
endif
|
|
if ((d.l(ad:0x48105a00+0x0c)&0xf)==(0x0||0x1||0x2||0x3||0x5||0x6||0x7||0x8))
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "PORTB_CONFIG1,VIN1_PARSER Configuration for Input Port B Register 1"
|
|
bitfld.long 0x00 12. " TVP5158_CHAN_ID_TYPE ,TVP5158 channel ID type" "All bits,Bits 2:0"
|
|
elif ((d.l(ad:0x48105a00+0x0c)&0xf)==(0x4||0x9||0xa))
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "PORTB_CONFIG1,VIN1_PARSER Configuration for Input Port B Register 1"
|
|
hexmask.long.word 0x00 0.--10. 1. " ANC_LINES ,Number of Ancillary Lines of data before the ACTIVE video lines start"
|
|
else
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x00 "PORTB_CONFIG1,VIN1_PARSER Configuration for Input Port B Register 1"
|
|
endif
|
|
width 16.
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x00 "PORTB_SRC,VIN1_PARSER Port B Source FID Register"
|
|
bitfld.long 0x00 31. " PRTB_SRC15_CURR_SOURCE_FID ,Source Field ID 15 for Current Field" "0,1"
|
|
bitfld.long 0x00 30. " PRTB_SRC15_PREV_SOURCE_FID ,Source Field ID 15 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PRTB_SRC14_CURR_SOURCE_FID ,Source Field ID 14 for Current Field" "0,1"
|
|
bitfld.long 0x00 28. " PRTB_SRC14_PREV_SOURCE_FID ,Source Field ID 14 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PRTB_SRC13_CURR_SOURCE_FID ,Source Field ID 13 for Current Field" "0,1"
|
|
bitfld.long 0x00 26. " PRTB_SRC13_PREV_SOURCE_FID ,Source Field ID 13 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PRTB_SRC12_CURR_SOURCE_FID ,Source Field ID 12 for Current Field" "0,1"
|
|
bitfld.long 0x00 24. " PRTB_SRC12_PREV_SOURCE_FID ,Source Field ID 12 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PRTB_SRC11_CURR_SOURCE_FID ,Source Field ID 11 for Current Field" "0,1"
|
|
bitfld.long 0x00 22. " PRTB_SRC11_PREV_SOURCE_FID ,Source Field ID 11 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PRTB_SRC10_CURR_SOURCE_FID ,Source Field ID 10 for Current Field" "0,1"
|
|
bitfld.long 0x00 20. " PRTB_SRC10_PREV_SOURCE_FID ,Source Field ID 10 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PRTB_SRC9_CURR_SOURCE_FID ,Source Field ID 9 for Current Field" "0,1"
|
|
bitfld.long 0x00 18. " PRTB_SRC9_PREV_SOURCE_FID ,Source Field ID 9 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PRTB_SRC8_CURR_SOURCE_FID ,Source Field ID 8 for Current Field" "0,1"
|
|
bitfld.long 0x00 16. " PRTB_SRC8_PREV_SOURCE_FID ,Source Field ID 8 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PRTB_SRC7_CURR_SOURCE_FID ,Source Field ID 7 for Current Field" "0,1"
|
|
bitfld.long 0x00 14. " PRTB_SRC7_PREV_SOURCE_FID ,Source Field ID 7 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PRTB_SRC6_CURR_SOURCE_FID ,Source Field ID 6 for Current Field" "0,1"
|
|
bitfld.long 0x00 12. " PRTB_SRC6_PREV_SOURCE_FID ,Source Field ID 6 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PRTB_SRC5_CURR_SOURCE_FID ,Source Field ID 5 for Current Field" "0,1"
|
|
bitfld.long 0x00 10. " PRTB_SRC5_PREV_SOURCE_FID ,Source Field ID 5 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PRTB_SRC4_CURR_SOURCE_FID ,Source Field ID 4 for Current Field" "0,1"
|
|
bitfld.long 0x00 8. " PRTB_SRC4_PREV_SOURCE_FID ,Source Field ID 4 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PRTB_SRC3_CURR_SOURCE_FID ,Source Field ID 3 for Current Field" "0,1"
|
|
bitfld.long 0x00 6. " PRTB_SRC3_PREV_SOURCE_FID ,Source Field ID 3 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PRTB_SRC2_CURR_SOURCE_FID ,Source Field ID 2 for Current Field" "0,1"
|
|
bitfld.long 0x00 4. " PRTB_SRC2_PREV_SOURCE_FID ,Source Field ID 2 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PRTB_SRC1_CURR_SOURCE_FID ,Source Field ID 1 for Current Field" "0,1"
|
|
bitfld.long 0x00 2. " PRTB_SRC1_PREV_SOURCE_FID ,Source Field ID 1 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PRTB_SRC0_CURR_SOURCE_FID ,Source Field ID 0 for Current Field" "0,1"
|
|
bitfld.long 0x00 0. " PRTB_SRC0_PREV_SOURCE_FID ,Source Field ID 0 for Previous Field" "0,1"
|
|
line.long 0x04 "PORTB_ENC,VIN1_PARSER Port B Encoder FID Register"
|
|
bitfld.long 0x04 31. " PRTB_SRC15_CURR_ENC_FID ,Encoder Field ID 15 for Current Field" "0,1"
|
|
bitfld.long 0x04 30. " PRTB_SRC15_PREV_ENC_FID ,Encoder Field ID 15 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 29. " PRTB_SRC14_CURR_ENC_FID ,Encoder Field ID 14 for Current Field" "0,1"
|
|
bitfld.long 0x04 28. " PRTB_SRC14_PREV_ENC_FID ,Encoder Field ID 14 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PRTB_SRC13_CURR_ENC_FID ,Encoder Field ID 13 for Current Field" "0,1"
|
|
bitfld.long 0x04 26. " PRTB_SRC13_PREV_ENC_FID ,Encoder Field ID 13 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 25. " PRTB_SRC12_CURR_ENC_FID ,Encoder Field ID 12 for Current Field" "0,1"
|
|
bitfld.long 0x04 24. " PRTB_SRC12_PREV_ENC_FID ,Encoder Field ID 12 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PRTB_SRC11_CURR_ENC_FID ,Encoder Field ID 11 for Current Field" "0,1"
|
|
bitfld.long 0x04 22. " PRTB_SRC11_PREV_ENC_FID ,Encoder Field ID 11 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 21. " PRTB_SRC10_CURR_ENC_FID ,Encoder Field ID 10 for Current Field" "0,1"
|
|
bitfld.long 0x04 20. " PRTB_SRC10_PREV_ENC_FID ,Encoder Field ID 10 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PRTB_SRC9_CURR_ENC_FID ,Encoder Field ID 9 for Current Field" "0,1"
|
|
bitfld.long 0x04 18. " PRTB_SRC9_PREV_ENC_FID ,Encoder Field ID 9 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " PRTB_SRC8_CURR_ENC_FID ,Encoder Field ID 8 for Current Field" "0,1"
|
|
bitfld.long 0x04 16. " PRTB_SRC8_PREV_ENC_FID ,Encoder Field ID 8 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 15. " PRTB_SRC7_CURR_ENC_FID ,Encoder Field ID 7 for Current Field" "0,1"
|
|
bitfld.long 0x04 14. " PRTB_SRC7_PREV_ENC_FID ,Encoder Field ID 7 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PRTB_SRC6_CURR_ENC_FID ,Encoder Field ID 6 for Current Field" "0,1"
|
|
bitfld.long 0x04 12. " PRTB_SRC6_PREV_ENC_FID ,Encoder Field ID 6 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PRTB_SRC5_CURR_ENC_FID ,Encoder Field ID 5 for Current Field" "0,1"
|
|
bitfld.long 0x04 10. " PRTB_SRC5_PREV_ENC_FID ,Encoder Field ID 5 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PRTB_SRC4_CURR_ENC_FID ,Encoder Field ID 4 for Current Field" "0,1"
|
|
bitfld.long 0x04 8. " PRTB_SRC4_PREV_ENC_FID ,Encoder Field ID 4 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PRTB_SRC3_CURR_ENC_FID ,Encoder Field ID 3 for Current Field" "0,1"
|
|
bitfld.long 0x04 6. " PRTB_SRC3_PREV_ENC_FID ,Encoder Field ID 3 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PRTB_SRC2_CURR_ENC_FID ,Encoder Field ID 2 for Current Field" "0,1"
|
|
bitfld.long 0x04 4. " PRTB_SRC2_PREV_ENC_FID ,Encoder Field ID 2 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PRTB_SRC1_CURR_ENC_FID ,Encoder Field ID 1 for Current Field" "0,1"
|
|
bitfld.long 0x04 2. " PRTB_SRC1_PREV_ENC_FID ,Encoder Field ID 1 for Previous Field" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PRTB_SRC0_CURR_ENC_FID ,Encoder Field ID 0 for Current Field" "0,1"
|
|
bitfld.long 0x04 0. " PRTB_SRC0_PREV_ENC_FID ,Encoder Field ID 0 for Previous Field" "0,1"
|
|
width 16.
|
|
group.long 0x70++0x3f
|
|
line.long 0x0 "PORTB_SRC0_SZ,VIN1_PARSER Output Port B Source 0 Size"
|
|
hexmask.long.word 0x0 16.--26. 1. " WIDTH ,Source 0 width"
|
|
hexmask.long.word 0x0 0.--10. 1. " HEIGHT ,Source 0 height"
|
|
line.long 0x4 "PORTB_SRC1_SZ,VIN1_PARSER Output Port B Source 1 Size"
|
|
hexmask.long.word 0x4 16.--26. 1. " WIDTH ,Source 1 width"
|
|
hexmask.long.word 0x4 0.--10. 1. " HEIGHT ,Source 1 height"
|
|
line.long 0x8 "PORTB_SRC2_SZ,VIN1_PARSER Output Port B Source 2 Size"
|
|
hexmask.long.word 0x8 16.--26. 1. " WIDTH ,Source 2 width"
|
|
hexmask.long.word 0x8 0.--10. 1. " HEIGHT ,Source 2 height"
|
|
line.long 0xC "PORTB_SRC3_SZ,VIN1_PARSER Output Port B Source 3 Size"
|
|
hexmask.long.word 0xC 16.--26. 1. " WIDTH ,Source 3 width"
|
|
hexmask.long.word 0xC 0.--10. 1. " HEIGHT ,Source 3 height"
|
|
line.long 0x10 "PORTB_SRC4_SZ,VIN1_PARSER Output Port B Source 4 Size"
|
|
hexmask.long.word 0x10 16.--26. 1. " WIDTH ,Source 4 width"
|
|
hexmask.long.word 0x10 0.--10. 1. " HEIGHT ,Source 4 height"
|
|
line.long 0x14 "PORTB_SRC5_SZ,VIN1_PARSER Output Port B Source 5 Size"
|
|
hexmask.long.word 0x14 16.--26. 1. " WIDTH ,Source 5 width"
|
|
hexmask.long.word 0x14 0.--10. 1. " HEIGHT ,Source 5 height"
|
|
line.long 0x18 "PORTB_SRC6_SZ,VIN1_PARSER Output Port B Source 6 Size"
|
|
hexmask.long.word 0x18 16.--26. 1. " WIDTH ,Source 6 width"
|
|
hexmask.long.word 0x18 0.--10. 1. " HEIGHT ,Source 6 height"
|
|
line.long 0x1C "PORTB_SRC7_SZ,VIN1_PARSER Output Port B Source 7 Size"
|
|
hexmask.long.word 0x1C 16.--26. 1. " WIDTH ,Source 7 width"
|
|
hexmask.long.word 0x1C 0.--10. 1. " HEIGHT ,Source 7 height"
|
|
line.long 0x20 "PORTB_SRC8_SZ,VIN1_PARSER Output Port B Source 8 Size"
|
|
hexmask.long.word 0x20 16.--26. 1. " WIDTH ,Source 8 width"
|
|
hexmask.long.word 0x20 0.--10. 1. " HEIGHT ,Source 8 height"
|
|
line.long 0x24 "PORTB_SRC9_SZ,VIN1_PARSER Output Port B Source 9 Size"
|
|
hexmask.long.word 0x24 16.--26. 1. " WIDTH ,Source 9 width"
|
|
hexmask.long.word 0x24 0.--10. 1. " HEIGHT ,Source 9 height"
|
|
line.long 0x28 "PORTB_SRC10_SZ,VIN1_PARSER Output Port B Source 10 Size"
|
|
hexmask.long.word 0x28 16.--26. 1. " WIDTH ,Source 10 width"
|
|
hexmask.long.word 0x28 0.--10. 1. " HEIGHT ,Source 10 height"
|
|
line.long 0x2C "PORTB_SRC11_SZ,VIN1_PARSER Output Port B Source 11 Size"
|
|
hexmask.long.word 0x2C 16.--26. 1. " WIDTH ,Source 11 width"
|
|
hexmask.long.word 0x2C 0.--10. 1. " HEIGHT ,Source 11 height"
|
|
line.long 0x30 "PORTB_SRC12_SZ,VIN1_PARSER Output Port B Source 12 Size"
|
|
hexmask.long.word 0x30 16.--26. 1. " WIDTH ,Source 12 width"
|
|
hexmask.long.word 0x30 0.--10. 1. " HEIGHT ,Source 12 height"
|
|
line.long 0x34 "PORTB_SRC13_SZ,VIN1_PARSER Output Port B Source 13 Size"
|
|
hexmask.long.word 0x34 16.--26. 1. " WIDTH ,Source 13 width"
|
|
hexmask.long.word 0x34 0.--10. 1. " HEIGHT ,Source 13 height"
|
|
line.long 0x38 "PORTB_SRC14_SZ,VIN1_PARSER Output Port B Source 14 Size"
|
|
hexmask.long.word 0x38 16.--26. 1. " WIDTH ,Source 14 width"
|
|
hexmask.long.word 0x38 0.--10. 1. " HEIGHT ,Source 14 height"
|
|
line.long 0x3C "PORTB_SRC15_SZ,VIN1_PARSER Output Port B Source 15 Size"
|
|
hexmask.long.word 0x3C 16.--26. 1. " WIDTH ,Source 15 width"
|
|
hexmask.long.word 0x3C 0.--10. 1. " HEIGHT ,Source 15 height"
|
|
if ((d.l(ad:0x48105a00+0x0c)&0xf)==(0x0||0x1||0x2||0x3||0x5||0x6||0x7||0x8))
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "PORTB_DETVEC,VIN1_PARSER Port B Detector Vector"
|
|
else
|
|
hgroup.long 0xb4++0x3
|
|
hide.long 0x00 "PORTB_DETVEC,VIN1_PARSER Port B Detector Vector"
|
|
endif
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
tree "VIN1_CSC_R2Y"
|
|
base ad:0x48105c00
|
|
width 7.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "CSC00,VIN1_CSC_R2Y Coefficients of Color Space Converter Register 0"
|
|
hexmask.long.word 0x00 16.--28. 1. " B0 ,B0 coefficient of color space converter"
|
|
hexmask.long.word 0x00 0.--12. 1. " A0 ,A0 coefficient of color space converter"
|
|
line.long 0x04 "CSC01,VIN1_CSC_R2Y Coefficients of Color Space Converter Register 1"
|
|
hexmask.long.word 0x04 16.--28. 1. " A1 ,A1 coefficient of color space converter"
|
|
hexmask.long.word 0x04 0.--12. 1. " C0 ,C0 coefficient of color space converter"
|
|
line.long 0x08 "CSC02,VIN1_CSC_R2Y Coefficients of Color Space Converter Register 2"
|
|
hexmask.long.word 0x08 16.--28. 1. " C1 ,C1 coefficient of color space converter"
|
|
hexmask.long.word 0x08 0.--12. 1. " B1 ,B1 coefficient of color space converter"
|
|
line.long 0x0c "CSC03,VIN1_CSC_R2Y Coefficients of Color Space Converter Register 3"
|
|
hexmask.long.word 0x0c 16.--28. 1. " B2 ,B2 coefficient of color space converter"
|
|
hexmask.long.word 0x0c 0.--12. 1. " A2 ,A2 coefficient of color space converter"
|
|
line.long 0x10 "CSC04,VIN1_CSC_R2Y Coefficients of Color Space Converter Register 4"
|
|
hexmask.long.word 0x10 16.--27. 1. " D0 ,D0 coefficient of color space converter"
|
|
hexmask.long.word 0x10 0.--12. 1. " C2 ,C2 coefficient of color space converter"
|
|
line.long 0x14 "CSC05,VIN1_CSC_R2Y Coefficients of Color Space Converter Register 5"
|
|
bitfld.long 0x14 28. " BYPASS ,Full CSC bypass mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x14 16.--27. 1. " D2 ,D2 coefficient of color space converter"
|
|
hexmask.long.word 0x14 0.--11. 1. " D1 ,D1 coefficient of color space converter"
|
|
width 11.
|
|
tree.end
|
|
tree "VIN1_SC"
|
|
base ad:0x48105d00
|
|
width 10.
|
|
group.long 0x00++0x1b
|
|
line.long 0x00 "CFG_SC0,VIN1_SC CFG_SC0 Register"
|
|
bitfld.long 0x00 16. " CFG_SELFGEN_FID ,Self Generate FID Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CFG_TRIM ,Trimming enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CFG_Y_PK_EN ,Luma peaking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CFG_ENABLE_SIN2_VER_INTP ,Bilinear interpolation select" "Original,Modified"
|
|
bitfld.long 0x00 10. " CFG_INTERLACE_I ,Input video format" "Progressive,Interlace"
|
|
bitfld.long 0x00 9. " CFG_HP_BYPASS ,Polyphase scaler bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CFG_DCM_4X ,4X decimation filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CFG_DCM_2X ,2X decimation filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CFG_AUTO_HS ,Hardware autoselect scalling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CFG_ENABLE_EV ,Edge-detection block output" "Forced to 0,Normal"
|
|
bitfld.long 0x00 4. " CFG_USE_RAV ,Vertical scaling filter select" "Poly-phase,Running average"
|
|
bitfld.long 0x00 3. " CFG_INVT_FID ,Field ID inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CFG_SC_BYPASS ,Scaling module bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 1. " CFG_LINEAR ,Scaling" "Anamorphic,Linear"
|
|
bitfld.long 0x00 0. " CFG_INTERLACE_O ,Output format of SC" "Progressive,Interlace"
|
|
line.long 0x04 "CFG_SC1,VIN1_SC CFG_SC1 Register"
|
|
hexmask.long 0x04 0.--26. 1. " CFG_ROW_ACC_INC ,Increment of row accumulator in vertical poly-phase filter"
|
|
line.long 0x08 "CFG_SC2,VIN1_SC CFG_SC2 Register"
|
|
hexmask.long 0x08 0.--27. 1. " CFG_ROW_ACC_OFFSET ,Vertical offset during vertical scaling"
|
|
line.long 0x0c "CFG_SC3,VIN1_SC CFG_SC3 Register"
|
|
hexmask.long 0x0c 0.--27. 1. " CFG_ROW_ACC_OFFSET_B ,Vertical offset during vertical scaling"
|
|
line.long 0x10 "CFG_SC4,VIN1_SC CFG_SC4 Register"
|
|
bitfld.long 0x10 28.--30. " CFG_NLIN_ACC_INIT_U ,3 MSBs of nlin_acc_init" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x10 24.--26. " CFG_LIN_ACC_INC_U ,3 MSBs of lin_acc_inc" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
hexmask.long.word 0x10 12.--22. 1. " CFG_TAR_W ,Scaled target picture width (in pixels)"
|
|
hexmask.long.word 0x10 0.--10. 1. " CFG_TAR_H ,Scaled target picture height (in lines)"
|
|
line.long 0x14 "CFG_SC5,VIN1_SC CFG_SC5 Register"
|
|
bitfld.long 0x14 24.--26. " CFG_NLIN_ACC_INC_U ,3 MSBs of nlin_acc_inc" "000,001,010,011,100,101,110,111"
|
|
hexmask.long.word 0x14 12.--22. 1. " CFG_SRC_W ,Source image width"
|
|
hexmask.long.word 0x14 0.--10. 1. " CFG_SRC_H ,Source image height"
|
|
line.long 0x18 "CFG_SC6,VIN1_SC CFG_SC6 Register"
|
|
hexmask.long.word 0x18 10.--19. 1. " CFG_ROW_ACC_INIT_RAV ,Running average filter row accumulator init value (bottom field of interlace format)"
|
|
hexmask.long.word 0x18 0.--9. 1. " CFG_ROW_ACC_INIT_RAV_B ,Running average filter row accumulator init value (progressive format / top field of interlace format)"
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "CFG_SC8,VIN1_SC CFG_SC8 Register"
|
|
hexmask.long.word 0x00 12.--22. 1. " CFG_NLIN_RIGHT ,Strip on right-hand side width (in anamorphic mode)"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFG_NLIN_LEFT ,Strip on left-hand side width (in anamorphic mode)"
|
|
line.long 0x04 "CFG_SC9,VIN1_SC CFG_SC9 Register"
|
|
line.long 0x08 "CFG_SC10,VIN1_SC CFG_SC10 Register"
|
|
line.long 0x0c "CFG_SC11,VIN1_SC CFG_SC11 Register"
|
|
line.long 0x10 "CFG_SC12,VIN1_SC CFG_SC12 Register"
|
|
hexmask.long 0x10 0.--24. 1. " CFG_COL_ACC_OFFSET ,Luma accumulators offset"
|
|
line.long 0x14 "CFG_SC13,VIN1_SC CFG_SC13 Register"
|
|
bitfld.long 0x14 24.--27. " CFG_DELTA_CHROMA_THR ,Range for chroma soft switch based on pixel differences" "0,1,2,3,4,5,6,7,8,?..."
|
|
hexmask.long.word 0x14 12.--21. 1. " CFG_CHROMA_INTP_THR ,Difference-threshold between chroma pixels"
|
|
hexmask.long.word 0x14 0.--9. 1. " CFG_SC_FACTOR_RAV ,Vertical scaling factor (1024*tarH/srcH)"
|
|
group.long 0x44++0x23
|
|
line.long 0x00 "CFG_SC17,VIN1_SC CFG_SC17 Register"
|
|
bitfld.long 0x00 28.--31. " CFG_DELTA_EV_THR ,Range of luma soft switch based on edge vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " CFG_DELTA_LUMA_THR ,Range for luma soft switch based on pixel differences" "0,1,2,3,4,5,6,7,8,?..."
|
|
hexmask.long.word 0x00 12.--21. 1. " CFG_EV_THR ,Edge vector threshold (8.2)"
|
|
line.long 0x04 "CFG_SC18,VIN1_SC CFG_SC18 Register"
|
|
hexmask.long.word 0x04 16.--24. 1. " CFG_CONF_DEFAULT ,Confidence factor when edge detection is disabled"
|
|
hexmask.long.word 0x04 0.--9. 1. " CFG_HS_FACTOR ,Horizontal scaling factor (tarWi/srcWi)(6.4)"
|
|
line.long 0x08 "CFG_SC19,VIN1_SC CFG_SC19 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " CFG_HPF_COEF3 ,Coefficient 3 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFG_HPF_COEF2 ,Coefficient 2 of HPF used in peaking filter"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " CFG_HPF_COEF1 ,Coefficient 1 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFG_HPF_COEF0 ,Coefficient 0 of HPF used in peaking filter"
|
|
line.long 0x0c "CFG_SC20,VIN1_SC CFG_SC20 Register"
|
|
hexmask.long.word 0x0C 20.--28. 1. " CFG_NL_LIMIT ,Maximum of clipping"
|
|
bitfld.long 0x0C 16.--18. " CFG_HPF_NORM_SHIFT ,Decimal point of hpf coefficient" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 8.--15. 1. " CFG_HPF_COEF5 ,Coefficient 5 of HPF used in peaking filter"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CFG_HPF_COEF4 ,Coefficient 4 of HPF used in peaking filter"
|
|
line.long 0x10 "CFG_SC21,VIN1_SC CFG_SC21 Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. " CFG_NL_LO_SLOPE ,Slope of nonlinear peaking function"
|
|
hexmask.long.word 0x10 0.--8. 1. " CFG_NL_LO_THR ,Threshold for nonlinear peaking function"
|
|
line.long 0x14 "CFG_SC22,VIN1_SC CFG_SC22 Register"
|
|
bitfld.long 0x14 16.--18. " CFG_NL_HI_SLOPE_SHIFT ,Slope of nonlinear peaking function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x14 0.--8. 1. " CFG_NL_HI_THR ,Threshold for nonlinear peaking function"
|
|
line.long 0x18 "CFG_SC23,VIN1_SC CFG_SC23 Register"
|
|
bitfld.long 0x18 28.--31. " CFG_MIN_GY_THR_RANGE ,Soft switch range of small Gy decay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x18 16.--25. 1. " CFG_MIN_GY_THR ,Threshold for soft switch of decay for small Gy"
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " CFG_GRADIENT_THR_RANGE ,Soft switch range of edge strength test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x18 0.--10. 1. " CFG_GRADIENT_THR ,Threshold for gradient for edge strength test"
|
|
line.long 0x1c "CFG_SC24,VIN1_SC CFG_SC24 Register"
|
|
hexmask.long.word 0x1C 16.--26. 1. " CFG_ORG_W ,Width of original input image"
|
|
hexmask.long.word 0x1C 0.--10. 1. " CFG_ORG_H ,Height of original input image"
|
|
line.long 0x20 "CFG_SC25,VIN1_SC CFG_SC25 Register"
|
|
hexmask.long.word 0x20 16.--26. 1. " CFG_OFF_W ,Horizontal offset from left of original input image"
|
|
hexmask.long.word 0x20 0.--10. 1. " CFG_OFF_H ,Vertical offset from top of original input image"
|
|
width 11.
|
|
tree.end
|
|
endif
|
|
tree "SD_VENC"
|
|
base ad:0x48105e00
|
|
width 11.
|
|
group.long 0x00++0x5f
|
|
line.long 0x00 "PID,SD_VENC Peripheral Identification Register"
|
|
line.long 0x04 "VMOD,SD_VENC VMOD Register"
|
|
bitfld.long 0x04 5. " DIIV ,Input data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 4. " CBAR ,Color-bar mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " UEL ,Unequal lines per field" "Normal,Unequal"
|
|
bitfld.long 0x04 2. " ITLC ,Scan mode" "Progressive,Interlace"
|
|
bitfld.long 0x04 0. " VIEN ,VENC enable" "Disabled,Enabled"
|
|
line.long 0x08 "SLAVE,SD_VENC SLAVE Register"
|
|
bitfld.long 0x08 4.--5. " FMD ,Field detection mode" "Latch,Raw,Vsync,Phase"
|
|
bitfld.long 0x08 3. " FIP ,FID input polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x08 2. " VIN ,VSYNC input polarity" "High,Low"
|
|
bitfld.long 0x08 1. " HIP ,HSYNC input polarity" "High,Low"
|
|
bitfld.long 0x08 0. " SLV ,Master/slave select" "Master,Slave"
|
|
line.long 0x0c "SIZE,SD_VENC SIZE Register"
|
|
hexmask.long.word 0x0C 16.--28. 1. " VITV ,Vertical interval"
|
|
hexmask.long.word 0x0C 0.--12. 1. " HITV ,Horizontal interval"
|
|
width 11.
|
|
line.long 0x10 "POL,SD_VENC Output Polarity Register"
|
|
bitfld.long 0x10 8. " TVDETGP_POL ,TVDETGP output polarity" "High,Low"
|
|
bitfld.long 0x10 7. " VOUT_AVID_POL ,VOUT AVID output polarity" "High,Low"
|
|
bitfld.long 0x10 6. " VOUT_FID_POL ,VOUT FID output polarity" "High,Low"
|
|
bitfld.long 0x10 5. " VOUT_VS_POL ,VOUT VSYNC output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x10 4. " VOUT_HS_POL ,VOUT HSYNC output polarity" "High,Low"
|
|
bitfld.long 0x10 3. " DTV_AVID_POL ,DTV AVID output polarity" "High,Low"
|
|
bitfld.long 0x10 2. " DTV_FID_POL ,DTV FID output polarity" "High,Low"
|
|
bitfld.long 0x10 1. " DTV_VS_POL ,DTV VSYNC output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x10 0. " DTV_HS_POL ,DTV HSYNC output polarity" "High,Low"
|
|
line.long 0x14 "DTVS0,SD_VENC DTVS0 Register"
|
|
hexmask.long.word 0x14 16.--28. 1. " DTV_HS_H_STP ,DTV HSYNC output stop pixel"
|
|
hexmask.long.word 0x14 0.--12. 1. " DTV_HS_H_STA ,DTV HSYNC output start pixel"
|
|
line.long 0x18 "DTVS1,SD_VENC DTVS1 Register"
|
|
hexmask.long.word 0x18 16.--28. 1. " DTV_VS_H_STP ,DTV VSYNC output stop pixel"
|
|
hexmask.long.word 0x18 0.--12. 1. " DTV_VS_H_STA ,DTV VSYNC output start pixel"
|
|
line.long 0x1c "DTVS2,SD_VENC DTVS2 Register"
|
|
hexmask.long.word 0x1c 16.--28. 1. " DTV_VS_V_STP ,DTV VSYNC output stop line"
|
|
hexmask.long.word 0x1c 0.--12. 1. " DTV_VS_V_STA ,DTV VSYNC output start line"
|
|
line.long 0x20 "DTVS3,SD_VENC DTVS3 Register"
|
|
hexmask.long.word 0x20 0.--12. 1. " DTV_FID_H_STA ,DTV FID output toggle pixel position"
|
|
line.long 0x24 "DTVS4,SD_VENC DTVS4 Register"
|
|
bitfld.long 0x24 29. " DTV_FID_F_STA1 ,DTV FID output start field" "0,1"
|
|
hexmask.long.word 0x24 16.--28. 1. " DTV_FID_V_STA1 ,DTV FID output start line"
|
|
bitfld.long 0x24 13. " DTV_FID_F_STA0 ,DTV FID output start field" "0,1"
|
|
hexmask.long.word 0x24 0.--12. 1. " DTV_FID_V_STA0 ,DTV FID output start line"
|
|
line.long 0x28 "DTVS5,SD_VENC DTVS5 Register"
|
|
hexmask.long.word 0x28 16.--28. 1. " DTV_AVID_H_STP ,DTV AVID output stop pixel"
|
|
hexmask.long.word 0x28 0.--12. 1. " DTV_AVID_H_STA ,DTV AVID output start pixel"
|
|
line.long 0x2c "DTVS6,SD_VENC DTVS6 Register"
|
|
hexmask.long.word 0x2c 16.--28. 1. " DTV_AVID_V_STP0 ,DTV AVID output stop line"
|
|
hexmask.long.word 0x2c 0.--12. 1. " DTV_AVID_V_STA0 ,DTV AVID output start line"
|
|
line.long 0x30 "DTVS7,SD_VENC DTVS7 Register"
|
|
hexmask.long.word 0x30 16.--28. 1. " DTV_AVID_V_STP1 ,DTV AVID output stop line"
|
|
hexmask.long.word 0x30 0.--12. 1. " DTV_AVID_V_STA1 ,DTV AVID output start line"
|
|
line.long 0x34 "VOUTS0,SD_VENC VOUTS0 Register"
|
|
hexmask.long.word 0x34 16.--28. 1. " VOUT_HS_H_STP ,VOUT HSYNC output stop pixel"
|
|
hexmask.long.word 0x34 0.--12. 1. " VOUT_HS_H_STA ,VOUT HSYNC output start pixel"
|
|
line.long 0x38 "VOUTS1,SD_VENC VOUTS1 Register"
|
|
hexmask.long.word 0x38 16.--28. 1. " VOUT_VS_H_STP ,VOUT VSYNC output stop pixel"
|
|
hexmask.long.word 0x38 0.--12. 1. " VOUT_VS_H_STA ,VOUT VSYNC output start pixel"
|
|
line.long 0x3c "VOUTS2,SD_VENC VOUTS2 Register"
|
|
hexmask.long.word 0x3c 16.--28. 1. " VOUT_VS_V_STP ,VOUT VSYNC output stop line"
|
|
hexmask.long.word 0x3c 0.--12. 1. " VOUT_VS_V_STA ,VOUT VSYNC output start line"
|
|
line.long 0x40 "VOUTS3,SD_VENC VOUTS3 Register"
|
|
hexmask.long.word 0x40 16.--28. 1. " VOUT_DELAY ,VOUT signal horizontal delay"
|
|
hexmask.long.word 0x40 0.--12. 1. " VOUT_FID_H_STA ,VOUT FID output toggle pixel position"
|
|
line.long 0x44 "VOUTS4,SD_VENC VOUTS4 Register"
|
|
bitfld.long 0x44 29. " VOUT_FID_F_STA1 ,VOUT FID output start field" "0,1"
|
|
hexmask.long.word 0x44 16.--28. 1. " VOUT_FID_V_STA1 ,VOUT FID output start line"
|
|
bitfld.long 0x44 13. " VOUT_FID_F_STA0 ,VOUT FID output start field" "0,1"
|
|
hexmask.long.word 0x44 0.--12. 1. " VOUT_FID_V_STA0 ,VOUT FID output start line"
|
|
line.long 0x48 "VOUTS5,SD_VENC VOUTS5 Register"
|
|
hexmask.long.word 0x48 16.--28. 1. " VOUT_AVID_H_STP ,VOUT AVID output stop pixel"
|
|
hexmask.long.word 0x48 0.--12. 1. " VOUT_AVID_H_STA ,VOUT AVID output start pixel"
|
|
line.long 0x4c "VOUTS6,SD_VENC VOUTS6 Register"
|
|
hexmask.long.word 0x4c 16.--28. 1. " VOUT_AVID_V_STP0 ,VOUT AVID output stop line"
|
|
hexmask.long.word 0x4c 0.--12. 1. " VOUT_AVID_V_STA0 ,VOUT AVID output start line"
|
|
line.long 0x50 "VOUTS7,SD_VENC VOUTS7 Register"
|
|
hexmask.long.word 0x50 16.--28. 1. " VOUT_AVID_V_STP1 ,VOUT AVID output stop line"
|
|
hexmask.long.word 0x50 0.--12. 1. " VOUT_AVID_V_STA1 ,VOUT AVID output start line"
|
|
line.long 0x54 "TVDETGP0,SD_VENC TVDETGP0 Register"
|
|
hexmask.long.word 0x54 16.--28. 1. " TVDETGP_H_STP ,TVDETGP output stop pixel"
|
|
hexmask.long.word 0x54 0.--12. 1. " TVDETGP_H_STA ,TVDETGP output start pixel"
|
|
line.long 0x58 "TVDETGP1,SD_VENC TVDETGP1 Register"
|
|
hexmask.long.word 0x58 16.--28. 1. " TVDETGP_V_STP ,TVDETGP output stop line"
|
|
hexmask.long.word 0x58 0.--12. 1. " TVDETGP_V_STA ,TVDETGP output start line"
|
|
line.long 0x5c "IRQ0,SD_VENC IRQ0 Register"
|
|
hexmask.long.word 0x5c 16.--28. 1. " IRQ_V_STA ,IRQ output start line"
|
|
hexmask.long.word 0x5c 0.--12. 1. " IRQ_H_STA ,IRQ output start pixel"
|
|
group.long 0x80++0x2b
|
|
line.long 0x00 "ESTAT,SD_VENC ESTAT Register"
|
|
bitfld.long 0x00 4. " FIDST ,Field ID monitor" "Low,High"
|
|
bitfld.long 0x00 1. " CAEST ,Closed caption status" "Ready,Busy"
|
|
bitfld.long 0x00 0. " CAOST ,Closed caption status" "Ready,Busy"
|
|
line.long 0x04 "ECTL,SD_VENC ECTL Register"
|
|
bitfld.long 0x04 9.--11. " FMT ,TV scan format select" "525i,625i,525P,625P,1080I,720P,1080P,?..."
|
|
bitfld.long 0x04 6. " PXLR ,Pixel rate" "1x,2x"
|
|
bitfld.long 0x04 5. " VBIEN ,VBI enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " BLS ,Blanking shape disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SVSW ,SD vertical sync width" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DUPS ,DAC 2x oversampling enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " UPS ,2x up-sampling enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " GAM ,Gamma correction" "Disabled,Enabled"
|
|
width 11.
|
|
line.long 0x08 "ETMG0,SD_VENC ETMG0 Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " AV_H_STP ,Active video horizontal stop position"
|
|
hexmask.long.word 0x08 0.--12. 1. " AV_H_STA ,Active video horizontal start position"
|
|
line.long 0x0c "ETMG1,SD_VENC ETMG1 Register"
|
|
hexmask.long.word 0x0c 16.--28. 1. " AV_V_STP0 ,Active video vertical stop position"
|
|
hexmask.long.word 0x0c 0.--12. 1. " AV_V_STA0 ,Active video vertical start position"
|
|
line.long 0x10 "ETMG2,SD_VENC ETMG2 Register"
|
|
hexmask.long.word 0x10 16.--28. 1. " AV_V_STP1 ,Active video vertical stop position"
|
|
hexmask.long.word 0x10 0.--12. 1. " AV_V_STA1 ,Active video vertical start position"
|
|
line.long 0x14 "ETMG3,SD_VENC ETMG3 Register"
|
|
hexmask.long.word 0x14 16.--24. 1. " BST_H_STP ,Color burst stop position"
|
|
hexmask.long.word 0x14 0.--8. 1. " BST_H_STA ,Color burst start position"
|
|
line.long 0x18 "ETMG4,SD_VENC ETMG4 Register"
|
|
hexmask.long.word 0x18 16.--28. 1. " VBI_H_STP ,VBI request stop position"
|
|
hexmask.long.word 0x18 0.--12. 1. " VBI_H_STA ,VBI request start position"
|
|
line.long 0x1c "CVBS0,SD_VENC CVBS0 Register"
|
|
hexmask.long.word 0x1c 16.--27. 1. " CSLVL ,CVBS sync amplitude"
|
|
hexmask.long.word 0x1c 0.--11. 1. " CTLVL ,CVBS sync-tip amplitude"
|
|
line.long 0x20 "CVBS1,SD_VENC CVBS1 Register"
|
|
hexmask.long.word 0x20 16.--27. 1. " CBLVL ,CVBS burst amplitude"
|
|
bitfld.long 0x20 8.--11. " CYDLY ,CVBS Y delay adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x20 4.--5. " CCM ,CVBS color modulation mode" "NTSC,PAL,SECAM,?..."
|
|
bitfld.long 0x20 2. " CLPF ,CVBS chroma LPF enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 1. " YLPF ,CVBS luma LPF enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " CPSR ,CVBS picture sync ratio" "10:4,7:3"
|
|
line.long 0x24 "CMPNT0,SD_VENC CMPNT0 Register"
|
|
hexmask.long.word 0x24 16.--27. 1. " MSLVL ,Component sync amplitude"
|
|
hexmask.long.word 0x24 0.--11. 1. " MTLVL ,Component sync-tip amplitude"
|
|
line.long 0x28 "CMPNT1,SD_VENC CMPNT1 Register"
|
|
bitfld.long 0x28 6. " MSOVR ,Sync on Pr (or R)" "No sync,Sync on"
|
|
bitfld.long 0x28 5. " MSOUB ,Sync on Pb (or B)" "No sync,Sync on"
|
|
bitfld.long 0x28 4. " MSOYG ,Sync on Y (or G)" "No sync,Sync on"
|
|
bitfld.long 0x28 1. " MRGB ,RGB select for component output" "YPbPr,RGB"
|
|
textline " "
|
|
bitfld.long 0x28 0. " MPSR ,Component picture sync ratio" "10:4,7:3"
|
|
group.long 0xAC++0x23
|
|
line.long 0x00 "CCSC0,SD_VENC CCSC0 Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CCSCB0 ,B0 coefficient of color space converter for CVBS"
|
|
hexmask.long.word 0x00 0.--12. 1. " CCSCA0 ,A0 coefficient of color space converter for CVBS"
|
|
line.long 0x04 "CCSC1,SD_VENC CCSC1 Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " CCSCD0 ,D0 coefficient of color space converter for CVBS"
|
|
hexmask.long.word 0x04 0.--12. 1. " CCSCC0 ,C0 coefficient of color space converter for CVBS"
|
|
line.long 0x08 "CCSC2,SD_VENC CCSC2 Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " CCSCE0 ,E0 coefficient of color space converter for CVBS"
|
|
line.long 0x0c "CCSC3,SD_VENC CCSC3 Register"
|
|
hexmask.long.word 0x0c 16.--28. 1. " CCSCB1 ,B1 coefficient of color space converter for CVBS"
|
|
hexmask.long.word 0x0c 0.--12. 1. " CCSCA1 ,A1 coefficient of color space converter for CVBS"
|
|
line.long 0x10 "CCSC4,SD_VENC CCSC4 Register"
|
|
hexmask.long.word 0x10 16.--28. 1. " CCSCD1 ,D1 coefficient of color space converter for CVBS"
|
|
hexmask.long.word 0x10 0.--12. 1. " CCSCC1 ,C1 coefficient of color space converter for CVBS"
|
|
line.long 0x14 "CCSC5,SD_VENC CCSC5 Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " CCSCE1 ,E1 coefficient of color space converter for CVBS"
|
|
line.long 0x18 "CCSC6,SD_VENC CCSC6 Register"
|
|
hexmask.long.word 0x18 16.--28. 1. " CCSCB2 ,B2 coefficient of color space converter for CVBS"
|
|
hexmask.long.word 0x18 0.--12. 1. " CCSCA2 ,A2 coefficient of color space converter for CVBS"
|
|
line.long 0x1c "CCSC7,SD_VENC CCSC7 Register"
|
|
hexmask.long.word 0x1c 16.--28. 1. " CCSCD2 ,D2 coefficient of color space converter for CVBS"
|
|
hexmask.long.word 0x1c 0.--12. 1. " CCSCC2 ,C2 coefficient of color space converter for CVBS"
|
|
line.long 0x20 "CCSC8,SD_VENC CCSC8 Register"
|
|
hexmask.long.word 0x20 0.--12. 1. " CCSCE2 ,E2 coefficient of color space converter for CVBS"
|
|
group.long 0xD0++0x23
|
|
line.long 0x00 "MCSC0,SD_VENC MCSC0 Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " MCSCB0 ,B0 coefficient of color space converter for component"
|
|
hexmask.long.word 0x00 0.--12. 1. " MCSCA0 ,A0 coefficient of color space converter for component"
|
|
line.long 0x04 "MCSC1,SD_VENC MCSC1 Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " MCSCD0 ,D0 coefficient of color space converter for component"
|
|
hexmask.long.word 0x04 0.--12. 1. " MCSCC0 ,C0 coefficient of color space converter for component"
|
|
line.long 0x08 "MCSC2,SD_VENC MCSC2 Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " MCSCE0 ,E0 coefficient of color space converter for component"
|
|
line.long 0x0c "MCSC3,SD_VENC MCSC3 Register"
|
|
hexmask.long.word 0x0c 16.--28. 1. " MCSCB1 ,B1 coefficient of color space converter for component"
|
|
hexmask.long.word 0x0c 0.--12. 1. " MCSCA1 ,A1 coefficient of color space converter for component"
|
|
line.long 0x10 "MCSC4,SD_VENC MCSC4 Register"
|
|
hexmask.long.word 0x10 16.--28. 1. " MCSCD1 ,D1 coefficient of color space converter for component"
|
|
hexmask.long.word 0x10 0.--12. 1. " MCSCC1 ,C1 coefficient of color space converter for component"
|
|
line.long 0x14 "MCSC5,SD_VENC MCSC5 Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MCSCE1 ,E1 coefficient of color space converter for component"
|
|
line.long 0x18 "MCSC6,SD_VENC MCSC6 Register"
|
|
hexmask.long.word 0x18 16.--28. 1. " MCSCB2 ,B2 coefficient of color space converter for component"
|
|
hexmask.long.word 0x18 0.--12. 1. " MCSCA2 ,A2 coefficient of color space converter for component"
|
|
line.long 0x1c "MCSC7,SD_VENC MCSC7 Register"
|
|
hexmask.long.word 0x1c 16.--28. 1. " MCSCD2 ,D2 coefficient of color space converter for component"
|
|
hexmask.long.word 0x1c 0.--12. 1. " MCSCC2 ,C2 coefficient of color space converter for component"
|
|
line.long 0x20 "MCSC8,SD_VENC MCSC8 Register"
|
|
hexmask.long.word 0x20 0.--12. 1. " MCSCE2 ,E2 coefficient of color space converter for component"
|
|
group.long 0xf4++0x6b
|
|
line.long 0x00 "CYGCLP,SD_VENC CYGCLP Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CYLCLP ,CVBS Y Lower Limit"
|
|
hexmask.long.word 0x00 0.--12. 1. " CYUCLP ,CVBS Y Upper Limit"
|
|
line.long 0x04 "CUBCLP,SD_VENC CUBCLP Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " CULCLP ,CVBS U Lower Limit"
|
|
hexmask.long.word 0x04 0.--12. 1. " CUUCLP ,CVBS U Upper Limit"
|
|
line.long 0x08 "CVRCLP,SD_VENC CVRCLP Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CVLCLP ,CVBS V Lower Limit"
|
|
hexmask.long.word 0x08 0.--12. 1. " CVUCLP ,CVBS V Upper Limit"
|
|
line.long 0x0c "MYGCLP,SD_VENC MYGCLP Register"
|
|
hexmask.long.word 0x0c 16.--28. 1. " MYGLCLP ,Component YG Lower Limit"
|
|
hexmask.long.word 0x0c 0.--12. 1. " MYGLCLP ,Component YG Upper Limit"
|
|
line.long 0x10 "MUBCLP,SD_VENC MUBCLP Register"
|
|
hexmask.long.word 0x10 16.--28. 1. " MUBLCLP ,Component UB Lower Limit"
|
|
hexmask.long.word 0x10 0.--12. 1. " MUBLCLP ,Component UB Upper Limit"
|
|
line.long 0x14 "MVRCLP,SD_VENC MVRCLP Register"
|
|
hexmask.long.word 0x14 16.--28. 1. " MVRLCLP ,Component VR Lower Limit"
|
|
hexmask.long.word 0x14 0.--12. 1. " MVRUCLP ,Component VR Upper Limit"
|
|
line.long 0x18 "YLPF0,SD_VENC YLPF0 Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " YLPFC3 ,Luma LPF coefficient 3"
|
|
hexmask.long.byte 0x18 16.--23. 1. " YLPFC2 ,Luma LPF coefficient 2"
|
|
hexmask.long.byte 0x18 8.--15. 1. " YLPFC1 ,Luma LPF coefficient 1"
|
|
hexmask.long.byte 0x18 0.--7. 1. " YLPFC0 ,Luma LPF coefficient 0"
|
|
line.long 0x1c "YLPF1,SD_VENC YLPF1 Register"
|
|
hexmask.long.byte 0x1c 8.--15. 1. " YLPFC5 ,Luma LPF coefficient 5"
|
|
hexmask.long.byte 0x1c 0.--7. 1. " YLPFC4 ,Luma LPF coefficient 4"
|
|
line.long 0x20 "CLPF0,SD_VENC CLPF0 Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " CLPFC3 ,Luma LPF coefficient 3"
|
|
hexmask.long.byte 0x20 16.--23. 1. " CLPFC2 ,Luma LPF coefficient 2"
|
|
hexmask.long.byte 0x20 8.--15. 1. " CLPFC1 ,Luma LPF coefficient 1"
|
|
hexmask.long.byte 0x20 0.--7. 1. " CLPFC0 ,Luma LPF coefficient 0"
|
|
line.long 0x24 "CLPF1,SD_VENC CLPF1 Register"
|
|
hexmask.long.byte 0x24 8.--15. 1. " CLPFC5 ,Luma LPF coefficient 5"
|
|
hexmask.long.byte 0x24 0.--7. 1. " CLPFC4 ,Luma LPF coefficient 4"
|
|
line.long 0x28 "UPF0,SD_VENC UPF0 Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " UPFC3 ,2x up-sampling filter LPF coefficient 3"
|
|
hexmask.long.byte 0x28 16.--23. 1. " UPFC2 ,2x up-sampling filter LPF coefficient 2"
|
|
hexmask.long.byte 0x28 8.--15. 1. " UPFC1 ,2x up-sampling filter LPF coefficient 1"
|
|
hexmask.long.byte 0x28 0.--7. 1. " UPFC0 ,2x up-sampling filter LPF coefficient 0"
|
|
line.long 0x2c "UPF1,SD_VENC UPF1 Register"
|
|
hexmask.long.byte 0x2c 16.--23. 1. " UPFC6 ,2x up-sampling filter LPF coefficient 6"
|
|
hexmask.long.byte 0x2c 8.--15. 1. " UPFC5 ,2x up-sampling filter LPF coefficient 5"
|
|
hexmask.long.byte 0x2c 0.--7. 1. " UPFC4 ,2x up-sampling filter LPF coefficient 4"
|
|
line.long 0x30 "L21CTL,SD_VENC L21CTL Register"
|
|
hexmask.long.byte 0x30 8.--15. 1. " L21DF ,Closed caption default data register"
|
|
bitfld.long 0x30 0.--1. " L21EN ,Closed caption field select" "No data,Odd,Even,Both"
|
|
line.long 0x34 "L21D0,SD_VENC L21D0 Register"
|
|
hexmask.long.byte 0x34 8.--15. 1. " L21DO0 ,Closed caption data0 (odd field)"
|
|
hexmask.long.byte 0x34 0.--7. 1. " L21DO1 ,Closed caption data1 (odd field)"
|
|
line.long 0x38 "L21DE,SD_VENC L21DE Register"
|
|
hexmask.long.byte 0x38 8.--15. 1. " L21DE0 ,Closed caption data0 (even field)"
|
|
hexmask.long.byte 0x38 0.--7. 1. " L21DE1 ,Closed caption data1 (even field)"
|
|
line.long 0x3c "WSS,SD_VENC WSS Register"
|
|
bitfld.long 0x3C 28. " WSS_EN ,CGMS/WSS insertion enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x3C 0.--19. 1. " WSS_DATA ,WSS data register"
|
|
line.long 0x40 "WIDBCTL,SD_VENC WIDBCTL Register"
|
|
bitfld.long 0x40 28. " VIDB_EN ,CGMS Type B packet insertion enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 0.--5. " VIDBH ,Type B packet header (h0-h5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x44 "WIDBDATA0,SD_VENC WIDBDATA0 Register"
|
|
line.long 0x48 "WIDBDATA1,SD_VENC WIDBDATA1 Register"
|
|
line.long 0x4c "WIDBDATA2,SD_VENC WIDBDATA2 Register"
|
|
line.long 0x50 "WIDBDATA3,SD_VENC WIDBDATA3 Register"
|
|
line.long 0x54 "SCCTL0,SD_VENC SCCTL0 Register"
|
|
hexmask.long.byte 0x54 16.--23. 1. " SCP0 ,Sub-carrier frequency parameter 0"
|
|
hexmask.long.word 0x54 0.--9. 1. " SCSD ,Sub-carrier initial phase value"
|
|
line.long 0x58 "SCCTL1,SD_VENC SCCTL1 Register"
|
|
hexmask.long.word 0x58 16.--31. 1. " SCP2 ,Sub-carrier frequency parameter 2"
|
|
hexmask.long.word 0x58 0.--15. 1. " SCP1 ,Sub-carrier frequency parameter 1"
|
|
line.long 0x5c "DACSEL,SD_VENC DACSEL Register"
|
|
bitfld.long 0x5c 27. " DA3E ,DAC3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x5c 26. " DA2E ,DAC2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x5c 25. " DA1E ,DAC1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x5c 24. " DA0E ,DAC0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5c 12.--15. " DA3S ,DAC3 output select" "CVBS,S-Video Y,S-Video C,Y/G,Pb/B,Pr/R,?..."
|
|
bitfld.long 0x5c 8.--11. " DA2S ,DAC2 output select" "CVBS,S-Video Y,S-Video C,Y/G,Pb/B,Pr/R,?..."
|
|
bitfld.long 0x5c 4.--7. " DA1S ,DAC1 output select" "CVBS,S-Video Y,S-Video C,Y/G,Pb/B,Pr/R,?..."
|
|
bitfld.long 0x5c 0.--3. " DA0S ,DAC0 output select" "CVBS,S-Video Y,S-Video C,Y/G,Pb/B,Pr/R,?..."
|
|
line.long 0x60 "DUPF0,SD_VENC DUPF0 Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " DUPFC3 ,DAC 2x oversampling filter coefficient 3"
|
|
hexmask.long.byte 0x60 16.--23. 1. " DUPFC2 ,DAC 2x oversampling filter coefficient 2"
|
|
hexmask.long.byte 0x60 8.--15. 1. " DUPFC1 ,DAC 2x oversampling filter coefficient 1"
|
|
hexmask.long.byte 0x60 0.--7. 1. " DUPFC0 ,DAC 2x oversampling filter coefficient 0"
|
|
line.long 0x64 "DUPF1,SD_VENC DUPF1 Register"
|
|
hexmask.long.byte 0x64 16.--23. 1. " DUPFC6 ,DAC 2x oversampling filter coefficient 6"
|
|
hexmask.long.byte 0x64 8.--15. 1. " DUPFC5 ,DAC 2x oversampling filter coefficient 5"
|
|
hexmask.long.byte 0x64 0.--7. 1. " DUPFC4 ,DAC 2x oversampling filter coefficient 4"
|
|
line.long 0x68 "DACTST,SD_VENC DACTST Register"
|
|
bitfld.long 0x68 17. " DAIV ,DAC output invert mode" "Not inverted,Inverted"
|
|
bitfld.long 0x68 16. " DADC ,DAC DC output mode" "Normal,DC output"
|
|
hexmask.long.word 0x68 0.--11. 1. " DALVL ,DAC DC level control"
|
|
width 11.
|
|
tree.end
|
|
sif (cpu()!="C6A8143")
|
|
tree "HD_VENC_D_VOUT1"
|
|
base ad:0x48106000
|
|
width 7.
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "CFG0,HD_VENC_D_VOUT1 CFG0 Register"
|
|
bitfld.long 0x00 31. " CMV ,Component video (480p and 576p) Macro-Vision enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " START ,Encoder enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " JED ,JEIDA output format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " HF_LINE ,Starting point of VOUT_VS and VOUT_FID signals on a video line" "Beginning,Middle"
|
|
bitfld.long 0x00 27. " VOUT_OFF ,Force the VOUT to 0s" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " S_422 ,CbCr format (When the VOUT output is in 4:2:2 YCbCr format)" "444-to-422,Every-other pixel"
|
|
bitfld.long 0x00 25. " I_VOUT_A ,Polarity of VOUT_ACTVID signal" "Not inverted,Inverted"
|
|
bitfld.long 0x00 24. " I_VOUT_H ,Polarity of VOUT_HS signal" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I_VOUT_V ,Polarity of VOUT_VS signal" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " I_OVOUT_F ,Polarity of VOUT_FID signal" "Not inverted,Inverted"
|
|
bitfld.long 0x00 21. " IVT_FID ,Polarity of DTV_FID signal" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DAC_RF1 ,Internal voltage reference of DAC3/4/5" "On,Off"
|
|
bitfld.long 0x00 19. " DAC_RF0 ,Internal voltage reference of DAC0/1/2" "On,Off"
|
|
bitfld.long 0x00 16.--18. " VOUT_FMT ,Format of digital video output port" "1 stream for SD video CCIR656,2 streams CCIR656 & YCbCr 422,3 streams & SAV/EAV & YCbCr 444 or RGB,3 streams & HS/VS/FID/ACTVID & RGB or YCbCr 444,2 streams & HS/VS/FID/ACTVID & YCbCr 422,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " STEST ,Self test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RD_MEM ,Read Gamma-correction memories by ARM" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BYPS_GC ,Bypass Gamma Correction block" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--12. " VOUT_CS ,Video data source for VOUT port" "Data manager,After Gamma correction,After color space conversion,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVT ,Invert data to DAC0, DAC1, and DAC2" "Not inverted,Inverted"
|
|
bitfld.long 0x00 9. " PWD_2 ,DAC2 power down" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PWD_1 ,DAC1 power down" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWD_0 ,DAC0 power down" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " Y_RGBN ,Color space setting" "RGB,YUV"
|
|
bitfld.long 0x00 5. " BYPS_CS ,Bypass color space converter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BYPS_2X ,Bypass 2X up-sampling block" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " I_PN ,Scan format" "Progressive,Interlace"
|
|
bitfld.long 0x00 0.--2. " DM_SEL ,Display mode selection" "480i,480p,1080i,720p,576i,576p,?..."
|
|
line.long 0x04 "CFG1,HD_VENC_D_VOUT1 CFG1 Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " B0 ,Coefficients of color space converter"
|
|
hexmask.long.word 0x04 0.--12. 1. " A0 ,Coefficients of color space converter"
|
|
line.long 0x08 "CFG2,HD_VENC_D_VOUT1 CFG2 Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " A1 ,Coefficients of color space converter"
|
|
hexmask.long.word 0x08 0.--12. 1. " C0 ,Coefficients of color space converter"
|
|
line.long 0x0C "CFG3,HD_VENC_D_VOUT1 CFG3 Register"
|
|
hexmask.long.word 0x0C 16.--28. 1. " C1 ,Coefficients of color space converter"
|
|
hexmask.long.word 0x0C 0.--12. 1. " B1 ,Coefficients of color space converter"
|
|
line.long 0x10 "CFG4,HD_VENC_D_VOUT1 CFG4 Register"
|
|
hexmask.long.word 0x10 16.--28. 1. " B2 ,Coefficients of color space converter"
|
|
hexmask.long.word 0x10 0.--12. 1. " A2 ,Coefficients of color space converter"
|
|
line.long 0x14 "CFG5,HD_VENC_D_VOUT1 CFG5 Register"
|
|
bitfld.long 0x14 28.--31. " MV_PK_H2 ,MacroVision AGC pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 16.--27. 1. " D0 ,Coefficients of color space converter"
|
|
hexmask.long.word 0x14 0.--12. 1. " C2 ,Coefficients of color space converter"
|
|
line.long 0x18 "CFG6,HD_VENC_D_VOUT1 CFG6 Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " MV_PK_L8 ,MacroVision AGC pulse"
|
|
hexmask.long.word 0x18 12.--23. 1. " D2 ,Coefficients of color space converter"
|
|
hexmask.long.word 0x18 0.--11. 1. " D1 ,Coefficients of color space converter"
|
|
line.long 0x1C "CFG7,HD_VENC_D_VOUT1 CFG7 Register"
|
|
hexmask.long.word 0x1C 20.--31. 1. " BL_0 ,Blank level of first channel output"
|
|
hexmask.long.byte 0x1C 12.--19. 1. " SHIFT0 ,Shifting coefficient of channel 0"
|
|
hexmask.long.word 0x1C 0.--11. 1. " SCALE0 ,Scaling coefficient of scalier 0"
|
|
line.long 0x20 "CFG8,HD_VENC_D_VOUT1 CFG8 Register"
|
|
hexmask.long.word 0x20 20.--31. 1. " BL_1 ,Blank level of second channel output"
|
|
hexmask.long.byte 0x20 12.--19. 1. " SHIFT1 ,Shifting coefficient of scalier 1"
|
|
hexmask.long.word 0x20 0.--11. 1. " SCALE1 ,Scaling coefficient of scalier 1"
|
|
line.long 0x24 "CFG9,HD_VENC_D_VOUT1 CFG9 Register"
|
|
hexmask.long.word 0x24 20.--31. 1. " BL_2 ,Blank level of third channel output"
|
|
hexmask.long.byte 0x24 12.--19. 1. " SHIFT2 ,Shifting coefficient of scalier 0"
|
|
hexmask.long.word 0x24 0.--11. 1. " SCALE2 ,Scaling coefficient of scalier 0"
|
|
line.long 0x28 "CFG10,HD_VENC_D_VOUT1 CFG10 Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " CLAMP ,CLAMP period of the sync pulse in 1080i format"
|
|
hexmask.long.word 0x28 12.--23. 1. " LINES ,Number of lines per frame"
|
|
hexmask.long.word 0x28 0.--11. 1. " PIXELS ,Number of pixels per line"
|
|
if (((d.l(ad:0x48106000))&0x8)==0x8)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "CFG11,HD_VENC_D_VOUT1 CFG11 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " EQ_WTH ,Width of pre-equalization and post-equalization pulse"
|
|
hexmask.long.word 0x00 12.--23. 1. " V_BLA2 ,Line location in a frame where the 2nd vertical blank period ends"
|
|
hexmask.long.word 0x00 0.--11. 1. " V_BLA1 ,Line location in a frame where 1st vertical blank period ends"
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "CFG11,HD_VENC_D_VOUT1 CFG11 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " EQ_WTH ,Width of pre-equalization and post-equalization pulse"
|
|
hexmask.long.word 0x00 0.--11. 1. " V_BLA1 ,Line location in a frame where 1st vertical blank period ends"
|
|
endif
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "CFG12,HD_VENC_D_VOUT1 CFG12 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " HS_WTH ,Width of HS pulse"
|
|
hexmask.long.word 0x00 12.--23. 1. " ACT_PIX ,Number of active pixels in one video line"
|
|
hexmask.long.word 0x00 0.--11. 1. " H_BLANK ,Location of the last non-active pixel on each line in front of the active video"
|
|
if (((d.l(ad:0x48106000))&0x8)==0x8)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "CFG13,HD_VENC_D_VOUT1 CFG13 Register"
|
|
bitfld.long 0x00 24.--27. " CBCR_S2 ,High-4-bits of CBCR_S1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 12.--23. 1. " OSD_HBI_ST ,Starting location of DTV_HBI signal"
|
|
hexmask.long.word 0x00 0.--11. 1. " END_F1 ,Last line of the first field"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "CFG13,HD_VENC_D_VOUT1 CFG13 Register"
|
|
bitfld.long 0x00 24.--27. " CBCR_S2 ,High-4-bits of CBCR_S1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 12.--23. 1. " OSD_HBI_ST ,Starting location of DTV_HBI signal"
|
|
endif
|
|
group.long 0x38++0x7
|
|
line.long 0x00 "CFG14,HD_VENC_D_VOUT1 CFG14 Register"
|
|
bitfld.long 0x00 24.--27. " CBCR_S1 ,Shifting of active video of channel CB and CR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 12.--23. 1. " SYNC_L ,Low level of the sync pulse"
|
|
hexmask.long.word 0x00 0.--11. 1. " SYNC_H ,High level of the sync pulse of a tri-level sync system"
|
|
line.long 0x04 "CFG15,HD_VENC_D_VOUT1 CFG15 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " VOUT_HS_WD ,Width of VOUT_HS pulse"
|
|
hexmask.long.word 0x04 12.--23. 1. " VOUT_AVD_HW ,Width of each active video line"
|
|
hexmask.long.word 0x04 0.--11. 1. " VOUT_AVST_H ,For VOUT interface"
|
|
if (((d.l(ad:0x48106000))&0x8)==0x8)
|
|
group.long 0x40++0x13
|
|
line.long 0x00 "CFG16,HD_VENC_D_VOUT1 CFG16 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BP_PK_L ,Peak value of BP pulse when MacroVision is enabled"
|
|
hexmask.long.word 0x00 12.--23. 1. " VOUT_AVST_V1 ,First active line of the first field in a frame"
|
|
hexmask.long.word 0x00 0.--11. 1. " VOUT_HS_ST ,Starting location of the HS pulse on each line"
|
|
line.long 0x04 "CFG17,HD_VENC_D_VOUT1 CFG17 Register"
|
|
bitfld.long 0x04 24.--26. " BP_PK_H ,Peak value of BP pulse when MacroVision is enabled" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 12.--23. 1. " VOUT_AVD_VW1 ,Number of active lines in the first field"
|
|
hexmask.long.word 0x04 0.--11. 1. " VOUT_AVST_V2 ,First active line of second field in a frame"
|
|
line.long 0x08 "CFG18,HD_VENC_D_VOUT1 CFG18 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " VOUT_VS_WD1 ,Width of the VS pulse of the first field"
|
|
hexmask.long.word 0x08 12.--23. 1. " VOUT_VS_ST1 ,Starting location of VS pulse of the first field"
|
|
hexmask.long.word 0x08 0.--11. 1. " VOUT_AVD_VW2 ,Number of active lines in the second field"
|
|
line.long 0x0C "CFG19,HD_VENC_D_VOUT1 CFG19 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " VOUT_VS_WD2 ,Width of the VS pulse of the second field"
|
|
hexmask.long.word 0x0C 12.--23. 1. " VOUT_FID_ST1 ,Starting location of the first field"
|
|
hexmask.long.word 0x0C 0.--11. 1. " VOUT_VS_ST2 ,Starting location of the VS of the second field"
|
|
line.long 0x10 "CFG20,HD_VENC_D_VOUT1 CFG20 Register"
|
|
hexmask.long.word 0x10 12.--23. 1. " osd_fid_st2 ,Starting location of the second field"
|
|
hexmask.long.word 0x10 0.--11. 1. " vout_fid_st2 ,Starting location of the second field"
|
|
else
|
|
group.long 0x40++0xF
|
|
line.long 0x00 "CFG16,HD_VENC_D_VOUT1 CFG16 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BP_PK_L ,Peak value of BP pulse when MacroVision is enabled"
|
|
hexmask.long.word 0x00 12.--23. 1. " VOUT_AVST_V1 ,first active line in a frame"
|
|
hexmask.long.word 0x00 0.--11. 1. " VOUT_HS_ST ,Starting location of the HS pulse on each line"
|
|
line.long 0x04 "CFG17,HD_VENC_D_VOUT1 CFG17 Register"
|
|
bitfld.long 0x04 24.--26. " BP_PK_H ,Peak value of BP pulse when MacroVision is enabled" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 12.--23. 1. " VOUT_AVD_VW1 ,Number of active video lines in a frame"
|
|
line.long 0x08 "CFG18,HD_VENC_D_VOUT1 CFG18 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " VOUT_VS_WD1 ,Width of the VS pulse"
|
|
hexmask.long.word 0x08 12.--23. 1. " VOUT_VS_ST1 ,Starting location of the VS pulse in a frame"
|
|
line.long 0x0C "CFG19,HD_VENC_D_VOUT1 CFG19 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " VOUT_VS_WD2 ,Width of the VS pulse of the second field"
|
|
hexmask.long.word 0x0C 12.--23. 1. " VOUT_FID_ST1 ,Location where the VOUT_FID will be toggled"
|
|
endif
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "CFG21,HD_VENC_D_VOUT1 CFG21 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " OSD_HS_WD ,Width of DTV_HS pulse"
|
|
hexmask.long.word 0x00 12.--23. 1. " OSD_AVD_HW ,Width of each active video line"
|
|
hexmask.long.word 0x00 0.--11. 1. " OSD_AVST_H ,Location of the last non-active pixel on each line (OSD interface)"
|
|
if (((d.l(ad:0x48106000))&0x8)==0x8)
|
|
group.long 0x58++0xF
|
|
line.long 0x00 "CFG22,HD_VENC_D_VOUT1 CFG22 Register"
|
|
hexmask.long.word 0x00 12.--23. 1. " OSD_AVST_V1 ,First active line of first field in a frame"
|
|
hexmask.long.word 0x00 0.--11. 1. " OSD_HS_ST ,Starting location of the DTV_HS pulse on each line"
|
|
line.long 0x04 "CFG23,HD_VENC_D_VOUT1 CFG23 Register"
|
|
hexmask.long.word 0x04 12.--23. 1. " OSD_AVD_VW1 ,Number of active lines in the first field"
|
|
hexmask.long.word 0x04 0.--11. 1. " OSD_AVST_V2 ,First active line of second field in a frame"
|
|
line.long 0x08 "CFG24,HD_VENC_D_VOUT1 CFG24 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " OSD_VS_WD1 ,Width of the first DTV_VS pulse (lines) in a frame"
|
|
hexmask.long.word 0x08 12.--23. 1. " OSD_VS_ST1 ,Starting location of the DTV_VS of first field"
|
|
hexmask.long.word 0x08 0.--11. 1. " OSD_AVD_VW2 ,Number of active lines in the second field"
|
|
line.long 0x0C "CFG25,HD_VENC_D_VOUT1 CFG25 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " OSD_VS_WD2 ,Width of the second DTV_VS pulse (lines)"
|
|
hexmask.long.word 0x0C 12.--23. 1. " OSD_FID_ST1 ,Starting location of the first field"
|
|
hexmask.long.word 0x0C 0.--11. 1. " OSD_VS_ST2 ,Starting location of the VS of the second field"
|
|
else
|
|
group.long 0x58++0xF
|
|
line.long 0x00 "CFG22,HD_VENC_D_VOUT1 CFG22 Register"
|
|
hexmask.long.word 0x00 12.--23. 1. " OSD_AVST_V1 ,First active line in a frame"
|
|
hexmask.long.word 0x00 0.--11. 1. " OSD_HS_ST ,Starting location of the DTV_HS pulse on each line"
|
|
line.long 0x04 "CFG23,HD_VENC_D_VOUT1 CFG23 Register"
|
|
hexmask.long.word 0x04 12.--23. 1. " OSD_AVD_VW1 ,Number of active lines in a frame"
|
|
line.long 0x08 "CFG24,HD_VENC_D_VOUT1 CFG24 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " OSD_VS_WD1 ,Width of the first DTV_VS pulse (lines) in a frame"
|
|
hexmask.long.word 0x08 12.--23. 1. " OSD_VS_ST1 ,Starting location of the DTV_VS"
|
|
line.long 0x0C "CFG25,HD_VENC_D_VOUT1 CFG25 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " OSD_VS_WD2 ,Width of the second DTV_VS pulse (lines)"
|
|
hexmask.long.word 0x0C 12.--23. 1. " OSD_FID_ST1 ,Location where the DTV_FID will be toggled"
|
|
endif
|
|
group.long 0x68++0xB
|
|
line.long 0x00 "CFG26,HD_VENC_D_VOUT1 CFG26 Register"
|
|
bitfld.long 0x00 28.--30. " N10_B ,Pseudo-sync pulse spacing control of format A" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " N10_A ,Pseudo-sync pulse spacing control of format A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " N9_B ,Location of 1st Pseudo-sync pulse of format B" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " N9_A ,Location of 1st pseudo-sync pulse of format A" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " N8_B ,Pseudo-sync pulse duration control of format B" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " N8_A ,Pseudo-sync pulse duration control of format A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. " NO_5 ,480i component MacroVision on/off control" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NO_4 ,End of field back porch pulse control" "Off,On"
|
|
bitfld.long 0x00 2. " NO_2 ,AGC pulse amplitude control" "Maximum,Varied"
|
|
bitfld.long 0x00 0.--1. " NO_1_0 ,Level reduction" "No Reduction,Reserved,None-VBI period,VBI & Active video period"
|
|
line.long 0x04 "CFG27,HD_VENC_D_VOUT1 CFG27 Register"
|
|
bitfld.long 0x04 30. " N12_14 ,Pseudo-Sync pulse and AGC pulse line 21 format" "A,B"
|
|
bitfld.long 0x04 29. " N12_13 ,Pseudo-Sync pulse and AGC pulse line 20 format" "A,B"
|
|
bitfld.long 0x04 28. " N12_12 ,Pseudo-Sync pulse and AGC pulse line 19 format" "A,B"
|
|
textline " "
|
|
bitfld.long 0x04 27. " N12_11 ,Pseudo-Sync pulse and AGC pulse line 18 format" "A,B"
|
|
bitfld.long 0x04 26. " N12_10 ,Pseudo-Sync pulse and AGC pulse line 17 format" "A,B"
|
|
bitfld.long 0x04 25. " N12_9 ,Pseudo-Sync pulse and AGC pulse line 16 format" "A,B"
|
|
textline " "
|
|
bitfld.long 0x04 24. " N12_8 ,Pseudo-Sync pulse and AGC pulse line 15 format" "A,B"
|
|
bitfld.long 0x04 23. " N12_7 ,Pseudo-Sync pulse and AGC pulse line 14 format" "A,B"
|
|
bitfld.long 0x04 22. " N12_6 ,Pseudo-Sync pulse and AGC pulse line 13 format" "A,B"
|
|
textline " "
|
|
bitfld.long 0x04 21. " N12_5 ,Pseudo-Sync pulse and AGC pulse line 12 format" "A,B"
|
|
bitfld.long 0x04 20. " N12_4 ,Pseudo-Sync pulse and AGC pulse line 11 format" "A,B"
|
|
bitfld.long 0x04 19. " N12_3 ,Pseudo-Sync pulse and AGC pulse line 10 format" "A,B"
|
|
textline " "
|
|
bitfld.long 0x04 18. " N12_2 ,Pseudo-Sync pulse and AGC pulse line 9 format" "A,B"
|
|
bitfld.long 0x04 17. " N12_1 ,Pseudo-Sync pulse and AGC pulse line 8 format" "A,B"
|
|
bitfld.long 0x04 16. " N12_0 ,Pseudo-Sync pulse and AGC pulse line 7 format" "A,B"
|
|
textline " "
|
|
bitfld.long 0x04 14. " N11_14 ,Pseudo-sync and AGC pulse enable line 21" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " N11_13 ,Pseudo-sync and AGC pulse enable line 20" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " N11_12 ,Pseudo-sync and AGC pulse enable line 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " N11_11 ,Pseudo-sync and AGC pulse enable line 18" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " N11_10 ,Pseudo-sync and AGC pulse enable line 17" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " N11_9 ,Pseudo-sync and AGC pulse enable line 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " N11_8 ,Pseudo-sync and AGC pulse enable line 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " N11_7 ,Pseudo-sync and AGC pulse enable line 14" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " N11_6 ,Pseudo-sync and AGC pulse enable line 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " N11_5 ,Pseudo-sync and AGC pulse enable line 12" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " N11_4 ,Pseudo-sync and AGC pulse enable line 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " N11_3 ,Pseudo-sync and AGC pulse enable line 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " N11_2 ,Pseudo-sync and AGC pulse enable line 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " N11_1 ,Pseudo-sync and AGC pulse enable line 8" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " N11_0 ,Pseudo-sync and AGC pulse enable line 7" "Disabled,Enabled"
|
|
width 7.
|
|
line.long 0x08 "CFG28,HD_VENC_D_VOUT1 CFG28 Register"
|
|
bitfld.long 0x08 20.--23. " N15_3_0 ,BP pulse insertion after the vertical sync (line for 525i/625i)" "No BP,7 and 270/4 and 316,7-8&270-271/4-5&316-317,7-9&270-272/4-6&316-318,7-10&270-273/4-7&316-319,7-11&270-274/4-8&316-320,7-12&270-275/4-9&316-321,7-13&270-276/4-10&316-322,7-14&270-277/4-11&316-323,7-15&270-278/4-12&316-324,7-16&270-279/4-13&316-325,7-17&270-280/4-14&316-326,7-18&270-281/4-15&316-327,7-19&270-282/4-16&316-328,7-20&270-283/4-17&316-329,7-21&270-284/4-18&316-330"
|
|
bitfld.long 0x08 16.--19. " N15_7_4 ,BP pulse insertion before the vertical sync (line for 525i/625i)" "no BP,3&266/312&625,2-3&265-266/311-312&624-625,1-3&264-266/310-312&623-625,1-3&263-266/309-312&622-625,1-3&262-266/308-312&621-625,1-3&261-266/307-312&620-625,1-3&260-266/306-312&619-625,1-3&259-266/305-312&618-625,1-3&258-266/304-312&617-625,1-3&257-266/303-312&616-625,1-3&256-266/302-312&615-625,1-3&255-266/301-312&614-625,1-3&254-266/300-312&613-625,1-3&253-266/209-312&612-625,514-525&1-3&264-266/298-312&611-625"
|
|
textline " "
|
|
bitfld.long 0x08 15. " N14_7 ,Format B PS/AGC pulse 8st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " N14_6 ,Format B PS/AGC pulse 7st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " N14_5 ,Format B PS/AGC pulse 6st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " N14_4 ,Format B PS/AGC pulse 5st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " N14_3 ,Format B PS/AGC pulse 4st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " N14_2 ,Format B PS/AGC pulse 3st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " N14_1 ,Format B PS/AGC pulse 2st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " N14_0 ,Format B PS/AGC pulse 1st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " N13_7 ,Format A PS/AGC pulse 8st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " N13_6 ,Format A PS/AGC pulse 7st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " N13_5 ,Format A PS/AGC pulse 6st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " N13_4 ,Format A PS/AGC pulse 5st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " N13_3 ,Format A PS/AGC pulse 4st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " N13_2 ,Format A PS/AGC pulse 3st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " N13_1 ,Format A PS/AGC pulse 2st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " N13_0 ,Format A PS/AGC pulse 1st pair enable" "Disabled,Enabled"
|
|
width 16.
|
|
hgroup.long 0x1000++0x03
|
|
hide.long 0x00 "LUT0_LUT1_LUT2,HD_VENC_D_VOUT1 LUT0_LUT1_LUT2 Memory Region"
|
|
button "LUT0_LUT1_LUT2" "d (ad:0x48106000+0x1000)--(ad:0x48106000+0x1FFF) /long"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "HD_VENC_D_VOUT0"
|
|
base ad:0x4810a000
|
|
width 7.
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "CFG0,HD_VENC_D_VOUT0 CFG0 Register"
|
|
bitfld.long 0x00 31. " CMV ,Component video (480p and 576p) Macro-Vision enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " START ,Encoder enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " JED ,JEIDA output format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " HF_LINE ,Starting point of VOUT_VS and VOUT_FID signals on a video line" "Beginning,Middle"
|
|
bitfld.long 0x00 27. " VOUT_OFF ,Force the VOUT to 0s" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " S_422 ,CbCr format (When the VOUT output is in 4:2:2 YCbCr format)" "444-to-422,Every-other pixel"
|
|
bitfld.long 0x00 25. " I_VOUT_A ,Polarity of VOUT_ACTVID signal" "Not inverted,Inverted"
|
|
bitfld.long 0x00 24. " I_VOUT_H ,Polarity of VOUT_HS signal" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I_VOUT_V ,Polarity of VOUT_VS signal" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " I_OVOUT_F ,Polarity of VOUT_FID signal" "Not inverted,Inverted"
|
|
bitfld.long 0x00 21. " IVT_FID ,Polarity of DTV_FID signal" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DAC_RF1 ,Internal voltage reference of DAC3/4/5" "On,Off"
|
|
bitfld.long 0x00 19. " DAC_RF0 ,Internal voltage reference of DAC0/1/2" "On,Off"
|
|
bitfld.long 0x00 16.--18. " VOUT_FMT ,Format of digital video output port" "1 stream for SD video CCIR656,2 streams CCIR656 & YCbCr 422,3 streams & SAV/EAV & YCbCr 444 or RGB,3 streams & HS/VS/FID/ACTVID & RGB or YCbCr 444,2 streams & HS/VS/FID/ACTVID & YCbCr 422,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " STEST ,Self test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RD_MEM ,Read Gamma-correction memories by ARM" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BYPS_GC ,Bypass Gamma Correction block" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--12. " VOUT_CS ,Video data source for VOUT port" "Data manager,After Gamma correction,After color space conversion,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVT ,Invert data to DAC0, DAC1, and DAC2" "Not inverted,Inverted"
|
|
bitfld.long 0x00 9. " PWD_2 ,DAC2 power down" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PWD_1 ,DAC1 power down" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWD_0 ,DAC0 power down" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " Y_RGBN ,Color space setting" "RGB,YUV"
|
|
bitfld.long 0x00 5. " BYPS_CS ,Bypass color space converter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BYPS_2X ,Bypass 2X up-sampling block" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " I_PN ,Scan format" "Progressive,Interlace"
|
|
bitfld.long 0x00 0.--2. " DM_SEL ,Display mode selection" "480i,480p,1080i,720p,576i,576p,?..."
|
|
line.long 0x04 "CFG1,HD_VENC_D_VOUT0 CFG1 Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " B0 ,Coefficients of color space converter"
|
|
hexmask.long.word 0x04 0.--12. 1. " A0 ,Coefficients of color space converter"
|
|
line.long 0x08 "CFG2,HD_VENC_D_VOUT0 CFG2 Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " A1 ,Coefficients of color space converter"
|
|
hexmask.long.word 0x08 0.--12. 1. " C0 ,Coefficients of color space converter"
|
|
line.long 0x0C "CFG3,HD_VENC_D_VOUT0 CFG3 Register"
|
|
hexmask.long.word 0x0C 16.--28. 1. " C1 ,Coefficients of color space converter"
|
|
hexmask.long.word 0x0C 0.--12. 1. " B1 ,Coefficients of color space converter"
|
|
line.long 0x10 "CFG4,HD_VENC_D_VOUT0 CFG4 Register"
|
|
hexmask.long.word 0x10 16.--28. 1. " B2 ,Coefficients of color space converter"
|
|
hexmask.long.word 0x10 0.--12. 1. " A2 ,Coefficients of color space converter"
|
|
line.long 0x14 "CFG5,HD_VENC_D_VOUT0 CFG5 Register"
|
|
bitfld.long 0x14 28.--31. " MV_PK_H2 ,MacroVision AGC pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 16.--27. 1. " D0 ,Coefficients of color space converter"
|
|
hexmask.long.word 0x14 0.--12. 1. " C2 ,Coefficients of color space converter"
|
|
line.long 0x18 "CFG6,HD_VENC_D_VOUT0 CFG6 Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " MV_PK_L8 ,MacroVision AGC pulse"
|
|
hexmask.long.word 0x18 12.--23. 1. " D2 ,Coefficients of color space converter"
|
|
hexmask.long.word 0x18 0.--11. 1. " D1 ,Coefficients of color space converter"
|
|
line.long 0x1C "CFG7,HD_VENC_D_VOUT0 CFG7 Register"
|
|
hexmask.long.word 0x1C 20.--31. 1. " BL_0 ,Blank level of first channel output"
|
|
hexmask.long.byte 0x1C 12.--19. 1. " SHIFT0 ,Shifting coefficient of channel 0"
|
|
hexmask.long.word 0x1C 0.--11. 1. " SCALE0 ,Scaling coefficient of scalier 0"
|
|
line.long 0x20 "CFG8,HD_VENC_D_VOUT0 CFG8 Register"
|
|
hexmask.long.word 0x20 20.--31. 1. " BL_1 ,Blank level of second channel output"
|
|
hexmask.long.byte 0x20 12.--19. 1. " SHIFT1 ,Shifting coefficient of scalier 1"
|
|
hexmask.long.word 0x20 0.--11. 1. " SCALE1 ,Scaling coefficient of scalier 1"
|
|
line.long 0x24 "CFG9,HD_VENC_D_VOUT0 CFG9 Register"
|
|
hexmask.long.word 0x24 20.--31. 1. " BL_2 ,Blank level of third channel output"
|
|
hexmask.long.byte 0x24 12.--19. 1. " SHIFT2 ,Shifting coefficient of scalier 0"
|
|
hexmask.long.word 0x24 0.--11. 1. " SCALE2 ,Scaling coefficient of scalier 0"
|
|
line.long 0x28 "CFG10,HD_VENC_D_VOUT0 CFG10 Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " CLAMP ,CLAMP period of the sync pulse in 1080i format"
|
|
hexmask.long.word 0x28 12.--23. 1. " LINES ,Number of lines per frame"
|
|
hexmask.long.word 0x28 0.--11. 1. " PIXELS ,Number of pixels per line"
|
|
if (((d.l(ad:0x4810a000))&0x8)==0x8)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "CFG11,HD_VENC_D_VOUT0 CFG11 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " EQ_WTH ,Width of pre-equalization and post-equalization pulse"
|
|
hexmask.long.word 0x00 12.--23. 1. " V_BLA2 ,Line location in a frame where the 2nd vertical blank period ends"
|
|
hexmask.long.word 0x00 0.--11. 1. " V_BLA1 ,Line location in a frame where 1st vertical blank period ends"
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "CFG11,HD_VENC_D_VOUT0 CFG11 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " EQ_WTH ,Width of pre-equalization and post-equalization pulse"
|
|
hexmask.long.word 0x00 0.--11. 1. " V_BLA1 ,Line location in a frame where 1st vertical blank period ends"
|
|
endif
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "CFG12,HD_VENC_D_VOUT0 CFG12 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " HS_WTH ,Width of HS pulse"
|
|
hexmask.long.word 0x00 12.--23. 1. " ACT_PIX ,Number of active pixels in one video line"
|
|
hexmask.long.word 0x00 0.--11. 1. " H_BLANK ,Location of the last non-active pixel on each line in front of the active video"
|
|
if (((d.l(ad:0x4810a000))&0x8)==0x8)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "CFG13,HD_VENC_D_VOUT0 CFG13 Register"
|
|
bitfld.long 0x00 24.--27. " CBCR_S2 ,High-4-bits of CBCR_S1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 12.--23. 1. " OSD_HBI_ST ,Starting location of DTV_HBI signal"
|
|
hexmask.long.word 0x00 0.--11. 1. " END_F1 ,Last line of the first field"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "CFG13,HD_VENC_D_VOUT0 CFG13 Register"
|
|
bitfld.long 0x00 24.--27. " CBCR_S2 ,High-4-bits of CBCR_S1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 12.--23. 1. " OSD_HBI_ST ,Starting location of DTV_HBI signal"
|
|
endif
|
|
group.long 0x38++0x7
|
|
line.long 0x00 "CFG14,HD_VENC_D_VOUT0 CFG14 Register"
|
|
bitfld.long 0x00 24.--27. " CBCR_S1 ,Shifting of active video of channel CB and CR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 12.--23. 1. " SYNC_L ,Low level of the sync pulse"
|
|
hexmask.long.word 0x00 0.--11. 1. " SYNC_H ,High level of the sync pulse of a tri-level sync system"
|
|
line.long 0x04 "CFG15,HD_VENC_D_VOUT0 CFG15 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " VOUT_HS_WD ,Width of VOUT_HS pulse"
|
|
hexmask.long.word 0x04 12.--23. 1. " VOUT_AVD_HW ,Width of each active video line"
|
|
hexmask.long.word 0x04 0.--11. 1. " VOUT_AVST_H ,For VOUT interface"
|
|
if (((d.l(ad:0x4810a000))&0x8)==0x8)
|
|
group.long 0x40++0x13
|
|
line.long 0x00 "CFG16,HD_VENC_D_VOUT0 CFG16 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BP_PK_L ,Peak value of BP pulse when MacroVision is enabled"
|
|
hexmask.long.word 0x00 12.--23. 1. " VOUT_AVST_V1 ,First active line of the first field in a frame"
|
|
hexmask.long.word 0x00 0.--11. 1. " VOUT_HS_ST ,Starting location of the HS pulse on each line"
|
|
line.long 0x04 "CFG17,HD_VENC_D_VOUT0 CFG17 Register"
|
|
bitfld.long 0x04 24.--26. " BP_PK_H ,Peak value of BP pulse when MacroVision is enabled" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 12.--23. 1. " VOUT_AVD_VW1 ,Number of active lines in the first field"
|
|
hexmask.long.word 0x04 0.--11. 1. " VOUT_AVST_V2 ,First active line of second field in a frame"
|
|
line.long 0x08 "CFG18,HD_VENC_D_VOUT0 CFG18 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " VOUT_VS_WD1 ,Width of the VS pulse of the first field"
|
|
hexmask.long.word 0x08 12.--23. 1. " VOUT_VS_ST1 ,Starting location of VS pulse of the first field"
|
|
hexmask.long.word 0x08 0.--11. 1. " VOUT_AVD_VW2 ,Number of active lines in the second field"
|
|
line.long 0x0C "CFG19,HD_VENC_D_VOUT0 CFG19 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " VOUT_VS_WD2 ,Width of the VS pulse of the second field"
|
|
hexmask.long.word 0x0C 12.--23. 1. " VOUT_FID_ST1 ,Starting location of the first field"
|
|
hexmask.long.word 0x0C 0.--11. 1. " VOUT_VS_ST2 ,Starting location of the VS of the second field"
|
|
line.long 0x10 "CFG20,HD_VENC_D_VOUT0 CFG20 Register"
|
|
hexmask.long.word 0x10 12.--23. 1. " osd_fid_st2 ,Starting location of the second field"
|
|
hexmask.long.word 0x10 0.--11. 1. " vout_fid_st2 ,Starting location of the second field"
|
|
else
|
|
group.long 0x40++0xF
|
|
line.long 0x00 "CFG16,HD_VENC_D_VOUT0 CFG16 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BP_PK_L ,Peak value of BP pulse when MacroVision is enabled"
|
|
hexmask.long.word 0x00 12.--23. 1. " VOUT_AVST_V1 ,first active line in a frame"
|
|
hexmask.long.word 0x00 0.--11. 1. " VOUT_HS_ST ,Starting location of the HS pulse on each line"
|
|
line.long 0x04 "CFG17,HD_VENC_D_VOUT0 CFG17 Register"
|
|
bitfld.long 0x04 24.--26. " BP_PK_H ,Peak value of BP pulse when MacroVision is enabled" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 12.--23. 1. " VOUT_AVD_VW1 ,Number of active video lines in a frame"
|
|
line.long 0x08 "CFG18,HD_VENC_D_VOUT0 CFG18 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " VOUT_VS_WD1 ,Width of the VS pulse"
|
|
hexmask.long.word 0x08 12.--23. 1. " VOUT_VS_ST1 ,Starting location of the VS pulse in a frame"
|
|
line.long 0x0C "CFG19,HD_VENC_D_VOUT0 CFG19 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " VOUT_VS_WD2 ,Width of the VS pulse of the second field"
|
|
hexmask.long.word 0x0C 12.--23. 1. " VOUT_FID_ST1 ,Location where the VOUT_FID will be toggled"
|
|
endif
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "CFG21,HD_VENC_D_VOUT0 CFG21 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " OSD_HS_WD ,Width of DTV_HS pulse"
|
|
hexmask.long.word 0x00 12.--23. 1. " OSD_AVD_HW ,Width of each active video line"
|
|
hexmask.long.word 0x00 0.--11. 1. " OSD_AVST_H ,Location of the last non-active pixel on each line (OSD interface)"
|
|
if (((d.l(ad:0x4810a000))&0x8)==0x8)
|
|
group.long 0x58++0xF
|
|
line.long 0x00 "CFG22,HD_VENC_D_VOUT0 CFG22 Register"
|
|
hexmask.long.word 0x00 12.--23. 1. " OSD_AVST_V1 ,First active line of first field in a frame"
|
|
hexmask.long.word 0x00 0.--11. 1. " OSD_HS_ST ,Starting location of the DTV_HS pulse on each line"
|
|
line.long 0x04 "CFG23,HD_VENC_D_VOUT0 CFG23 Register"
|
|
hexmask.long.word 0x04 12.--23. 1. " OSD_AVD_VW1 ,Number of active lines in the first field"
|
|
hexmask.long.word 0x04 0.--11. 1. " OSD_AVST_V2 ,First active line of second field in a frame"
|
|
line.long 0x08 "CFG24,HD_VENC_D_VOUT0 CFG24 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " OSD_VS_WD1 ,Width of the first DTV_VS pulse (lines) in a frame"
|
|
hexmask.long.word 0x08 12.--23. 1. " OSD_VS_ST1 ,Starting location of the DTV_VS of first field"
|
|
hexmask.long.word 0x08 0.--11. 1. " OSD_AVD_VW2 ,Number of active lines in the second field"
|
|
line.long 0x0C "CFG25,HD_VENC_D_VOUT0 CFG25 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " OSD_VS_WD2 ,Width of the second DTV_VS pulse (lines)"
|
|
hexmask.long.word 0x0C 12.--23. 1. " OSD_FID_ST1 ,Starting location of the first field"
|
|
hexmask.long.word 0x0C 0.--11. 1. " OSD_VS_ST2 ,Starting location of the VS of the second field"
|
|
else
|
|
group.long 0x58++0xF
|
|
line.long 0x00 "CFG22,HD_VENC_D_VOUT0 CFG22 Register"
|
|
hexmask.long.word 0x00 12.--23. 1. " OSD_AVST_V1 ,First active line in a frame"
|
|
hexmask.long.word 0x00 0.--11. 1. " OSD_HS_ST ,Starting location of the DTV_HS pulse on each line"
|
|
line.long 0x04 "CFG23,HD_VENC_D_VOUT0 CFG23 Register"
|
|
hexmask.long.word 0x04 12.--23. 1. " OSD_AVD_VW1 ,Number of active lines in a frame"
|
|
line.long 0x08 "CFG24,HD_VENC_D_VOUT0 CFG24 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " OSD_VS_WD1 ,Width of the first DTV_VS pulse (lines) in a frame"
|
|
hexmask.long.word 0x08 12.--23. 1. " OSD_VS_ST1 ,Starting location of the DTV_VS"
|
|
line.long 0x0C "CFG25,HD_VENC_D_VOUT0 CFG25 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " OSD_VS_WD2 ,Width of the second DTV_VS pulse (lines)"
|
|
hexmask.long.word 0x0C 12.--23. 1. " OSD_FID_ST1 ,Location where the DTV_FID will be toggled"
|
|
endif
|
|
group.long 0x68++0xB
|
|
line.long 0x00 "CFG26,HD_VENC_D_VOUT0 CFG26 Register"
|
|
bitfld.long 0x00 28.--30. " N10_B ,Pseudo-sync pulse spacing control of format A" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " N10_A ,Pseudo-sync pulse spacing control of format A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " N9_B ,Location of 1st Pseudo-sync pulse of format B" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " N9_A ,Location of 1st pseudo-sync pulse of format A" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " N8_B ,Pseudo-sync pulse duration control of format B" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " N8_A ,Pseudo-sync pulse duration control of format A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. " NO_5 ,480i component MacroVision on/off control" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NO_4 ,End of field back porch pulse control" "Off,On"
|
|
bitfld.long 0x00 2. " NO_2 ,AGC pulse amplitude control" "Maximum,Varied"
|
|
bitfld.long 0x00 0.--1. " NO_1_0 ,Level reduction" "No Reduction,Reserved,None-VBI period,VBI & Active video period"
|
|
line.long 0x04 "CFG27,HD_VENC_D_VOUT0 CFG27 Register"
|
|
bitfld.long 0x04 30. " N12_14 ,Pseudo-Sync pulse and AGC pulse line 21 format" "A,B"
|
|
bitfld.long 0x04 29. " N12_13 ,Pseudo-Sync pulse and AGC pulse line 20 format" "A,B"
|
|
bitfld.long 0x04 28. " N12_12 ,Pseudo-Sync pulse and AGC pulse line 19 format" "A,B"
|
|
textline " "
|
|
bitfld.long 0x04 27. " N12_11 ,Pseudo-Sync pulse and AGC pulse line 18 format" "A,B"
|
|
bitfld.long 0x04 26. " N12_10 ,Pseudo-Sync pulse and AGC pulse line 17 format" "A,B"
|
|
bitfld.long 0x04 25. " N12_9 ,Pseudo-Sync pulse and AGC pulse line 16 format" "A,B"
|
|
textline " "
|
|
bitfld.long 0x04 24. " N12_8 ,Pseudo-Sync pulse and AGC pulse line 15 format" "A,B"
|
|
bitfld.long 0x04 23. " N12_7 ,Pseudo-Sync pulse and AGC pulse line 14 format" "A,B"
|
|
bitfld.long 0x04 22. " N12_6 ,Pseudo-Sync pulse and AGC pulse line 13 format" "A,B"
|
|
textline " "
|
|
bitfld.long 0x04 21. " N12_5 ,Pseudo-Sync pulse and AGC pulse line 12 format" "A,B"
|
|
bitfld.long 0x04 20. " N12_4 ,Pseudo-Sync pulse and AGC pulse line 11 format" "A,B"
|
|
bitfld.long 0x04 19. " N12_3 ,Pseudo-Sync pulse and AGC pulse line 10 format" "A,B"
|
|
textline " "
|
|
bitfld.long 0x04 18. " N12_2 ,Pseudo-Sync pulse and AGC pulse line 9 format" "A,B"
|
|
bitfld.long 0x04 17. " N12_1 ,Pseudo-Sync pulse and AGC pulse line 8 format" "A,B"
|
|
bitfld.long 0x04 16. " N12_0 ,Pseudo-Sync pulse and AGC pulse line 7 format" "A,B"
|
|
textline " "
|
|
bitfld.long 0x04 14. " N11_14 ,Pseudo-sync and AGC pulse enable line 21" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " N11_13 ,Pseudo-sync and AGC pulse enable line 20" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " N11_12 ,Pseudo-sync and AGC pulse enable line 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " N11_11 ,Pseudo-sync and AGC pulse enable line 18" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " N11_10 ,Pseudo-sync and AGC pulse enable line 17" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " N11_9 ,Pseudo-sync and AGC pulse enable line 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " N11_8 ,Pseudo-sync and AGC pulse enable line 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " N11_7 ,Pseudo-sync and AGC pulse enable line 14" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " N11_6 ,Pseudo-sync and AGC pulse enable line 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " N11_5 ,Pseudo-sync and AGC pulse enable line 12" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " N11_4 ,Pseudo-sync and AGC pulse enable line 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " N11_3 ,Pseudo-sync and AGC pulse enable line 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " N11_2 ,Pseudo-sync and AGC pulse enable line 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " N11_1 ,Pseudo-sync and AGC pulse enable line 8" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " N11_0 ,Pseudo-sync and AGC pulse enable line 7" "Disabled,Enabled"
|
|
width 7.
|
|
line.long 0x08 "CFG28,HD_VENC_D_VOUT0 CFG28 Register"
|
|
bitfld.long 0x08 20.--23. " N15_3_0 ,BP pulse insertion after the vertical sync (line for 525i/625i)" "No BP,7 and 270/4 and 316,7-8&270-271/4-5&316-317,7-9&270-272/4-6&316-318,7-10&270-273/4-7&316-319,7-11&270-274/4-8&316-320,7-12&270-275/4-9&316-321,7-13&270-276/4-10&316-322,7-14&270-277/4-11&316-323,7-15&270-278/4-12&316-324,7-16&270-279/4-13&316-325,7-17&270-280/4-14&316-326,7-18&270-281/4-15&316-327,7-19&270-282/4-16&316-328,7-20&270-283/4-17&316-329,7-21&270-284/4-18&316-330"
|
|
bitfld.long 0x08 16.--19. " N15_7_4 ,BP pulse insertion before the vertical sync (line for 525i/625i)" "no BP,3&266/312&625,2-3&265-266/311-312&624-625,1-3&264-266/310-312&623-625,1-3&263-266/309-312&622-625,1-3&262-266/308-312&621-625,1-3&261-266/307-312&620-625,1-3&260-266/306-312&619-625,1-3&259-266/305-312&618-625,1-3&258-266/304-312&617-625,1-3&257-266/303-312&616-625,1-3&256-266/302-312&615-625,1-3&255-266/301-312&614-625,1-3&254-266/300-312&613-625,1-3&253-266/209-312&612-625,514-525&1-3&264-266/298-312&611-625"
|
|
textline " "
|
|
bitfld.long 0x08 15. " N14_7 ,Format B PS/AGC pulse 8st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " N14_6 ,Format B PS/AGC pulse 7st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " N14_5 ,Format B PS/AGC pulse 6st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " N14_4 ,Format B PS/AGC pulse 5st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " N14_3 ,Format B PS/AGC pulse 4st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " N14_2 ,Format B PS/AGC pulse 3st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " N14_1 ,Format B PS/AGC pulse 2st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " N14_0 ,Format B PS/AGC pulse 1st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " N13_7 ,Format A PS/AGC pulse 8st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " N13_6 ,Format A PS/AGC pulse 7st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " N13_5 ,Format A PS/AGC pulse 6st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " N13_4 ,Format A PS/AGC pulse 5st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " N13_3 ,Format A PS/AGC pulse 4st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " N13_2 ,Format A PS/AGC pulse 3st pair enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " N13_1 ,Format A PS/AGC pulse 2st pair enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " N13_0 ,Format A PS/AGC pulse 1st pair enable" "Disabled,Enabled"
|
|
width 16.
|
|
hgroup.long 0x1000++0x03
|
|
hide.long 0x00 "LUT0_LUT1_LUT2,HD_VENC_D_VOUT0 LUT0_LUT1_LUT2 Memory Region"
|
|
button "LUT0_LUT1_LUT2" "d (ad:0x4810a000+0x1000)--(ad:0x4810a000+0x1FFF) /long"
|
|
width 0xB
|
|
tree.end
|
|
tree "NF"
|
|
base ad:0x4810c200
|
|
width 9.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "NF_REG0,Mode Configuration Register"
|
|
bitfld.long 0x00 12. " NF_FRAME_NOISE_UPDATE_EN ,NF Frame Noise Update Enable" "Not updated,Updated"
|
|
bitfld.long 0x00 11. " NF_FRAME_NOISE_INIT_EN ,NF Frame Noise Load Enable" "Not overwritten,Overwritten"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPATIAL_DATA_BYPASS_ENABLE ,Spatial Data Bypass enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TEMPORAL_DATA_BYPASS_ENABLE ,Temporal Data Bypass enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " NF_VIDEO_INDEX ,NF Video Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " NF_REF_CFG ,NF Reference Frame Configuration (DMA/Output)" "Enabled/Passed,Enabled/Black,Disabled/Black,Disabled/Black"
|
|
bitfld.long 0x00 0. " NF_EN ,NF Enable" "Disabled,Enabled"
|
|
line.long 0x04 "NF_REG1,Width and Height of Video Register"
|
|
hexmask.long.word 0x04 16.--26. 1. " HEIGHT ,Number of lines per frame"
|
|
hexmask.long.word 0x04 0.--10. 1. " WIDTH ,Number of pixels per line"
|
|
line.long 0x08 "NF_REG2,Spatial Low and High Frequency Filter Strength of Y Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SPATIAL_STRENGTH_Y_HIGH ,Spatial high-frequency filter strength of Y channel"
|
|
hexmask.long.byte 0x08 0.--7. 1. " SPATIAL_STRENGTH_Y_LOW ,Spatial low-frequency filter strength of Y channel"
|
|
line.long 0x0c "NF_REG3,Spatial Low and High Frequency Filter Strength of UV Register"
|
|
hexmask.long.byte 0x0c 24.--31. 1. " SPATIAL_STRENGTH_V_HIGH ,Spatial high-frequency filter strength of V channel"
|
|
hexmask.long.byte 0x0c 16.--23. 1. " SPATIAL_STRENGTH_V_LOW ,Spatial low-frequency filter strength of V channel"
|
|
textline " "
|
|
hexmask.long.byte 0x0c 8.--15. 1. " SPATIAL_STRENGTH_U_HIGH ,Spatial high-frequency filter strength of U channel"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " SPATIAL_STRENGTH_U_LOW ,Spatial low-frequency filter strength of U channel"
|
|
line.long 0x10 "NF_REG4,Temporal Filter Configuration Register"
|
|
bitfld.long 0x10 8.--11. " TEMPORAL_FILTER_TRIGGER_NOISE ,The smallest noise level to fully trigger temporal filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--5. " TEMPORAL_STRENGTH ,Temporal filter strength" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "NF_REG5,Noise Level Configuration Register"
|
|
bitfld.long 0x14 4.--8. " MAX_NOISE ,Max of the possible noise level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x14 0.--3. " NOISE_IIR_COEFFICIENT ,Noise level IIR filter coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "NF_REG6,Pure Black and White Threshold Register"
|
|
bitfld.long 0x18 8.--13. " PURE_WHITE_THRESHOLD ,Threshold value(pure white indicator)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 0.--5. " PURE_BLACK_THRESHOLD ,Threshold value(pure black indicator)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x1c "NF_REG7,Saved Noise Frame Index Register"
|
|
bitfld.long 0x1C 0.--4. " FRAME_NOISE_READ_INDEX ,Saved Frame Noise Register Bank Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "NF_REG8,Saved Noise Frame Data (Luma) Register"
|
|
hexmask.long.word 0x20 0.--12. 1. " FRAME_NOISE_Y ,Saved Frame Noise Luma (y)"
|
|
line.long 0x24 "NF_REG9,Saved Noise Frame Data (Chroma) Register"
|
|
hexmask.long.word 0x24 16.--28. 1. " FRAME_NOISE_U ,Saved Frame Noise Chroma(cb/u)"
|
|
hexmask.long.word 0x24 0.--12. 1. " FRAME_NOISE_V ,Saved Frame Noise Chroma(cr/v)"
|
|
width 0xb
|
|
tree.end
|
|
tree "VPDMA"
|
|
base ad:0x4810d000
|
|
width 9.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "VPDMAR1,VPDMA Register 1"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AM3874")||(cpu()=="AM3872")
|
|
tree.open "HDMI (High-Definition Multimedia Interface)"
|
|
tree "HDMI_WP (HDMI Wrapper Registers)"
|
|
base ad:0x46C00000
|
|
width 24.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "HDMI_WP_REVISION,IP Revision Identifier"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "HDMI_WP_SYSCONFIG,Clock management configuration"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode"
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "HDMI_WP_IRQSTATUS_RAW,Raw Interrupt Status"
|
|
bitfld.long 0x00 10. " AUDIO_FIFO_SAMPLE_REQ_INTR ,Settable raw status for audio events" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " AUDIO_FIFO_OVERFLOW_INTR ,Settable raw status for audio events" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 8. " AUDIO_FIFO_UNDERFLOW_INTR ,Settable raw status for audio events" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " OCP_TIME_OUT_INTR ,Settable raw status for OCP time Out interrupt" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CORE_INTR ,Settable raw status for Core interrupt" "Not pending,Pending"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HDMI_WP_IRQSTATUS,Interrupt Status"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AUDIO_FIFO_SAMPLE_REQ_INTR_set/clr ,Status for audio events" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AUDIO_FIFO_OVERFLOW_INTR_set/clr ,Status for audio events" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AUDIO_FIFO_UNDERFLOW_INTR_set/clr ,Status for audio events" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " OCP_TIME_OUT_INTR_set/clr ,Status for OCP time Out interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CORE_INTR_set/clr ,Status for Core interrupt" "No interrupt,Interrupt"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "HDMI_WP_DEBOUNCE,glitch filter on Line 5Vshort and Rxdet"
|
|
hexmask.long.byte 0x00 8.--13. 1. " RXDET ,Glitch filter for RXDET input"
|
|
hexmask.long.byte 0x00 0.--5. 1. " LINE5VSHORT ,Glitch filter for line 5v short input"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "HDMI_WP_VIDEO_CFG,Configuration of HDMI Wrapper video"
|
|
bitfld.long 0x00 8.--10. " PACKING_MODE ,Packing mode" "10bits,24bits,20bitsYUV422,Reserved,Reserved,Reserved,Reserved,NoPack"
|
|
bitfld.long 0x00 5. " CORE_VSYNC_INV ,VSYNC signal provided to the HDMI core invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CORE_HSYNC_INV ,HSYNC signal provided to the HDMI core invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,Mode" "0,?..."
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "HDMI_WP_CLK,Configuration of clocks"
|
|
bitfld.long 0x00 16. " OCP_TIME_OUT_DIS ,Time out in case CEC_DDC_CLK not provided" "No timeout,Timeout"
|
|
hexmask.long.byte 0x00 0.--5. 1. " CEC_DIV ,CEC clock divisor"
|
|
if ((d.l(ad:(0x46C00000+0x80))&0x10)==0x0)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "HDMI_WP_AUDIO_CFG,Audio Configuration in FIFO"
|
|
bitfld.long 0x00 24.--26. " STEREO_CHANNEL_ENABLE ,Number of stereo channels enabled in the HDMI_CORE module" "No channel,1 channel,2 channels,3 channels,4 channels,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " AUDIO_CHANNEL_LOCATION ,Active channels"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_START_END_DISABLE ,Block end start generation disable" "No,Yes"
|
|
bitfld.long 0x00 4. " IEC ,Indicate if the format of the FIFO is compliant with the IEC format" "L-PCM,IEC 60958/61937"
|
|
textline " "
|
|
bitfld.long 0x00 3. " JUSTIFY ,Justification" "Justify left,Justify right"
|
|
bitfld.long 0x00 1. " SAMPLE_NBR ,Number of sample per word (32bits)" "1 sample,2 samples"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAMPLE_SIZE ,Audio sample size" "16 bits,24 bits"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "HDMI_WP_AUDIO_CFG,Audio Configuration in FIFO"
|
|
bitfld.long 0x00 24.--26. " STEREO_CHANNEL_ENABLE ,Number of stereo channels enabled in the HDMI_CORE module" "No channel,1 channel,2 channels,3 channels,4 channels,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " AUDIO_CHANNEL_LOCATION ,Active channels"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_START_END_DISABLE ,Block end start generation disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " IEC ,Indicate if the format of the FIFO is compliant with the IEC format" "L-PCM,IEC 60958/61937"
|
|
endif
|
|
group.long 0x84++0x07
|
|
line.long 0x00 "HDMI_WP_AUDIO_CFG2,Audio configuration of DMA"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DMA_TRANSFER ,Control the dma request"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLOCK_SIZE ,Define the block size if audio sample are compressed"
|
|
line.long 0x04 "HDMI_WP_AUDIO_CTRL,Audio FIFO control"
|
|
bitfld.long 0x04 31. " WRAPPER_ENABLE ,Enable the audio wrapper" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CORE_REQ_ENABLE ,Enables the Audio data request generated by the core" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 16.--25. 1. " NUMBER_OF_SAMPLE ,Number of valid sample (16 or 24 bits) in the FIFO (depends of the fifo format setting)"
|
|
bitfld.long 0x04 9. " DMA_OR_IRQ ,Indicated if the threshold generates a DMA or an IRQ" "DMA,IRQ"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--8. 1. " TRESHOLD_VALUE ,Treshold value"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "HDMI_WP_AUDIO_DATA,TX Data of FIFO"
|
|
width 0xb
|
|
tree.end
|
|
tree "HDMI_IP_CORE_SYSTEM (HDMI Core System Registers)"
|
|
base ad:0x46C00400
|
|
width 24.
|
|
rgroup.long 0x000++0x13
|
|
line.long 0x00 "VND_IDL,Vendor ID Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VND_ID ,Provides unique vendor identification through I2C. Vendor ID Low Byte"
|
|
line.long 0x04 "VND_IDH,Vendor ID Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VND_ID ,Provides unique vendor identification through I2C. Vendor ID High Byte"
|
|
line.long 0x08 "DEV_IDL,Device ID Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DEV_ID ,Provides unique device type identification through I2C. Device ID Low Byte"
|
|
line.long 0x0C "DEV_IDH,Device ID Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DEV_ID ,Provides unique device type identification through I2C. Device ID High Byte"
|
|
line.long 0x10 "DEV_REV,Device Revision Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DEV_REV ,Allows distinction between revisions of same device."
|
|
group.long 0x014++0x03
|
|
line.long 0x00 "SRST,Software Reset Register"
|
|
bitfld.long 0x00 1. " FIFORST ,Audio FIFO reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " SWRST ,Software reset" "No reset,Reset"
|
|
group.long 0x020++0x0B
|
|
line.long 0x00 "SYS_CTRL1,System Control Register 1"
|
|
bitfld.long 0x00 6. " VSYNC ,The current status of the VSYNC input pin" "Low,High"
|
|
bitfld.long 0x00 5. " VEN ,VSYNC enable" "Fixed LOW,Follow VSYNC"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEN ,HSYNC enable" "Fixed LOW,Follow HSYNC"
|
|
bitfld.long 0x00 2. " BSEL ,Input Bus Select" "12bit,24bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDGE ,Edge select" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 0. " PD ,Power down mode: HIGH is normal operation" "Low,High"
|
|
line.long 0x04 "SYS_STAT,System Status Register"
|
|
bitfld.long 0x04 2. " RSEN ,Receiver Sense" "Not connected,Connected"
|
|
bitfld.long 0x04 1. " HPD ,Hot Plug Detect" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P_STABLE ,IDCK (io_pclkpin) to TMDS clock (v_ck2x) is stable and the Transmitter can send reliable data on the TMDS link" "Low,High"
|
|
line.long 0x08 "SYS_CTRL3,Legacy Registers"
|
|
bitfld.long 0x08 1.--2. " CTL ,The states of these control bits are transmitted across the TMDS link during blanking times for DVI 1.0 mode only" "0,1,2,3"
|
|
group.long 0x034++0x03
|
|
line.long 0x00 "DCTL,Data Control Register"
|
|
bitfld.long 0x00 2. " VID_BLANK ,Video output blank enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUD_MUTE ,Send zeroes in audio pocket enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HDCP_SEL ,Value of the pin io_hdcp_sel" "Unencrypted,Only encrypted"
|
|
group.long 0x03C++0x03
|
|
line.long 0x00 "HDCP_CTRL,HDCP Control Register"
|
|
bitfld.long 0x00 6. " ENC_ON ,Encryption status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BKSV_ERR ,BKSV error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RX_RPTR ,Repeater" "Single HDMI,HDMI Receiver"
|
|
bitfld.long 0x00 3. " TX_ANSTOP ,AN control" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CP_RESTN ,Content protection reset" "Reset,No reset"
|
|
bitfld.long 0x00 1. " RI_RDY ,Ri Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENC_EN ,Encryption enabled" "Disabled,Enabled"
|
|
tree "BKSV"
|
|
group.long 0x040++0x13
|
|
line.long 0x0 "BKSV_0,HDCP BKSV Register 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " BKSV ,HDCP Receiver Key Selection Vector register value"
|
|
line.long 0x4 "BKSV_1,HDCP BKSV Register 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " BKSV ,HDCP Receiver Key Selection Vector register value"
|
|
line.long 0x8 "BKSV_2,HDCP BKSV Register 2"
|
|
hexmask.long.byte 0x8 0.--7. 1. " BKSV ,HDCP Receiver Key Selection Vector register value"
|
|
line.long 0xC "BKSV_3,HDCP BKSV Register 3"
|
|
hexmask.long.byte 0xC 0.--7. 1. " BKSV ,HDCP Receiver Key Selection Vector register value"
|
|
line.long 0x10 "BKSV_4,HDCP BKSV Register 4"
|
|
hexmask.long.byte 0x10 0.--7. 1. " BKSV ,HDCP Receiver Key Selection Vector register value"
|
|
tree.end
|
|
tree "AN"
|
|
group.long 0x054++0x1F
|
|
line.long 0x0 "AN_0,HDCP AN Register 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " AN ,HDCP pseudo-random value"
|
|
line.long 0x4 "AN_1,HDCP AN Register 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " AN ,HDCP pseudo-random value"
|
|
line.long 0x8 "AN_2,HDCP AN Register 2"
|
|
hexmask.long.byte 0x8 0.--7. 1. " AN ,HDCP pseudo-random value"
|
|
line.long 0xC "AN_3,HDCP AN Register 3"
|
|
hexmask.long.byte 0xC 0.--7. 1. " AN ,HDCP pseudo-random value"
|
|
line.long 0x10 "AN_4,HDCP AN Register 4"
|
|
hexmask.long.byte 0x10 0.--7. 1. " AN ,HDCP pseudo-random value"
|
|
line.long 0x14 "AN_5,HDCP AN Register 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. " AN ,HDCP pseudo-random value"
|
|
line.long 0x18 "AN_6,HDCP AN Register 6"
|
|
hexmask.long.byte 0x18 0.--7. 1. " AN ,HDCP pseudo-random value"
|
|
line.long 0x1C "AN_7,HDCP AN Register 7"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " AN ,HDCP pseudo-random value"
|
|
tree.end
|
|
tree "AKSV"
|
|
rgroup.long 0x074++0x13
|
|
line.long 0x0 "AKSV_0,HDCP AKSV Register 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " AKSV ,HDCP-capable Transmitter s Key Selection Vector"
|
|
line.long 0x4 "AKSV_1,HDCP AKSV Register 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " AKSV ,HDCP-capable Transmitter s Key Selection Vector"
|
|
line.long 0x8 "AKSV_2,HDCP AKSV Register 2"
|
|
hexmask.long.byte 0x8 0.--7. 1. " AKSV ,HDCP-capable Transmitter s Key Selection Vector"
|
|
line.long 0xC "AKSV_3,HDCP AKSV Register 3"
|
|
hexmask.long.byte 0xC 0.--7. 1. " AKSV ,HDCP-capable Transmitter s Key Selection Vector"
|
|
line.long 0x10 "AKSV_4,HDCP AKSV Register 4"
|
|
hexmask.long.byte 0x10 0.--7. 1. " AKSV ,HDCP-capable Transmitter s Key Selection Vector"
|
|
tree.end
|
|
rgroup.long 0x088++0x13
|
|
line.long 0x00 "RI1,HDCP Ri Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RI ,Ri Register"
|
|
line.long 0x04 "RI2,HDCP Ri Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RI ,Ri Register"
|
|
line.long 0x08 "RI_128_COMP,HDCP Ri 128 Compare Register"
|
|
hexmask.long.byte 0x08 0.--6. 1. " RI_128_COMP ,Limit counter for Ri comparison"
|
|
line.long 0x0C "I_CNT,HDCP I Counter Register"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " I_CNT ,Current value of I counter"
|
|
line.long 0x10 "RI_STAT,Ri Status Register"
|
|
bitfld.long 0x10 0. " RI_STARTED ,Ri check started status" "Low,High"
|
|
group.long 0x09C++0x07
|
|
line.long 0x00 "RI_CMD,Ri Command Register"
|
|
bitfld.long 0x00 1. " BCAP_EN ,Enable polling of the BCAP_DONE bit" "Disable,Enable"
|
|
bitfld.long 0x00 0. " RI_EN ,Enable Ri check" "Disable,Enable"
|
|
line.long 0x04 "RI_START,Ri Line Start Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RI_LINE_START ,Ri Check start line"
|
|
rgroup.long 0x0A4++0x07
|
|
line.long 0x00 "RI_RX_L,Ri From RX Registers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RI_RX ,HDMI Receiver s Ri value if any of the Ri Check errors occurred"
|
|
line.long 0x04 "RI_RX_H,Ri From RX Registers"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RI_RX ,HDMI Receiver s Ri value if any of the Ri Check errors occurred"
|
|
group.long 0x0AC++0x03
|
|
line.long 0x00 "RI_DEBUG,Ri Debug Registers"
|
|
bitfld.long 0x00 7. " RI_DBG_TRASH ,Force a corruption of the Ri values" "Continue,Force"
|
|
bitfld.long 0x00 6. " RI_DBG_HOLD ,Hold the Ri value steady" "Continue,Hold"
|
|
group.long 0x0C8++0x0B
|
|
line.long 0x00 "DE_DLY,Video DE Delay Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DE_DLY ,Width of the area to the left of the active display"
|
|
line.long 0x04 "DE_CTRL,Video DE Control Register"
|
|
bitfld.long 0x04 6. " DE_GEN ,Generate DE signal" "Disable,Enable"
|
|
bitfld.long 0x04 5. " VS_POL ,VSYNC polarity" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x04 4. " HS_POL ,HSYNC polarity" "Positive,Negative"
|
|
bitfld.long 0x04 0.--3. " DE_DLY ,The bit-field defines DE_DLY[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "DE_TOP,Video DE Top Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DE_TOP ,Defines the height of the area above the active display"
|
|
group.long 0x0D8++0x0F
|
|
line.long 0x00 "DE_CNTL,Video DE Count Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DE_CNT ,Defines the width of the active display"
|
|
line.long 0x04 "DE_CNTH,Video DE Count Register"
|
|
bitfld.long 0x04 0.--3. " DE_CNT ,Defines the width of the active display" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "DE_LINL,Video DE Line Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DE_LIN ,Defines the height of the active display"
|
|
line.long 0x0C "DE_LINH,Video DE Line Register"
|
|
bitfld.long 0x0C 0.--2. " DE_LIN ,Defines the height of the active display" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x0E8++0x0F
|
|
line.long 0x00 "HRES_L,Video H Resolution Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " H_RES ,Measures the time between two HSYNC active edges. The unit of measure is pixels"
|
|
line.long 0x04 "HRES_H,Video H Resolution Register"
|
|
bitfld.long 0x04 0.--4. " H_RES ,Measures the time between two HSYNC active edges" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "VRES_L,Video V Refresh Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " V_RES ,Measures the time between two VSYNC active edges"
|
|
line.long 0x0C "VRES_H,Video V Refresh Register"
|
|
bitfld.long 0x0C 0.--2. " V_RES ,Measures the time between two VSYNC active edges" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0F8++0x07
|
|
line.long 0x00 "IADJUST,Video Interlace Adjustment Register"
|
|
bitfld.long 0x00 2. " DE_ADJ ,VSYNC disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " F2VADJ ,Field 2 adjust enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " F2VOFST ,Field 2 offset" "Low,High"
|
|
line.long 0x04 "POL_DETECT,Video SYNC Polarity Detection Register"
|
|
bitfld.long 0x04 2. " I_DET ,Interlace detect" "Progressive,Interlace"
|
|
bitfld.long 0x04 1. " VPOL_DET ,Detected input VSYNC polarity using internal circuit" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x04 0. " HPOL_DET ,Detected input HSYNC polarity using internal circuit" "Active high,Active low"
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "HBIT_2HSYNC1,Video Hbit to HSYNC Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HBIT_TO_HSYNC ,Creates HSYNC pulses"
|
|
line.long 0x04 "HBIT_2HSYNC2,Video Hbit to HSYNC Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " HBIT_TO_HSYNC ,Creates HSYNC pulses"
|
|
line.long 0x08 "FLD2_HS_OFSTL,Video Field2 HSYNC Offset Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " FIELD2_OFST ,Determines VSYNC pixel offset for the odd field of an interlaced source"
|
|
line.long 0x0C "FLD2_HS_OFSTH,Video Field2 HSYNC Offset Register"
|
|
bitfld.long 0x0C 0.--3. " FIELD2_OFST ,Determines VSYNC pixel offset for the odd field of an interlaced source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "HWIDTH1,Video HSYNC Length Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " HWIDTH ,Sets the width of the HSYNC pulses"
|
|
line.long 0x14 "HWIDTH2,Video HSYNC Length Register"
|
|
bitfld.long 0x14 0.--1. " HWIDTH ,Sets the width of the HSYNC pulses" "0,1,2,3"
|
|
line.long 0x18 "VBIT_TO_VSYNC,Video Vbit to VSYNC Register"
|
|
hexmask.long.byte 0x18 0.--5. 1. " VBIT_TO_VSYNC ,VBIT to VSYNC delay"
|
|
line.long 0x1C "VWIDTH,Video VSYNC Length Register"
|
|
hexmask.long.byte 0x1C 0.--5. 1. " VWIDTH ,Sets the width of VSYNC pulse"
|
|
group.long 0x120++0x23
|
|
line.long 0x00 "VID_CTRL,Video Control Register"
|
|
bitfld.long 0x00 7. " IFPOL ,Invert field polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " EXTN ,Extended Bit mode" "8bit,12bit"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CSCSEL ,Color Space Conversion Standard select" "BT.601,BT.709"
|
|
bitfld.long 0x00 0.--1. " ICLK ,Clock mode" "Not replicated,Replicated 1 time,Reserved,Replicated 4 times"
|
|
line.long 0x04 "VID_ACEN,Video Action Enable Register"
|
|
bitfld.long 0x04 6.--7. " WIDE_BUS ,Identifies the number of bits per input video channel" "8bits_24bits,10bits_30bits,12bits_36bits,?..."
|
|
bitfld.long 0x04 4. " CLIP_CS_ID ,Identifies the output color space on the link" "RGBOutput,YCbCrOutput"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RANGE_CLIP ,Enable Range Clip from 16 to 235 (RGB and Y)/240 (CbCr)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RGB_2_YCBCR ,Enable RGB to YCbCr color-space converter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RANGE_CMPS ,Enable Range Compress 0-255 to 16-234" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DOWN_SMPL ,Enable down sampler 4:4:4 to 4:2:2" "Disabled,Enabled"
|
|
line.long 0x08 "VID_MODE,Video Mode1 Register"
|
|
bitfld.long 0x08 6.--7. " DITHER_MODE ,Identifies the number of bits per output video channel" "8bits,10bits,12bits,?..."
|
|
bitfld.long 0x08 5. " DITHER ,Dither enable," "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " RANGE ,Data Range 16-to-235 to 0-to-255 expansion" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CSC ,YcbCr to RGB Color Space Conversion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " UPSMP ,Upsampling 4:2:2 to 4:4:4" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DEMUX ,One- to Two-Data-Channel Demux" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SYNCEX ,Embedded Sync Extraction" "Disabled,Enabled"
|
|
line.long 0x0C "VID_BLANK1,Video Blanking Registers"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " VID_BLANK1 ,Defines the video blanking value for Channel 1 (Blue)"
|
|
line.long 0x10 "VID_BLANK2,Video Blanking Registers"
|
|
hexmask.long.byte 0x10 0.--7. 1. " VID_BLANK2 ,Defines the video blanking value for Channel 2 (Green)"
|
|
line.long 0x14 "VID_BLANK3,Video Blanking Registers"
|
|
hexmask.long.byte 0x14 0.--7. 1. " VID_BLANK3 ,Defines the video blanking value for Channel 3 (Red)"
|
|
line.long 0x18 "DC_HEADER,Deep Color Header Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DC_HEADER ,Least siginificant byte of the deep color header that sends the TMDS dynamic phase once per frame"
|
|
line.long 0x1C "VID_DITHER,Video Mode2 Register"
|
|
bitfld.long 0x1C 6. " M_D2 ,Dither + round option" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " UP2 ,Dither + 2 b10 option" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " STR_422_EN ,Enable Mode 4:2:2 for Dithering and Clipping" "Disable,Enable"
|
|
bitfld.long 0x1C 3. " D_BC_EN ,Enable adding random number on Blue channel data" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " D_GC_EN ,Enable adding random number on Green channel data" "Disable,Enable"
|
|
bitfld.long 0x1C 1. " D_RC_EN ,Enable adding random number on Red channel data" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " DRD ,Dither round" "Disable,Enable"
|
|
line.long 0x20 "RGB2XVYCC_CT,RGB_2_xvYCC control Register"
|
|
bitfld.long 0x20 2. " XV_CO_OV ,Override internal CSC coefficients with register 51 to XX values" "Disabled,Enabled"
|
|
bitfld.long 0x20 1. " XV_FUS ,xvYCC Fullscale mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0. " XV_EN ,xvYCC Enable" "Disabled,Enabled"
|
|
group.long 0x144++0x07
|
|
line.long 0x00 "R2Y_COEFF_LOW,RGB_2_xvYCC Conversion R to Y Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R2YCOEFF_L ,RGB to xvYCC conversion R to Y coefficient lower byte"
|
|
line.long 0x04 "R2Y_COEFF_UP,RGB_2_xvYCC Conversion R to Y Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " R2YCOEFF_H ,RGB to xvYCC conversion R to Y coefficient upper byte"
|
|
group.long 0x14C++0x07
|
|
line.long 0x00 "G2Y_COEFF_LOW,RGB_2_xvYCC Conversion G to Y Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " G2YCOEFF_L ,RGB to xvYCC conversion G to Y coefficient lower byte"
|
|
line.long 0x04 "G2Y_COEFF_UP,RGB_2_xvYCC Conversion G to Y Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " G2YCOEFF_H ,RGB to xvYCC conversion G to Y coefficient upper byte"
|
|
group.long 0x154++0x07
|
|
line.long 0x00 "B2Y_COEFF_LOW,RGB_2_xvYCC Conversion B to Y Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B2YCOEFF_L ,RGB to xvYCC conversion B to Y coefficient lower byte"
|
|
line.long 0x04 "B2Y_COEFF_UP,RGB_2_xvYCC Conversion B to Y Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " B2YCOEFF_H ,RGB to xvYCC conversion B to Y coefficient upper byte"
|
|
group.long 0x15C++0x07
|
|
line.long 0x00 "R2CB_COEFF_LOW,RGB_2_xvYCC Conversion R to Cb Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R2CBCOEFF_L ,RGB to xvYCC conversion R to Cb coefficient lower byte"
|
|
line.long 0x04 "R2CB_COEFF_UP,RGB_2_xvYCC Conversion R to Cb Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " R2CBCOEFF_H ,RGB to xvYCC conversion R to Cb coefficient upper byte"
|
|
group.long 0x164++0x07
|
|
line.long 0x00 "G2CB_COEFF_LOW,RGB_2_xvYCC Conversion G to Cb Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " G2CBCOEFF_L ,RGB to xvYCC conversion G to Cb coefficient lower byte"
|
|
line.long 0x04 "G2CB_COEFF_UP,RGB_2_xvYCC Conversion G to Cb Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " G2CBCOEFF_H ,RGB to xvYCC conversion G to Cb coefficient upper byte"
|
|
group.long 0x16C++0x07
|
|
line.long 0x00 "B2CB_COEFF_LOW,RGB_2_xvYCC Conversion B to Cb Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B2CBCOEFF_L ,RGB to xvYCC conversion B to Cb coefficient lower byte"
|
|
line.long 0x04 "B2CB_COEFF_UP,RGB_2_xvYCC Conversion B to Cb Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " B2CBCOEFF_H ,RGB to xvYCC conversion B to Cb coefficient upper byte"
|
|
group.long 0x174++0x07
|
|
line.long 0x00 "R2CR_COEFF_LOW,RGB_2_xvYCC Conversion R to Cr Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R2CRCOEFF_L ,RGB to xvYCC conversion R to Cr coefficient lower byte"
|
|
line.long 0x04 "R2CR_COEFF_UP,RGB_2_xvYCC Conversion R to Cr Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " R2CRCOEFF_H ,RGB to xvYCC conversion R to Cr coefficient upper byte"
|
|
group.long 0x17C++0x07
|
|
line.long 0x00 "G2CR_COEFF_LOW,RGB_2_xvYCC Conversion G to Cr Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " G2CRCOEFF_L ,RGB to xvYCC conversion G to Cr coefficient lower byte"
|
|
line.long 0x04 "G2CR_COEFF_UP,RGB_2_xvYCC Conversion G to Cr Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " G2CRCOEFF_H ,RGB to xvYCC conversion G to Cr coefficient upper byte"
|
|
group.long 0x184++0x07
|
|
line.long 0x00 "B2CR_COEFF_LOW,RGB_2_xvYCC Conversion B to Cr Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B2CRCOEFF_L ,RGB to xvYCC conversion B to Cr coefficient lower byte"
|
|
line.long 0x04 "B2CR_COEFF_UP,RGB_2_xvYCC Conversion B to Cr Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " B2CRCOEFF_H ,RGB to xvYCC conversion B to Cr coefficient upper byte"
|
|
group.long 0x18C++0x17
|
|
line.long 0x00 "RGB_OFFSET_LOW,RGB_2_xvYCC RGB Input Offset Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RGB_OFFS_L ,Input RGB offset value lower byte"
|
|
line.long 0x04 "RGB_OFFSET_UP,RGB_2_xvYCC RGB Input Offset Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RGB_OFFS_H ,Input RGB offset value upper byte"
|
|
line.long 0x08 "Y_OFFSET_LOW,RGB_2_xvYCC Conversion Y Output Offset Register"
|
|
hexmask.long.byte 0x08 0.--6. 1. " Y_OFFS_L ,Output Y offset value lower 7 bits"
|
|
line.long 0x0C "Y_OFFSET_UP,RGB_2_xvYCC Conversion Y Output Offset Register"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " Y_OFFS_H ,Output Y offset value upper 7 bits"
|
|
line.long 0x10 "CBCR_OFFSET_LOW,RGB_2_xvYCC Conversion CbCr Output Offset Register"
|
|
hexmask.long.byte 0x10 0.--6. 1. " CBCR_OFFS_L ,Output CbCr offset value lower 7 bits"
|
|
line.long 0x14 "CBCR_OFFSET_UP,RGB_2_xvYCC Conversion CbCr Output Offset Register"
|
|
hexmask.long.byte 0x14 0.--6. 1. " CBCR_OFFS_H ,Output CbCr offset value upper 7 bits"
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "INTR_STATE,Interrupt State Register"
|
|
bitfld.long 0x00 0. " INTR ,Interrupt State" "No intrrupt,Interrupt"
|
|
rgroup.long 0x1C4++0x0B
|
|
line.long 0x00 "INTR1,Interrupt Source Register"
|
|
bitfld.long 0x00 7. " SOFT ,Software Induced Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " HPD ,Monitor Detect Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RSEN ,Receiver Sense Interrupt asserted if RSEN has changed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " DROP_SAMPLE ,New preamble forced to drop sample (S/PDIF input only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIP_HASE_ERR ,Input S/PDIF stream has bi-phase error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RI_128 ,Input counted past frame count threshold set in RI_128_COMP register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVER_RUN ,Audio FIFO Overflow" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " UNDER_RUN ,Audio FIFO Underflow" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR2,Interrupt Source Register"
|
|
bitfld.long 0x04 7. " BCAP_DONE ,FIFORDY bit (0x74:0x40[5]) is set to 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " SPDIF_PAR ,S/PDIF Parity Error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ENC_DIS ,The ENC_EN bit (in register HDCP_CTRL) changed from 1 to 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " PREAM_ERR ,This condition is the opposite of the condition that causes DROP_SAMPLE (in register INTR1)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CTS_CHG ,Change in ACR CTS Value" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " ACR_OVR ,ACR Packet Overwrite" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TCLK_STBL ,TCLK_STABLE (register SYS_STA.P_STABLE) changes state" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " VSYNC_REC ,Asserted when VSYNC active edge is recognized" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR3,Interrupt Source Register"
|
|
bitfld.long 0x08 7. " RI_ERR_3 ,Ri and Ri do not match during frame 127 (ICNT .1)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " RI_ERR_2 ,Ri and Ri do not match during frame 0 (ICNT)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 5. " RI_ERR_1 ,Ri did not change between frame 127 and 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " RI_ERR_0 ,Ri not read within one frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DDC_CMD_DONE ,DDC command is complete" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " DDC_FIFO_HALF ,DDC FIFO is half full" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DDC_FIFO_FULL ,DDC FIFO is full" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " DDC_FIFO_EMPTY ,DDC FIFO is empty" "No interrupt,Interrupt"
|
|
group.long 0x1D0++0x0B
|
|
line.long 0x00 "INTR4,Interrupt Source Register"
|
|
eventfld.long 0x00 3. " REG_INTR4_STAT3 ,CEC interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " REG_INTR4_STAT2 ,Interrupt bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " REG_INTR4_STAT1 ,Interrupt bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " DSD_INVALID ,DSD stream got invalid sequence" "No interrupt,Interrupt"
|
|
line.long 0x04 "INT_UNMASK1,Interrupt Unmask Register"
|
|
bitfld.long 0x04 7. " SOFT ,Software Induced Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " HPD ,Monitor Detect Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RSEN ,Receiver Sense Interrupt asserted if RSEN has changed" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " DROP_SAMPLE ,New preamble forced to drop sample (S/PDIF input only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " BIP_HASE_ERR ,Input S/PDIF stream has bi-phase error" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RI_128 ,Input counted past frame count threshold set in RI_128_COMP register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OVER_RUN ,Audio FIFO Overflow" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " UNDER_RUN ,Audio FIFO Underflow" "No interrupt,Interrupt"
|
|
line.long 0x08 "INT_UNMASK2,Interrupt Unmask Register"
|
|
bitfld.long 0x08 7. " BCAP_DONE ,FIFORDY bit (0x74:0x40[5]) is set to 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " SPDIF_PAR ,S/PDIF Parity Error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ENC_DIS ,The ENC_EN bit (in register HDCP_CTRL) changed from 1 to 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " PREAM_ERR ,This condition is the opposite of the condition that causes DROP_SAMPLE (in register INTR1)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CTS_CHG ,Change in ACR CTS Value" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " ACR_OVR ,ACR Packet Overwrite" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TCLK_STBL ,TCLK_STABLE (register SYS_STA.P_STABLE) changes state" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " VSYNC_REC ,Asserted when VSYNC active edge is recognized" "No interrupt,Interrupt"
|
|
rgroup.long 0x1DC++0x03
|
|
line.long 0x00 "INT_UNMASK3,Interrupt Unmask Register"
|
|
bitfld.long 0x00 7. " RI_ERR_3 ,Ri and Ri do not match during frame 127 (ICNT .1)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RI_ERR_2 ,Ri and Ri do not match during frame 0 (ICNT)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RI_ERR_1 ,Ri did not change between frame 127 and 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RI_ERR_0 ,Ri not read within one frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DDC_CMD_DONE ,DDC command is complete" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " DDC_FIFO_HALF ,DDC FIFO is half full" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DDC_FIFO_FULL ,DDC FIFO is full" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DDC_FIFO_EMPTY ,DDC FIFO is empty" "No interrupt,Interrupt"
|
|
group.long 0x1E0++0x07
|
|
line.long 0x00 "INT_UNMASK4,Interrupt Unmask Register"
|
|
eventfld.long 0x00 3. " REG_INTR4_STAT3 ,CEC interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " REG_INTR4_STAT2 ,Interrupt bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " REG_INTR4_STAT1 ,Interrupt bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " DSD_INVALID ,DSD stream got invalid sequence" "No interrupt,Interrupt"
|
|
line.long 0x04 "INT_CTRL,Interrupt Control Register"
|
|
bitfld.long 0x04 3. " SOFT_INTR ,Set software interrupt" "Clear,Set"
|
|
bitfld.long 0x04 2. " OPEN_DRAIN ,INT pin output type" "Push/Pull,Open Drain pin"
|
|
textline " "
|
|
bitfld.long 0x04 1. " POLARITY ,INT pin assertion level" "Assert HIGH,Assert LOW"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "XVYCC2RGB_CTL,xvYCC_2_RGB Control Register"
|
|
bitfld.long 0x00 4. " EXP_ONLY ,CSC bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 3. " BYP_ALL ,All functions bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SW_OVR ,Software Over Ride" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FULLRANGE ,xvYCC full-range expansion enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XVYCCSEL ,Source select" "YcbCr,xvYCC"
|
|
group.long 0x244++0x07
|
|
line.long 0x00 "Y2R_COEFF_LOW,RGB_2_xvYCC Conversion Y to R Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Y2RCOEFF_L ,xvYCC to RGB conversion Y to R coefficient lower byte"
|
|
line.long 0x04 "Y2R_COEFF_UP,RGB_2_xvYCC Conversion Y to R Register"
|
|
hexmask.long.byte 0x04 0.--4. 1. " Y2RCOEFF_H ,xvYCC to RGB conversion Y to R coefficient upper byte"
|
|
group.long 0x24C++0x07
|
|
line.long 0x00 "CR2R_COEFF_LOW,RGB_2_xvYCC Conversion Cr to R Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CR2RCOEFF_L ,xvYCC to RGB conversion Cr to R coefficient lower byte"
|
|
line.long 0x04 "CR2R_COEFF_UP,RGB_2_xvYCC Conversion Cr to R Register"
|
|
hexmask.long.byte 0x04 0.--4. 1. " CR2RCOEFF_H ,xvYCC to RGB conversion Cr to R coefficient upper byte"
|
|
group.long 0x254++0x07
|
|
line.long 0x00 "CB2B_COEFF_LOW,RGB_2_xvYCC Conversion Cb to B Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CB2BCOEFF_L ,xvYCC to RGB conversion Cb to B coefficient lower byte"
|
|
line.long 0x04 "CB2B_COEFF_UP,RGB_2_xvYCC Conversion Cb to B Register"
|
|
hexmask.long.byte 0x04 0.--4. 1. " CB2BCOEFF_H ,xvYCC to RGB conversion Cb to B coefficient upper byte"
|
|
group.long 0x25C++0x07
|
|
line.long 0x00 "CR2G_COEFF_LOW,RGB_2_xvYCC Conversion Cr to G Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CR2GCOEFF_L ,xvYCC to RGB conversion Cr to G coefficient lower byte"
|
|
line.long 0x04 "CR2G_COEFF_UP,RGB_2_xvYCC Conversion Cr to G Register"
|
|
hexmask.long.byte 0x04 0.--4. 1. " CR2GCOEFF_H ,xvYCC to RGB conversion Cr to G coefficient upper byte"
|
|
group.long 0x264++0x07
|
|
line.long 0x00 "CB2G_COEFF_LOW,RGB_2_xvYCC Conversion Cb to G Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CB2GCOEFF_L ,xvYCC to RGB conversion Cb to G coefficient lower byte"
|
|
line.long 0x04 "CB2G_COEFF_UP,RGB_2_xvYCC Conversion Cb to G Register"
|
|
hexmask.long.byte 0x04 0.--4. 1. " CB2GCOEFF_H ,xvYCC to RGB conversion Cb to G coefficient upper byte"
|
|
group.long 0x26C++0x23
|
|
line.long 0x00 "YOFFSET1_LOW,xvYCC_2_RGB Conversion Y Offset Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " YOFFS1_L ,xvYCC2RGB Y Offset Coefficient lower byte"
|
|
line.long 0x04 "YOFFSET1_UP,xvYCC_2_RGB Conversion Y Offset Register"
|
|
bitfld.long 0x04 0.--3. " YOFFS1_H ,xvYCC2RGB Y Offset Coefficient upper byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "OFFSET1_LOW,xvYCC_2_RGB Conversion Offset1 Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " OFFS1_L ,xvYCC2RGB Offset1 Coefficient lower byte"
|
|
line.long 0x0C "OFFSET1_MID,xvYCC_2_RGB Conversion Offset1 Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " OFFS1_M ,xvYCC2RGB Y Offset Coefficient mid byte"
|
|
line.long 0x10 "OFFSET1_UP,xvYCC_2_RGB Conversion Offset1 Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " OFFS1_H ,xvYCC2RGB Y Offset Coefficient upper byte"
|
|
line.long 0x14 "OFFSET2_LOW,xvYCC_2_RGB Conversion Offset2 Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " OFFS2_L ,xvYCC2RGB Offset2 Coefficient lower byte "
|
|
line.long 0x18 "OFFSET2_UP,xvYCC_2_RGB Conversion Offset2 Register"
|
|
bitfld.long 0x18 0.--3. " OFFS2_H ,xvYCC2RGB Offset1 Coefficient uper byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "DCLEVEL_LOW,xvYCC_2_RGB Conversion DC Level Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " DC_LEV_L ,xvYCC2RGB DC lelvel coefficient lower byte"
|
|
line.long 0x20 "DC_LEVEL_UP,xvYCC_2_RGB Conversion DC Level Register"
|
|
hexmask.long.byte 0x20 0.--5. 1. " DC_LEV_H ,xvYCC2RGB DC lelvel coefficient upper byte"
|
|
group.long 0x3B0++0x17
|
|
line.long 0x00 "DDC_MAN,DDC I2C Manual Register"
|
|
bitfld.long 0x00 7. " MAN_OVR ,Manual Override of SCL and SDA output" "Normal,Override"
|
|
bitfld.long 0x00 5. " MAN_SDA ,Manual SDA output" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MAN_SCL ,Manual SCL output" "Low,High"
|
|
bitfld.long 0x00 1. " IO_SCL ,DDC SCL input state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IO_SDA ,DDC SDA input state" "Low,High"
|
|
line.long 0x04 "DDC_ADDR,DDC I2C Target Slave Address Register"
|
|
hexmask.long.byte 0x04 1.--7. 0x2 " DDC_ADDR ,DDC device address"
|
|
line.long 0x08 "DDC_SEGM,DDC I2C Target Segment Address Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DDC_SEGM ,DDC segment address"
|
|
line.long 0x0C "DDC_OFFSET,DDC I2C Target Offset Address Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DDC_OFFSET ,DDC offset address"
|
|
line.long 0x10 "DDC_COUNT1,DDC I2C Data Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DDC_COUNT ,DDC count 1"
|
|
line.long 0x14 "DDC_COUNT2,DDC I2C Data Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DDC_COUNT ,DDC count 2"
|
|
rgroup.long 0x3C8++0x03
|
|
line.long 0x00 "DDC_STATUS,DDC I2C Status Register"
|
|
bitfld.long 0x00 6. " BUS_LOW ,I2C bus pulled LOW" "Not pulled,Pulled"
|
|
bitfld.long 0x00 5. " NO_ACK ,HDMI tx ack not recieved" "Recived,Not recived"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IN_PROG ,DDC operation in progress" "Not in progress,In progress"
|
|
bitfld.long 0x00 3. " FIFO_FULL ,DDC FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIFO_EMP ,DDC FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 1. " FRD_USE ,DDC FIFO Read In Use" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FWT_USE ,DDC FIFO Write In Use" "Not used,Used"
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "DDC_CMD,DDC I2C Command Register"
|
|
bitfld.long 0x00 5. " DDC_FLT_EN ,Enable the DDC delay" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SDA_DEL_EN ,Enable 3ns glitch filtering on the DDC clock and data line" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DDC_CMD ,DDC command" "Current Address no ACK,Reserved,Sequential Read no ACK,Reserved,Enhanced DDC Read no ACK,Reserved,Sequential Write ignoring ACK,Sequential Write requiring ACK,Reserved,Clear FIFO,Clock SCL,Reserved,Reserved,Reserved,Reserved,Abort Transaction"
|
|
hgroup.long 0x3D0++0x03
|
|
hide.long 0x00 "DDC_DATA,DDC I2C Data Register"
|
|
in
|
|
rgroup.long 0x3D4++0x03
|
|
line.long 0x00 "DDC_FIFOCNT,DDC I2C FIFO Count Register"
|
|
bitfld.long 0x00 0.--4. " DDC_FIFOCNT ,FIFO data byte count (the number of bytes in the FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x3E4++0x07
|
|
line.long 0x00 "EPST,ROM Status Register"
|
|
bitfld.long 0x00 6. " BIST2_ERR ,BIST self authentication test 2 error" "No error,Error"
|
|
bitfld.long 0x00 5. " BIST1_ERR ,BIST self authentication test 1 error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CRC_ERR ,error" "No error,Error"
|
|
bitfld.long 0x00 0. " CMDD ,Command Done (last operation completed successfully)" "Not successfull,Successfull"
|
|
line.long 0x04 "EPCM,ROM Command Register"
|
|
bitfld.long 0x04 5. " LD_KSV ,Enable loading of KSV from OTP" "Dsiabled,Enabled"
|
|
bitfld.long 0x04 0.--4. " EPCM ,Command" "Reserved,Reserved,Reserved,All tests,CRC test,Reserved,Reserved,Reserved,BIST test 1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BIST test 2,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "HDMI_IP_CORE_GAMUT (HDMI IP Core Gamut Registers)"
|
|
base ad:0x46C00800
|
|
width 17.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "GAMUT_HEADER1,Gamut Metadata Registers "
|
|
hexmask.long.byte 0x00 0.--7. 1. " HEADER1 ,Gamut Metadata Header information"
|
|
line.long 0x04 "GAMUT_HEADER2,Gamut Metadata Registers "
|
|
bitfld.long 0x04 7. " NEXT_FIELD ,Indicates that the GBD will be effective on the next video field" "Low,High"
|
|
bitfld.long 0x04 4.--6. " GBD_PROFILE ,Transmission profile number. Values from 0x4 to 0x7 are reserved." "P0,P1,P2,P3,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFF_GAM_SEQ_NUM ,Indicates which video fields are relevant for this metadata" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "GAMUT_HEADER3,Gamut Metadata Registers "
|
|
bitfld.long 0x08 7. " NO_CRNT_GBD ,Indicates no gamut metadata available for currently transmitted video" "Low,High"
|
|
bitfld.long 0x08 4.--5. " PACKET_SEQ ,Indicates the position of current packet." "Intermediate packet,First packet,Last packet,Only sequence"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " CUR_GAM_SEQ_NUM ,Indicates the gamut number of the currently transmitted video stream. " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree "GAMUT_DBYTE"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_0,Gamut Metadata Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_1,Gamut Metadata Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_2,Gamut Metadata Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_3,Gamut Metadata Register 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_4,Gamut Metadata Register 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_5,Gamut Metadata Register 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_6,Gamut Metadata Register 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_7,Gamut Metadata Register 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_8,Gamut Metadata Register 8"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_9,Gamut Metadata Register 9"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_10,Gamut Metadata Register 10"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_11,Gamut Metadata Register 11"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_12,Gamut Metadata Register 12"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_13,Gamut Metadata Register 13"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_14,Gamut Metadata Register 14"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_15,Gamut Metadata Register 15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_16,Gamut Metadata Register 16"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_17,Gamut Metadata Register 17"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_18,Gamut Metadata Register 18"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_19,Gamut Metadata Register 19"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_20,Gamut Metadata Register 20"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_21,Gamut Metadata Register 21"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_22,Gamut Metadata Register 22"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_23,Gamut Metadata Register 23"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_24,Gamut Metadata Register 24"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_25,Gamut Metadata Register 25"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_26,Gamut Metadata Register 26"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "GAMUT_DBYTE_27,Gamut Metadata Register 27"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "HDMI_IP_CORE_AUDIO_VIDEO (HDMI IP Core Audio Video Registers)"
|
|
base ad:0x46C00900
|
|
width 24.
|
|
group.long 0x004++0x1F
|
|
line.long 0x00 "ACR_CTRL,ACR Control Register"
|
|
bitfld.long 0x00 1. " NCTSPKT_EN ,CTS Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CTS_SEL ,CTS Source Select" "HW,SW"
|
|
line.long 0x04 "FREQ_SVAL,ACR Audio Frequency Register"
|
|
bitfld.long 0x04 0.--2. " MCLK_CONF ,MCLK input mode" "128*Fs,256*Fs,384*Fs,512*Fs,768*Fs,1024*Fs,1152*Fs,192*Fs"
|
|
line.long 0x08 "N_SVAL1,ACR N Software Value Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " N_SVAL ,N Value for audio clock regeneration method"
|
|
line.long 0x0C "N_SVAL2,ACR N Software Value Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " N_SVAL ,N Value for audio clock regeneration method"
|
|
line.long 0x10 "N_SVAL3,ACR N Software Value Register"
|
|
bitfld.long 0x10 0.--3. " N_SVAL ,N Value for audio clock regeneration method" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "CTS_SVAL1,ACR CTS Software Value Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " CTS_SVAL ,CTS Value for audio clock regeneration method"
|
|
line.long 0x18 "CTS_SVAL2,ACR CTS Software Value Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " CTS_SVAL ,CTS Value for audio clock regeneration method"
|
|
line.long 0x1C "CTS_SVAL3,ACR CTS Software Value Register"
|
|
bitfld.long 0x1C 0.--3. " CTS_SVAL ,CTS Value for audio clock regeneration method" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x024++0x0B
|
|
line.long 0x00 "CTS_HVAL1,ACR CTS Hardware Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTS_HVAL ,CTS Value for audio clock regeneration method"
|
|
line.long 0x04 "CTS_HVAL2,ACR CTS Hardware Value Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CTS_HVAL ,CTS Value for audio clock regeneration method"
|
|
line.long 0x08 "CTS_HVAL3,ACR CTS Hardware Value Register"
|
|
bitfld.long 0x08 0.--3. " CTS_HVAL ,CTS Value for audio clock regeneration method" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x050++0x07
|
|
line.long 0x00 "AUD_MODE,Audio In Mode Register"
|
|
bitfld.long 0x00 7. " SD3_EN ,I2S input channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SD2_EN ,I2S input channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SD1_EN ,I2S input channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SD0_EN ,I2S input channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSD_EN ,Direct Stream Digital Audio enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AUD_PAR_EN ,Parallel audio input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPDIF_EN ,S/PDIF input stream enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AUD_EN ,Audio input stream enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPDIF_CTRL,Audio In S/PDIF Control Register"
|
|
bitfld.long 0x04 3. " NOAUDIO ,No S/PDIF audio" "Detected,Not detected"
|
|
bitfld.long 0x04 1. " FS_OVERRIDE ,S/PDIF input stream override" "S/PDIF input,S/W FS"
|
|
rgroup.long 0x060++0x03
|
|
line.long 0x00 "HW_SPDIF_FS,Audio In S/PDIF Extracted Fs and Length Register"
|
|
bitfld.long 0x00 5.--7. " HW_SPDIF_LEN ,Channel status bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. " HW_MAXLEN ,Maximum sample length" "20bits,24bits"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " HW_SPDIF_FS ,Set to the FS extracted from the S/PDIF input channel status bits 24-27." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x064++0x03
|
|
line.long 0x00 "SWAP_I2S,Audio In I2S Channel Swap Register"
|
|
bitfld.long 0x00 7. " SWCH3 ,Swap left-right channels for I2S Channel 3" "Not swap,Swap"
|
|
bitfld.long 0x00 6. " SWCH2 ,Swap left-right channels for I2S Channel 2" "Not swap,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SWCH1 ,Swap left-right channels for I2S Channel 1" "Not swap,Swap"
|
|
bitfld.long 0x00 4. " SWCH0 ,Swap left-right channels for I2S Channel 0" "Not swap,Swap"
|
|
group.long 0x06C++0x27
|
|
line.long 0x00 "SPDIF_ERTH,Audio Error Threshold Register"
|
|
hexmask.long.byte 0x00 0.--5. 1. " AUD_ERR_THRESH ,Specifies the error threshold level"
|
|
line.long 0x04 "I2S_IN_MAP,Audio In I2S Data In Map Register"
|
|
bitfld.long 0x04 6.--7. " FIFO3_MAP ,Channel map to FIFO 3" "SD0,SD1,SD2,SD3"
|
|
bitfld.long 0x04 4.--5. " FIFO2_MAP ,Channel map to FIFO 2" "SD0,SD1,SD2,SD3"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " FIFO1_MAP ,Channel map to FIFO 1" "SD0,SD1,SD2,SD3"
|
|
bitfld.long 0x04 0.--1. " FIFO0_MAP ,Channel map to FIFO 0" "SD0,SD1,SD2,SD3"
|
|
line.long 0x08 "I2S_IN_CTRL,Audio In I2S Control Register"
|
|
bitfld.long 0x08 7. " HBRA_ON ,High Bit Rate Audio On" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " SCK_EDGE ,SCK sample edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x08 5. " CBIT_ORDER ,This bit should be set to 1 for High Bit Rate Audio" "Low,High"
|
|
bitfld.long 0x08 4. " VBIT ,V bit value" "PCM,Compressed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " I2S_WS ,WS polarity" "Low,High"
|
|
bitfld.long 0x08 2. " I2S_JUST ,SD justify" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x08 1. " I2S_DIR ,SD direction" "MSB,LSB"
|
|
bitfld.long 0x08 0. " I2S_SHIFT ,WS to SD first bit shift" "First bit shift,No shift"
|
|
line.long 0x0C "I2S_CHST0,Audio In I2S Channel Status Registers"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " I2S_CHST0 ,Channel Status Byte 0"
|
|
line.long 0x10 "I2S_CHST1,Audio In I2S Channel Status Registers"
|
|
hexmask.long.byte 0x10 0.--7. 1. " I2S_CHST1 ,Channel Status Byte 1"
|
|
line.long 0x14 "I2S_CHST2,Audio In I2S Channel Status Registers"
|
|
bitfld.long 0x14 4.--7. " I2S_CHAN_NUM ,Channel Status Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " I2S_SRC_NUM ,Channel Status Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "I2S_CHST4,Audio In I2S Channel Status Registers"
|
|
bitfld.long 0x18 4.--7. " CLK_ACCUR ,Clock Accuracy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 0.--3. " SW_SPDIF_FS ,Sampling frequency as set by software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "I2S_CHST5,Audio In I2S Channel Status Registers"
|
|
bitfld.long 0x1C 4.--7. " FS_ORIG ,Original Fs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 1.--3. " I2S_LEN ,Audio sample word length" "Not indicated,16 20,18 20,Reserved,19 23,20 24,17 21,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 0. " I2S_MAXLEN ,Maximum audio sample word length" "20bits,24bits"
|
|
line.long 0x20 "ASRC,Audio Sample Rate Conversion Register"
|
|
bitfld.long 0x20 7. " HBR_SPR_MASK_3 ,Mask for the sample present and flat bit of the High Bit Rate Audio header 3" "Masked,Not masked"
|
|
bitfld.long 0x20 6. " HBR_SPR_MASK_2 ,Mask for the sample present and flat bit of the High Bit Rate Audio header 2" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x20 5. " HBR_SPR_MASK_1 ,Mask for the sample present and flat bit of the High Bit Rate Audio header 1" "Masked,Not masked"
|
|
bitfld.long 0x20 4. " HBR_SPR_MASK_0 ,Mask for the sample present and flat bit of the High Bit Rate Audio header 0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x20 1. " RATIO ,Sample rate down-conversion ratio" "2-to-1,4-to-1"
|
|
bitfld.long 0x20 0. " SRC_EN ,Audio sample rate conversion" "Disabled,Enabled"
|
|
line.long 0x24 "I2S_IN_LEN,Audio I2S Input Length Register"
|
|
bitfld.long 0x24 4.--7. " HDR_PKT_ID ,The ID of the High Bit Rate Audio packet header" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 0.--3. " IN_LENGTH ,Number of valid bits in the input I2S stream" "Reserved,Reserved,16bit,Reserved,18bit,22bit,Reserved,Reserved,19bit,23bit,20bit,24bit,17bit,21bit,?..."
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|
group.long 0x0BC++0x07
|
|
line.long 0x00 "HDMI_CTRL,HDMI Control Register"
|
|
bitfld.long 0x00 6. " DC_EN ,Deep-color packet enable" "Not send,Send"
|
|
bitfld.long 0x00 3.--5. " PACKET_MODE ,Specifies the number of bits per pixel sent to the paketizer" "Reserved,Reserved,Reserved,Reserved,24bits,30bits,36bits,48bits"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " LAYOUT ,Audio packet header layout indicator" "Layout 0,Layout 1,?..."
|
|
bitfld.long 0x00 0. " HDMI_MODE ,HDMI mode" "Disabled,Enabled"
|
|
line.long 0x04 "AUDO_TXSTAT,Audio Path Status Register"
|
|
bitfld.long 0x04 2. " MUTE ,General Control Packet mute status" "No packet,Packet"
|
|
bitfld.long 0x04 1. " NPACKET_EN_VS_HIGH ,Enables null packet flooding only when VSync is high" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " NPACKET_EN ,Enables null packet flooding all the time" "Disabled,Enabled"
|
|
group.long 0x0CC++0x0B
|
|
line.long 0x00 "AUD_PAR_BUSCLK_1,Audio Input Data Rate Adjustment Register "
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUD_PAR_BUSCLK_1 ,Decimal part of adjusment parameter"
|
|
line.long 0x04 "AUD_PAR_BUSCLK_2,Audio Input Data Rate Adjustment Register "
|
|
hexmask.long.byte 0x04 0.--7. 1. " AUD_PAR_BUSCLK_2 ,Lower byte of integer part of parameter"
|
|
line.long 0x08 "AUD_PAR_BUSCLK_3,Audio Input Data Rate Adjustment Register "
|
|
hexmask.long.byte 0x08 0.--7. 1. " AUD_PAR_BUSCLK_3 ,Upper byte of integer part of parameter"
|
|
group.long 0x0F0++0x1F
|
|
line.long 0x00 "TEST_TXCTRL,Test Control Register"
|
|
bitfld.long 0x00 3. " DIV_ENC_BYP ,DVI encoder bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 2. " CORE_ISO_EN ,TMDS Core Isolation Enable" "Normal,Mixed"
|
|
line.long 0x04 "DPD,Diagnostic Power Down Register"
|
|
bitfld.long 0x04 7. " VID_BYP_EN ,Enable bypath of the video path" "Disable,Enable"
|
|
bitfld.long 0x04 3. " TCLKPHZ ,Selects the TCLK phase" "Default phase,Invert TCLK"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PDIDCK ,Power down IDCK input" "Power down,Normal operation"
|
|
bitfld.long 0x04 1. " PDOSC ,Power donw internal oscillator" "Power down,Normal operation"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PDTOT ,Power down total" "Power down,Normal operation"
|
|
line.long 0x08 "PB_CTRL1,Packet Buffer Control 1 Register"
|
|
bitfld.long 0x08 7. " MPEG_EN ,Enable MPEG InfoFrame transmission" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " MPEG_RPT ,Repeat MPEG InfoFrame transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " AUD_EN ,Enable Audio InfoFrame transmission" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " AUD_RPT ,Repeat Audio InfoFrame transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SPD_EN ,Enable SPD InfoFrame transmission" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SPD_RPT ,Repeat SPD InfoFrame transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " AVI_EN ,Enable AVI InfoFrame transmission" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " AVI_RPT ,Repeat AVI InfoFrame transmission" "Disabled,Enabled"
|
|
line.long 0x0C "PB_CTRL2,Packet Buffer Control 2 Register"
|
|
bitfld.long 0x0C 7. " GAM_EN ,Enable Gamut Metadata InfoFrame transmission on HDMI" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " GAM_RPT ,Repeat Gamut Metadata InfoFrame Packet data each frame" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " GEN2_EN ,Enable Generic 2 Packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " GEN2_RPT ,Repeat Generic 2 Packet transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " CP_EN ,Enable General Control Packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " CP_RPT ,Repeat General Control Packet transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " GEN_EN ,Enable Generic Packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " GEN_RPT ,Repeat Generic Packet transmission" "Disabled,Enabled"
|
|
line.long 0x10 "AVI_TYPE,Packet Registers"
|
|
hexmask.long.byte 0x10 0.--7. 1. " AVI_TYPE ,AVI InfoFrame Type Code"
|
|
line.long 0x14 "AVI_VERS,Packet Registers"
|
|
hexmask.long.byte 0x14 0.--7. 1. " AVI_VERS ,AVI InfoFrame Version Code"
|
|
line.long 0x18 "AVI_LEN,Packet Registers"
|
|
hexmask.long.byte 0x18 0.--7. 1. " AVI_LEN ,AVI InfoFrame Length"
|
|
line.long 0x1C "AVI_CHSUM,Packet Registers"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " AVI_CHSUM ,AVI InfoFrame Checksum"
|
|
tree "AVI_DBYTE"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "AVI_DBYTE_0,Packet Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "AVI_DBYTE_1,Packet Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "AVI_DBYTE_2,Packet Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "AVI_DBYTE_3,Packet Register 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "AVI_DBYTE_4,Packet Register 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "AVI_DBYTE_5,Packet Register 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "AVI_DBYTE_6,Packet Register 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "AVI_DBYTE_7,Packet Register 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "AVI_DBYTE_8,Packet Register 8"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "AVI_DBYTE_9,Packet Register 9"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
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group.long 0x138++0x03
|
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line.long 0x00 "AVI_DBYTE_10,Packet Register 10"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
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group.long 0x13C++0x03
|
|
line.long 0x00 "AVI_DBYTE_11,Packet Register 11"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "AVI_DBYTE_12,Packet Register 12"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
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group.long 0x144++0x03
|
|
line.long 0x00 "AVI_DBYTE_13,Packet Register 13"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
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group.long 0x148++0x03
|
|
line.long 0x00 "AVI_DBYTE_14,Packet Register 14"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
|
|
tree.end
|
|
textline " "
|
|
group.long 0x180++0x0F
|
|
line.long 0x00 "SPD_TYPE,SPD InfoFrame Registers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_TYPE ,SPD InfoFrame Type Code"
|
|
line.long 0x04 "SPD_VERS,SPD InfoFrame Registers"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SPD_VERS ,SPD InfoFrame Version Code"
|
|
line.long 0x08 "SPD_LEN,SPD InfoFrame Registers"
|
|
hexmask.long.byte 0x08 0.--7. 1. " SPD_LEN ,SPD InfoFrame Length"
|
|
line.long 0x0C "SPD_CHSUM,SPD InfoFrame Registers"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " SPD_CHSUM ,SPD InfoFrame Checksum"
|
|
tree "SPD_DBYTE"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "SPD_DBYTE_0,SPD InfoFrame Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "SPD_DBYTE_1,SPD InfoFrame Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "SPD_DBYTE_2,SPD InfoFrame Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "SPD_DBYTE_3,SPD InfoFrame Register 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "SPD_DBYTE_4,SPD InfoFrame Register 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "SPD_DBYTE_5,SPD InfoFrame Register 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "SPD_DBYTE_6,SPD InfoFrame Register 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "SPD_DBYTE_7,SPD InfoFrame Register 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "SPD_DBYTE_8,SPD InfoFrame Register 8"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "SPD_DBYTE_9,SPD InfoFrame Register 9"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "SPD_DBYTE_10,SPD InfoFrame Register 10"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "SPD_DBYTE_11,SPD InfoFrame Register 11"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "SPD_DBYTE_12,SPD InfoFrame Register 12"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "SPD_DBYTE_13,SPD InfoFrame Register 13"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "SPD_DBYTE_14,SPD InfoFrame Register 14"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "SPD_DBYTE_15,SPD InfoFrame Register 15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "SPD_DBYTE_16,SPD InfoFrame Register 16"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "SPD_DBYTE_17,SPD InfoFrame Register 17"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "SPD_DBYTE_18,SPD InfoFrame Register 18"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "SPD_DBYTE_19,SPD InfoFrame Register 19"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SPD_DBYTE_20,SPD InfoFrame Register 20"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "SPD_DBYTE_21,SPD InfoFrame Register 21"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "SPD_DBYTE_22,SPD InfoFrame Register 22"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "SPD_DBYTE_23,SPD InfoFrame Register 23"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "SPD_DBYTE_24,SPD InfoFrame Register 24"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "SPD_DBYTE_25,SPD InfoFrame Register 25"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "SPD_DBYTE_26,SPD InfoFrame Register 26"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
|
|
tree.end
|
|
textline " "
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "AUDIO_TYPE,Audio InfoFrame Registers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_TYPE ,AUDIO InfoFrame Type Code"
|
|
line.long 0x04 "AUDIO_VERS,Audio InfoFrame Registers"
|
|
hexmask.long.byte 0x04 0.--7. 1. " AUDIO_VERS ,AUDIO InfoFrame Version Code"
|
|
line.long 0x08 "AUDIO_LEN,Audio InfoFrame Registers"
|
|
hexmask.long.byte 0x08 0.--7. 1. " AUDIO_LEN ,AUDIO InfoFrame Length"
|
|
line.long 0x0C "AUDIO_CHSUM,Audio InfoFrame Registers"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " AUDIO_CHSUM ,AUDIO InfoFrame Checksum"
|
|
tree "AUDIO_DBYTE"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "AUDIO_DBYTE_0,Audio InfoFrame Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "AUDIO_DBYTE_1,Audio InfoFrame Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "AUDIO_DBYTE_2,Audio InfoFrame Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "AUDIO_DBYTE_3,Audio InfoFrame Register 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "AUDIO_DBYTE_4,Audio InfoFrame Register 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "AUDIO_DBYTE_5,Audio InfoFrame Register 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "AUDIO_DBYTE_6,Audio InfoFrame Register 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "AUDIO_DBYTE_7,Audio InfoFrame Register 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "AUDIO_DBYTE_8,Audio InfoFrame Register 8"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "AUDIO_DBYTE_9,Audio InfoFrame Register 9"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
|
|
tree.end
|
|
textline " "
|
|
group.long 0x280++0x0F
|
|
line.long 0x00 "MPEG_TYPE,MPEG InfoFrame Registers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_TYPE ,MPEG InfoFrame Type Code"
|
|
line.long 0x04 "MPEG_VERS,MPEG InfoFrame Registers"
|
|
hexmask.long.byte 0x04 0.--7. 1. " MPEG_VERS ,MPEG InfoFrame Version Code"
|
|
line.long 0x08 "MPEG_LEN,MPEG InfoFrame Registers"
|
|
hexmask.long.byte 0x08 0.--7. 1. " MPEG_LEN ,MPEG InfoFrame Length"
|
|
line.long 0x0C "MPEG_CHSUM,MPEG InfoFrame Registers"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " MPEG_CHSUM ,MPEG InfoFrame Checksum"
|
|
tree "MPEG_DBYTE"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "MPEG_DBYTE_0,MPEG InfoFrame Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "MPEG_DBYTE_1,MPEG InfoFrame Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "MPEG_DBYTE_2,MPEG InfoFrame Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "MPEG_DBYTE_3,MPEG InfoFrame Register 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "MPEG_DBYTE_4,MPEG InfoFrame Register 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "MPEG_DBYTE_5,MPEG InfoFrame Register 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "MPEG_DBYTE_6,MPEG InfoFrame Register 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "MPEG_DBYTE_7,MPEG InfoFrame Register 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "MPEG_DBYTE_8,MPEG InfoFrame Register 8"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "MPEG_DBYTE_9,MPEG InfoFrame Register 9"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "MPEG_DBYTE_10,MPEG InfoFrame Register 10"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "MPEG_DBYTE_11,MPEG InfoFrame Register 11"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "MPEG_DBYTE_12,MPEG InfoFrame Register 12"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "MPEG_DBYTE_13,MPEG InfoFrame Register 13"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "MPEG_DBYTE_14,MPEG InfoFrame Register 14"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "MPEG_DBYTE_15,MPEG InfoFrame Register 15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "MPEG_DBYTE_16,MPEG InfoFrame Register 16"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "MPEG_DBYTE_17,MPEG InfoFrame Register 17"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "MPEG_DBYTE_18,MPEG InfoFrame Register 18"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "MPEG_DBYTE_19,MPEG InfoFrame Register 19"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "MPEG_DBYTE_20,MPEG InfoFrame Register 20"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "MPEG_DBYTE_21,MPEG InfoFrame Register 21"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "MPEG_DBYTE_22,MPEG InfoFrame Register 22"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "MPEG_DBYTE_23,MPEG InfoFrame Register 23"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "MPEG_DBYTE_24,MPEG InfoFrame Register 24"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "MPEG_DBYTE_25,MPEG InfoFrame Register 25"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "MPEG_DBYTE_26,MPEG InfoFrame Register 26"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
|
|
tree.end
|
|
tree "GEN_DBYTE"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "GEN_DBYTE_0,Generic Packet Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "GEN_DBYTE_1,Generic Packet Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "GEN_DBYTE_2,Generic Packet Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "GEN_DBYTE_3,Generic Packet Register 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "GEN_DBYTE_4,Generic Packet Register 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "GEN_DBYTE_5,Generic Packet Register 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "GEN_DBYTE_6,Generic Packet Register 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "GEN_DBYTE_7,Generic Packet Register 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "GEN_DBYTE_8,Generic Packet Register 8"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "GEN_DBYTE_9,Generic Packet Register 9"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "GEN_DBYTE_10,Generic Packet Register 10"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "GEN_DBYTE_11,Generic Packet Register 11"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "GEN_DBYTE_12,Generic Packet Register 12"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "GEN_DBYTE_13,Generic Packet Register 13"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "GEN_DBYTE_14,Generic Packet Register 14"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "GEN_DBYTE_15,Generic Packet Register 15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "GEN_DBYTE_16,Generic Packet Register 16"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "GEN_DBYTE_17,Generic Packet Register 17"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "GEN_DBYTE_18,Generic Packet Register 18"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "GEN_DBYTE_19,Generic Packet Register 19"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "GEN_DBYTE_20,Generic Packet Register 20"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "GEN_DBYTE_21,Generic Packet Register 21"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "GEN_DBYTE_22,Generic Packet Register 22"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "GEN_DBYTE_23,Generic Packet Register 23"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "GEN_DBYTE_24,Generic Packet Register 24"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "GEN_DBYTE_25,Generic Packet Register 25"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "GEN_DBYTE_26,Generic Packet Register 26"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x36C++0x03
|
|
line.long 0x00 "GEN_DBYTE_27,Generic Packet Register 27"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "GEN_DBYTE_28,Generic Packet Register 28"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x374++0x03
|
|
line.long 0x00 "GEN_DBYTE_29,Generic Packet Register 29"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "GEN_DBYTE_30,Generic Packet Register 30"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
|
|
tree.end
|
|
textline " "
|
|
group.long 0x37C++0x03
|
|
line.long 0x00 "CP_BYTE1,General Control Packet Register"
|
|
bitfld.long 0x00 4. " CLRAVM ,Clear AV Mute flag" "Low,High"
|
|
bitfld.long 0x00 0. " SETAVM ,Set AV Mute flag" "Low,High"
|
|
tree "GEN2_DBYTE"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "GEN2_DBYTE_0,Generic Packet 2 Registers 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "GEN2_DBYTE_1,Generic Packet 2 Registers 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "GEN2_DBYTE_2,Generic Packet 2 Registers 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "GEN2_DBYTE_3,Generic Packet 2 Registers 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "GEN2_DBYTE_4,Generic Packet 2 Registers 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "GEN2_DBYTE_5,Generic Packet 2 Registers 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "GEN2_DBYTE_6,Generic Packet 2 Registers 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "GEN2_DBYTE_7,Generic Packet 2 Registers 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "GEN2_DBYTE_8,Generic Packet 2 Registers 8"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "GEN2_DBYTE_9,Generic Packet 2 Registers 9"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "GEN2_DBYTE_10,Generic Packet 2 Registers 10"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "GEN2_DBYTE_11,Generic Packet 2 Registers 11"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "GEN2_DBYTE_12,Generic Packet 2 Registers 12"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "GEN2_DBYTE_13,Generic Packet 2 Registers 13"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "GEN2_DBYTE_14,Generic Packet 2 Registers 14"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "GEN2_DBYTE_15,Generic Packet 2 Registers 15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "GEN2_DBYTE_16,Generic Packet 2 Registers 16"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3C4++0x03
|
|
line.long 0x00 "GEN2_DBYTE_17,Generic Packet 2 Registers 17"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3C8++0x03
|
|
line.long 0x00 "GEN2_DBYTE_18,Generic Packet 2 Registers 18"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "GEN2_DBYTE_19,Generic Packet 2 Registers 19"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "GEN2_DBYTE_20,Generic Packet 2 Registers 20"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "GEN2_DBYTE_21,Generic Packet 2 Registers 21"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3D8++0x03
|
|
line.long 0x00 "GEN2_DBYTE_22,Generic Packet 2 Registers 22"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3DC++0x03
|
|
line.long 0x00 "GEN2_DBYTE_23,Generic Packet 2 Registers 23"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "GEN2_DBYTE_24,Generic Packet 2 Registers 24"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3E4++0x03
|
|
line.long 0x00 "GEN2_DBYTE_25,Generic Packet 2 Registers 25"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3E8++0x03
|
|
line.long 0x00 "GEN2_DBYTE_26,Generic Packet 2 Registers 26"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3EC++0x03
|
|
line.long 0x00 "GEN2_DBYTE_27,Generic Packet 2 Registers 27"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "GEN2_DBYTE_28,Generic Packet 2 Registers 28"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3F4++0x03
|
|
line.long 0x00 "GEN2_DBYTE_29,Generic Packet 2 Registers 29"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
group.long 0x3F8++0x03
|
|
line.long 0x00 "GEN2_DBYTE_30,Generic Packet 2 Registers 30"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
|
|
tree.end
|
|
textline " "
|
|
group.long 0x3FC++0x03
|
|
line.long 0x00 "CEC_ADDR_ID,CEC Slave ID Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_ID ,CEC I2C slave address ID"
|
|
width 0xb
|
|
tree.end
|
|
tree "HDMI_IP_CORE_CEC (HDMI IP Core CEC Registers)"
|
|
base ad:0x46C00D00
|
|
width 23.
|
|
rgroup.long 0x00++0x1B
|
|
line.long 0x00 "CEC_DEV_ID,CEC Device ID Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_DEV_ID ,ID of CEC device"
|
|
line.long 0x04 "CEC_SPEC,CEC Specification Register"
|
|
bitfld.long 0x04 4.--7. " CEC_REL ,CEC Specification major release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " CEC_REV ,CEC Specification minor release (rev. 1.2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "CEC_SUFF,CEC Specification Suffix Register"
|
|
bitfld.long 0x08 7. " SUB_SYS ,Subsytem" "Firmware,Hardware"
|
|
bitfld.long 0x08 0.--3. " CEC_SUFF ,CEC Specification Suffix" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "CEC_FW,CEC Firmware Revision Register"
|
|
bitfld.long 0x0C 4.--7. " FW_REL_ID ,Firmware Release ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. " FW_REV_ID ,Firmware Revision ID " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "CEC_DBG_0,CEC Debug Register0"
|
|
hexmask.long.byte 0x10 0.--7. 1. " STB_LOW_P ,Start Bit Low Period"
|
|
line.long 0x14 "CEC_DBG_1,CEC Debug Register1 "
|
|
hexmask.long.byte 0x14 0.--7. 1. " STB_DUR_P ,Start Bit Duration Period"
|
|
line.long 0x18 "CEC_DBG_2,CEC Debug Register2"
|
|
bitfld.long 0x18 4.--7. " CEC_SN_INI ,CEC Snoop Initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 0.--3. " CEC_BUS_OWN ,Current CEC bus owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "CEC_DBG_3,CEC Debug Register3"
|
|
bitfld.long 0x00 7. " FL_FIF ,Flush Tx FIFO" "Not flushed,Flushed"
|
|
bitfld.long 0x00 4.--6. " FR_RT_CNT ,Frame Retransmit Count Values 0 to 5," "0,1,2,3,4,5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " INV_ACK ,Invert ACK to Broadcast Commands" "Not inverted,Inverted"
|
|
bitfld.long 0x00 1. " ACKN_HEAD ,ACK/NACK Header Block" "ACK,NACK"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CEC_SN ,CEC snoop" "Disabled,Enabled"
|
|
line.long 0x04 "CEC_TX_INIT,CEC Tx Initialization Register"
|
|
bitfld.long 0x04 0.--3. " CEC_INIT_ID ,CEC Initiator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "CEC_TX_DEST,CEC Tx Destination Register"
|
|
bitfld.long 0x08 7. " CEC_SD_POLL ,Generate a polling message" "Not generated,Generated"
|
|
bitfld.long 0x08 0.--3. " CEC_DEST_ID ,CEC Destination ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "CEC_SETUP,CEC Set Up Register"
|
|
bitfld.long 0x00 4. " CEC_PTRH ,CEC passthru register" "Low,High"
|
|
bitfld.long 0x00 2. " CEC_FORCE_NON_CALIB ,CEC force no calibration" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CEC_CAL_EN ,CEC calibration enable register" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CEC_CAL_SW ,CEC calibration SW" "Low,High"
|
|
line.long 0x04 "CEC_TX_COMMAND,CEC Tx Command Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CEC_TX_COM ,CEC Tx command"
|
|
tree "CEC_TX_OPERAND"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_0,CEC Tx Operand Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_1,CEC Tx Operand Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_2,CEC Tx Operand Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_3,CEC Tx Operand Register 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_4,CEC Tx Operand Register 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_5,CEC Tx Operand Register 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_6,CEC Tx Operand Register 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_7,CEC Tx Operand Register 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_8,CEC Tx Operand Register 8"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_9,CEC Tx Operand Register 9"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_10,CEC Tx Operand Register 10"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_11,CEC Tx Operand Register 11"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_12,CEC Tx Operand Register 12"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_13,CEC Tx Operand Register 13"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CEC_TX_OPERAND_14,CEC Tx Operand Register 14"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
|
|
tree.end
|
|
textline " "
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CEC_TRANSMIT_DATA,CEC Transmit Data Register"
|
|
bitfld.long 0x00 6. " TX_BFR_ACC ,Read back internal buffer contents from 0x8F-0x9E" "No,Yes"
|
|
bitfld.long 0x00 5. " TX_AUT_CALC ,Auto-Calculate TX_CNT and send" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TRA_CEC_CMD ,Send CEC Command and TX_CNT Operands" "No,Yes"
|
|
bitfld.long 0x00 0.--3. " TX_CNT ,Transmit Byte Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x88++0x17
|
|
line.long 0x00 "CEC_CA_7_0,CEC Capture ID0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_CAP_ID ,The CEC Capture ID register is separate from the CEC Initiator ID"
|
|
line.long 0x04 "CEC_CA_15_8,CEC Capture ID0 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CEC_CAP_ID ,The CEC Capture ID register is separate from the CEC Initiator ID"
|
|
line.long 0x08 "CEC_INT_ENABLE_0,CEC Interrupt Enable Register0"
|
|
bitfld.long 0x08 5. " CEC_INTR1_MASK5 ,Tx: Transmit Buffer Full/Empty Change event" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CEC_INTR1_MASK2 ,Transmitter FIFO Empty event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CEC_INTR1_MASK1 ,Receiver FIFO Not Empty event" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CEC_INTR1_MASK0 ,Command Being Received event" "Disabled,Enabled"
|
|
line.long 0x0C "CEC_INT_ENABLE_1,CEC Interrupt Enable Register1"
|
|
bitfld.long 0x0C 3. " CEC_INTR2_MASK3 ,Rx FIFO Overrun Error event" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " CEC_INTR2_MASK2 ,Short Pulse Detected event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CEC_INTR2_MASK1 ,Frame Retransmit Count Exceeded event" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " CEC_INTR2_MASK0 ,Start Bit Irregularity event" "Disabled,Enabled"
|
|
line.long 0x10 "CEC_INT_STATUS_0,CEC Interrupt Status Register0"
|
|
bitfld.long 0x10 7. " CEC_LSTAT ,CEC line current state" "Low,High"
|
|
bitfld.long 0x10 6. " TFIF_BFULL ,Tx FIFO Transmit Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x10 5. " CEC_INTR1_STAT4 ,Tx: Transmit Buffer Full/Empty Change event Pending" "Not pending,Pending"
|
|
bitfld.long 0x10 2. " CEC_INTR1_STAT2 ,Transmitter FIFO Empty event pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x10 1. " CEC_INTR1_STAT1 ,Receiver FIFO Not Empty event pending" "Not pending,Pending"
|
|
bitfld.long 0x10 0. " CEC_INTR1_STAT0 ,Command Being Received event pending" "Not pending,Pending"
|
|
line.long 0x14 "CEC_INT_STATUS_1,CEC Interrupt Status Register1"
|
|
bitfld.long 0x14 3. " CEC_INTR2_STAT3 ,Rx FIFO Overrun Error event" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " CEC_INTR2_STAT2 ,Short Pulse Detected event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " CEC_INTR2_STAT1 ,Frame Retransmit Count Exceeded event" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " CEC_INTR2_STAT0 ,Start Bit Irregularity event" "Disabled,Enabled"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CEC_RX_CONTROL,CEC RX Control Register"
|
|
bitfld.long 0x00 1. " CLR_RX_FIF_ALL ,Clear All Frames from Rx FIFO" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " CLR_RX_FIF_CUR ,Clear Current Frame from Rx FIFO" "Not cleared,Cleared"
|
|
rgroup.long 0xB4++0x07
|
|
line.long 0x00 "CEC_RX_COUNT,CEC Rx Count Register"
|
|
bitfld.long 0x00 7. " RX_ERROR ,Error associated with this message" "No error,Error"
|
|
bitfld.long 0x00 4.--6. " CEC_RX_CMD_CNT ,CEC Receive FIFO Frame Count" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CEC_RX_BYTE_CNT ,CEC Receive Byte Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CEC_RX_CMD_HEADER,CEC Rx Command Header Register"
|
|
bitfld.long 0x04 4.--7. " CEC_RX_INIT ,CEC Initiator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " CEC_RX_DEST ,CEC Destination ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CEC_RX_COMMAND,CEC Rx Command Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_COM ,CEC Rx command"
|
|
tree "CEC_RX_OPERAND"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_0,CEC Rx Operand Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_1,CEC Rx Operand Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_2,CEC Rx Operand Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_3,CEC Rx Operand Register 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_4,CEC Rx Operand Register 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_5,CEC Rx Operand Register 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_6,CEC Rx Operand Register 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_7,CEC Rx Operand Register 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_8,CEC Rx Operand Register 8"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_9,CEC Rx Operand Register 9"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_10,CEC Rx Operand Register 10"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_11,CEC Rx Operand Register 11"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_12,CEC Rx Operand Register 12"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_13,CEC Rx Operand Register 13"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CEC_RX_OPERAND_14,CEC Rx Operand Register 14"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
tree "HDMI_PHY (HDMI PHY Registers)"
|
|
base ad:0x48122000
|
|
width 26.
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "TMDS_CNTL2,TMDS Control Register"
|
|
bitfld.long 0x00 5. " OE ,Output enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TERM_EN ,Source termination enable control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKDETECT ,Clock detector output" "Clock < 2.5MHz,Clock > 2.5MHz"
|
|
bitfld.long 0x00 0. " RSEN ,Receiver sense output" "Disconnected,Connected"
|
|
line.long 0x04 "TMDS_CNTL3,TMDS Control Register"
|
|
bitfld.long 0x04 3.--4. " CLKMULT_CTL ,Clock multiplication factor control" "0.5x,1x,2x,4x"
|
|
bitfld.long 0x04 1.--2. " DPCOLOR_CTL ,Deep color mode control" "8bit,10bit,12bit,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0. " PDB ,Powerdown Control" "Powered,Not powered"
|
|
line.long 0x08 "BIST_CNTL,BIST Control Register"
|
|
bitfld.long 0x08 0. " ENC_BYP ,Bypass the DVI encoder" "Not bypassed,Bypassed"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TMDS_CNTL9,TMDS Control Register"
|
|
bitfld.long 0x00 0. " TEN_BIT_BYPASS ,TEN bit bypass" "Not bypassed,Bypassed"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.open "I2C (Inter Integrated Circuit)"
|
|
tree "I2C 0"
|
|
base ad:0x48028000
|
|
width 22.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "I2C_REVNB_LO,Module Revision Register (LOW BYTES)"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
|
|
line.long 0x04 "I2C_REVNB_HI,Module Revision Register (HIGH BYTES)"
|
|
bitfld.long 0x04 14.--15. " SCHEME ,Distinguish between old Scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " FUNC ,Indicates a software compatible module family"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C_SYSC,System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "Both off,Ocp on,Sys on,Both on"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits" "Force idle,No idle,Smart idle,Smartidle_wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SRST ,SoftReset bit" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Autoidle bit" "Disabled,Enabled"
|
|
width 22.
|
|
sif (!cpuis("AM335*"))
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "I2C_EOI,I2C End of Interrupt Register"
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "I2C_IRQSTATUS_RAW,I2C Status Raw Register"
|
|
bitfld.long 0x00 14. " XDR ,Transmit draining IRQ status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDR ,Receive draining IRQ status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy"
|
|
endif
|
|
bitfld.long 0x00 11. " ROVR ,Receive overrun status" "Normal,Received"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow"
|
|
bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status" "No action,Recognized"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BF ,Bus Free IRQ status" "No action,Free"
|
|
bitfld.long 0x00 7. " AERR ,Access Error IRQ status" "No action,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " STC ,Start Condition IRQ status" "No action,Detected"
|
|
eventfld.long 0x00 5. " GC ,General call IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not ready,Ready"
|
|
eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ status" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARDY ,Register access ready IRQ status" "Not ready,Ready"
|
|
eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ status" "Normal,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status" "Normal,Detected"
|
|
group.long 0x28++0x0b
|
|
line.long 0x00 "I2C_IRQSTATUS,I2C Status Register"
|
|
eventfld.long 0x00 14. " XDR ,Transmit draining IRQ enabled status" "Disabled,Enabled"
|
|
eventfld.long 0x00 13. " RDR ,Receive draining IRQ enabled status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BB ,Bus busy enabled status" "Not busy,Busy"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
|
|
bitfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received"
|
|
else
|
|
eventfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 10. " XUDF ,Transmit underflow enabled status" "No underflow,Underflow"
|
|
eventfld.long 0x00 9. " AAS ,Address recognized as slave IRQ enabled status" "No action,Recognized"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BF ,Bus Free IRQ enabled status" "No action,Free"
|
|
eventfld.long 0x00 7. " AERR ,Access Error IRQ enabled status" "No action,Error"
|
|
textline " "
|
|
eventfld.long 0x00 6. " STC ,Start Condition IRQ enabled status" "No action,Detected"
|
|
eventfld.long 0x00 5. " GC ,General call IRQ enabled status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ enabled status" "Not ready,Ready"
|
|
eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ enabled status" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARDY ,Register access ready IRQ enabled status" "Not ready,Ready"
|
|
eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ enabled status" "Normal,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 0. " AL ,Arbitration lost IRQ enabled status" "Normal,Detected"
|
|
line.long 0x04 "I2C_IRQENABLE_SET,I2C Interrupt Enable Set Register"
|
|
bitfld.long 0x04 14. " XDR_IE ,Transmit draining IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " RDR_IE ,Receive draining IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " ROVR ,Receive overrun enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XUDF ,Transmit underflow enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " AAS_IE ,Address recognized as slave IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " BF_IE ,Bus Free IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " AERR_IE ,Access Error IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " STC_IE ,Start Condition IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " GC_IE ,General call IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XRDY_IE ,Transmit data ready IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDY_IE ,Receive data ready IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ARDY_IE ,Register access ready IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " NACK_IE ,No acknowledgement IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " AL_IE ,Arbitration lost IRQ enable set" "Disabled,Enabled"
|
|
line.long 0x08 "I2C_IRQENABLE_CLR,I2C Interrupt Enable Clear Register"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM387*"))||(cpuis("AM335*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
|
|
bitfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled"
|
|
else
|
|
eventfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x34++0x1b
|
|
line.long 0x00 "I2C_WE,I2C Wakeup Enable Register"
|
|
bitfld.long 0x00 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
|
|
width 22.
|
|
line.long 0x04 "I2C_DMARXENABLE_SET,Receive DMA Enable Set Register"
|
|
bitfld.long 0x04 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set" "Disabled,Enabled"
|
|
line.long 0x08 "I2C_DMATXENABLE_SET,Transmit DMA Enable Set Register"
|
|
bitfld.long 0x08 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set" "Disabled,Enabled"
|
|
line.long 0x0c "I2C_DMARXENABLE_CLR,Receive DMA Enable Clear Register"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear"
|
|
else
|
|
eventfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear"
|
|
endif
|
|
line.long 0x10 "I2C_DMATXENABLE_CLR,Transmit DMA Enable Clear Register"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear"
|
|
else
|
|
eventfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear"
|
|
endif
|
|
width 22.
|
|
line.long 0x14 "I2C_DMARXWAKE_EN,Receive DMA Wakeup Register"
|
|
bitfld.long 0x14 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
|
|
line.long 0x18 "I2C_DMATXWAKE_EN,Transmit DMA Wakeup Register"
|
|
bitfld.long 0x18 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
|
|
group.long 0x90++0x0b
|
|
line.long 0x00 "I2C_SYSS,System Status Register"
|
|
bitfld.long 0x00 0. " RDONE ,Reset done bit" "Ongoing,Completed"
|
|
line.long 0x04 "I2C_BUF,Buffer Configuration Register"
|
|
bitfld.long 0x04 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--13. 1. " RXTRSH ,Threshold value for FIFO buffer in RX mode"
|
|
bitfld.long 0x04 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TXFIFO_CLR ,Transmit FIFO clear" "Normal,Reset"
|
|
bitfld.long 0x04 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "I2C_CNT,Data Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DCOUNT ,Data count (Master mode only)"
|
|
hgroup.long 0x9C++0x03
|
|
hide.long 0x00 "I2C_DATA,Data Access Register"
|
|
in
|
|
width 22.
|
|
if (((d.l(ad:0x48028000+0xa4))&0x400)==0x400)
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "I2C_CON,I2C Configuration Register"
|
|
bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " STB ,Start byte mode" "Normal,Start byte"
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TRX ,Transmitter/Receiver mode" "Receiver,Transmitter"
|
|
bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit"
|
|
bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit"
|
|
bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STP ,Stop condition" "No action/stop detected,Stop queried"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STT ,Start condition" "No action/start detected,Start queried"
|
|
else
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "I2C_CON,I2C Configuration Register"
|
|
bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit"
|
|
bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit"
|
|
bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit"
|
|
endif
|
|
width 22.
|
|
if (((d.l(ad:0x48028000+0xa4))&0x80)==0x80)
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "I2C_OA,I2C Own Address Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA ,Own address"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "I2C_OA,I2C Own Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA ,Own address"
|
|
endif
|
|
if (((d.l(ad:0x48028000+0xa4))&0x100)==0x100)
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "I2C_SA,Slave Address Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " SA ,Slave address"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "I2C_SA,Slave Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SA ,Slave address"
|
|
endif
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value"
|
|
if (((d.l(ad:0x48028000+0xa4))&0x400)==0x400)
|
|
group.long 0xB4++0x07
|
|
line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time"
|
|
line.long 0x04 "I2C_SCLH,I2C SCL High Time Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCLH ,Fast/Standard mode SCL high time"
|
|
else
|
|
hgroup.long 0xB4++0x07
|
|
hide.long 0x00 "I2C_SCLL,I2C SCL Low Time Register"
|
|
hide.long 0x04 "I2C_SCLH,I2C SCL High Time Register"
|
|
endif
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "I2C_SYSTEST,I2C System Test Register"
|
|
bitfld.long 0x00 15. " ST_EN ,System test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FREE ,Free running mode" "Stop,Free"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,Test,Loopback"
|
|
bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Set"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High"
|
|
rbitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High"
|
|
rbitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High"
|
|
rbitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High"
|
|
rbitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High"
|
|
else
|
|
bitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High"
|
|
bitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High"
|
|
bitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High"
|
|
bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High"
|
|
bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High"
|
|
endif
|
|
rgroup.long 0xc0++0x03
|
|
line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register"
|
|
bitfld.long 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth" "8-bytes,16-bytes,32-bytes,64-bytes"
|
|
bitfld.long 0x00 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " TXSTAT ,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((d.l(ad:0x48028000+0xa4))&0x40)==0x00)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA1 ,Own address 1"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA1 ,Own address 1"
|
|
endif
|
|
if (((d.l(ad:0x48028000+0xa4))&0x20)==0x00)
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA2 ,Own address 2"
|
|
else
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA2 ,Own address 2"
|
|
endif
|
|
if (((d.l(ad:0x48028000+0xa4))&0x10)==0x00)
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA3 ,Own address 3"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA3 ,Own address 3"
|
|
endif
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register"
|
|
bitfld.long 0x00 3. " OA3_ACT ,Own Address 3 active" "Inactive,Active"
|
|
bitfld.long 0x00 2. " OA2_ACT ,Own Address 2 active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OA1_ACT ,Own Address 1 active" "Inactive,Active"
|
|
bitfld.long 0x00 0. " OA0_ACT ,Own Address 0 active" "Inactive,Active"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register"
|
|
bitfld.long 0x00 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3" "Released,Blocked"
|
|
bitfld.long 0x00 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2" "Released,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1" "Released,Blocked"
|
|
bitfld.long 0x00 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0" "Released,Blocked"
|
|
width 0xb
|
|
tree.end
|
|
tree "I2C 1"
|
|
base ad:0x4802a000
|
|
width 22.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "I2C_REVNB_LO,Module Revision Register (LOW BYTES)"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
|
|
line.long 0x04 "I2C_REVNB_HI,Module Revision Register (HIGH BYTES)"
|
|
bitfld.long 0x04 14.--15. " SCHEME ,Distinguish between old Scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " FUNC ,Indicates a software compatible module family"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C_SYSC,System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "Both off,Ocp on,Sys on,Both on"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits" "Force idle,No idle,Smart idle,Smartidle_wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SRST ,SoftReset bit" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Autoidle bit" "Disabled,Enabled"
|
|
width 22.
|
|
sif (!cpuis("AM335*"))
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "I2C_EOI,I2C End of Interrupt Register"
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "I2C_IRQSTATUS_RAW,I2C Status Raw Register"
|
|
bitfld.long 0x00 14. " XDR ,Transmit draining IRQ status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDR ,Receive draining IRQ status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy"
|
|
endif
|
|
bitfld.long 0x00 11. " ROVR ,Receive overrun status" "Normal,Received"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow"
|
|
bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status" "No action,Recognized"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BF ,Bus Free IRQ status" "No action,Free"
|
|
bitfld.long 0x00 7. " AERR ,Access Error IRQ status" "No action,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " STC ,Start Condition IRQ status" "No action,Detected"
|
|
eventfld.long 0x00 5. " GC ,General call IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not ready,Ready"
|
|
eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ status" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARDY ,Register access ready IRQ status" "Not ready,Ready"
|
|
eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ status" "Normal,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status" "Normal,Detected"
|
|
group.long 0x28++0x0b
|
|
line.long 0x00 "I2C_IRQSTATUS,I2C Status Register"
|
|
eventfld.long 0x00 14. " XDR ,Transmit draining IRQ enabled status" "Disabled,Enabled"
|
|
eventfld.long 0x00 13. " RDR ,Receive draining IRQ enabled status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BB ,Bus busy enabled status" "Not busy,Busy"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
|
|
bitfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received"
|
|
else
|
|
eventfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 10. " XUDF ,Transmit underflow enabled status" "No underflow,Underflow"
|
|
eventfld.long 0x00 9. " AAS ,Address recognized as slave IRQ enabled status" "No action,Recognized"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BF ,Bus Free IRQ enabled status" "No action,Free"
|
|
eventfld.long 0x00 7. " AERR ,Access Error IRQ enabled status" "No action,Error"
|
|
textline " "
|
|
eventfld.long 0x00 6. " STC ,Start Condition IRQ enabled status" "No action,Detected"
|
|
eventfld.long 0x00 5. " GC ,General call IRQ enabled status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ enabled status" "Not ready,Ready"
|
|
eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ enabled status" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARDY ,Register access ready IRQ enabled status" "Not ready,Ready"
|
|
eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ enabled status" "Normal,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 0. " AL ,Arbitration lost IRQ enabled status" "Normal,Detected"
|
|
line.long 0x04 "I2C_IRQENABLE_SET,I2C Interrupt Enable Set Register"
|
|
bitfld.long 0x04 14. " XDR_IE ,Transmit draining IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " RDR_IE ,Receive draining IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " ROVR ,Receive overrun enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XUDF ,Transmit underflow enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " AAS_IE ,Address recognized as slave IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " BF_IE ,Bus Free IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " AERR_IE ,Access Error IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " STC_IE ,Start Condition IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " GC_IE ,General call IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XRDY_IE ,Transmit data ready IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDY_IE ,Receive data ready IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ARDY_IE ,Register access ready IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " NACK_IE ,No acknowledgement IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " AL_IE ,Arbitration lost IRQ enable set" "Disabled,Enabled"
|
|
line.long 0x08 "I2C_IRQENABLE_CLR,I2C Interrupt Enable Clear Register"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM387*"))||(cpuis("AM335*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
|
|
bitfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled"
|
|
else
|
|
eventfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x34++0x1b
|
|
line.long 0x00 "I2C_WE,I2C Wakeup Enable Register"
|
|
bitfld.long 0x00 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
|
|
width 22.
|
|
line.long 0x04 "I2C_DMARXENABLE_SET,Receive DMA Enable Set Register"
|
|
bitfld.long 0x04 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set" "Disabled,Enabled"
|
|
line.long 0x08 "I2C_DMATXENABLE_SET,Transmit DMA Enable Set Register"
|
|
bitfld.long 0x08 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set" "Disabled,Enabled"
|
|
line.long 0x0c "I2C_DMARXENABLE_CLR,Receive DMA Enable Clear Register"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear"
|
|
else
|
|
eventfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear"
|
|
endif
|
|
line.long 0x10 "I2C_DMATXENABLE_CLR,Transmit DMA Enable Clear Register"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear"
|
|
else
|
|
eventfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear"
|
|
endif
|
|
width 22.
|
|
line.long 0x14 "I2C_DMARXWAKE_EN,Receive DMA Wakeup Register"
|
|
bitfld.long 0x14 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
|
|
line.long 0x18 "I2C_DMATXWAKE_EN,Transmit DMA Wakeup Register"
|
|
bitfld.long 0x18 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
|
|
group.long 0x90++0x0b
|
|
line.long 0x00 "I2C_SYSS,System Status Register"
|
|
bitfld.long 0x00 0. " RDONE ,Reset done bit" "Ongoing,Completed"
|
|
line.long 0x04 "I2C_BUF,Buffer Configuration Register"
|
|
bitfld.long 0x04 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--13. 1. " RXTRSH ,Threshold value for FIFO buffer in RX mode"
|
|
bitfld.long 0x04 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TXFIFO_CLR ,Transmit FIFO clear" "Normal,Reset"
|
|
bitfld.long 0x04 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "I2C_CNT,Data Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DCOUNT ,Data count (Master mode only)"
|
|
hgroup.long 0x9C++0x03
|
|
hide.long 0x00 "I2C_DATA,Data Access Register"
|
|
in
|
|
width 22.
|
|
if (((d.l(ad:0x4802a000+0xa4))&0x400)==0x400)
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "I2C_CON,I2C Configuration Register"
|
|
bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " STB ,Start byte mode" "Normal,Start byte"
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TRX ,Transmitter/Receiver mode" "Receiver,Transmitter"
|
|
bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit"
|
|
bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit"
|
|
bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STP ,Stop condition" "No action/stop detected,Stop queried"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STT ,Start condition" "No action/start detected,Start queried"
|
|
else
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "I2C_CON,I2C Configuration Register"
|
|
bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit"
|
|
bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit"
|
|
bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit"
|
|
endif
|
|
width 22.
|
|
if (((d.l(ad:0x4802a000+0xa4))&0x80)==0x80)
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "I2C_OA,I2C Own Address Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA ,Own address"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "I2C_OA,I2C Own Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA ,Own address"
|
|
endif
|
|
if (((d.l(ad:0x4802a000+0xa4))&0x100)==0x100)
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "I2C_SA,Slave Address Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " SA ,Slave address"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "I2C_SA,Slave Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SA ,Slave address"
|
|
endif
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value"
|
|
if (((d.l(ad:0x4802a000+0xa4))&0x400)==0x400)
|
|
group.long 0xB4++0x07
|
|
line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time"
|
|
line.long 0x04 "I2C_SCLH,I2C SCL High Time Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCLH ,Fast/Standard mode SCL high time"
|
|
else
|
|
hgroup.long 0xB4++0x07
|
|
hide.long 0x00 "I2C_SCLL,I2C SCL Low Time Register"
|
|
hide.long 0x04 "I2C_SCLH,I2C SCL High Time Register"
|
|
endif
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "I2C_SYSTEST,I2C System Test Register"
|
|
bitfld.long 0x00 15. " ST_EN ,System test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FREE ,Free running mode" "Stop,Free"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,Test,Loopback"
|
|
bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Set"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High"
|
|
rbitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High"
|
|
rbitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High"
|
|
rbitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High"
|
|
rbitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High"
|
|
else
|
|
bitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High"
|
|
bitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High"
|
|
bitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High"
|
|
bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High"
|
|
bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High"
|
|
endif
|
|
rgroup.long 0xc0++0x03
|
|
line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register"
|
|
bitfld.long 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth" "8-bytes,16-bytes,32-bytes,64-bytes"
|
|
bitfld.long 0x00 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " TXSTAT ,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((d.l(ad:0x4802a000+0xa4))&0x40)==0x00)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA1 ,Own address 1"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA1 ,Own address 1"
|
|
endif
|
|
if (((d.l(ad:0x4802a000+0xa4))&0x20)==0x00)
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA2 ,Own address 2"
|
|
else
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA2 ,Own address 2"
|
|
endif
|
|
if (((d.l(ad:0x4802a000+0xa4))&0x10)==0x00)
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA3 ,Own address 3"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA3 ,Own address 3"
|
|
endif
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register"
|
|
bitfld.long 0x00 3. " OA3_ACT ,Own Address 3 active" "Inactive,Active"
|
|
bitfld.long 0x00 2. " OA2_ACT ,Own Address 2 active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OA1_ACT ,Own Address 1 active" "Inactive,Active"
|
|
bitfld.long 0x00 0. " OA0_ACT ,Own Address 0 active" "Inactive,Active"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register"
|
|
bitfld.long 0x00 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3" "Released,Blocked"
|
|
bitfld.long 0x00 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2" "Released,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1" "Released,Blocked"
|
|
bitfld.long 0x00 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0" "Released,Blocked"
|
|
width 0xb
|
|
tree.end
|
|
tree "I2C 2"
|
|
base ad:0x4819C000
|
|
width 22.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "I2C_REVNB_LO,Module Revision Register (LOW BYTES)"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
|
|
line.long 0x04 "I2C_REVNB_HI,Module Revision Register (HIGH BYTES)"
|
|
bitfld.long 0x04 14.--15. " SCHEME ,Distinguish between old Scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " FUNC ,Indicates a software compatible module family"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C_SYSC,System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "Both off,Ocp on,Sys on,Both on"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits" "Force idle,No idle,Smart idle,Smartidle_wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SRST ,SoftReset bit" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Autoidle bit" "Disabled,Enabled"
|
|
width 22.
|
|
sif (!cpuis("AM335*"))
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "I2C_EOI,I2C End of Interrupt Register"
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "I2C_IRQSTATUS_RAW,I2C Status Raw Register"
|
|
bitfld.long 0x00 14. " XDR ,Transmit draining IRQ status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDR ,Receive draining IRQ status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy"
|
|
endif
|
|
bitfld.long 0x00 11. " ROVR ,Receive overrun status" "Normal,Received"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow"
|
|
bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status" "No action,Recognized"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BF ,Bus Free IRQ status" "No action,Free"
|
|
bitfld.long 0x00 7. " AERR ,Access Error IRQ status" "No action,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " STC ,Start Condition IRQ status" "No action,Detected"
|
|
eventfld.long 0x00 5. " GC ,General call IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not ready,Ready"
|
|
eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ status" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARDY ,Register access ready IRQ status" "Not ready,Ready"
|
|
eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ status" "Normal,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status" "Normal,Detected"
|
|
group.long 0x28++0x0b
|
|
line.long 0x00 "I2C_IRQSTATUS,I2C Status Register"
|
|
eventfld.long 0x00 14. " XDR ,Transmit draining IRQ enabled status" "Disabled,Enabled"
|
|
eventfld.long 0x00 13. " RDR ,Receive draining IRQ enabled status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BB ,Bus busy enabled status" "Not busy,Busy"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
|
|
bitfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received"
|
|
else
|
|
eventfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 10. " XUDF ,Transmit underflow enabled status" "No underflow,Underflow"
|
|
eventfld.long 0x00 9. " AAS ,Address recognized as slave IRQ enabled status" "No action,Recognized"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BF ,Bus Free IRQ enabled status" "No action,Free"
|
|
eventfld.long 0x00 7. " AERR ,Access Error IRQ enabled status" "No action,Error"
|
|
textline " "
|
|
eventfld.long 0x00 6. " STC ,Start Condition IRQ enabled status" "No action,Detected"
|
|
eventfld.long 0x00 5. " GC ,General call IRQ enabled status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ enabled status" "Not ready,Ready"
|
|
eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ enabled status" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARDY ,Register access ready IRQ enabled status" "Not ready,Ready"
|
|
eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ enabled status" "Normal,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 0. " AL ,Arbitration lost IRQ enabled status" "Normal,Detected"
|
|
line.long 0x04 "I2C_IRQENABLE_SET,I2C Interrupt Enable Set Register"
|
|
bitfld.long 0x04 14. " XDR_IE ,Transmit draining IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " RDR_IE ,Receive draining IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " ROVR ,Receive overrun enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XUDF ,Transmit underflow enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " AAS_IE ,Address recognized as slave IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " BF_IE ,Bus Free IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " AERR_IE ,Access Error IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " STC_IE ,Start Condition IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " GC_IE ,General call IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XRDY_IE ,Transmit data ready IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDY_IE ,Receive data ready IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ARDY_IE ,Register access ready IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " NACK_IE ,No acknowledgement IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " AL_IE ,Arbitration lost IRQ enable set" "Disabled,Enabled"
|
|
line.long 0x08 "I2C_IRQENABLE_CLR,I2C Interrupt Enable Clear Register"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM387*"))||(cpuis("AM335*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
|
|
bitfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled"
|
|
else
|
|
eventfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x34++0x1b
|
|
line.long 0x00 "I2C_WE,I2C Wakeup Enable Register"
|
|
bitfld.long 0x00 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
|
|
width 22.
|
|
line.long 0x04 "I2C_DMARXENABLE_SET,Receive DMA Enable Set Register"
|
|
bitfld.long 0x04 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set" "Disabled,Enabled"
|
|
line.long 0x08 "I2C_DMATXENABLE_SET,Transmit DMA Enable Set Register"
|
|
bitfld.long 0x08 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set" "Disabled,Enabled"
|
|
line.long 0x0c "I2C_DMARXENABLE_CLR,Receive DMA Enable Clear Register"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear"
|
|
else
|
|
eventfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear"
|
|
endif
|
|
line.long 0x10 "I2C_DMATXENABLE_CLR,Transmit DMA Enable Clear Register"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear"
|
|
else
|
|
eventfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear"
|
|
endif
|
|
width 22.
|
|
line.long 0x14 "I2C_DMARXWAKE_EN,Receive DMA Wakeup Register"
|
|
bitfld.long 0x14 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
|
|
line.long 0x18 "I2C_DMATXWAKE_EN,Transmit DMA Wakeup Register"
|
|
bitfld.long 0x18 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
|
|
group.long 0x90++0x0b
|
|
line.long 0x00 "I2C_SYSS,System Status Register"
|
|
bitfld.long 0x00 0. " RDONE ,Reset done bit" "Ongoing,Completed"
|
|
line.long 0x04 "I2C_BUF,Buffer Configuration Register"
|
|
bitfld.long 0x04 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--13. 1. " RXTRSH ,Threshold value for FIFO buffer in RX mode"
|
|
bitfld.long 0x04 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TXFIFO_CLR ,Transmit FIFO clear" "Normal,Reset"
|
|
bitfld.long 0x04 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "I2C_CNT,Data Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DCOUNT ,Data count (Master mode only)"
|
|
hgroup.long 0x9C++0x03
|
|
hide.long 0x00 "I2C_DATA,Data Access Register"
|
|
in
|
|
width 22.
|
|
if (((d.l(ad:0x4819C000+0xa4))&0x400)==0x400)
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "I2C_CON,I2C Configuration Register"
|
|
bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " STB ,Start byte mode" "Normal,Start byte"
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TRX ,Transmitter/Receiver mode" "Receiver,Transmitter"
|
|
bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit"
|
|
bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit"
|
|
bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STP ,Stop condition" "No action/stop detected,Stop queried"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STT ,Start condition" "No action/start detected,Start queried"
|
|
else
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "I2C_CON,I2C Configuration Register"
|
|
bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit"
|
|
bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit"
|
|
bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit"
|
|
endif
|
|
width 22.
|
|
if (((d.l(ad:0x4819C000+0xa4))&0x80)==0x80)
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "I2C_OA,I2C Own Address Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA ,Own address"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "I2C_OA,I2C Own Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA ,Own address"
|
|
endif
|
|
if (((d.l(ad:0x4819C000+0xa4))&0x100)==0x100)
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "I2C_SA,Slave Address Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " SA ,Slave address"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "I2C_SA,Slave Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SA ,Slave address"
|
|
endif
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value"
|
|
if (((d.l(ad:0x4819C000+0xa4))&0x400)==0x400)
|
|
group.long 0xB4++0x07
|
|
line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time"
|
|
line.long 0x04 "I2C_SCLH,I2C SCL High Time Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCLH ,Fast/Standard mode SCL high time"
|
|
else
|
|
hgroup.long 0xB4++0x07
|
|
hide.long 0x00 "I2C_SCLL,I2C SCL Low Time Register"
|
|
hide.long 0x04 "I2C_SCLH,I2C SCL High Time Register"
|
|
endif
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "I2C_SYSTEST,I2C System Test Register"
|
|
bitfld.long 0x00 15. " ST_EN ,System test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FREE ,Free running mode" "Stop,Free"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,Test,Loopback"
|
|
bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Set"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High"
|
|
rbitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High"
|
|
rbitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High"
|
|
rbitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High"
|
|
rbitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High"
|
|
else
|
|
bitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High"
|
|
bitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High"
|
|
bitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High"
|
|
bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High"
|
|
bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High"
|
|
endif
|
|
rgroup.long 0xc0++0x03
|
|
line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register"
|
|
bitfld.long 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth" "8-bytes,16-bytes,32-bytes,64-bytes"
|
|
bitfld.long 0x00 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " TXSTAT ,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((d.l(ad:0x4819C000+0xa4))&0x40)==0x00)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA1 ,Own address 1"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA1 ,Own address 1"
|
|
endif
|
|
if (((d.l(ad:0x4819C000+0xa4))&0x20)==0x00)
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA2 ,Own address 2"
|
|
else
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA2 ,Own address 2"
|
|
endif
|
|
if (((d.l(ad:0x4819C000+0xa4))&0x10)==0x00)
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA3 ,Own address 3"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA3 ,Own address 3"
|
|
endif
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register"
|
|
bitfld.long 0x00 3. " OA3_ACT ,Own Address 3 active" "Inactive,Active"
|
|
bitfld.long 0x00 2. " OA2_ACT ,Own Address 2 active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OA1_ACT ,Own Address 1 active" "Inactive,Active"
|
|
bitfld.long 0x00 0. " OA0_ACT ,Own Address 0 active" "Inactive,Active"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register"
|
|
bitfld.long 0x00 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3" "Released,Blocked"
|
|
bitfld.long 0x00 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2" "Released,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1" "Released,Blocked"
|
|
bitfld.long 0x00 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0" "Released,Blocked"
|
|
width 0xb
|
|
tree.end
|
|
tree "I2C 3"
|
|
base ad:0x4819E000
|
|
width 22.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "I2C_REVNB_LO,Module Revision Register (LOW BYTES)"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
|
|
line.long 0x04 "I2C_REVNB_HI,Module Revision Register (HIGH BYTES)"
|
|
bitfld.long 0x04 14.--15. " SCHEME ,Distinguish between old Scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " FUNC ,Indicates a software compatible module family"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C_SYSC,System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "Both off,Ocp on,Sys on,Both on"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits" "Force idle,No idle,Smart idle,Smartidle_wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SRST ,SoftReset bit" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Autoidle bit" "Disabled,Enabled"
|
|
width 22.
|
|
sif (!cpuis("AM335*"))
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "I2C_EOI,I2C End of Interrupt Register"
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "I2C_IRQSTATUS_RAW,I2C Status Raw Register"
|
|
bitfld.long 0x00 14. " XDR ,Transmit draining IRQ status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDR ,Receive draining IRQ status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy"
|
|
endif
|
|
bitfld.long 0x00 11. " ROVR ,Receive overrun status" "Normal,Received"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow"
|
|
bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status" "No action,Recognized"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BF ,Bus Free IRQ status" "No action,Free"
|
|
bitfld.long 0x00 7. " AERR ,Access Error IRQ status" "No action,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " STC ,Start Condition IRQ status" "No action,Detected"
|
|
eventfld.long 0x00 5. " GC ,General call IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not ready,Ready"
|
|
eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ status" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARDY ,Register access ready IRQ status" "Not ready,Ready"
|
|
eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ status" "Normal,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status" "Normal,Detected"
|
|
group.long 0x28++0x0b
|
|
line.long 0x00 "I2C_IRQSTATUS,I2C Status Register"
|
|
eventfld.long 0x00 14. " XDR ,Transmit draining IRQ enabled status" "Disabled,Enabled"
|
|
eventfld.long 0x00 13. " RDR ,Receive draining IRQ enabled status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BB ,Bus busy enabled status" "Not busy,Busy"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
|
|
bitfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received"
|
|
else
|
|
eventfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 10. " XUDF ,Transmit underflow enabled status" "No underflow,Underflow"
|
|
eventfld.long 0x00 9. " AAS ,Address recognized as slave IRQ enabled status" "No action,Recognized"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BF ,Bus Free IRQ enabled status" "No action,Free"
|
|
eventfld.long 0x00 7. " AERR ,Access Error IRQ enabled status" "No action,Error"
|
|
textline " "
|
|
eventfld.long 0x00 6. " STC ,Start Condition IRQ enabled status" "No action,Detected"
|
|
eventfld.long 0x00 5. " GC ,General call IRQ enabled status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ enabled status" "Not ready,Ready"
|
|
eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ enabled status" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARDY ,Register access ready IRQ enabled status" "Not ready,Ready"
|
|
eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ enabled status" "Normal,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 0. " AL ,Arbitration lost IRQ enabled status" "Normal,Detected"
|
|
line.long 0x04 "I2C_IRQENABLE_SET,I2C Interrupt Enable Set Register"
|
|
bitfld.long 0x04 14. " XDR_IE ,Transmit draining IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " RDR_IE ,Receive draining IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " ROVR ,Receive overrun enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XUDF ,Transmit underflow enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " AAS_IE ,Address recognized as slave IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " BF_IE ,Bus Free IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " AERR_IE ,Access Error IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " STC_IE ,Start Condition IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " GC_IE ,General call IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XRDY_IE ,Transmit data ready IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDY_IE ,Receive data ready IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ARDY_IE ,Register access ready IRQ enable set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " NACK_IE ,No acknowledgement IRQ enable set" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " AL_IE ,Arbitration lost IRQ enable set" "Disabled,Enabled"
|
|
line.long 0x08 "I2C_IRQENABLE_CLR,I2C Interrupt Enable Clear Register"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM387*"))||(cpuis("AM335*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
|
|
bitfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled"
|
|
else
|
|
eventfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x34++0x1b
|
|
line.long 0x00 "I2C_WE,I2C Wakeup Enable Register"
|
|
bitfld.long 0x00 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
|
|
width 22.
|
|
line.long 0x04 "I2C_DMARXENABLE_SET,Receive DMA Enable Set Register"
|
|
bitfld.long 0x04 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set" "Disabled,Enabled"
|
|
line.long 0x08 "I2C_DMATXENABLE_SET,Transmit DMA Enable Set Register"
|
|
bitfld.long 0x08 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set" "Disabled,Enabled"
|
|
line.long 0x0c "I2C_DMARXENABLE_CLR,Receive DMA Enable Clear Register"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear"
|
|
else
|
|
eventfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear"
|
|
endif
|
|
line.long 0x10 "I2C_DMATXENABLE_CLR,Transmit DMA Enable Clear Register"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear"
|
|
else
|
|
eventfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear"
|
|
endif
|
|
width 22.
|
|
line.long 0x14 "I2C_DMARXWAKE_EN,Receive DMA Wakeup Register"
|
|
bitfld.long 0x14 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
|
|
line.long 0x18 "I2C_DMATXWAKE_EN,Transmit DMA Wakeup Register"
|
|
bitfld.long 0x18 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
|
|
group.long 0x90++0x0b
|
|
line.long 0x00 "I2C_SYSS,System Status Register"
|
|
bitfld.long 0x00 0. " RDONE ,Reset done bit" "Ongoing,Completed"
|
|
line.long 0x04 "I2C_BUF,Buffer Configuration Register"
|
|
bitfld.long 0x04 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--13. 1. " RXTRSH ,Threshold value for FIFO buffer in RX mode"
|
|
bitfld.long 0x04 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TXFIFO_CLR ,Transmit FIFO clear" "Normal,Reset"
|
|
bitfld.long 0x04 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "I2C_CNT,Data Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DCOUNT ,Data count (Master mode only)"
|
|
hgroup.long 0x9C++0x03
|
|
hide.long 0x00 "I2C_DATA,Data Access Register"
|
|
in
|
|
width 22.
|
|
if (((d.l(ad:0x4819E000+0xa4))&0x400)==0x400)
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "I2C_CON,I2C Configuration Register"
|
|
bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " STB ,Start byte mode" "Normal,Start byte"
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TRX ,Transmitter/Receiver mode" "Receiver,Transmitter"
|
|
bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit"
|
|
bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit"
|
|
bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STP ,Stop condition" "No action/stop detected,Stop queried"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STT ,Start condition" "No action/start detected,Start queried"
|
|
else
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "I2C_CON,I2C Configuration Register"
|
|
bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit"
|
|
bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit"
|
|
bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit"
|
|
endif
|
|
width 22.
|
|
if (((d.l(ad:0x4819E000+0xa4))&0x80)==0x80)
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "I2C_OA,I2C Own Address Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA ,Own address"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "I2C_OA,I2C Own Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA ,Own address"
|
|
endif
|
|
if (((d.l(ad:0x4819E000+0xa4))&0x100)==0x100)
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "I2C_SA,Slave Address Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " SA ,Slave address"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "I2C_SA,Slave Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SA ,Slave address"
|
|
endif
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value"
|
|
if (((d.l(ad:0x4819E000+0xa4))&0x400)==0x400)
|
|
group.long 0xB4++0x07
|
|
line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time"
|
|
line.long 0x04 "I2C_SCLH,I2C SCL High Time Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCLH ,Fast/Standard mode SCL high time"
|
|
else
|
|
hgroup.long 0xB4++0x07
|
|
hide.long 0x00 "I2C_SCLL,I2C SCL Low Time Register"
|
|
hide.long 0x04 "I2C_SCLH,I2C SCL High Time Register"
|
|
endif
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "I2C_SYSTEST,I2C System Test Register"
|
|
bitfld.long 0x00 15. " ST_EN ,System test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FREE ,Free running mode" "Stop,Free"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,Test,Loopback"
|
|
bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Set"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High"
|
|
rbitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High"
|
|
rbitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High"
|
|
rbitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High"
|
|
rbitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High"
|
|
else
|
|
bitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High"
|
|
bitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High"
|
|
bitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High"
|
|
bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High"
|
|
bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High"
|
|
endif
|
|
rgroup.long 0xc0++0x03
|
|
line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register"
|
|
bitfld.long 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth" "8-bytes,16-bytes,32-bytes,64-bytes"
|
|
bitfld.long 0x00 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " TXSTAT ,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((d.l(ad:0x4819E000+0xa4))&0x40)==0x00)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA1 ,Own address 1"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA1 ,Own address 1"
|
|
endif
|
|
if (((d.l(ad:0x4819E000+0xa4))&0x20)==0x00)
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA2 ,Own address 2"
|
|
else
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA2 ,Own address 2"
|
|
endif
|
|
if (((d.l(ad:0x4819E000+0xa4))&0x10)==0x00)
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OA3 ,Own address 3"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA3 ,Own address 3"
|
|
endif
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register"
|
|
bitfld.long 0x00 3. " OA3_ACT ,Own Address 3 active" "Inactive,Active"
|
|
bitfld.long 0x00 2. " OA2_ACT ,Own Address 2 active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OA1_ACT ,Own Address 1 active" "Inactive,Active"
|
|
bitfld.long 0x00 0. " OA0_ACT ,Own Address 0 active" "Inactive,Active"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register"
|
|
bitfld.long 0x00 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3" "Released,Blocked"
|
|
bitfld.long 0x00 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2" "Released,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1" "Released,Blocked"
|
|
bitfld.long 0x00 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0" "Released,Blocked"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "McASP (Multichannel Audio Serial Port)"
|
|
tree "McASP 0"
|
|
base ad:0x48038000
|
|
width 11.
|
|
tree "General Registers"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REV,Revision Identification Register"
|
|
sif (!cpuis("DRA62*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
|
|
width 18.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWRIDLESYSCONFIG,Power Idle SYSCONFIG"
|
|
endif
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "PFUNC,Pin Function Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "McASP,GPIO"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "McASP,GPIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "McASP,GPIO"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "PDIR,Pin Direction Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "Input,Output"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "Input,Output"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "Input,Output"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "Input,Output"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "Input,Output"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "Input,Output"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "Input,Output"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "Input,Output"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "Input,Output"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "Input,Output"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "Input,Output"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "Input,Output"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "Input,Output"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "Input,Output"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "Input,Output"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "Input,Output"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "Input,Output"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "Input,Output"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "PDOUT,Pin Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR_set/clr ,Drive on AFSR" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR_set/clr ,Drive on AHCLKR" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR_set/clr ,Drive on ACLKR" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX_set/clr ,Drive on AFSX" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX_set/clr ,Drive on AHCLKX" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX_set/clr ,Drive on ACLKX" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE_set/clr ,Drive on AMUTE" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
setclrfld.long 0x00 15. 0x05 15. 0x08 15. " AXR15_set/clr ,Drive on AXR[15]" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR14_set/clr ,Drive on AXR[14]" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR13_set/clr ,Drive on AXR[13]" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR12_set/clr ,Drive on AXR[12]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x05 11. 0x08 11. " AXR11_set/clr ,Drive on AXR[11]" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR10_set/clr ,Drive on AXR[10]" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR9_set/clr ,Drive on AXR[9]" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR8_set/clr ,Drive on AXR[8]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR7_set/clr ,Drive on AXR[7]" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR6_set/clr ,Drive on AXR[6]" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. 0x05 5. 0x08 5. " AXR5_set/clr ,Drive on AXR[5]" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR4_set/clr ,Drive on AXR[4]" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR3_set/clr ,Drive on AXR[3]" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_set/clr ,Drive on AXR[2]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_set/clr ,Drive on AXR[1]" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_set/clr ,Drive on AXR[0]" "Low,High"
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "PDIN,Pin Data Input Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR logic level" "Low,High"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR logic level" "Low,High"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR logic level" "Low,High"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX logic level" "Low,High"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX logic level" "Low,High"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE logic level" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] logic level" "Low,High"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] logic level" "Low,High"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] logic level" "Low,High"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] logic level" "Low,High"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] logic level" "Low,High"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] logic level" "Low,High"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] logic level" "Low,High"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] logic level" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] logic level" "Low,High"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] logic level" "Low,High"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] logic level" "Low,High"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] logic level" "Low,High"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] logic level" "Low,High"
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "GBLCTL,Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "AMUTE,Audio Mute Control Register"
|
|
bitfld.long 0x00 12. " XDMAERR ,Transmit DMA Error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDMAERR ,Receive DMA Error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCKFAIL ,Transmit clock failure - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RCKFAIL ,Receive clock failure - AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XSYNCERR ,Transmit frame sync error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RSYNCERR ,Receive frame sync error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XUNDRN ,Transmit underrun error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ROVRN ,Receive underrun error - AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AN335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
else
|
|
bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
endif
|
|
bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low"
|
|
bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..."
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "DLBCTL,Digital Loopback Control Register"
|
|
bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..."
|
|
bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even"
|
|
bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "DITCTL,Digital Mode Control Register"
|
|
bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1"
|
|
bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1"
|
|
bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Receive Registers"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "RGBLCTLR,Receiver Global Control Register"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
else
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
endif
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "RXMASK,Receive Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " RXMASK31 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " RXMASK30 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " RXMASK29 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXMASK28 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " RXMASK27 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " RXMASK26 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RXMASK25 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " RXMASK24 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " RXMASK23 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXMASK22 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " RXMASK21 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " RXMASK20 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RXMASK19 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RXMASK18 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " RXMASK17 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXMASK16 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " RXMASK15 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " RXMASK14 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXMASK13 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " RXMASK12 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " RXMASK11 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXMASK10 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " RXMASK9 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " RXMASK8 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXMASK7 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " RXMASK6 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " RXMASK5 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXMASK4 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " RXMASK3 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " RXMASK2 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXMASK1 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " RXMASK0 ,Receive data mask enable" "Masked,Not masked"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "RXFMT,Receive Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0x6c++0x3
|
|
line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select"
|
|
bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "ACLKRCTL,Receive Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal"
|
|
bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "RXTDM,Receive TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " RXTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " RXTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " RXTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " RXTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " RXTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RXTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " RXTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " RXTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " RXTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " RXTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RXTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " RXTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " RXTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " RXTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " RXTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " RXTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " RXTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " RXTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " RXTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " RXTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " RXTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RXTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " RXTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " RXTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "RINTCTL,Receiver Interrupt Control Register"
|
|
bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "RXSTAT,Receiver Status Register"
|
|
bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
else
|
|
bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "RXCLKCHK,Receive Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "REVTCTL,Receiver DMA Event Control Register"
|
|
bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,?..."
|
|
tree.end
|
|
tree "Transmit Registers"
|
|
group.long 0xa0++0x3
|
|
line.long 0x00 "XGBLCTL,Transmitter Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
else
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
endif
|
|
group.long 0xa4++0x3
|
|
line.long 0x00 "TXMASK,Transmit Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " TXMASK31 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " TXMASK30 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " TXMASK29 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXMASK28 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " TXMASK27 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " TXMASK26 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TXMASK25 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " TXMASK24 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " TXMASK23 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXMASK22 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " TXMASK21 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " TXMASK20 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXMASK19 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " TXMASK18 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " TXMASK17 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXMASK16 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " TXMASK15 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " TXMASK14 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TXMASK13 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " TXMASK12 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " TXMASK11 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXMASK10 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " TXMASK9 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " TXMASK8 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXMASK7 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " TXMASK6 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " TXMASK5 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXMASK4 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " TXMASK3 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " TXMASK2 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXMASK1 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " TXMASK0 ,Transmit data mask enable" "Masked,Not masked"
|
|
group.long 0xa8++0x3
|
|
line.long 0x00 "TXFMT,Transmit Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0xac++0x3
|
|
line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select"
|
|
bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ACLKXCTL,Transmit Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio"
|
|
group.long 0xb8++0x3
|
|
line.long 0x00 "TXTDM,Transmit TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " TXTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " TXTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " TXTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " TXTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " TXTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TXTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " TXTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " TXTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " TXTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " TXTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " TXTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " TXTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " TXTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " TXTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TXTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " TXTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " TXTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " TXTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " TXTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " TXTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " TXTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " TXTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " TXTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " TXTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register"
|
|
bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0xc0++0x3
|
|
line.long 0x00 "TXSTAT,Transmitter Status Register"
|
|
eventfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
else
|
|
bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred"
|
|
rgroup.long 0xc4++0x3
|
|
line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))||(cpuis("AM335*")))
|
|
hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
endif
|
|
group.long 0xc8++0x7
|
|
line.long 0x00 "TXCLKCHK,Transmit Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register"
|
|
bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,?..."
|
|
sif (!cpuis("AM335*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CLKADJEN,One-shot Clock Adjust Enable"
|
|
endif
|
|
tree.end
|
|
width 9.
|
|
tree "Serializer Control Registers"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SRCTL0,Serializer Control Register 0"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "SRCTL1,Serializer Control Register 1"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "SRCTL2,Serializer Control Register 2"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SRCTL3,Serializer Control Register 3"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "SRCTL4,Serializer Control Register 4"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "SRCTL5,Serializer Control Register 5"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
tree.end
|
|
tree "DIT Channel Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DITCSRA0,DIT Left Channel Status Register 0"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DITCSRA1,DIT Left Channel Status Register 1"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DITCSRA2,DIT Left Channel Status Register 2"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DITCSRA3,DIT Left Channel Status Register 3"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DITCSRA4,DIT Left Channel Status Register 4"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DITCSRA5,DIT Left Channel Status Register 5"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DITCSRB0,DIT Right Channel Status Register 0"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DITCSRB1,DIT Right Channel Status Register 1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DITCSRB2,DIT Right Channel Status Register 2"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DITCSRB3,DIT Right Channel Status Register 3"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DITCSRB4,DIT Right Channel Status Register 4"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DITCSRB5,DIT Right Channel Status Register 5"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "DITUDRA0,DIT Left Channel User Data Register 0"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "DITUDRA1,DIT Left Channel User Data Register 1"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "DITUDRA2,DIT Left Channel User Data Register 2"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "DITUDRA3,DIT Left Channel User Data Register 3"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DITUDRA4,DIT Left Channel User Data Register 4"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DITUDRA5,DIT Left Channel User Data Register 5"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DITUDRB0,DIT Right Channel User Data Register 0"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "DITUDRB1,DIT Right Channel User Data Register 1"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "DITUDRB2,DIT Right Channel User Data Register 2"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DITUDRB3,DIT Right Channel User Data Register 3"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "DITUDRB4,DIT Right Channel User Data Register 4"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "DITUDRB5,DIT Right Channel User Data Register 5"
|
|
tree.end
|
|
tree "Transmit Buffer Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "XBUF0,Transmit Buffer Register"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "XBUF1,Transmit Buffer Register"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "XBUF2,Transmit Buffer Register"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "XBUF3,Transmit Buffer Register"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "XBUF4,Transmit Buffer Register"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "XBUF5,Transmit Buffer Register"
|
|
tree.end
|
|
tree "Receive Buffer Registers"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "RBUF0,Receive Buffer Register"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "RBUF1,Receive Buffer Register"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "RBUF2,Receive Buffer Register"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "RBUF3,Receive Buffer Register"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "RBUF4,Receive Buffer Register"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "RBUF5,Receive Buffer Register"
|
|
tree.end
|
|
tree "McASP AFIFO Registers"
|
|
group.long 0x1000++0x3
|
|
line.long 0x00 "WFIFOCTL,Write FIFO Control Register"
|
|
bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x00 "WFIFOSTS,Write FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level"
|
|
group.long 0x1008++0x3
|
|
line.long 0x00 "RFIFOCTL,Read FIFO Control Register"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*")))
|
|
bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)"
|
|
rgroup.long 0x100c++0x3
|
|
line.long 0x00 "RFIFOSTS,Read FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "McASP 1"
|
|
base ad:0x4803c000
|
|
width 11.
|
|
tree "General Registers"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REV,Revision Identification Register"
|
|
sif (!cpuis("DRA62*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
|
|
width 18.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWRIDLESYSCONFIG,Power Idle SYSCONFIG"
|
|
endif
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "PFUNC,Pin Function Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "McASP,GPIO"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "McASP,GPIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "McASP,GPIO"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "PDIR,Pin Direction Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "Input,Output"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "Input,Output"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "Input,Output"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "Input,Output"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "Input,Output"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "Input,Output"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "Input,Output"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "Input,Output"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "Input,Output"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "Input,Output"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "Input,Output"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "Input,Output"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "Input,Output"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "Input,Output"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "Input,Output"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "Input,Output"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "Input,Output"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "Input,Output"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "PDOUT,Pin Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR_set/clr ,Drive on AFSR" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR_set/clr ,Drive on AHCLKR" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR_set/clr ,Drive on ACLKR" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX_set/clr ,Drive on AFSX" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX_set/clr ,Drive on AHCLKX" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX_set/clr ,Drive on ACLKX" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE_set/clr ,Drive on AMUTE" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
setclrfld.long 0x00 15. 0x05 15. 0x08 15. " AXR15_set/clr ,Drive on AXR[15]" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR14_set/clr ,Drive on AXR[14]" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR13_set/clr ,Drive on AXR[13]" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR12_set/clr ,Drive on AXR[12]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x05 11. 0x08 11. " AXR11_set/clr ,Drive on AXR[11]" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR10_set/clr ,Drive on AXR[10]" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR9_set/clr ,Drive on AXR[9]" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR8_set/clr ,Drive on AXR[8]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR7_set/clr ,Drive on AXR[7]" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR6_set/clr ,Drive on AXR[6]" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. 0x05 5. 0x08 5. " AXR5_set/clr ,Drive on AXR[5]" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR4_set/clr ,Drive on AXR[4]" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR3_set/clr ,Drive on AXR[3]" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_set/clr ,Drive on AXR[2]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_set/clr ,Drive on AXR[1]" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_set/clr ,Drive on AXR[0]" "Low,High"
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "PDIN,Pin Data Input Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR logic level" "Low,High"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR logic level" "Low,High"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR logic level" "Low,High"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX logic level" "Low,High"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX logic level" "Low,High"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE logic level" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] logic level" "Low,High"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] logic level" "Low,High"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] logic level" "Low,High"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] logic level" "Low,High"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] logic level" "Low,High"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] logic level" "Low,High"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] logic level" "Low,High"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] logic level" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] logic level" "Low,High"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] logic level" "Low,High"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] logic level" "Low,High"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] logic level" "Low,High"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] logic level" "Low,High"
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "GBLCTL,Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "AMUTE,Audio Mute Control Register"
|
|
bitfld.long 0x00 12. " XDMAERR ,Transmit DMA Error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDMAERR ,Receive DMA Error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCKFAIL ,Transmit clock failure - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RCKFAIL ,Receive clock failure - AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XSYNCERR ,Transmit frame sync error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RSYNCERR ,Receive frame sync error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XUNDRN ,Transmit underrun error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ROVRN ,Receive underrun error - AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AN335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
else
|
|
bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
endif
|
|
bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low"
|
|
bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..."
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "DLBCTL,Digital Loopback Control Register"
|
|
bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..."
|
|
bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even"
|
|
bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "DITCTL,Digital Mode Control Register"
|
|
bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1"
|
|
bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1"
|
|
bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Receive Registers"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "RGBLCTLR,Receiver Global Control Register"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
else
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
endif
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "RXMASK,Receive Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " RXMASK31 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " RXMASK30 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " RXMASK29 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXMASK28 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " RXMASK27 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " RXMASK26 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RXMASK25 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " RXMASK24 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " RXMASK23 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXMASK22 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " RXMASK21 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " RXMASK20 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RXMASK19 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RXMASK18 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " RXMASK17 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXMASK16 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " RXMASK15 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " RXMASK14 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXMASK13 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " RXMASK12 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " RXMASK11 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXMASK10 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " RXMASK9 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " RXMASK8 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXMASK7 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " RXMASK6 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " RXMASK5 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXMASK4 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " RXMASK3 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " RXMASK2 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXMASK1 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " RXMASK0 ,Receive data mask enable" "Masked,Not masked"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "RXFMT,Receive Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0x6c++0x3
|
|
line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select"
|
|
bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "ACLKRCTL,Receive Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal"
|
|
bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "RXTDM,Receive TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " RXTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " RXTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " RXTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " RXTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " RXTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RXTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " RXTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " RXTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " RXTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " RXTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RXTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " RXTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " RXTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " RXTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " RXTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " RXTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " RXTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " RXTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " RXTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " RXTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " RXTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RXTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " RXTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " RXTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "RINTCTL,Receiver Interrupt Control Register"
|
|
bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "RXSTAT,Receiver Status Register"
|
|
bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
else
|
|
bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "RXCLKCHK,Receive Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "REVTCTL,Receiver DMA Event Control Register"
|
|
bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,?..."
|
|
tree.end
|
|
tree "Transmit Registers"
|
|
group.long 0xa0++0x3
|
|
line.long 0x00 "XGBLCTL,Transmitter Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
else
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
endif
|
|
group.long 0xa4++0x3
|
|
line.long 0x00 "TXMASK,Transmit Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " TXMASK31 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " TXMASK30 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " TXMASK29 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXMASK28 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " TXMASK27 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " TXMASK26 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TXMASK25 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " TXMASK24 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " TXMASK23 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXMASK22 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " TXMASK21 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " TXMASK20 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXMASK19 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " TXMASK18 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " TXMASK17 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXMASK16 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " TXMASK15 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " TXMASK14 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TXMASK13 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " TXMASK12 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " TXMASK11 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXMASK10 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " TXMASK9 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " TXMASK8 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXMASK7 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " TXMASK6 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " TXMASK5 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXMASK4 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " TXMASK3 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " TXMASK2 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXMASK1 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " TXMASK0 ,Transmit data mask enable" "Masked,Not masked"
|
|
group.long 0xa8++0x3
|
|
line.long 0x00 "TXFMT,Transmit Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0xac++0x3
|
|
line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select"
|
|
bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ACLKXCTL,Transmit Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio"
|
|
group.long 0xb8++0x3
|
|
line.long 0x00 "TXTDM,Transmit TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " TXTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " TXTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " TXTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " TXTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " TXTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TXTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " TXTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " TXTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " TXTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " TXTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " TXTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " TXTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " TXTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " TXTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TXTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " TXTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " TXTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " TXTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " TXTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " TXTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " TXTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " TXTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " TXTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " TXTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register"
|
|
bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0xc0++0x3
|
|
line.long 0x00 "TXSTAT,Transmitter Status Register"
|
|
eventfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
else
|
|
bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred"
|
|
rgroup.long 0xc4++0x3
|
|
line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))||(cpuis("AM335*")))
|
|
hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
endif
|
|
group.long 0xc8++0x7
|
|
line.long 0x00 "TXCLKCHK,Transmit Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register"
|
|
bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,?..."
|
|
sif (!cpuis("AM335*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CLKADJEN,One-shot Clock Adjust Enable"
|
|
endif
|
|
tree.end
|
|
width 9.
|
|
tree "Serializer Control Registers"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SRCTL0,Serializer Control Register 0"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "SRCTL1,Serializer Control Register 1"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "SRCTL2,Serializer Control Register 2"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SRCTL3,Serializer Control Register 3"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "SRCTL4,Serializer Control Register 4"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "SRCTL5,Serializer Control Register 5"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
tree.end
|
|
tree "DIT Channel Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DITCSRA0,DIT Left Channel Status Register 0"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DITCSRA1,DIT Left Channel Status Register 1"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DITCSRA2,DIT Left Channel Status Register 2"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DITCSRA3,DIT Left Channel Status Register 3"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DITCSRA4,DIT Left Channel Status Register 4"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DITCSRA5,DIT Left Channel Status Register 5"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DITCSRB0,DIT Right Channel Status Register 0"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DITCSRB1,DIT Right Channel Status Register 1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DITCSRB2,DIT Right Channel Status Register 2"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DITCSRB3,DIT Right Channel Status Register 3"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DITCSRB4,DIT Right Channel Status Register 4"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DITCSRB5,DIT Right Channel Status Register 5"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "DITUDRA0,DIT Left Channel User Data Register 0"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "DITUDRA1,DIT Left Channel User Data Register 1"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "DITUDRA2,DIT Left Channel User Data Register 2"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "DITUDRA3,DIT Left Channel User Data Register 3"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DITUDRA4,DIT Left Channel User Data Register 4"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DITUDRA5,DIT Left Channel User Data Register 5"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DITUDRB0,DIT Right Channel User Data Register 0"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "DITUDRB1,DIT Right Channel User Data Register 1"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "DITUDRB2,DIT Right Channel User Data Register 2"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DITUDRB3,DIT Right Channel User Data Register 3"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "DITUDRB4,DIT Right Channel User Data Register 4"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "DITUDRB5,DIT Right Channel User Data Register 5"
|
|
tree.end
|
|
tree "Transmit Buffer Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "XBUF0,Transmit Buffer Register"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "XBUF1,Transmit Buffer Register"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "XBUF2,Transmit Buffer Register"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "XBUF3,Transmit Buffer Register"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "XBUF4,Transmit Buffer Register"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "XBUF5,Transmit Buffer Register"
|
|
tree.end
|
|
tree "Receive Buffer Registers"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "RBUF0,Receive Buffer Register"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "RBUF1,Receive Buffer Register"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "RBUF2,Receive Buffer Register"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "RBUF3,Receive Buffer Register"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "RBUF4,Receive Buffer Register"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "RBUF5,Receive Buffer Register"
|
|
tree.end
|
|
tree "McASP AFIFO Registers"
|
|
group.long 0x1000++0x3
|
|
line.long 0x00 "WFIFOCTL,Write FIFO Control Register"
|
|
bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x00 "WFIFOSTS,Write FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level"
|
|
group.long 0x1008++0x3
|
|
line.long 0x00 "RFIFOCTL,Read FIFO Control Register"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*")))
|
|
bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)"
|
|
rgroup.long 0x100c++0x3
|
|
line.long 0x00 "RFIFOSTS,Read FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "McASP 2"
|
|
base ad:0x48050000
|
|
width 11.
|
|
tree "General Registers"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REV,Revision Identification Register"
|
|
sif (!cpuis("DRA62*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
|
|
width 18.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWRIDLESYSCONFIG,Power Idle SYSCONFIG"
|
|
endif
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "PFUNC,Pin Function Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "McASP,GPIO"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "McASP,GPIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "McASP,GPIO"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "PDIR,Pin Direction Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "Input,Output"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "Input,Output"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "Input,Output"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "Input,Output"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "Input,Output"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "Input,Output"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "Input,Output"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "Input,Output"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "Input,Output"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "Input,Output"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "Input,Output"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "Input,Output"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "Input,Output"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "Input,Output"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "Input,Output"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "Input,Output"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "Input,Output"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "Input,Output"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "PDOUT,Pin Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR_set/clr ,Drive on AFSR" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR_set/clr ,Drive on AHCLKR" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR_set/clr ,Drive on ACLKR" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX_set/clr ,Drive on AFSX" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX_set/clr ,Drive on AHCLKX" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX_set/clr ,Drive on ACLKX" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE_set/clr ,Drive on AMUTE" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
setclrfld.long 0x00 15. 0x05 15. 0x08 15. " AXR15_set/clr ,Drive on AXR[15]" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR14_set/clr ,Drive on AXR[14]" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR13_set/clr ,Drive on AXR[13]" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR12_set/clr ,Drive on AXR[12]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x05 11. 0x08 11. " AXR11_set/clr ,Drive on AXR[11]" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR10_set/clr ,Drive on AXR[10]" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR9_set/clr ,Drive on AXR[9]" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR8_set/clr ,Drive on AXR[8]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR7_set/clr ,Drive on AXR[7]" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR6_set/clr ,Drive on AXR[6]" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. 0x05 5. 0x08 5. " AXR5_set/clr ,Drive on AXR[5]" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR4_set/clr ,Drive on AXR[4]" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR3_set/clr ,Drive on AXR[3]" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_set/clr ,Drive on AXR[2]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_set/clr ,Drive on AXR[1]" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_set/clr ,Drive on AXR[0]" "Low,High"
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "PDIN,Pin Data Input Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR logic level" "Low,High"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR logic level" "Low,High"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR logic level" "Low,High"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX logic level" "Low,High"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX logic level" "Low,High"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE logic level" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] logic level" "Low,High"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] logic level" "Low,High"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] logic level" "Low,High"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] logic level" "Low,High"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] logic level" "Low,High"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] logic level" "Low,High"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] logic level" "Low,High"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] logic level" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] logic level" "Low,High"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] logic level" "Low,High"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] logic level" "Low,High"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] logic level" "Low,High"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] logic level" "Low,High"
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "GBLCTL,Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "AMUTE,Audio Mute Control Register"
|
|
bitfld.long 0x00 12. " XDMAERR ,Transmit DMA Error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDMAERR ,Receive DMA Error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCKFAIL ,Transmit clock failure - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RCKFAIL ,Receive clock failure - AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XSYNCERR ,Transmit frame sync error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RSYNCERR ,Receive frame sync error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XUNDRN ,Transmit underrun error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ROVRN ,Receive underrun error - AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AN335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
else
|
|
bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
endif
|
|
bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low"
|
|
bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..."
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "DLBCTL,Digital Loopback Control Register"
|
|
bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..."
|
|
bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even"
|
|
bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "DITCTL,Digital Mode Control Register"
|
|
bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1"
|
|
bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1"
|
|
bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Receive Registers"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "RGBLCTLR,Receiver Global Control Register"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
else
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
endif
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "RXMASK,Receive Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " RXMASK31 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " RXMASK30 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " RXMASK29 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXMASK28 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " RXMASK27 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " RXMASK26 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RXMASK25 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " RXMASK24 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " RXMASK23 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXMASK22 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " RXMASK21 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " RXMASK20 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RXMASK19 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RXMASK18 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " RXMASK17 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXMASK16 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " RXMASK15 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " RXMASK14 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXMASK13 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " RXMASK12 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " RXMASK11 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXMASK10 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " RXMASK9 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " RXMASK8 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXMASK7 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " RXMASK6 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " RXMASK5 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXMASK4 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " RXMASK3 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " RXMASK2 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXMASK1 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " RXMASK0 ,Receive data mask enable" "Masked,Not masked"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "RXFMT,Receive Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0x6c++0x3
|
|
line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select"
|
|
bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "ACLKRCTL,Receive Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal"
|
|
bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "RXTDM,Receive TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " RXTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " RXTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " RXTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " RXTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " RXTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RXTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " RXTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " RXTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " RXTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " RXTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RXTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " RXTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " RXTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " RXTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " RXTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " RXTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " RXTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " RXTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " RXTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " RXTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " RXTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RXTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " RXTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " RXTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "RINTCTL,Receiver Interrupt Control Register"
|
|
bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "RXSTAT,Receiver Status Register"
|
|
bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
else
|
|
bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "RXCLKCHK,Receive Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "REVTCTL,Receiver DMA Event Control Register"
|
|
bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,?..."
|
|
tree.end
|
|
tree "Transmit Registers"
|
|
group.long 0xa0++0x3
|
|
line.long 0x00 "XGBLCTL,Transmitter Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
else
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
endif
|
|
group.long 0xa4++0x3
|
|
line.long 0x00 "TXMASK,Transmit Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " TXMASK31 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " TXMASK30 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " TXMASK29 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXMASK28 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " TXMASK27 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " TXMASK26 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TXMASK25 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " TXMASK24 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " TXMASK23 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXMASK22 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " TXMASK21 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " TXMASK20 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXMASK19 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " TXMASK18 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " TXMASK17 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXMASK16 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " TXMASK15 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " TXMASK14 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TXMASK13 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " TXMASK12 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " TXMASK11 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXMASK10 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " TXMASK9 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " TXMASK8 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXMASK7 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " TXMASK6 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " TXMASK5 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXMASK4 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " TXMASK3 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " TXMASK2 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXMASK1 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " TXMASK0 ,Transmit data mask enable" "Masked,Not masked"
|
|
group.long 0xa8++0x3
|
|
line.long 0x00 "TXFMT,Transmit Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0xac++0x3
|
|
line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select"
|
|
bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ACLKXCTL,Transmit Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio"
|
|
group.long 0xb8++0x3
|
|
line.long 0x00 "TXTDM,Transmit TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " TXTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " TXTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " TXTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " TXTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " TXTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TXTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " TXTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " TXTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " TXTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " TXTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " TXTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " TXTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " TXTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " TXTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TXTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " TXTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " TXTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " TXTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " TXTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " TXTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " TXTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " TXTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " TXTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " TXTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register"
|
|
bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0xc0++0x3
|
|
line.long 0x00 "TXSTAT,Transmitter Status Register"
|
|
eventfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
else
|
|
bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred"
|
|
rgroup.long 0xc4++0x3
|
|
line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))||(cpuis("AM335*")))
|
|
hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
endif
|
|
group.long 0xc8++0x7
|
|
line.long 0x00 "TXCLKCHK,Transmit Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register"
|
|
bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,?..."
|
|
sif (!cpuis("AM335*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CLKADJEN,One-shot Clock Adjust Enable"
|
|
endif
|
|
tree.end
|
|
width 9.
|
|
tree "Serializer Control Registers"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SRCTL0,Serializer Control Register 0"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "SRCTL1,Serializer Control Register 1"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "SRCTL2,Serializer Control Register 2"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SRCTL3,Serializer Control Register 3"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "SRCTL4,Serializer Control Register 4"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "SRCTL5,Serializer Control Register 5"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
tree.end
|
|
tree "DIT Channel Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DITCSRA0,DIT Left Channel Status Register 0"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DITCSRA1,DIT Left Channel Status Register 1"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DITCSRA2,DIT Left Channel Status Register 2"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DITCSRA3,DIT Left Channel Status Register 3"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DITCSRA4,DIT Left Channel Status Register 4"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DITCSRA5,DIT Left Channel Status Register 5"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DITCSRB0,DIT Right Channel Status Register 0"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DITCSRB1,DIT Right Channel Status Register 1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DITCSRB2,DIT Right Channel Status Register 2"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DITCSRB3,DIT Right Channel Status Register 3"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DITCSRB4,DIT Right Channel Status Register 4"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DITCSRB5,DIT Right Channel Status Register 5"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "DITUDRA0,DIT Left Channel User Data Register 0"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "DITUDRA1,DIT Left Channel User Data Register 1"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "DITUDRA2,DIT Left Channel User Data Register 2"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "DITUDRA3,DIT Left Channel User Data Register 3"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DITUDRA4,DIT Left Channel User Data Register 4"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DITUDRA5,DIT Left Channel User Data Register 5"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DITUDRB0,DIT Right Channel User Data Register 0"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "DITUDRB1,DIT Right Channel User Data Register 1"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "DITUDRB2,DIT Right Channel User Data Register 2"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DITUDRB3,DIT Right Channel User Data Register 3"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "DITUDRB4,DIT Right Channel User Data Register 4"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "DITUDRB5,DIT Right Channel User Data Register 5"
|
|
tree.end
|
|
tree "Transmit Buffer Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "XBUF0,Transmit Buffer Register"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "XBUF1,Transmit Buffer Register"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "XBUF2,Transmit Buffer Register"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "XBUF3,Transmit Buffer Register"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "XBUF4,Transmit Buffer Register"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "XBUF5,Transmit Buffer Register"
|
|
tree.end
|
|
tree "Receive Buffer Registers"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "RBUF0,Receive Buffer Register"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "RBUF1,Receive Buffer Register"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "RBUF2,Receive Buffer Register"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "RBUF3,Receive Buffer Register"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "RBUF4,Receive Buffer Register"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "RBUF5,Receive Buffer Register"
|
|
tree.end
|
|
tree "McASP AFIFO Registers"
|
|
group.long 0x1000++0x3
|
|
line.long 0x00 "WFIFOCTL,Write FIFO Control Register"
|
|
bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x00 "WFIFOSTS,Write FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level"
|
|
group.long 0x1008++0x3
|
|
line.long 0x00 "RFIFOCTL,Read FIFO Control Register"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*")))
|
|
bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)"
|
|
rgroup.long 0x100c++0x3
|
|
line.long 0x00 "RFIFOSTS,Read FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "McASP 3"
|
|
base ad:0x4A1A2000
|
|
width 11.
|
|
tree "General Registers"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REV,Revision Identification Register"
|
|
sif (!cpuis("DRA62*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
|
|
width 18.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWRIDLESYSCONFIG,Power Idle SYSCONFIG"
|
|
endif
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "PFUNC,Pin Function Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "McASP,GPIO"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "McASP,GPIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "McASP,GPIO"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "PDIR,Pin Direction Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "Input,Output"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "Input,Output"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "Input,Output"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "Input,Output"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "Input,Output"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "Input,Output"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "Input,Output"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "Input,Output"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "Input,Output"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "Input,Output"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "Input,Output"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "Input,Output"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "Input,Output"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "Input,Output"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "Input,Output"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "Input,Output"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "Input,Output"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "Input,Output"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "PDOUT,Pin Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR_set/clr ,Drive on AFSR" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR_set/clr ,Drive on AHCLKR" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR_set/clr ,Drive on ACLKR" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX_set/clr ,Drive on AFSX" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX_set/clr ,Drive on AHCLKX" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX_set/clr ,Drive on ACLKX" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE_set/clr ,Drive on AMUTE" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
setclrfld.long 0x00 15. 0x05 15. 0x08 15. " AXR15_set/clr ,Drive on AXR[15]" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR14_set/clr ,Drive on AXR[14]" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR13_set/clr ,Drive on AXR[13]" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR12_set/clr ,Drive on AXR[12]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x05 11. 0x08 11. " AXR11_set/clr ,Drive on AXR[11]" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR10_set/clr ,Drive on AXR[10]" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR9_set/clr ,Drive on AXR[9]" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR8_set/clr ,Drive on AXR[8]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR7_set/clr ,Drive on AXR[7]" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR6_set/clr ,Drive on AXR[6]" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. 0x05 5. 0x08 5. " AXR5_set/clr ,Drive on AXR[5]" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR4_set/clr ,Drive on AXR[4]" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR3_set/clr ,Drive on AXR[3]" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_set/clr ,Drive on AXR[2]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_set/clr ,Drive on AXR[1]" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_set/clr ,Drive on AXR[0]" "Low,High"
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "PDIN,Pin Data Input Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR logic level" "Low,High"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR logic level" "Low,High"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR logic level" "Low,High"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX logic level" "Low,High"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX logic level" "Low,High"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE logic level" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] logic level" "Low,High"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] logic level" "Low,High"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] logic level" "Low,High"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] logic level" "Low,High"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] logic level" "Low,High"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] logic level" "Low,High"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] logic level" "Low,High"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] logic level" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] logic level" "Low,High"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] logic level" "Low,High"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] logic level" "Low,High"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] logic level" "Low,High"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] logic level" "Low,High"
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "GBLCTL,Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "AMUTE,Audio Mute Control Register"
|
|
bitfld.long 0x00 12. " XDMAERR ,Transmit DMA Error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDMAERR ,Receive DMA Error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCKFAIL ,Transmit clock failure - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RCKFAIL ,Receive clock failure - AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XSYNCERR ,Transmit frame sync error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RSYNCERR ,Receive frame sync error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XUNDRN ,Transmit underrun error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ROVRN ,Receive underrun error - AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AN335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
else
|
|
bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
endif
|
|
bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low"
|
|
bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..."
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "DLBCTL,Digital Loopback Control Register"
|
|
bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..."
|
|
bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even"
|
|
bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "DITCTL,Digital Mode Control Register"
|
|
bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1"
|
|
bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1"
|
|
bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Receive Registers"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "RGBLCTLR,Receiver Global Control Register"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
else
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
endif
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "RXMASK,Receive Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " RXMASK31 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " RXMASK30 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " RXMASK29 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXMASK28 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " RXMASK27 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " RXMASK26 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RXMASK25 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " RXMASK24 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " RXMASK23 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXMASK22 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " RXMASK21 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " RXMASK20 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RXMASK19 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RXMASK18 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " RXMASK17 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXMASK16 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " RXMASK15 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " RXMASK14 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXMASK13 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " RXMASK12 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " RXMASK11 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXMASK10 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " RXMASK9 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " RXMASK8 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXMASK7 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " RXMASK6 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " RXMASK5 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXMASK4 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " RXMASK3 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " RXMASK2 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXMASK1 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " RXMASK0 ,Receive data mask enable" "Masked,Not masked"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "RXFMT,Receive Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0x6c++0x3
|
|
line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select"
|
|
bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "ACLKRCTL,Receive Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal"
|
|
bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "RXTDM,Receive TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " RXTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " RXTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " RXTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " RXTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " RXTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RXTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " RXTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " RXTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " RXTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " RXTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RXTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " RXTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " RXTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " RXTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " RXTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " RXTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " RXTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " RXTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " RXTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " RXTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " RXTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RXTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " RXTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " RXTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "RINTCTL,Receiver Interrupt Control Register"
|
|
bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "RXSTAT,Receiver Status Register"
|
|
bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
else
|
|
bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "RXCLKCHK,Receive Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "REVTCTL,Receiver DMA Event Control Register"
|
|
bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,?..."
|
|
tree.end
|
|
tree "Transmit Registers"
|
|
group.long 0xa0++0x3
|
|
line.long 0x00 "XGBLCTL,Transmitter Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
else
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
endif
|
|
group.long 0xa4++0x3
|
|
line.long 0x00 "TXMASK,Transmit Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " TXMASK31 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " TXMASK30 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " TXMASK29 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXMASK28 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " TXMASK27 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " TXMASK26 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TXMASK25 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " TXMASK24 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " TXMASK23 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXMASK22 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " TXMASK21 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " TXMASK20 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXMASK19 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " TXMASK18 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " TXMASK17 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXMASK16 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " TXMASK15 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " TXMASK14 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TXMASK13 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " TXMASK12 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " TXMASK11 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXMASK10 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " TXMASK9 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " TXMASK8 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXMASK7 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " TXMASK6 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " TXMASK5 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXMASK4 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " TXMASK3 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " TXMASK2 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXMASK1 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " TXMASK0 ,Transmit data mask enable" "Masked,Not masked"
|
|
group.long 0xa8++0x3
|
|
line.long 0x00 "TXFMT,Transmit Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0xac++0x3
|
|
line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select"
|
|
bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ACLKXCTL,Transmit Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio"
|
|
group.long 0xb8++0x3
|
|
line.long 0x00 "TXTDM,Transmit TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " TXTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " TXTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " TXTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " TXTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " TXTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TXTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " TXTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " TXTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " TXTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " TXTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " TXTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " TXTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " TXTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " TXTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TXTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " TXTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " TXTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " TXTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " TXTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " TXTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " TXTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " TXTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " TXTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " TXTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register"
|
|
bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0xc0++0x3
|
|
line.long 0x00 "TXSTAT,Transmitter Status Register"
|
|
eventfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
else
|
|
bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred"
|
|
rgroup.long 0xc4++0x3
|
|
line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))||(cpuis("AM335*")))
|
|
hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
endif
|
|
group.long 0xc8++0x7
|
|
line.long 0x00 "TXCLKCHK,Transmit Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register"
|
|
bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,?..."
|
|
sif (!cpuis("AM335*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CLKADJEN,One-shot Clock Adjust Enable"
|
|
endif
|
|
tree.end
|
|
width 9.
|
|
tree "Serializer Control Registers"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SRCTL0,Serializer Control Register 0"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "SRCTL1,Serializer Control Register 1"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "SRCTL2,Serializer Control Register 2"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SRCTL3,Serializer Control Register 3"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "SRCTL4,Serializer Control Register 4"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "SRCTL5,Serializer Control Register 5"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
tree.end
|
|
tree "DIT Channel Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DITCSRA0,DIT Left Channel Status Register 0"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DITCSRA1,DIT Left Channel Status Register 1"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DITCSRA2,DIT Left Channel Status Register 2"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DITCSRA3,DIT Left Channel Status Register 3"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DITCSRA4,DIT Left Channel Status Register 4"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DITCSRA5,DIT Left Channel Status Register 5"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DITCSRB0,DIT Right Channel Status Register 0"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DITCSRB1,DIT Right Channel Status Register 1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DITCSRB2,DIT Right Channel Status Register 2"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DITCSRB3,DIT Right Channel Status Register 3"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DITCSRB4,DIT Right Channel Status Register 4"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DITCSRB5,DIT Right Channel Status Register 5"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "DITUDRA0,DIT Left Channel User Data Register 0"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "DITUDRA1,DIT Left Channel User Data Register 1"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "DITUDRA2,DIT Left Channel User Data Register 2"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "DITUDRA3,DIT Left Channel User Data Register 3"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DITUDRA4,DIT Left Channel User Data Register 4"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DITUDRA5,DIT Left Channel User Data Register 5"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DITUDRB0,DIT Right Channel User Data Register 0"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "DITUDRB1,DIT Right Channel User Data Register 1"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "DITUDRB2,DIT Right Channel User Data Register 2"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DITUDRB3,DIT Right Channel User Data Register 3"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "DITUDRB4,DIT Right Channel User Data Register 4"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "DITUDRB5,DIT Right Channel User Data Register 5"
|
|
tree.end
|
|
tree "Transmit Buffer Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "XBUF0,Transmit Buffer Register"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "XBUF1,Transmit Buffer Register"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "XBUF2,Transmit Buffer Register"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "XBUF3,Transmit Buffer Register"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "XBUF4,Transmit Buffer Register"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "XBUF5,Transmit Buffer Register"
|
|
tree.end
|
|
tree "Receive Buffer Registers"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "RBUF0,Receive Buffer Register"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "RBUF1,Receive Buffer Register"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "RBUF2,Receive Buffer Register"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "RBUF3,Receive Buffer Register"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "RBUF4,Receive Buffer Register"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "RBUF5,Receive Buffer Register"
|
|
tree.end
|
|
tree "McASP AFIFO Registers"
|
|
group.long 0x1000++0x3
|
|
line.long 0x00 "WFIFOCTL,Write FIFO Control Register"
|
|
bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x00 "WFIFOSTS,Write FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level"
|
|
group.long 0x1008++0x3
|
|
line.long 0x00 "RFIFOCTL,Read FIFO Control Register"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*")))
|
|
bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)"
|
|
rgroup.long 0x100c++0x3
|
|
line.long 0x00 "RFIFOSTS,Read FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "McASP 4"
|
|
base ad:0x4A1A8000
|
|
width 11.
|
|
tree "General Registers"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REV,Revision Identification Register"
|
|
sif (!cpuis("DRA62*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
|
|
width 18.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWRIDLESYSCONFIG,Power Idle SYSCONFIG"
|
|
endif
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "PFUNC,Pin Function Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "McASP,GPIO"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "McASP,GPIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "McASP,GPIO"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "PDIR,Pin Direction Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "Input,Output"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "Input,Output"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "Input,Output"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "Input,Output"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "Input,Output"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "Input,Output"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "Input,Output"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "Input,Output"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "Input,Output"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "Input,Output"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "Input,Output"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "Input,Output"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "Input,Output"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "Input,Output"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "Input,Output"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "Input,Output"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "Input,Output"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "Input,Output"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "PDOUT,Pin Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR_set/clr ,Drive on AFSR" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR_set/clr ,Drive on AHCLKR" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR_set/clr ,Drive on ACLKR" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX_set/clr ,Drive on AFSX" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX_set/clr ,Drive on AHCLKX" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX_set/clr ,Drive on ACLKX" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE_set/clr ,Drive on AMUTE" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
setclrfld.long 0x00 15. 0x05 15. 0x08 15. " AXR15_set/clr ,Drive on AXR[15]" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR14_set/clr ,Drive on AXR[14]" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR13_set/clr ,Drive on AXR[13]" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR12_set/clr ,Drive on AXR[12]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x05 11. 0x08 11. " AXR11_set/clr ,Drive on AXR[11]" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR10_set/clr ,Drive on AXR[10]" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR9_set/clr ,Drive on AXR[9]" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR8_set/clr ,Drive on AXR[8]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR7_set/clr ,Drive on AXR[7]" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR6_set/clr ,Drive on AXR[6]" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. 0x05 5. 0x08 5. " AXR5_set/clr ,Drive on AXR[5]" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR4_set/clr ,Drive on AXR[4]" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR3_set/clr ,Drive on AXR[3]" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_set/clr ,Drive on AXR[2]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_set/clr ,Drive on AXR[1]" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_set/clr ,Drive on AXR[0]" "Low,High"
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "PDIN,Pin Data Input Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR logic level" "Low,High"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR logic level" "Low,High"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR logic level" "Low,High"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX logic level" "Low,High"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX logic level" "Low,High"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE logic level" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] logic level" "Low,High"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] logic level" "Low,High"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] logic level" "Low,High"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] logic level" "Low,High"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] logic level" "Low,High"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] logic level" "Low,High"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] logic level" "Low,High"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] logic level" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] logic level" "Low,High"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] logic level" "Low,High"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] logic level" "Low,High"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] logic level" "Low,High"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] logic level" "Low,High"
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "GBLCTL,Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "AMUTE,Audio Mute Control Register"
|
|
bitfld.long 0x00 12. " XDMAERR ,Transmit DMA Error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDMAERR ,Receive DMA Error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCKFAIL ,Transmit clock failure - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RCKFAIL ,Receive clock failure - AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XSYNCERR ,Transmit frame sync error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RSYNCERR ,Receive frame sync error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XUNDRN ,Transmit underrun error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ROVRN ,Receive underrun error - AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AN335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
else
|
|
bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
endif
|
|
bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low"
|
|
bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..."
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "DLBCTL,Digital Loopback Control Register"
|
|
bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..."
|
|
bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even"
|
|
bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "DITCTL,Digital Mode Control Register"
|
|
bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1"
|
|
bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1"
|
|
bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Receive Registers"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "RGBLCTLR,Receiver Global Control Register"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
else
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
endif
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "RXMASK,Receive Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " RXMASK31 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " RXMASK30 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " RXMASK29 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXMASK28 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " RXMASK27 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " RXMASK26 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RXMASK25 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " RXMASK24 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " RXMASK23 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXMASK22 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " RXMASK21 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " RXMASK20 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RXMASK19 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RXMASK18 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " RXMASK17 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXMASK16 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " RXMASK15 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " RXMASK14 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXMASK13 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " RXMASK12 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " RXMASK11 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXMASK10 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " RXMASK9 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " RXMASK8 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXMASK7 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " RXMASK6 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " RXMASK5 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXMASK4 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " RXMASK3 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " RXMASK2 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXMASK1 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " RXMASK0 ,Receive data mask enable" "Masked,Not masked"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "RXFMT,Receive Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0x6c++0x3
|
|
line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select"
|
|
bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "ACLKRCTL,Receive Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal"
|
|
bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "RXTDM,Receive TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " RXTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " RXTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " RXTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " RXTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " RXTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RXTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " RXTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " RXTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " RXTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " RXTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RXTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " RXTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " RXTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " RXTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " RXTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " RXTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " RXTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " RXTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " RXTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " RXTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " RXTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RXTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " RXTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " RXTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "RINTCTL,Receiver Interrupt Control Register"
|
|
bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "RXSTAT,Receiver Status Register"
|
|
bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
else
|
|
bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "RXCLKCHK,Receive Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "REVTCTL,Receiver DMA Event Control Register"
|
|
bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,?..."
|
|
tree.end
|
|
tree "Transmit Registers"
|
|
group.long 0xa0++0x3
|
|
line.long 0x00 "XGBLCTL,Transmitter Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
else
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
endif
|
|
group.long 0xa4++0x3
|
|
line.long 0x00 "TXMASK,Transmit Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " TXMASK31 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " TXMASK30 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " TXMASK29 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXMASK28 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " TXMASK27 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " TXMASK26 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TXMASK25 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " TXMASK24 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " TXMASK23 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXMASK22 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " TXMASK21 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " TXMASK20 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXMASK19 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " TXMASK18 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " TXMASK17 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXMASK16 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " TXMASK15 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " TXMASK14 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TXMASK13 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " TXMASK12 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " TXMASK11 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXMASK10 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " TXMASK9 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " TXMASK8 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXMASK7 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " TXMASK6 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " TXMASK5 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXMASK4 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " TXMASK3 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " TXMASK2 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXMASK1 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " TXMASK0 ,Transmit data mask enable" "Masked,Not masked"
|
|
group.long 0xa8++0x3
|
|
line.long 0x00 "TXFMT,Transmit Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0xac++0x3
|
|
line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select"
|
|
bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ACLKXCTL,Transmit Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio"
|
|
group.long 0xb8++0x3
|
|
line.long 0x00 "TXTDM,Transmit TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " TXTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " TXTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " TXTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " TXTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " TXTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TXTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " TXTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " TXTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " TXTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " TXTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " TXTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " TXTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " TXTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " TXTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TXTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " TXTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " TXTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " TXTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " TXTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " TXTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " TXTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " TXTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " TXTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " TXTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register"
|
|
bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0xc0++0x3
|
|
line.long 0x00 "TXSTAT,Transmitter Status Register"
|
|
eventfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
else
|
|
bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred"
|
|
rgroup.long 0xc4++0x3
|
|
line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))||(cpuis("AM335*")))
|
|
hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
endif
|
|
group.long 0xc8++0x7
|
|
line.long 0x00 "TXCLKCHK,Transmit Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register"
|
|
bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,?..."
|
|
sif (!cpuis("AM335*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CLKADJEN,One-shot Clock Adjust Enable"
|
|
endif
|
|
tree.end
|
|
width 9.
|
|
tree "Serializer Control Registers"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SRCTL0,Serializer Control Register 0"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "SRCTL1,Serializer Control Register 1"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "SRCTL2,Serializer Control Register 2"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SRCTL3,Serializer Control Register 3"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "SRCTL4,Serializer Control Register 4"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "SRCTL5,Serializer Control Register 5"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
tree.end
|
|
tree "DIT Channel Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DITCSRA0,DIT Left Channel Status Register 0"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DITCSRA1,DIT Left Channel Status Register 1"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DITCSRA2,DIT Left Channel Status Register 2"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DITCSRA3,DIT Left Channel Status Register 3"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DITCSRA4,DIT Left Channel Status Register 4"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DITCSRA5,DIT Left Channel Status Register 5"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DITCSRB0,DIT Right Channel Status Register 0"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DITCSRB1,DIT Right Channel Status Register 1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DITCSRB2,DIT Right Channel Status Register 2"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DITCSRB3,DIT Right Channel Status Register 3"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DITCSRB4,DIT Right Channel Status Register 4"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DITCSRB5,DIT Right Channel Status Register 5"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "DITUDRA0,DIT Left Channel User Data Register 0"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "DITUDRA1,DIT Left Channel User Data Register 1"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "DITUDRA2,DIT Left Channel User Data Register 2"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "DITUDRA3,DIT Left Channel User Data Register 3"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DITUDRA4,DIT Left Channel User Data Register 4"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DITUDRA5,DIT Left Channel User Data Register 5"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DITUDRB0,DIT Right Channel User Data Register 0"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "DITUDRB1,DIT Right Channel User Data Register 1"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "DITUDRB2,DIT Right Channel User Data Register 2"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DITUDRB3,DIT Right Channel User Data Register 3"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "DITUDRB4,DIT Right Channel User Data Register 4"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "DITUDRB5,DIT Right Channel User Data Register 5"
|
|
tree.end
|
|
tree "Transmit Buffer Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "XBUF0,Transmit Buffer Register"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "XBUF1,Transmit Buffer Register"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "XBUF2,Transmit Buffer Register"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "XBUF3,Transmit Buffer Register"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "XBUF4,Transmit Buffer Register"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "XBUF5,Transmit Buffer Register"
|
|
tree.end
|
|
tree "Receive Buffer Registers"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "RBUF0,Receive Buffer Register"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "RBUF1,Receive Buffer Register"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "RBUF2,Receive Buffer Register"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "RBUF3,Receive Buffer Register"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "RBUF4,Receive Buffer Register"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "RBUF5,Receive Buffer Register"
|
|
tree.end
|
|
tree "McASP AFIFO Registers"
|
|
group.long 0x1000++0x3
|
|
line.long 0x00 "WFIFOCTL,Write FIFO Control Register"
|
|
bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x00 "WFIFOSTS,Write FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level"
|
|
group.long 0x1008++0x3
|
|
line.long 0x00 "RFIFOCTL,Read FIFO Control Register"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*")))
|
|
bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)"
|
|
rgroup.long 0x100c++0x3
|
|
line.long 0x00 "RFIFOSTS,Read FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "McASP 5"
|
|
base ad:0x4A1AE000
|
|
width 11.
|
|
tree "General Registers"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REV,Revision Identification Register"
|
|
sif (!cpuis("DRA62*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
|
|
width 18.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWRIDLESYSCONFIG,Power Idle SYSCONFIG"
|
|
endif
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "PFUNC,Pin Function Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "McASP,GPIO"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "McASP,GPIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "McASP,GPIO"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "PDIR,Pin Direction Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "Input,Output"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "Input,Output"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "Input,Output"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "Input,Output"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "Input,Output"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "Input,Output"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "Input,Output"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "Input,Output"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "Input,Output"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "Input,Output"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "Input,Output"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "Input,Output"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "Input,Output"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "Input,Output"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "Input,Output"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "Input,Output"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "Input,Output"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "Input,Output"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "PDOUT,Pin Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR_set/clr ,Drive on AFSR" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR_set/clr ,Drive on AHCLKR" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR_set/clr ,Drive on ACLKR" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX_set/clr ,Drive on AFSX" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX_set/clr ,Drive on AHCLKX" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX_set/clr ,Drive on ACLKX" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE_set/clr ,Drive on AMUTE" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
setclrfld.long 0x00 15. 0x05 15. 0x08 15. " AXR15_set/clr ,Drive on AXR[15]" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR14_set/clr ,Drive on AXR[14]" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR13_set/clr ,Drive on AXR[13]" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR12_set/clr ,Drive on AXR[12]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x05 11. 0x08 11. " AXR11_set/clr ,Drive on AXR[11]" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR10_set/clr ,Drive on AXR[10]" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR9_set/clr ,Drive on AXR[9]" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR8_set/clr ,Drive on AXR[8]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR7_set/clr ,Drive on AXR[7]" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR6_set/clr ,Drive on AXR[6]" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. 0x05 5. 0x08 5. " AXR5_set/clr ,Drive on AXR[5]" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR4_set/clr ,Drive on AXR[4]" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR3_set/clr ,Drive on AXR[3]" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_set/clr ,Drive on AXR[2]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_set/clr ,Drive on AXR[1]" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_set/clr ,Drive on AXR[0]" "Low,High"
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "PDIN,Pin Data Input Register"
|
|
bitfld.long 0x00 31. " AFSR ,AFSR logic level" "Low,High"
|
|
bitfld.long 0x00 30. " AHCLKR ,AHCLKR logic level" "Low,High"
|
|
bitfld.long 0x00 29. " ACLKR ,ACLKR logic level" "Low,High"
|
|
bitfld.long 0x00 28. " AFSX ,AFSX logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AHCLKX ,AHCLKX logic level" "Low,High"
|
|
bitfld.long 0x00 26. " ACLKX ,ACLKX logic level" "Low,High"
|
|
bitfld.long 0x00 25. " AMUTE ,AMUTE logic level" "Low,High"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 15. " AXR15 ,AXR[15] logic level" "Low,High"
|
|
bitfld.long 0x00 14. " AXR14 ,AXR[14] logic level" "Low,High"
|
|
bitfld.long 0x00 13. " AXR13 ,AXR[13] logic level" "Low,High"
|
|
bitfld.long 0x00 12. " AXR12 ,AXR[12] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR11 ,AXR[11] logic level" "Low,High"
|
|
bitfld.long 0x00 10. " AXR10 ,AXR[10] logic level" "Low,High"
|
|
bitfld.long 0x00 9. " AXR9 ,AXR[9] logic level" "Low,High"
|
|
bitfld.long 0x00 8. " AXR8 ,AXR[8] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR7 ,AXR[7] logic level" "Low,High"
|
|
bitfld.long 0x00 6. " AXR6 ,AXR[6] logic level" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " AXR5 ,AXR[5] logic level" "Low,High"
|
|
bitfld.long 0x00 4. " AXR4 ,AXR[4] logic level" "Low,High"
|
|
bitfld.long 0x00 3. " AXR3 ,AXR[3] logic level" "Low,High"
|
|
bitfld.long 0x00 2. " AXR2 ,AXR[2] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1 ,AXR[1] logic level" "Low,High"
|
|
bitfld.long 0x00 0. " AXR0 ,AXR[0] logic level" "Low,High"
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "GBLCTL,Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "AMUTE,Audio Mute Control Register"
|
|
bitfld.long 0x00 12. " XDMAERR ,Transmit DMA Error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDMAERR ,Receive DMA Error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCKFAIL ,Transmit clock failure - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RCKFAIL ,Receive clock failure - AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XSYNCERR ,Transmit frame sync error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RSYNCERR ,Receive frame sync error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XUNDRN ,Transmit underrun error - AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ROVRN ,Receive underrun error - AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AN335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
else
|
|
bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
endif
|
|
bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low"
|
|
bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..."
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "DLBCTL,Digital Loopback Control Register"
|
|
bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..."
|
|
bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even"
|
|
bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "DITCTL,Digital Mode Control Register"
|
|
bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1"
|
|
bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1"
|
|
bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Receive Registers"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "RGBLCTLR,Receiver Global Control Register"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
else
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
endif
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "RXMASK,Receive Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " RXMASK31 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " RXMASK30 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " RXMASK29 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXMASK28 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " RXMASK27 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " RXMASK26 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RXMASK25 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " RXMASK24 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " RXMASK23 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXMASK22 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " RXMASK21 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " RXMASK20 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RXMASK19 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RXMASK18 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " RXMASK17 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXMASK16 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " RXMASK15 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " RXMASK14 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXMASK13 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " RXMASK12 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " RXMASK11 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXMASK10 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " RXMASK9 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " RXMASK8 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXMASK7 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " RXMASK6 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " RXMASK5 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXMASK4 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " RXMASK3 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " RXMASK2 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXMASK1 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " RXMASK0 ,Receive data mask enable" "Masked,Not masked"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "RXFMT,Receive Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0x6c++0x3
|
|
line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select"
|
|
bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "ACLKRCTL,Receive Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal"
|
|
bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "RXTDM,Receive TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " RXTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " RXTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " RXTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " RXTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " RXTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RXTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " RXTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " RXTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " RXTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " RXTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RXTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " RXTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " RXTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " RXTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " RXTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " RXTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " RXTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " RXTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " RXTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " RXTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " RXTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RXTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " RXTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " RXTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "RINTCTL,Receiver Interrupt Control Register"
|
|
bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "RXSTAT,Receiver Status Register"
|
|
bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
else
|
|
bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "RXCLKCHK,Receive Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "REVTCTL,Receiver DMA Event Control Register"
|
|
bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,?..."
|
|
tree.end
|
|
tree "Transmit Registers"
|
|
group.long 0xa0++0x3
|
|
line.long 0x00 "XGBLCTL,Transmitter Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
else
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
endif
|
|
group.long 0xa4++0x3
|
|
line.long 0x00 "TXMASK,Transmit Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " TXMASK31 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " TXMASK30 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " TXMASK29 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXMASK28 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " TXMASK27 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " TXMASK26 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TXMASK25 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " TXMASK24 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " TXMASK23 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXMASK22 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " TXMASK21 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " TXMASK20 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXMASK19 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " TXMASK18 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " TXMASK17 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXMASK16 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " TXMASK15 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " TXMASK14 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TXMASK13 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " TXMASK12 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " TXMASK11 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXMASK10 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " TXMASK9 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " TXMASK8 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXMASK7 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " TXMASK6 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " TXMASK5 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXMASK4 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " TXMASK3 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " TXMASK2 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXMASK1 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " TXMASK0 ,Transmit data mask enable" "Masked,Not masked"
|
|
group.long 0xa8++0x3
|
|
line.long 0x00 "TXFMT,Transmit Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0xac++0x3
|
|
line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select"
|
|
bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ACLKXCTL,Transmit Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio"
|
|
group.long 0xb8++0x3
|
|
line.long 0x00 "TXTDM,Transmit TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " TXTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " TXTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " TXTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " TXTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " TXTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TXTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " TXTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " TXTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " TXTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " TXTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " TXTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " TXTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " TXTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " TXTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TXTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " TXTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " TXTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " TXTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " TXTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " TXTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " TXTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " TXTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " TXTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " TXTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register"
|
|
bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0xc0++0x3
|
|
line.long 0x00 "TXSTAT,Transmitter Status Register"
|
|
eventfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
else
|
|
bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred"
|
|
rgroup.long 0xc4++0x3
|
|
line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))||(cpuis("AM335*")))
|
|
hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
endif
|
|
group.long 0xc8++0x7
|
|
line.long 0x00 "TXCLKCHK,Transmit Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register"
|
|
bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,?..."
|
|
sif (!cpuis("AM335*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CLKADJEN,One-shot Clock Adjust Enable"
|
|
endif
|
|
tree.end
|
|
width 9.
|
|
tree "Serializer Control Registers"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SRCTL0,Serializer Control Register 0"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "SRCTL1,Serializer Control Register 1"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "SRCTL2,Serializer Control Register 2"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SRCTL3,Serializer Control Register 3"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "SRCTL4,Serializer Control Register 4"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "SRCTL5,Serializer Control Register 5"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
else
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
tree.end
|
|
tree "DIT Channel Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DITCSRA0,DIT Left Channel Status Register 0"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DITCSRA1,DIT Left Channel Status Register 1"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DITCSRA2,DIT Left Channel Status Register 2"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DITCSRA3,DIT Left Channel Status Register 3"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DITCSRA4,DIT Left Channel Status Register 4"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DITCSRA5,DIT Left Channel Status Register 5"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DITCSRB0,DIT Right Channel Status Register 0"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DITCSRB1,DIT Right Channel Status Register 1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DITCSRB2,DIT Right Channel Status Register 2"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DITCSRB3,DIT Right Channel Status Register 3"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DITCSRB4,DIT Right Channel Status Register 4"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DITCSRB5,DIT Right Channel Status Register 5"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "DITUDRA0,DIT Left Channel User Data Register 0"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "DITUDRA1,DIT Left Channel User Data Register 1"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "DITUDRA2,DIT Left Channel User Data Register 2"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "DITUDRA3,DIT Left Channel User Data Register 3"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DITUDRA4,DIT Left Channel User Data Register 4"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DITUDRA5,DIT Left Channel User Data Register 5"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DITUDRB0,DIT Right Channel User Data Register 0"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "DITUDRB1,DIT Right Channel User Data Register 1"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "DITUDRB2,DIT Right Channel User Data Register 2"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DITUDRB3,DIT Right Channel User Data Register 3"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "DITUDRB4,DIT Right Channel User Data Register 4"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "DITUDRB5,DIT Right Channel User Data Register 5"
|
|
tree.end
|
|
tree "Transmit Buffer Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "XBUF0,Transmit Buffer Register"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "XBUF1,Transmit Buffer Register"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "XBUF2,Transmit Buffer Register"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "XBUF3,Transmit Buffer Register"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "XBUF4,Transmit Buffer Register"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "XBUF5,Transmit Buffer Register"
|
|
tree.end
|
|
tree "Receive Buffer Registers"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "RBUF0,Receive Buffer Register"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "RBUF1,Receive Buffer Register"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "RBUF2,Receive Buffer Register"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "RBUF3,Receive Buffer Register"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "RBUF4,Receive Buffer Register"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "RBUF5,Receive Buffer Register"
|
|
tree.end
|
|
tree "McASP AFIFO Registers"
|
|
group.long 0x1000++0x3
|
|
line.long 0x00 "WFIFOCTL,Write FIFO Control Register"
|
|
bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x00 "WFIFOSTS,Write FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level"
|
|
group.long 0x1008++0x3
|
|
line.long 0x00 "RFIFOCTL,Read FIFO Control Register"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*")))
|
|
bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)"
|
|
rgroup.long 0x100c++0x3
|
|
line.long 0x00 "RFIFOSTS,Read FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "McBSP (Multichannel Buffered Serial Port)"
|
|
sif (cpuis("DRA62*"))
|
|
base ad:0x47000100
|
|
width 17.
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
base ad:0x47000100-0x100
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REVNB,Revision Number Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SYSCONFIG_REG,System Configuration Register"
|
|
bitfld.long 0x00 9. " CLOCKACTIVITY[9] ,Functional clock" "Switched off,Maintained"
|
|
bitfld.long 0x00 8. " CLOCKACTIVITY[8] ,OCP interface clock" "Switched off,Maintained"
|
|
textline " "
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,Smart-idle Wakeup"
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x00 "EOI,End of Interrupt Register"
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x00 "IRQSTATUS_RAW,Interrupt Status Raw Register"
|
|
bitfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
bitfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "IRQSTATUS,Interrupt Status Register"
|
|
eventfld.long 0x04 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x04 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x04 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x04 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x04 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x04 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x04 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x04 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x04 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x04 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x08 "IRQENABLE_SET,Interrupt Enable Set Register"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x0C 14. " XEMPTYEOF_set/clr ,Transmit buffer empty at end of frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 12. 0x08 12. 0x0C 12. " XOVFLSTAT_set/clr ,Transmit buffer overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " XUNDFLSTAT_set/clr ,Transmit buffer underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 10. 0x08 10. 0x0C 10. " XRDY_set/clr ,Transmit buffer threshold reached interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 9. 0x08 9. 0x0C 9. " XEOF_set/clr ,Transmit end of frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " XFSX_set/clr ,Transmit frame synchronization interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x0C 7. " XSYNCERR_set/clr ,Transmit frame synchronization error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. 0x08 5. 0x0C 5. " ROVFLSTAT_set/clr ,Receive buffer overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " RUNDFLSTAT_set/clr ,Receive buffer underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 3. 0x08 3. 0x0C 3. " RRDY_set/clr ,Receive buffer threshold reached interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 2. 0x08 2. 0x0C 2. " REOF_set/clr ,Receive end of frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x0C 1. " RFSR_set/clr ,Receive frame synchronization interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " RSYNCERR_set/clr ,Receive frame synchronization error interrupt enable" "Disabled,Enabled"
|
|
group.long 0x34++0x7
|
|
line.long 0x00 "DMARXENABLE_SET,DMA Rx Enable Set Register"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " DMARX_ENABLE_SET_set/clr ,Receive DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMATXENABLE_SET,DMA Tx Enable Set Register"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x0C 0. " DMATX_ENABLE_SET_set/clr ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
group.long 0x48++0x7
|
|
line.long 0x00 "DMARXWAKE_EN,DMA Rx Wake Enable Register"
|
|
bitfld.long 0x00 14. " XEMPTYEOF_EN ,Transmit buffer empty at end of frame WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XRDY_EN ,Transmit buffer threshold reached WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XEOF_EN ,Transmit end of frame WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XFSX_EN ,Transmit frame synchronization WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XSYNCERR_EN ,Transmit frame synchronization error WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RRDY_EN ,Receive buffer threshold reached WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " REOF_EN ,Receive end of frame WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RFSR_EN ,Receive frame synchronization WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RSYNCERR_EN ,Receive frame synchronization error WK enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMATXWAKE_EN,DMA Tx Wake Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOF_EN ,Transmit buffer empty at end of frame WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDY_EN ,Transmit buffer threshold reached WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XEOF_EN ,Transmit end of frame WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSX_EN ,Transmit frame synchronization WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XSYNCERR_EN ,Transmit frame synchronization error WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDY_EN ,Receive buffer threshold reached WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " REOF_EN ,Receive end of frame WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSR_EN ,Receive frame synchronization WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " RSYNCERR_EN ,Receive frame synchronization error WK enable" "Disabled,Enabled"
|
|
base ad:0x47000100
|
|
endif
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "DRR_REG,McBSP Data Receive Register"
|
|
in
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "DXR_REG,McBSP Data Transmit Register"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "SPCR2_REG,McBSP Serial Port Control Register 2"
|
|
bitfld.long 0x00 9. " FREE ,Free running mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFT ,Soft Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FRST ,Frame-sync generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 6. " GRST ,Sample-rate generator reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " XINTM ,Transmit interrupt mode" "XRDY,End-of-frame,New frame,XSYNCERR"
|
|
bitfld.long 0x00 3. " XSYNCERR ,Transmit synchronization error" "No error,Error"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
rbitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
else
|
|
bitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " XRST ,Transmitter reset" "Reset,Enabled"
|
|
line.long 0x04 "SPCR1_REG,McBSP Serial Port Control Register 1"
|
|
bitfld.long 0x04 15. " ALB ,Analog loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right-justify and zero-fill MSBs,Right-justify and sign-extend MSBs,Left-justify and zero-fill LSBs,?..."
|
|
textline " "
|
|
bitfld.long 0x04 7. " DXENA ,DX enabler" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RINTM ,Receive interrupt mode" "RRDY,End-of-block/End-of-frame,New frame,RSYNCERR"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RSYNCERR ,Receive synchronization error" "No error,Error"
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
else
|
|
bitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
endif
|
|
bitfld.long 0x04 0. " RRST ,Receiver reset" "Reset,Enabled"
|
|
line.long 0x08 "RCR2_REG,McBSP Receive Control Register 2"
|
|
bitfld.long 0x08 15. " RPHASE ,Receive phases" "Single,Dual"
|
|
hexmask.long.byte 0x08 8.--14. 1. " RFRLEN2 ,Receive frame length 2"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " RWDLEN2 ,Receive word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x08 3.--4. " RREVERSE ,Receive reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x0c "RCR1_REG,McBSP Receive Control Register 1"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RFRLEN1 ,Receive frame length 1"
|
|
bitfld.long 0x0C 5.--7. " RWDLEN1 ,Receive word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
line.long 0x10 "XCR2_REG,McBSP Transmit Control Register 2"
|
|
bitfld.long 0x10 15. " XPHASE ,Transmit phases" "Single,Dual"
|
|
hexmask.long.byte 0x10 8.--14. 1. " XFRLEN2 ,Transmit frame length 2"
|
|
textline " "
|
|
bitfld.long 0x10 5.--7. " XWDLEN2 ,Transmit word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x10 3.--4. " XREVERSE ,Transmit reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x14 "XCR1_REG,McBSP Transmit Control Register 1"
|
|
hexmask.long.byte 0x14 8.--14. 1. " XFRLEN1 ,Transmit frame length 1"
|
|
bitfld.long 0x14 5.--7. " XWDLEN1 ,Transmit word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
if ((((d.l((ad:0x47000100+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x47000100+0x48)))&0x880)==0x0)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,OCP clock"
|
|
else
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x47000100+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x47000100+0x48)))&0x880)==0x800)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,OCP clock"
|
|
else
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x47000100+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x47000100+0x48)))&0x880)==0x880)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x47000100+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x47000100+0x48)))&0x880)==0x80)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x47000100+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x47000100+0x48)))&0x880)==0x0)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,OCP clock"
|
|
else
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x47000100+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x47000100+0x48)))&0x880)==0x80)))
|
|
;CLKSM==1 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x47000100+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x47000100+0x48)))&0x880)==0x800)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,OCP clock"
|
|
else
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
else
|
|
;CLKSM==1 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
endif
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "SRGR1_REG,McBSP SRG Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample rate generator clock divider"
|
|
if (((d.l((ad:0x47000100+0x30)))&0x3)==0x0)
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCR2_REG,McBSP Multi Channel Register 2"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168"))
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 6"
|
|
else
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
endif
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
else
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCR2_REG,McBSP Multi Channel Register 2"
|
|
bitfld.long 0x00 9. " XMCME ,Transmit multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168"))
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 6"
|
|
else
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
endif
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
endif
|
|
if (((d.l((ad:0x47000100+0x34)))&0x1)==0x0)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCR1_REG,McBSP Multi Channel Register 1"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168"))
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 6"
|
|
else
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
endif
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCR1_REG,McBSP Multi Channel Register 1"
|
|
bitfld.long 0x00 9. " RMCME ,Receive multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168"))
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 6"
|
|
else
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
endif
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
endif
|
|
if (d.l((ad:0x47000100+0x34))&0x01)==0x00
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
|
|
elif (d.l((ad:0x47000100+0x34))&0x261)==0x021
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
elif (d.l((ad:0x47000100+0x34))&0x261)==0x041
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
elif (d.l((ad:0x47000100+0x34))&0x261)==0x061
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[111] ,Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[110] ,Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[109] ,Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[108] ,Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[107] ,Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[106] ,Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[105] ,Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[104] ,Receive channel 014 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[103] ,Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[102] ,Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[101] ,Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[100] ,Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[15] ,Receive channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[14] ,Receive channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[13] ,Receive channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[12] ,Receive channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[11] ,Receive channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[10] ,Receive channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[9] ,Receive channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[8] ,Receive channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[7] ,Receive channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[6] ,Receive channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[5] ,Receive channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[4] ,Receive channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[3] ,Receive channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[2] ,Receive channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[1] ,Receive channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[0] ,Receive channel 0 enable" "Disabled,Enabled"
|
|
endif
|
|
if (d.l(ad:0x47000100+0x34)&0x01)==0x00
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
|
|
elif (d.l((ad:0x47000100+0x34))&0x381)==0x081
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " RCERB[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERB[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERB[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERB[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERB[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERB[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERB[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERB[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERB[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERB[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERB[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERB[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERB[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERB[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERB[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERB[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
elif (d.l((ad:0x47000100+0x34))&0x381)==0x101
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " RCERB[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERB[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERB[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERB[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERB[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERB[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERB[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERB[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERB[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERB[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERB[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERB[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERB[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERB[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERB[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERB[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
elif (d.l((ad:0x47000100+0x34))&0x381)==0x181
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " RCERB[127] ,Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERB[126] ,Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERB[125] ,Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERB[124] ,Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERB[123] ,Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERB[122] ,Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERB[121] ,Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERB[120] ,Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERB[119] ,Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERB[118] ,Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERB[117] ,Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERB[116] ,Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERB[115] ,Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERB[114] ,Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERB[113] ,Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERB[112] ,Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " RCERB[31] ,Receive channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERB[30] ,Receive channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERB[29] ,Receive channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERB[28] ,Receive channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERB[27] ,Receive channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERB[26] ,Receive channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERB[25] ,Receive channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERB[24] ,Receive channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERB[23] ,Receive channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERB[22] ,Receive channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERB[21] ,Receive channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERB[20] ,Receive channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERB[19] ,Receive channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERB[18] ,Receive channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERB[17] ,Receive channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERB[16] ,Receive channel 16 enable" "Disabled,Enabled"
|
|
endif
|
|
if (d.l((ad:0x47000100+0x30))&0x03)==0x00
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
|
|
elif ((d.l((ad:0x47000100+0x30))&0x263)==(0x021||0x022))||(((d.l((ad:0x47000100+0x30))&0x3)==0x3)&&((d.l((ad:0x47000100+0x34))&0x060)==0x020))
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " XCERA[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERA[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERA[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERA[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERA[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERA[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERA[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERA[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERA[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERA[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERA[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERA[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERA[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERA[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERA[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERA[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
elif ((d.l((ad:0x47000100+0x30))&0x263)==(0x041||0x042))||(((d.l((ad:0x47000100+0x30))&0x3)==0x3)&&((d.l((ad:0x47000100+0x34))&0x060)==0x040))
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " XCERA[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERA[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERA[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERA[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERA[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERA[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERA[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERA[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERA[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERA[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERA[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERA[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERA[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERA[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERA[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERA[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
elif ((d.l((ad:0x47000100+0x30))&0x263)==(0x061||0x062))||(((d.l((ad:0x47000100+0x30))&0x3)==0x3)&&((d.l((ad:0x47000100+0x34))&0x060)==0x060))
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " XCERA[111] ,Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERA[110] ,Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERA[109] ,Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERA[108] ,Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERA[107] ,Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERA[106] ,Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERA[105] ,Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERA[104] ,Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERA[103] ,Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERA[102] ,Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERA[101] ,Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERA[100] ,Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERA[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERA[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERA[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERA[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " XCERA[15] ,Transmit channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERA[14] ,Transmit channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERA[13] ,Transmit channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERA[12] ,Transmit channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERA[11] ,Transmit channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERA[10] ,Transmit channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERA[9] ,Transmit channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERA[8] ,Transmit channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERA[7] ,Transmit channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERA[6] ,Transmit channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERA[5] ,Transmit channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERA[4] ,Transmit channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERA[3] ,Transmit channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERA[2] ,Transmit channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERA[1] ,Transmit channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERA[0] ,Transmit channel 0 enable" "Disabled,Enabled"
|
|
endif
|
|
if (d.l((ad:0x47000100+0x30))&0x03)==0x00
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition A"
|
|
elif ((d.l((ad:0x47000100+0x30))&0x383)==(0x081||0x082))||(((d.l((ad:0x47000100+0x30))&0x3)==0x3)&&((d.l((ad:0x47000100+0x34))&0x180)==0x080))
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " XCERB[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERB[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERB[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERB[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERB[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERB[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERB[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERB[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERB[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERB[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERB[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERB[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERB[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERB[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERB[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERB[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
elif ((d.l((ad:0x47000100+0x30))&0x383)==(0x101||0x102))||(((d.l((ad:0x47000100+0x30))&0x3)==0x3)&&((d.l((ad:0x47000100+0x34))&0x180)==0x100))
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " XCERB[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERB[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERB[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERB[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERB[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERB[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERB[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERB[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERB[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERB[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERB[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERB[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERB[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERB[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERB[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERB[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
elif ((d.l((ad:0x47000100+0x30))&0x383)==(0x181||0x182))||(((d.l((ad:0x47000100+0x30))&0x3)==0x3)&&((d.l((ad:0x47000100+0x34))&0x180)==0x180))
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " XCERB[127] ,Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERB[126] ,Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERB[125] ,Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERB[124] ,Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERB[123] ,Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERB[122] ,Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERB[121] ,Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERB[120] ,Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERB[119] ,Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERB[118] ,Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERB[117] ,Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERB[116] ,Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERB[115] ,Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERB[114] ,Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERB[113] ,Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERB[112] ,Transmit channel 1126 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " XCERB[31] ,Transmit channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERB[30] ,Transmit channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERB[29] ,Transmit channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERB[28] ,Transmit channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERB[27] ,Transmit channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERB[26] ,Transmit channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERB[25] ,Transmit channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERB[24] ,Transmit channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERB[23] ,Transmit channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERB[22] ,Transmit channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERB[21] ,Transmit channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERB[20] ,Transmit channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERB[19] ,Transmit channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERB[18] ,Transmit channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERB[17] ,Transmit channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERB[16] ,Transmit channel 16 enable" "Disabled,Enabled"
|
|
endif
|
|
if ((((d.l((ad:0x47000100+0x10)))&0x1)==0x0)&&(((d.l((ad:0x47000100+0x14)))&0x1)==0x0)&&(((d.l((ad:0x47000100+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x47000100+0x10)))&0x1)==0x0)&&(((d.l((ad:0x47000100+0x14)))&0x1)==0x0)&&(((d.l((ad:0x47000100+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "CLKXM,CLKRM"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x47000100+0x10)))&0x1)==0x0)&&(((d.l((ad:0x47000100+0x14)))&0x1)==0x1)&&(((d.l((ad:0x47000100+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x47000100+0x10)))&0x1)==0x0)&&(((d.l((ad:0x47000100+0x14)))&0x1)==0x1)&&(((d.l((ad:0x47000100+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "CLKXM,CLKRM"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x47000100+0x10)))&0x1)==0x1)&&(((d.l((ad:0x47000100+0x14)))&0x1)==0x0)&&(((d.l((ad:0x47000100+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x47000100+0x10)))&0x1)==0x1)&&(((d.l((ad:0x47000100+0x14)))&0x1)==0x0)&&(((d.l((ad:0x47000100+0xac)))&0x20)==0x20))
|
|
;xrst==1 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "CLKXM,CLKRM"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x47000100+0x10)))&0x1)==0x1)&&(((d.l((ad:0x47000100+0x14)))&0x1)==0x1)&&(((d.l((ad:0x47000100+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
else
|
|
;xrst==1 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "CLKXM,CLKRM"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
endif
|
|
if ((((d.l((ad:0x47000100+0x34)))&0x201)==0x201))
|
|
group.long 0x4c++0x7
|
|
line.long 0x00 "RCERC_REG,McBSP Receive Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " RCERC[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERC[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERC[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERC[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERC[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERC[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERC[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERC[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERC[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERC[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERC[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERC[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERC[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERC[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERC[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERC[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "RCERD_REG,McBSP Receive Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " RCERD[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERD[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERD[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERD[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERD[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERD[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERD[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERD[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERD[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERD[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERD[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERD[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERD[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERD[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERD[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERD[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x4c++0x7
|
|
hide.long 0x00 "RCERC_REG,McBSP Receive Channel Enable Register Partition C"
|
|
hide.long 0x04 "RCERD_REG,McBSP Receive Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x47000100+0x30)))&0x200)==0x200)&&(((d.l((ad:0x47000100+0x30)))&0x3)!=0x0))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "XCERC_REG,McBSP Transmit Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " XCERC[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERC[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERC[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERC[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERC[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERC[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERC[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERC[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERC[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERC[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERC[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERC[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERC[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERC[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERC[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERC[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "XCERD_REG,McBSP Transmit Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " XCERD[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERD[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERD[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERD[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERD[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERD[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERD[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERD[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERD[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERD[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERD[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERD[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERD[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERD[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERD[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERD[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x54++0x7
|
|
hide.long 0x00 "XCERC_REG,McBSP Transmit Channel Enable Register Partition C"
|
|
hide.long 0x04 "XCERD_REG,McBSP Transmit Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x47000100+0x34)))&0x201)==0x201))
|
|
group.long 0x5c++0x7
|
|
line.long 0x00 "RCERE_REG,McBSP Receive Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " RCERE[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERE[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERE[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERE[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERE[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERE[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERE[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERE[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERE[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERE[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERE[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERE[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERE[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERE[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERE[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERE[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "RCERF_REG,McBSP Receive Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " RCERF[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERF[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERF[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERF[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERF[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERF[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERF[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERF[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERF[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERF[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERF[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERF[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERF[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERF[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERF[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERF[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x5c++0x7
|
|
hide.long 0x00 "RCERE_REG,McBSP Receive Channel Enable Register Partition E"
|
|
hide.long 0x04 "RCERF_REG,McBSP Receive Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x47000100+0x30)))&0x200)==0x200)&&(((d.l((ad:0x47000100+0x30)))&0x3)!=0x0))
|
|
group.long 0x64++0x7
|
|
line.long 0x00 "XCERE_REG,McBSP Transmit Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " XCERE[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERE[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERE[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERE[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERE[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERE[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERE[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERE[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERE[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERE[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERE[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERE[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERE[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERE[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERE[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERE[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "XCERF_REG,McBSP Transmit Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " XCERF[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERF[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERF[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERF[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERF[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERF[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERF[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERF[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERF[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERF[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERF[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERF[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERF[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERF[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERF[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERF[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x64++0x7
|
|
hide.long 0x00 "XCERE_REG,McBSP Transmit Channel Enable Register Partition E"
|
|
hide.long 0x04 "XCERF_REG,McBSP Transmit Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x47000100+0x34)))&0x201)==0x201))
|
|
group.long 0x6c++0x7
|
|
line.long 0x00 "RCERG_REG,McBSP Receive Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " RCERG[111] ,Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERG[110] ,Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERG[109] ,Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERG[108] ,Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERG[107] ,Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERG[106] ,Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERG[105] ,Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERG[104] ,Receive channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERG[103] ,Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERG[102] ,Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERG[101] ,Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERG[100] ,Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERG[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERG[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERG[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERG[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "RCERH_REG,McBSP Receive Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " RCERH[127] ,Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERH[126] ,Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERH[125] ,Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERH[124] ,Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERH[123] ,Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERH[122] ,Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERH[121] ,Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERH[120] ,Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERH[119] ,Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERH[118] ,Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERH[117] ,Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERH[116] ,Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERH[115] ,Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERH[114] ,Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERH[113] ,Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERH[112] ,Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x6c++0x7
|
|
hide.long 0x00 "RCERG_REG,McBSP Receive Channel Enable Register Partition G"
|
|
hide.long 0x04 "RCERH_REG,McBSP Receive Channel Enable Register Partition H"
|
|
endif
|
|
if ((((d.l((ad:0x47000100+0x30)))&0x200)==0x200)&&(((d.l((ad:0x47000100+0x30)))&0x3)!=0x0))
|
|
group.long 0x74++0x7
|
|
line.long 0x00 "XCERG_REG,McBSP Transmit Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " XCERG[111] ,Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERG[110] ,Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERG[109] ,Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERG[108] ,Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERG[107] ,Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERG[106] ,Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERG[105] ,Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERG[104] ,Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERG[103] ,Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERG[102] ,Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERG[101] ,Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERG[100] ,Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERG[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERG[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERG[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERG[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "XCERH_REG,McBSP Transmit Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " XCERH[127] ,Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERH[126] ,Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERH[125] ,Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERH[124] ,Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERH[123] ,Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERH[122] ,Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERH[121] ,Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERH[120] ,Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERH[119] ,Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERH[118] ,Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERH[117] ,Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERH[116] ,Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERH[115] ,Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERH[114] ,Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERH[113] ,Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERH[112] ,Transmit channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x74++0x7
|
|
hide.long 0x00 "XCERG_REG,McBSP Transmit Channel Enable Register Partition G"
|
|
hide.long 0x04 "XCERH_REG,McBSP Transmit Channel Enable Register Partition H"
|
|
endif
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "THRSH2_REG,McBSP Transmit Buffer Threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x04 "THRSH1_REG,McBSP Receive Buffer Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
else
|
|
rgroup.long 0x7c++0x03
|
|
line.long 0x00 "REV_REG,McBSP Revision Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision number"
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "RINTCLR_REG,McBSP Receive Interrupt Clear"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "XINTCLR_REG,McBSP Transmit Interrupt Clear"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "ROVFLCLR_REG,McBSP Receive Overflow Interrupt Clear"
|
|
in
|
|
group.long 0x8c++0xb
|
|
line.long 0x00 "SYSCONFIG_REG,McBSP System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity (McBSPi_ICLK/PRCM)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
line.long 0x04 "THRSH2_REG,McBSP Transmit Buffer Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x08 "THRSH1_REG,McBSP Receive Buffer Threshold"
|
|
hexmask.long.word 0x08 0.--11. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
endif
|
|
group.long 0xa0++0x13
|
|
line.long 0x00 "IRQSTATUS_REG,McBSP Interrupt Status Register"
|
|
eventfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "IRQENABLE_REG,McBSP Interrupt Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " XOVFLEN ,Transmit buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " XUNDFLEN ,Transmit buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDYEN ,Transmit buffer threshold reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " XEOFEN ,Transmit end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSXEN ,Transmit frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " XSYNCERREN ,Transmit frame synchronization error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ROVFLEN ,Receive buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RUNDFLEN ,Receive buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDYEN ,Receive buffer threshold enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REOFEN ,Receive end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSREN ,Receive frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RSYNCERREN ,Receive frame synchronization error enable" "Disabled,Enabled"
|
|
line.long 0x08 "WAKEUPEN_REG,McBSP Wakeup Enable Register"
|
|
bitfld.long 0x08 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 10. " XRDYEN ,Transmit buffer threshold reached WK enable" "Not active,Active"
|
|
bitfld.long 0x08 9. " XEOFEN ,Transmit end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XFSXEN ,Transmit frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 7. " XSYNCERREN ,Transmit frame synchronization error WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDYEN ,Receive buffer threshold wakeup enable" "Not active,Active"
|
|
bitfld.long 0x08 2. " REOFEN ,Receive end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSREN ,Receive frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 0. " RSYNCERREN ,Receive frame synchronization error WK enable" "Not active,Active"
|
|
line.long 0x0c "XCCR_REG,McBSP Transmit Configuration Control Register"
|
|
bitfld.long 0x0C 15. " EXTCLKGATE ,External clock gating enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PPCONNECT ,Pair to pair connection" "No connection,Connection"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "8 ns,14 ns,20 ns,28 ns"
|
|
else
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "18 ns,26 ns,35 ns,42 ns"
|
|
endif
|
|
bitfld.long 0x0C 11. " XFULL_CYCLE ,Transmit full cycle mode" "Half-cycle,Full-cycle"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DLB ,Digital loop-back" "No DLB,DLB"
|
|
bitfld.long 0x0C 3. " XDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " XDISABLE ,Transmit disable" "Not stopped,Stopped"
|
|
line.long 0x10 "RCCR_REG,McBSP Receive Configuration Control Register"
|
|
bitfld.long 0x10 11. " RFULL_CYCLE ,Receive full cycle mode" "Half-cycle,Full-cycle"
|
|
bitfld.long 0x10 3. " RDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " RDISABLE ,Receive disable" "Not stopped,Stopped"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "XBUFFSTAT_REG,McBSP Transmit Buffer Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "RBUFFSTAT_REG,McBSP Receive Buffer Status"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RBUFFSTAT ,Receive buffer status"
|
|
else
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "XBUFFSTAT_REG,McBSP Transmit Buffer Status"
|
|
hexmask.long.word 0x00 0.--10. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "RBUFFSTAT_REG,McBSP Receive Buffer Status"
|
|
hexmask.long.word 0x04 0.--10. 1. " RBUFFSTAT ,Receive buffer status"
|
|
endif
|
|
rgroup.long 0xc0++0x3
|
|
line.long 0x00 "STATUS_REG,McBSP Status Register"
|
|
bitfld.long 0x00 0. " CLKMUXSTATUS ,Response to a different register access delayed" "Not delayed,Delayed"
|
|
width 11.
|
|
else
|
|
base ad:0x47000000
|
|
width 17.
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
base ad:0x47000000-0x100
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REVNB,Revision Number Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SYSCONFIG_REG,System Configuration Register"
|
|
bitfld.long 0x00 9. " CLOCKACTIVITY[9] ,Functional clock" "Switched off,Maintained"
|
|
bitfld.long 0x00 8. " CLOCKACTIVITY[8] ,OCP interface clock" "Switched off,Maintained"
|
|
textline " "
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,Smart-idle Wakeup"
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x00 "EOI,End of Interrupt Register"
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x00 "IRQSTATUS_RAW,Interrupt Status Raw Register"
|
|
bitfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
bitfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "IRQSTATUS,Interrupt Status Register"
|
|
eventfld.long 0x04 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x04 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x04 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x04 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x04 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x04 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x04 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x04 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x04 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x04 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x08 "IRQENABLE_SET,Interrupt Enable Set Register"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x0C 14. " XEMPTYEOF_set/clr ,Transmit buffer empty at end of frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 12. 0x08 12. 0x0C 12. " XOVFLSTAT_set/clr ,Transmit buffer overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " XUNDFLSTAT_set/clr ,Transmit buffer underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 10. 0x08 10. 0x0C 10. " XRDY_set/clr ,Transmit buffer threshold reached interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 9. 0x08 9. 0x0C 9. " XEOF_set/clr ,Transmit end of frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " XFSX_set/clr ,Transmit frame synchronization interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x0C 7. " XSYNCERR_set/clr ,Transmit frame synchronization error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. 0x08 5. 0x0C 5. " ROVFLSTAT_set/clr ,Receive buffer overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " RUNDFLSTAT_set/clr ,Receive buffer underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 3. 0x08 3. 0x0C 3. " RRDY_set/clr ,Receive buffer threshold reached interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 2. 0x08 2. 0x0C 2. " REOF_set/clr ,Receive end of frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x0C 1. " RFSR_set/clr ,Receive frame synchronization interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " RSYNCERR_set/clr ,Receive frame synchronization error interrupt enable" "Disabled,Enabled"
|
|
group.long 0x34++0x7
|
|
line.long 0x00 "DMARXENABLE_SET,DMA Rx Enable Set Register"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " DMARX_ENABLE_SET_set/clr ,Receive DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMATXENABLE_SET,DMA Tx Enable Set Register"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x0C 0. " DMATX_ENABLE_SET_set/clr ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
group.long 0x48++0x7
|
|
line.long 0x00 "DMARXWAKE_EN,DMA Rx Wake Enable Register"
|
|
bitfld.long 0x00 14. " XEMPTYEOF_EN ,Transmit buffer empty at end of frame WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XRDY_EN ,Transmit buffer threshold reached WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XEOF_EN ,Transmit end of frame WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XFSX_EN ,Transmit frame synchronization WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XSYNCERR_EN ,Transmit frame synchronization error WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RRDY_EN ,Receive buffer threshold reached WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " REOF_EN ,Receive end of frame WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RFSR_EN ,Receive frame synchronization WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RSYNCERR_EN ,Receive frame synchronization error WK enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMATXWAKE_EN,DMA Tx Wake Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOF_EN ,Transmit buffer empty at end of frame WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDY_EN ,Transmit buffer threshold reached WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XEOF_EN ,Transmit end of frame WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSX_EN ,Transmit frame synchronization WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XSYNCERR_EN ,Transmit frame synchronization error WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDY_EN ,Receive buffer threshold reached WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " REOF_EN ,Receive end of frame WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSR_EN ,Receive frame synchronization WK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " RSYNCERR_EN ,Receive frame synchronization error WK enable" "Disabled,Enabled"
|
|
base ad:0x47000000
|
|
endif
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "DRR_REG,McBSP Data Receive Register"
|
|
in
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "DXR_REG,McBSP Data Transmit Register"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "SPCR2_REG,McBSP Serial Port Control Register 2"
|
|
bitfld.long 0x00 9. " FREE ,Free running mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFT ,Soft Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FRST ,Frame-sync generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 6. " GRST ,Sample-rate generator reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " XINTM ,Transmit interrupt mode" "XRDY,End-of-frame,New frame,XSYNCERR"
|
|
bitfld.long 0x00 3. " XSYNCERR ,Transmit synchronization error" "No error,Error"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
rbitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
else
|
|
bitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " XRST ,Transmitter reset" "Reset,Enabled"
|
|
line.long 0x04 "SPCR1_REG,McBSP Serial Port Control Register 1"
|
|
bitfld.long 0x04 15. " ALB ,Analog loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right-justify and zero-fill MSBs,Right-justify and sign-extend MSBs,Left-justify and zero-fill LSBs,?..."
|
|
textline " "
|
|
bitfld.long 0x04 7. " DXENA ,DX enabler" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RINTM ,Receive interrupt mode" "RRDY,End-of-block/End-of-frame,New frame,RSYNCERR"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RSYNCERR ,Receive synchronization error" "No error,Error"
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
else
|
|
bitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
endif
|
|
bitfld.long 0x04 0. " RRST ,Receiver reset" "Reset,Enabled"
|
|
line.long 0x08 "RCR2_REG,McBSP Receive Control Register 2"
|
|
bitfld.long 0x08 15. " RPHASE ,Receive phases" "Single,Dual"
|
|
hexmask.long.byte 0x08 8.--14. 1. " RFRLEN2 ,Receive frame length 2"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " RWDLEN2 ,Receive word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x08 3.--4. " RREVERSE ,Receive reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x0c "RCR1_REG,McBSP Receive Control Register 1"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RFRLEN1 ,Receive frame length 1"
|
|
bitfld.long 0x0C 5.--7. " RWDLEN1 ,Receive word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
line.long 0x10 "XCR2_REG,McBSP Transmit Control Register 2"
|
|
bitfld.long 0x10 15. " XPHASE ,Transmit phases" "Single,Dual"
|
|
hexmask.long.byte 0x10 8.--14. 1. " XFRLEN2 ,Transmit frame length 2"
|
|
textline " "
|
|
bitfld.long 0x10 5.--7. " XWDLEN2 ,Transmit word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x10 3.--4. " XREVERSE ,Transmit reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x14 "XCR1_REG,McBSP Transmit Control Register 1"
|
|
hexmask.long.byte 0x14 8.--14. 1. " XFRLEN1 ,Transmit frame length 1"
|
|
bitfld.long 0x14 5.--7. " XWDLEN1 ,Transmit word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
if ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x0)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,OCP clock"
|
|
else
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x800)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,OCP clock"
|
|
else
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x880)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x80)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x0)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,OCP clock"
|
|
else
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x80)))
|
|
;CLKSM==1 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x800)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,OCP clock"
|
|
else
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
else
|
|
;CLKSM==1 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
endif
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "SRGR1_REG,McBSP SRG Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample rate generator clock divider"
|
|
if (((d.l((ad:0x47000000+0x30)))&0x3)==0x0)
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCR2_REG,McBSP Multi Channel Register 2"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168"))
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 6"
|
|
else
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
endif
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
else
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCR2_REG,McBSP Multi Channel Register 2"
|
|
bitfld.long 0x00 9. " XMCME ,Transmit multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168"))
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 6"
|
|
else
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
endif
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
endif
|
|
if (((d.l((ad:0x47000000+0x34)))&0x1)==0x0)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCR1_REG,McBSP Multi Channel Register 1"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168"))
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 6"
|
|
else
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
endif
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCR1_REG,McBSP Multi Channel Register 1"
|
|
bitfld.long 0x00 9. " RMCME ,Receive multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168"))
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 6"
|
|
else
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
endif
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
endif
|
|
if (d.l((ad:0x47000000+0x34))&0x01)==0x00
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
|
|
elif (d.l((ad:0x47000000+0x34))&0x261)==0x021
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
elif (d.l((ad:0x47000000+0x34))&0x261)==0x041
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
elif (d.l((ad:0x47000000+0x34))&0x261)==0x061
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[111] ,Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[110] ,Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[109] ,Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[108] ,Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[107] ,Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[106] ,Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[105] ,Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[104] ,Receive channel 014 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[103] ,Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[102] ,Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[101] ,Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[100] ,Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[15] ,Receive channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[14] ,Receive channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[13] ,Receive channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[12] ,Receive channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[11] ,Receive channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[10] ,Receive channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[9] ,Receive channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[8] ,Receive channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[7] ,Receive channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[6] ,Receive channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[5] ,Receive channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[4] ,Receive channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[3] ,Receive channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[2] ,Receive channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[1] ,Receive channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[0] ,Receive channel 0 enable" "Disabled,Enabled"
|
|
endif
|
|
if (d.l(ad:0x47000000+0x34)&0x01)==0x00
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
|
|
elif (d.l((ad:0x47000000+0x34))&0x381)==0x081
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " RCERB[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERB[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERB[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERB[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERB[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERB[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERB[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERB[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERB[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERB[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERB[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERB[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERB[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERB[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERB[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERB[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
elif (d.l((ad:0x47000000+0x34))&0x381)==0x101
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " RCERB[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERB[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERB[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERB[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERB[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERB[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERB[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERB[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERB[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERB[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERB[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERB[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERB[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERB[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERB[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERB[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
elif (d.l((ad:0x47000000+0x34))&0x381)==0x181
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " RCERB[127] ,Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERB[126] ,Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERB[125] ,Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERB[124] ,Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERB[123] ,Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERB[122] ,Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERB[121] ,Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERB[120] ,Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERB[119] ,Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERB[118] ,Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERB[117] ,Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERB[116] ,Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERB[115] ,Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERB[114] ,Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERB[113] ,Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERB[112] ,Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " RCERB[31] ,Receive channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERB[30] ,Receive channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERB[29] ,Receive channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERB[28] ,Receive channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERB[27] ,Receive channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERB[26] ,Receive channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERB[25] ,Receive channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERB[24] ,Receive channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERB[23] ,Receive channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERB[22] ,Receive channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERB[21] ,Receive channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERB[20] ,Receive channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERB[19] ,Receive channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERB[18] ,Receive channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERB[17] ,Receive channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERB[16] ,Receive channel 16 enable" "Disabled,Enabled"
|
|
endif
|
|
if (d.l((ad:0x47000000+0x30))&0x03)==0x00
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
|
|
elif ((d.l((ad:0x47000000+0x30))&0x263)==(0x021||0x022))||(((d.l((ad:0x47000000+0x30))&0x3)==0x3)&&((d.l((ad:0x47000000+0x34))&0x060)==0x020))
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " XCERA[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERA[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERA[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERA[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERA[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERA[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERA[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERA[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERA[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERA[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERA[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERA[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERA[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERA[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERA[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERA[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
elif ((d.l((ad:0x47000000+0x30))&0x263)==(0x041||0x042))||(((d.l((ad:0x47000000+0x30))&0x3)==0x3)&&((d.l((ad:0x47000000+0x34))&0x060)==0x040))
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " XCERA[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERA[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERA[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERA[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERA[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERA[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERA[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERA[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERA[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERA[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERA[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERA[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERA[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERA[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERA[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERA[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
elif ((d.l((ad:0x47000000+0x30))&0x263)==(0x061||0x062))||(((d.l((ad:0x47000000+0x30))&0x3)==0x3)&&((d.l((ad:0x47000000+0x34))&0x060)==0x060))
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " XCERA[111] ,Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERA[110] ,Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERA[109] ,Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERA[108] ,Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERA[107] ,Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERA[106] ,Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERA[105] ,Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERA[104] ,Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERA[103] ,Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERA[102] ,Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERA[101] ,Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERA[100] ,Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERA[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERA[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERA[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERA[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " XCERA[15] ,Transmit channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERA[14] ,Transmit channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERA[13] ,Transmit channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERA[12] ,Transmit channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERA[11] ,Transmit channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERA[10] ,Transmit channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERA[9] ,Transmit channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERA[8] ,Transmit channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERA[7] ,Transmit channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERA[6] ,Transmit channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERA[5] ,Transmit channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERA[4] ,Transmit channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERA[3] ,Transmit channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERA[2] ,Transmit channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERA[1] ,Transmit channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERA[0] ,Transmit channel 0 enable" "Disabled,Enabled"
|
|
endif
|
|
if (d.l((ad:0x47000000+0x30))&0x03)==0x00
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition A"
|
|
elif ((d.l((ad:0x47000000+0x30))&0x383)==(0x081||0x082))||(((d.l((ad:0x47000000+0x30))&0x3)==0x3)&&((d.l((ad:0x47000000+0x34))&0x180)==0x080))
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " XCERB[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERB[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERB[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERB[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERB[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERB[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERB[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERB[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERB[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERB[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERB[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERB[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERB[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERB[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERB[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERB[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
elif ((d.l((ad:0x47000000+0x30))&0x383)==(0x101||0x102))||(((d.l((ad:0x47000000+0x30))&0x3)==0x3)&&((d.l((ad:0x47000000+0x34))&0x180)==0x100))
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " XCERB[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERB[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERB[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERB[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERB[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERB[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERB[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERB[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERB[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERB[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERB[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERB[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERB[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERB[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERB[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERB[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
elif ((d.l((ad:0x47000000+0x30))&0x383)==(0x181||0x182))||(((d.l((ad:0x47000000+0x30))&0x3)==0x3)&&((d.l((ad:0x47000000+0x34))&0x180)==0x180))
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " XCERB[127] ,Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERB[126] ,Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERB[125] ,Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERB[124] ,Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERB[123] ,Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERB[122] ,Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERB[121] ,Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERB[120] ,Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERB[119] ,Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERB[118] ,Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERB[117] ,Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERB[116] ,Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERB[115] ,Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERB[114] ,Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERB[113] ,Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERB[112] ,Transmit channel 1126 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x00 15. " XCERB[31] ,Transmit channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERB[30] ,Transmit channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERB[29] ,Transmit channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERB[28] ,Transmit channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERB[27] ,Transmit channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERB[26] ,Transmit channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERB[25] ,Transmit channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERB[24] ,Transmit channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERB[23] ,Transmit channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERB[22] ,Transmit channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERB[21] ,Transmit channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERB[20] ,Transmit channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERB[19] ,Transmit channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERB[18] ,Transmit channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERB[17] ,Transmit channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERB[16] ,Transmit channel 16 enable" "Disabled,Enabled"
|
|
endif
|
|
if ((((d.l((ad:0x47000000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x47000000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "CLKXM,CLKRM"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x47000000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x47000000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "CLKXM,CLKRM"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x47000000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x47000000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x20))
|
|
;xrst==1 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "CLKXM,CLKRM"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x47000000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
|
|
else
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
else
|
|
;xrst==1 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "CLKXM,CLKRM"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
sif (cpuis("DRA62*"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
endif
|
|
if ((((d.l((ad:0x47000000+0x34)))&0x201)==0x201))
|
|
group.long 0x4c++0x7
|
|
line.long 0x00 "RCERC_REG,McBSP Receive Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " RCERC[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERC[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERC[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERC[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERC[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERC[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERC[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERC[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERC[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERC[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERC[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERC[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERC[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERC[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERC[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERC[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "RCERD_REG,McBSP Receive Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " RCERD[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERD[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERD[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERD[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERD[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERD[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERD[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERD[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERD[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERD[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERD[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERD[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERD[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERD[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERD[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERD[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x4c++0x7
|
|
hide.long 0x00 "RCERC_REG,McBSP Receive Channel Enable Register Partition C"
|
|
hide.long 0x04 "RCERD_REG,McBSP Receive Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x47000000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x47000000+0x30)))&0x3)!=0x0))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "XCERC_REG,McBSP Transmit Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " XCERC[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERC[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERC[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERC[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERC[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERC[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERC[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERC[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERC[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERC[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERC[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERC[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERC[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERC[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERC[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERC[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "XCERD_REG,McBSP Transmit Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " XCERD[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERD[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERD[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERD[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERD[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERD[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERD[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERD[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERD[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERD[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERD[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERD[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERD[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERD[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERD[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERD[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x54++0x7
|
|
hide.long 0x00 "XCERC_REG,McBSP Transmit Channel Enable Register Partition C"
|
|
hide.long 0x04 "XCERD_REG,McBSP Transmit Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x47000000+0x34)))&0x201)==0x201))
|
|
group.long 0x5c++0x7
|
|
line.long 0x00 "RCERE_REG,McBSP Receive Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " RCERE[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERE[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERE[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERE[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERE[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERE[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERE[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERE[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERE[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERE[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERE[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERE[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERE[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERE[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERE[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERE[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "RCERF_REG,McBSP Receive Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " RCERF[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERF[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERF[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERF[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERF[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERF[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERF[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERF[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERF[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERF[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERF[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERF[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERF[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERF[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERF[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERF[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x5c++0x7
|
|
hide.long 0x00 "RCERE_REG,McBSP Receive Channel Enable Register Partition E"
|
|
hide.long 0x04 "RCERF_REG,McBSP Receive Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x47000000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x47000000+0x30)))&0x3)!=0x0))
|
|
group.long 0x64++0x7
|
|
line.long 0x00 "XCERE_REG,McBSP Transmit Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " XCERE[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERE[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERE[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERE[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERE[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERE[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERE[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERE[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERE[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERE[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERE[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERE[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERE[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERE[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERE[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERE[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "XCERF_REG,McBSP Transmit Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " XCERF[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERF[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERF[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERF[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERF[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERF[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERF[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERF[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERF[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERF[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERF[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERF[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERF[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERF[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERF[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERF[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x64++0x7
|
|
hide.long 0x00 "XCERE_REG,McBSP Transmit Channel Enable Register Partition E"
|
|
hide.long 0x04 "XCERF_REG,McBSP Transmit Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x47000000+0x34)))&0x201)==0x201))
|
|
group.long 0x6c++0x7
|
|
line.long 0x00 "RCERG_REG,McBSP Receive Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " RCERG[111] ,Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERG[110] ,Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERG[109] ,Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERG[108] ,Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERG[107] ,Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERG[106] ,Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERG[105] ,Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERG[104] ,Receive channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERG[103] ,Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERG[102] ,Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERG[101] ,Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERG[100] ,Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERG[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERG[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERG[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERG[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "RCERH_REG,McBSP Receive Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " RCERH[127] ,Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERH[126] ,Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERH[125] ,Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERH[124] ,Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERH[123] ,Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERH[122] ,Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERH[121] ,Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERH[120] ,Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERH[119] ,Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERH[118] ,Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERH[117] ,Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERH[116] ,Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERH[115] ,Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERH[114] ,Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERH[113] ,Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERH[112] ,Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x6c++0x7
|
|
hide.long 0x00 "RCERG_REG,McBSP Receive Channel Enable Register Partition G"
|
|
hide.long 0x04 "RCERH_REG,McBSP Receive Channel Enable Register Partition H"
|
|
endif
|
|
if ((((d.l((ad:0x47000000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x47000000+0x30)))&0x3)!=0x0))
|
|
group.long 0x74++0x7
|
|
line.long 0x00 "XCERG_REG,McBSP Transmit Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " XCERG[111] ,Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERG[110] ,Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERG[109] ,Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERG[108] ,Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERG[107] ,Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERG[106] ,Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERG[105] ,Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERG[104] ,Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERG[103] ,Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERG[102] ,Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERG[101] ,Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERG[100] ,Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERG[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERG[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERG[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERG[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "XCERH_REG,McBSP Transmit Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " XCERH[127] ,Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERH[126] ,Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERH[125] ,Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERH[124] ,Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERH[123] ,Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERH[122] ,Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERH[121] ,Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERH[120] ,Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERH[119] ,Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERH[118] ,Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERH[117] ,Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERH[116] ,Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERH[115] ,Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERH[114] ,Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERH[113] ,Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERH[112] ,Transmit channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x74++0x7
|
|
hide.long 0x00 "XCERG_REG,McBSP Transmit Channel Enable Register Partition G"
|
|
hide.long 0x04 "XCERH_REG,McBSP Transmit Channel Enable Register Partition H"
|
|
endif
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "THRSH2_REG,McBSP Transmit Buffer Threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x04 "THRSH1_REG,McBSP Receive Buffer Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
else
|
|
rgroup.long 0x7c++0x03
|
|
line.long 0x00 "REV_REG,McBSP Revision Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision number"
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "RINTCLR_REG,McBSP Receive Interrupt Clear"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "XINTCLR_REG,McBSP Transmit Interrupt Clear"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "ROVFLCLR_REG,McBSP Receive Overflow Interrupt Clear"
|
|
in
|
|
group.long 0x8c++0xb
|
|
line.long 0x00 "SYSCONFIG_REG,McBSP System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity (McBSPi_ICLK/PRCM)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
line.long 0x04 "THRSH2_REG,McBSP Transmit Buffer Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x08 "THRSH1_REG,McBSP Receive Buffer Threshold"
|
|
hexmask.long.word 0x08 0.--11. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
endif
|
|
group.long 0xa0++0x13
|
|
line.long 0x00 "IRQSTATUS_REG,McBSP Interrupt Status Register"
|
|
eventfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "IRQENABLE_REG,McBSP Interrupt Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " XOVFLEN ,Transmit buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " XUNDFLEN ,Transmit buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDYEN ,Transmit buffer threshold reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " XEOFEN ,Transmit end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSXEN ,Transmit frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " XSYNCERREN ,Transmit frame synchronization error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ROVFLEN ,Receive buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RUNDFLEN ,Receive buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDYEN ,Receive buffer threshold enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REOFEN ,Receive end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSREN ,Receive frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RSYNCERREN ,Receive frame synchronization error enable" "Disabled,Enabled"
|
|
line.long 0x08 "WAKEUPEN_REG,McBSP Wakeup Enable Register"
|
|
bitfld.long 0x08 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 10. " XRDYEN ,Transmit buffer threshold reached WK enable" "Not active,Active"
|
|
bitfld.long 0x08 9. " XEOFEN ,Transmit end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XFSXEN ,Transmit frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 7. " XSYNCERREN ,Transmit frame synchronization error WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDYEN ,Receive buffer threshold wakeup enable" "Not active,Active"
|
|
bitfld.long 0x08 2. " REOFEN ,Receive end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSREN ,Receive frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 0. " RSYNCERREN ,Receive frame synchronization error WK enable" "Not active,Active"
|
|
line.long 0x0c "XCCR_REG,McBSP Transmit Configuration Control Register"
|
|
bitfld.long 0x0C 15. " EXTCLKGATE ,External clock gating enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PPCONNECT ,Pair to pair connection" "No connection,Connection"
|
|
textline " "
|
|
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "8 ns,14 ns,20 ns,28 ns"
|
|
else
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "18 ns,26 ns,35 ns,42 ns"
|
|
endif
|
|
bitfld.long 0x0C 11. " XFULL_CYCLE ,Transmit full cycle mode" "Half-cycle,Full-cycle"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DLB ,Digital loop-back" "No DLB,DLB"
|
|
bitfld.long 0x0C 3. " XDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " XDISABLE ,Transmit disable" "Not stopped,Stopped"
|
|
line.long 0x10 "RCCR_REG,McBSP Receive Configuration Control Register"
|
|
bitfld.long 0x10 11. " RFULL_CYCLE ,Receive full cycle mode" "Half-cycle,Full-cycle"
|
|
bitfld.long 0x10 3. " RDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " RDISABLE ,Receive disable" "Not stopped,Stopped"
|
|
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "XBUFFSTAT_REG,McBSP Transmit Buffer Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "RBUFFSTAT_REG,McBSP Receive Buffer Status"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RBUFFSTAT ,Receive buffer status"
|
|
else
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "XBUFFSTAT_REG,McBSP Transmit Buffer Status"
|
|
hexmask.long.word 0x00 0.--10. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "RBUFFSTAT_REG,McBSP Receive Buffer Status"
|
|
hexmask.long.word 0x04 0.--10. 1. " RBUFFSTAT ,Receive buffer status"
|
|
endif
|
|
rgroup.long 0xc0++0x3
|
|
line.long 0x00 "STATUS_REG,McBSP Status Register"
|
|
bitfld.long 0x00 0. " CLKMUXSTATUS ,Response to a different register access delayed" "Not delayed,Delayed"
|
|
width 11.
|
|
endif
|
|
tree.end
|
|
sif (cpuis("DRA6*"))
|
|
tree "MLB (Media Local Bus)"
|
|
base ad:0x4A180000
|
|
width 10.
|
|
rgroup.long 0x00++0x03 "Top Level Registers"
|
|
line.long 0x00 "MLBSSREV,MLBSS HL0.8 Compliant Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Uses Current scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,FUNC is assigned 0xA088 for MLB IP"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL release version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MLBSSPWR,MLBSS Power management Register"
|
|
bitfld.long 0x00 0. " MSTANDBY ,MStandby bus of the power management interface" "Not asserted,Asserted"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MLBSSPRF,MLBSS Performance Register"
|
|
bitfld.long 0x00 16. " WRNP ,Writes issued by DMA OCP non-posted" "Posted,Non-posted"
|
|
bitfld.long 0x00 12.--14. " ASYNC_PRI ,Asynchronous priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 8.--10. " SYNC_PRI ,Synchronous priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--5. " ASYNC_FLAG ,Asynchronous flag priority on chip network" "Lowest,Medium,Reserved,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SYNC_FLAG ,Synchronous flag priority on chip network" "Lowest,Medium,Reserved,Highest"
|
|
group.long 0x400++0x03 "MediaLB Registers"
|
|
line.long 0x00 "MLBC0,MediaLB Control 0 Register"
|
|
bitfld.long 0x00 15.--17. " FCNT ,Number of frames per sub-buffer for synchronous channels" "1,2,4,8,16,32,64,?..."
|
|
bitfld.long 0x00 14. " CTLRETRY ,Control Tx packet retry" "Skipped,Re-transmitted"
|
|
bitfld.long 0x00 12. " ASYRETRY ,Asynchronous Tx packet retry" "Skipped,Re-transmitted"
|
|
bitfld.long 0x00 7. " MLBLK ,MLBLK MediaLB lock status" "Set,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MLBPEN ,MLBPEN MediaLB 6-pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " MLBCLK ,MediaLB clock speed select" "256*Fs,512*Fs,1024*Fs,2048*Fs,?..."
|
|
bitfld.long 0x00 0. " MLBEN ,MLBEN MediaLB enable" "Disabled,Enabled"
|
|
group.long 0x408++0x7
|
|
line.long 0x00 "MLBPC0,MediaLB 6-pin Control 0 Register"
|
|
bitfld.long 0x00 11. " MCLKHYS ,MCLKHYS MediaLB (6-pin) hysteresis enable" "Disabled,Enabled"
|
|
line.long 0x04 "MS0,MediaLB Channel Status 0 Register"
|
|
bitfld.long 0x04 31. " MCS[31] ,MCS[31] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 30. " MCS[30] ,MCS[30] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 29. " MCS[29] ,MCS[29] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 28. " MCS[28] ,MCS[28] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MCS[27] ,MCS[27] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 26. " MCS[26] ,MCS[26] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 25. " MCS[25] ,MCS[25] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 24. " MCS[24] ,MCS[24] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x04 23. " MCS[23] ,MCS[23] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 22. " MCS[22] ,MCS[22] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 21. " MCS[21] ,MCS[21] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 20. " MCS[20] ,MCS[20] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MCS[19] ,MCS[19] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 18. " MCS[18] ,MCS[18] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 17. " MCS[17] ,MCS[17] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 16. " MCS[16] ,MCS[16] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MCS[15] ,MCS[15] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 14. " MCS[14] ,MCS[14] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 13. " MCS[13] ,MCS[13] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 12. " MCS[12] ,MCS[12] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " MCS[11] ,MCS[11] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 10. " MCS[10] ,MCS[10] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 9. " MCS[9] ,MCS[9] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 8. " MCS[8] ,MCS[8] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MCS[7] ,MCS[7] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 6. " MCS[6] ,MCS[6] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 5. " MCS[5] ,MCS[5] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 4. " MCS[4] ,MCS[4] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MCS[3] ,MCS[3] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 2. " MCS[2] ,MCS[2] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 1. " MCS[1] ,MCS[1] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x04 0. " MCS[0] ,MCS[0] MediaLB channel status" "Cleared,Set"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "MS1,MediaLB Channel Status 1 Register"
|
|
bitfld.long 0x00 31. " MCS[63] ,MCS[63] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 30. " MCS[62] ,MCS[62] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 29. " MCS[61] ,MCS[61] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 28. " MCS[60] ,MCS[60] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MCS[59] ,MCS[59] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 26. " MCS[58] ,MCS[58] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 25. " MCS[57] ,MCS[57] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 24. " MCS[56] ,MCS[56] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MCS[55] ,MCS[55] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 22. " MCS[54] ,MCS[54] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 21. " MCS[53] ,MCS[53] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 20. " MCS[52] ,MCS[52] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MCS[51] ,MCS[51] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 18. " MCS[50] ,MCS[50] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 17. " MCS[49] ,MCS[49] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 16. " MCS[48] ,MCS[48] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MCS[47] ,MCS[47] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 14. " MCS[46] ,MCS[46] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 13. " MCS[45] ,MCS[45] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 12. " MCS[44] ,MCS[44] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MCS[43] ,MCS[43] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 10. " MCS[42] ,MCS[42] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 9. " MCS[41] ,MCS[41] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 8. " MCS[40] ,MCS[40] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MCS[39] ,MCS[39] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 6. " MCS[38] ,MCS[38] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 5. " MCS[37] ,MCS[37] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 4. " MCS[36] ,MCS[36] MediaLB channel status" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MCS[35] ,MCS[35] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 2. " MCS[34] ,MCS[34] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 1. " MCS[33] ,MCS[33] MediaLB channel status" "Cleared,Set"
|
|
bitfld.long 0x00 0. " MCS[32] ,MCS[32] MediaLB channel status" "Cleared,Set"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "MSS,MediaLB System Status Register"
|
|
bitfld.long 0x00 5. " SERVREQ ,Service request enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SWSYSCMD ,Software system command detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " CSSYSCMD ,Channel scan system command detected" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " ULKSYSCMD ,Network unlock system command detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LKSYSCMD ,Network lock system command detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " RSTSYSCMD ,Reset system command detected" "Not detected,Detected"
|
|
rgroup.long 0x424++0x03
|
|
line.long 0x00 "MSD,MediaLB System Data Register"
|
|
bitfld.long 0x00 31. " SD3[7] ,System data (byte 3) " "Not updated,Updated"
|
|
bitfld.long 0x00 30. " SD3[6] ,System data (byte 3) " "Not updated,Updated"
|
|
bitfld.long 0x00 29. " SD3[5] ,System data (byte 3) " "Not updated,Updated"
|
|
bitfld.long 0x00 28. " SD3[4] ,System data (byte 3) " "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SD3[3] ,System data (byte 3) " "Not updated,Updated"
|
|
bitfld.long 0x00 26. " SD3[2] ,System data (byte 3) " "Not updated,Updated"
|
|
bitfld.long 0x00 25. " SD3[1] ,System data (byte 3) " "Not updated,Updated"
|
|
bitfld.long 0x00 24. " SD3[0] ,System data (byte 3) " "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SD2[7] ,System data (byte 2) " "Not updated,Updated"
|
|
bitfld.long 0x00 22. " SD2[6] ,System data (byte 2) " "Not updated,Updated"
|
|
bitfld.long 0x00 21. " SD2[5] ,System data (byte 2) " "Not updated,Updated"
|
|
bitfld.long 0x00 20. " SD2[4] ,System data (byte 2) " "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SD2[3] ,System data (byte 2) " "Not updated,Updated"
|
|
bitfld.long 0x00 18. " SD2[2] ,System data (byte 2) " "Not updated,Updated"
|
|
bitfld.long 0x00 17. " SD2[1] ,System data (byte 2) " "Not updated,Updated"
|
|
bitfld.long 0x00 16. " SD2[0] ,System data (byte 2) " "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SD1[7] ,System data (byte 1) " "Not updated,Updated"
|
|
bitfld.long 0x00 14. " SD1[6] ,System data (byte 1) " "Not updated,Updated"
|
|
bitfld.long 0x00 13. " SD1[5] ,System data (byte 1) " "Not updated,Updated"
|
|
bitfld.long 0x00 12. " SD1[4] ,System data (byte 1) " "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SD13] ,System data (byte 1) " "Not updated,Updated"
|
|
bitfld.long 0x00 10. " SD1[2] ,System data (byte 1) " "Not updated,Updated"
|
|
bitfld.long 0x00 9. " SD1[1] ,System data (byte 1) " "Not updated,Updated"
|
|
bitfld.long 0x00 8. " SD1[0] ,System data (byte 1) " "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SD0[7] ,System data (byte 0) " "Not updated,Updated"
|
|
bitfld.long 0x00 6. " SD0[6] ,System data (byte 0) " "Not updated,Updated"
|
|
bitfld.long 0x00 5. " SD0[5] ,System data (byte 0) " "Not updated,Updated"
|
|
bitfld.long 0x00 4. " SD0[4] ,System data (byte 0) " "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SD0[3] ,System data (byte 0) " "Not updated,Updated"
|
|
bitfld.long 0x00 2. " SD0[2] ,System data (byte 0) " "Not updated,Updated"
|
|
bitfld.long 0x00 1. " SD0[1] ,System data (byte 0) " "Not updated,Updated"
|
|
bitfld.long 0x00 0. " SD0[0] ,System data (byte 0) " "Not updated,Updated"
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "MIEN,MediaLB Interrupt Enable Register"
|
|
bitfld.long 0x00 29. " CTX_BREAK ,Control Tx break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CTX_PE ,Control Tx protocol error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CTX_DONE ,Control Tx packet done enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " CRX_BREAK ,Control Rx break enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CRX_PE ,Control Rx protocol error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CRX_DONE ,Control Rx packet done enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ATX_BREAK ,Asynchronous Tx break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ATX_PE ,Asynchronous Tx protocol error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ATX_DONE ,Asynchronous Tx packet done enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ARX_BREAK ,Asynchronous Rx break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ARX_PE ,Asynchronous Rx protocol error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ARX_DONE ,Asynchronous Rx packet done enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SYNC_PE ,Synchronous protocol error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ISOC_BUFO ,Isochronous Rx buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ISOC_PE ,Isochronous Rx protocol error enable" "Disabled,Enabled"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "MLBC1,MediaLB Control 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NDA ,Node device address"
|
|
bitfld.long 0x00 7. " CLKMERR ,MediaLB clock error status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LOCKERR ,MediaLB lock missing status" "Disabled,Enabled"
|
|
group.long 0x4C0++0x27 "Memory Interface Registers"
|
|
line.long 0x00 "MDAT0,MIF Data 0 Register"
|
|
line.long 0x04 "MDAT1,MIF Data 1 Register"
|
|
line.long 0x08 "MDAT2,MIF Data 2 Register"
|
|
line.long 0x0C "MDAT3,MIF Data 3 Register"
|
|
line.long 0x10 "MDWE0,MIF Data Write Enable 0 Register"
|
|
bitfld.long 0x10 31. " MASK[31] ,Bitwise write enable for CTR data 31" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " MASK[30] ,Bitwise write enable for CTR data 30" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " MASK[29] ,Bitwise write enable for CTR data 29" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " MASK[28] ,Bitwise write enable for CTR data 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " MASK[27] ,Bitwise write enable for CTR data 27" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " MASK[26] ,Bitwise write enable for CTR data 26" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " MASK[25] ,Bitwise write enable for CTR data 25" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " MASK[24] ,Bitwise write enable for CTR data 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " MASK[23] ,Bitwise write enable for CTR data 23" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " MASK[22] ,Bitwise write enable for CTR data 22" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " MASK[21] ,Bitwise write enable for CTR data 21" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " MASK[20] ,Bitwise write enable for CTR data 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " MASK[19] ,Bitwise write enable for CTR data 19" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " MASK[18] ,Bitwise write enable for CTR data 18" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " MASK[17] ,Bitwise write enable for CTR data 17" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " MASK[16] ,Bitwise write enable for CTR data 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " MASK[15] ,Bitwise write enable for CTR data 15" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " MASK[14] ,Bitwise write enable for CTR data 14" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " MASK[13] ,Bitwise write enable for CTR data 13" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " MASK[12] ,Bitwise write enable for CTR data 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " MASK[11] ,Bitwise write enable for CTR data 11" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " MASK[10] ,Bitwise write enable for CTR data 10" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " MASK[9] ,Bitwise write enable for CTR data 9" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " MASK[8] ,Bitwise write enable for CTR data 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " MASK[7] ,Bitwise write enable for CTR data 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " MASK[6] ,Bitwise write enable for CTR data 6" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " MASK[5] ,Bitwise write enable for CTR data 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " MASK[4] ,Bitwise write enable for CTR data 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " MASK[3] ,Bitwise write enable for CTR data 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " MASK[2] ,Bitwise write enable for CTR data 2" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " MASK[1] ,Bitwise write enable for CTR data 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " MASK[0] ,Bitwise write enable for CTR data 0" "Disabled,Enabled"
|
|
line.long 0x14 "MDWE1,MIF Data Write Enable 1 Register"
|
|
bitfld.long 0x14 31. " MASK[63] ,Bitwise write enable for CTR data 63" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " MASK[62] ,Bitwise write enable for CTR data 62" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " MASK[61] ,Bitwise write enable for CTR data 61" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " MASK[60] ,Bitwise write enable for CTR data 60" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " MASK[59] ,Bitwise write enable for CTR data 59" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " MASK[58] ,Bitwise write enable for CTR data 58" "Disabled,Enabled"
|
|
bitfld.long 0x14 25. " MASK[57] ,Bitwise write enable for CTR data 57" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " MASK[56] ,Bitwise write enable for CTR data 56" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " MASK[55] ,Bitwise write enable for CTR data 55" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " MASK[54] ,Bitwise write enable for CTR data 54" "Disabled,Enabled"
|
|
bitfld.long 0x14 21. " MASK[53] ,Bitwise write enable for CTR data 53" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " MASK[52] ,Bitwise write enable for CTR data 52" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " MASK[51] ,Bitwise write enable for CTR data 51" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " MASK[50] ,Bitwise write enable for CTR data 50" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " MASK[49] ,Bitwise write enable for CTR data 49" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " MASK[48] ,Bitwise write enable for CTR data 48" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " MASK[47] ,Bitwise write enable for CTR data 47" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " MASK[46] ,Bitwise write enable for CTR data 46" "Disabled,Enabled"
|
|
bitfld.long 0x14 13. " MASK[45] ,Bitwise write enable for CTR data 45" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " MASK[44] ,Bitwise write enable for CTR data 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " MASK[43] ,Bitwise write enable for CTR data 43" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " MASK[42] ,Bitwise write enable for CTR data 42" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " MASK[41] ,Bitwise write enable for CTR data 41" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " MASK[40] ,Bitwise write enable for CTR data 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " MASK[39] ,Bitwise write enable for CTR data 39" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " MASK[38] ,Bitwise write enable for CTR data 38" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " MASK[37] ,Bitwise write enable for CTR data 37" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " MASK[36] ,Bitwise write enable for CTR data 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " MASK[35] ,Bitwise write enable for CTR data 35" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " MASK[34] ,Bitwise write enable for CTR data 34" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " MASK[33] ,Bitwise write enable for CTR data 33" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " MASK[32] ,Bitwise write enable for CTR data 32" "Disabled,Enabled"
|
|
line.long 0x18 "MDWE2,MIF Data Write Enable 2 Register"
|
|
bitfld.long 0x18 31. " MASK[95] ,Bitwise write enable for CTR data 95" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " MASK[94] ,Bitwise write enable for CTR data 94" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " MASK[93] ,Bitwise write enable for CTR data 93" "Disabled,Enabled"
|
|
bitfld.long 0x18 28. " MASK[92] ,Bitwise write enable for CTR data 92" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 27. " MASK[91] ,Bitwise write enable for CTR data 91" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " MASK[90] ,Bitwise write enable for CTR data 90" "Disabled,Enabled"
|
|
bitfld.long 0x18 25. " MASK[89] ,Bitwise write enable for CTR data 89" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " MASK[88] ,Bitwise write enable for CTR data 88" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 23. " MASK[87] ,Bitwise write enable for CTR data 87" "Disabled,Enabled"
|
|
bitfld.long 0x18 22. " MASK[86] ,Bitwise write enable for CTR data 86" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " MASK[85] ,Bitwise write enable for CTR data 85" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " MASK[84] ,Bitwise write enable for CTR data 84" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 19. " MASK[83] ,Bitwise write enable for CTR data 83" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " MASK[82] ,Bitwise write enable for CTR data 82" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " MASK[81] ,Bitwise write enable for CTR data 81" "Disabled,Enabled"
|
|
bitfld.long 0x18 16. " MASK[80] ,Bitwise write enable for CTR data 80" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 15. " MASK[79] ,Bitwise write enable for CTR data 79" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " MASK[78] ,Bitwise write enable for CTR data 78" "Disabled,Enabled"
|
|
bitfld.long 0x18 13. " MASK[77] ,Bitwise write enable for CTR data 77" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " MASK[76] ,Bitwise write enable for CTR data 76" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " MASK[75] ,Bitwise write enable for CTR data 75" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " MASK[74] ,Bitwise write enable for CTR data 74" "Disabled,Enabled"
|
|
bitfld.long 0x18 9. " MASK[73] ,Bitwise write enable for CTR data 73" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " MASK[72] ,Bitwise write enable for CTR data 72" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 7. " MASK[71] ,Bitwise write enable for CTR data 71" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " MASK[70] ,Bitwise write enable for CTR data 70" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " MASK[69] ,Bitwise write enable for CTR data 69" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " MASK[68] ,Bitwise write enable for CTR data 68" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 3. " MASK[67] ,Bitwise write enable for CTR data 67" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " MASK[66] ,Bitwise write enable for CTR data 66" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " MASK[65] ,Bitwise write enable for CTR data 65" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " MASK[64] ,Bitwise write enable for CTR data 64" "Disabled,Enabled"
|
|
line.long 0x1C "MDWE3,MIF Data Write Enable 3 Register"
|
|
bitfld.long 0x1C 31. " MASK[127] ,Bitwise write enable for CTR data 127" "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " MASK[126] ,Bitwise write enable for CTR data 126" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " MASK[125] ,Bitwise write enable for CTR data 125" "Disabled,Enabled"
|
|
bitfld.long 0x1C 28. " MASK[124] ,Bitwise write enable for CTR data 124" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " MASK[123] ,Bitwise write enable for CTR data 123" "Disabled,Enabled"
|
|
bitfld.long 0x1C 26. " MASK[122] ,Bitwise write enable for CTR data 122" "Disabled,Enabled"
|
|
bitfld.long 0x1C 25. " MASK[121] ,Bitwise write enable for CTR data 121" "Disabled,Enabled"
|
|
bitfld.long 0x1C 24. " MASK[120] ,Bitwise write enable for CTR data 120" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " MASK[119] ,Bitwise write enable for CTR data 119" "Disabled,Enabled"
|
|
bitfld.long 0x1C 22. " MASK[118] ,Bitwise write enable for CTR data 118" "Disabled,Enabled"
|
|
bitfld.long 0x1C 21. " MASK[117] ,Bitwise write enable for CTR data 117" "Disabled,Enabled"
|
|
bitfld.long 0x1C 20. " MASK[116] ,Bitwise write enable for CTR data 116" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " MASK[115] ,Bitwise write enable for CTR data 115" "Disabled,Enabled"
|
|
bitfld.long 0x1C 18. " MASK[114] ,Bitwise write enable for CTR data 114" "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " MASK[113] ,Bitwise write enable for CTR data 113" "Disabled,Enabled"
|
|
bitfld.long 0x1C 16. " MASK[112] ,Bitwise write enable for CTR data 112" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " MASK[111] ,Bitwise write enable for CTR data 111" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " MASK[110] ,Bitwise write enable for CTR data 110" "Disabled,Enabled"
|
|
bitfld.long 0x1C 13. " MASK[109] ,Bitwise write enable for CTR data 109" "Disabled,Enabled"
|
|
bitfld.long 0x1C 12. " MASK[108] ,Bitwise write enable for CTR data 108" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " MASK[107] ,Bitwise write enable for CTR data 107" "Disabled,Enabled"
|
|
bitfld.long 0x1C 10. " MASK[106] ,Bitwise write enable for CTR data 106" "Disabled,Enabled"
|
|
bitfld.long 0x1C 9. " MASK[105] ,Bitwise write enable for CTR data 105" "Disabled,Enabled"
|
|
bitfld.long 0x1C 8. " MASK[104] ,Bitwise write enable for CTR data 104" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " MASK[103] ,Bitwise write enable for CTR data 103" "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " MASK[102] ,Bitwise write enable for CTR data 102" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " MASK[101] ,Bitwise write enable for CTR data 101" "Disabled,Enabled"
|
|
bitfld.long 0x1C 4. " MASK[100] ,Bitwise write enable for CTR data 100" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " MASK[99] ,Bitwise write enable for CTR data 99" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " MASK[98] ,Bitwise write enable for CTR data 98" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " MASK[97] ,Bitwise write enable for CTR data 97" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " MASK[96] ,Bitwise write enable for CTR data 96" "Disabled,Enabled"
|
|
line.long 0x20 "MCTL,MIF Control Register"
|
|
bitfld.long 0x20 0. " XCMP ,Transfer complete" "Disabled,Enabled"
|
|
line.long 0x24 "MADR,MIF Address Register"
|
|
bitfld.long 0x24 31. " WNR ,Write-Not-Read selection" "Read,Write"
|
|
hexmask.long.byte 0x24 0.--7. 1. " ADDR ,CTR address of 128-bit entry or DBR address of 8-bit entry"
|
|
group.long 0x480++0x03 "DMA Registers"
|
|
line.long 0x00 "DIENR,DMA (Internal) Enable Register"
|
|
bitfld.long 0x00 15. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long 0x488++0x07
|
|
line.long 0x00 "DICER0,DMA (Internal) Channel Enable 0 Register"
|
|
bitfld.long 0x00 31. " CHE[31] ,Bitwise channel enable bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHE[30] ,Bitwise channel enable bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CHE[29] ,Bitwise channel enable bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CHE[28] ,Bitwise channel enable bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHE[27] ,Bitwise channel enable bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " CHE[26] ,Bitwise channel enable bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CHE[25] ,Bitwise channel enable bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CHE[24] ,Bitwise channel enable bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CHE[23] ,Bitwise channel enable bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CHE[22] ,Bitwise channel enable bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CHE[21] ,Bitwise channel enable bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CHE[20] ,Bitwise channel enable bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CHE[19] ,Bitwise channel enable bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CHE[18] ,Bitwise channel enable bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CHE[17] ,Bitwise channel enable bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CHE[16] ,Bitwise channel enable bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHE[15] ,Bitwise channel enable bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHE[14] ,Bitwise channel enable bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CHE[13] ,Bitwise channel enable bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " CHE[12] ,Bitwise channel enable bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHE[11] ,Bitwise channel enable bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CHE[10] ,Bitwise channel enable bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CHE[9] ,Bitwise channel enable bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CHE[8] ,Bitwise channel enable bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHE[7] ,Bitwise channel enable bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHE[6] ,Bitwise channel enable bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CHE[5] ,Bitwise channel enable bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CHE[4] ,Bitwise channel enable bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHE[3] ,Bitwise channel enable bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CHE[2] ,Bitwise channel enable bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CHE[1] ,Bitwise channel enable bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CHE[0] ,Bitwise channel enable bit 0" "Disabled,Enabled"
|
|
line.long 0x04 "DICER1,DMA (Internal) Channel Enable 1 Register"
|
|
bitfld.long 0x04 31. " CHE[31] ,Bitwise channel enable bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CHE[30] ,Bitwise channel enable bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CHE[29] ,Bitwise channel enable bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " CHE[28] ,Bitwise channel enable bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CHE[27] ,Bitwise channel enable bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " CHE[26] ,Bitwise channel enable bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " CHE[25] ,Bitwise channel enable bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CHE[24] ,Bitwise channel enable bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " CHE[23] ,Bitwise channel enable bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " CHE[22] ,Bitwise channel enable bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CHE[21] ,Bitwise channel enable bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CHE[20] ,Bitwise channel enable bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CHE[19] ,Bitwise channel enable bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CHE[18] ,Bitwise channel enable bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CHE[17] ,Bitwise channel enable bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CHE[16] ,Bitwise channel enable bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " CHE[15] ,Bitwise channel enable bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " CHE[14] ,Bitwise channel enable bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " CHE[13] ,Bitwise channel enable bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " CHE[12] ,Bitwise channel enable bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CHE[11] ,Bitwise channel enable bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CHE[10] ,Bitwise channel enable bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CHE[9] ,Bitwise channel enable bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CHE[8] ,Bitwise channel enable bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CHE[7] ,Bitwise channel enable bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CHE[6] ,Bitwise channel enable bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CHE[5] ,Bitwise channel enable bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CHE[4] ,Bitwise channel enable bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CHE[3] ,Bitwise channel enable bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CHE[2] ,Bitwise channel enable bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CHE[1] ,Bitwise channel enable bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CHE[0] ,Bitwise channel enable bit 0" "Disabled,Enabled"
|
|
group.long 0x7C0++0x03
|
|
line.long 0x00 "DCTL,DMA Control Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 4. " PKT_MODE ,Packet mode for async/control packets" "Single,Multi"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " DMA_MODE ,DMA mode" "0,1"
|
|
bitfld.long 0x00 1. " SMX ,DMA interrupt mux enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SCE ,Software clear enable" "Disabled,Enabled"
|
|
group.long 0x7D0++0x0F
|
|
line.long 0x00 "DCSR0,DMA Channel Status 0 Register"
|
|
bitfld.long 0x00 31. " CHS[31] ,Interrupt status for logical channel 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " CHS[30] ,Interrupt status for logical channel 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " CHS[29] ,Interrupt status for logical channel 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " CHS[28] ,Interrupt status for logical channel 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHS[27] ,Interrupt status for logical channel 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " CHS[26] ,Interrupt status for logical channel 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " CHS[25] ,Interrupt status for logical channel 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " CHS[24] ,Interrupt status for logical channel 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CHS[23] ,Interrupt status for logical channel 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " CHS[22] ,Interrupt status for logical channel 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " CHS[21] ,Interrupt status for logical channel 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " CHS[20] ,Interrupt status for logical channel 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CHS[19] ,Interrupt status for logical channel 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " CHS[18] ,Interrupt status for logical channel 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " CHS[17] ,Interrupt status for logical channel 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " CHS[16] ,Interrupt status for logical channel 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHS[15] ,Interrupt status for logical channel 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " CHS[14] ,Interrupt status for logical channel 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " CHS[13] ,Interrupt status for logical channel 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " CHS[12] ,Interrupt status for logical channel 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHS[11] ,Interrupt status for logical channel 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " CHS[10] ,Interrupt status for logical channel 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " CHS[9] ,Interrupt status for logical channel 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " CHS[8] ,Interrupt status for logical channel 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHS[7] ,Interrupt status for logical channel 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " CHS[6] ,Interrupt status for logical channel 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " CHS[5] ,Interrupt status for logical channel 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " CHS[4] ,Interrupt status for logical channel 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHS[3] ,Interrupt status for logical channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " CHS[2] ,Interrupt status for logical channel 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " CHS[1] ,Interrupt status for logical channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " CHS[0] ,Interrupt status for logical channel 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "DCSR1,DMA Channel Status 1 Register"
|
|
bitfld.long 0x04 31. " CHS[63] ,Interrupt status for logical channel 63" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " CHS[62] ,Interrupt status for logical channel 62" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " CHS[61] ,Interrupt status for logical channel 61" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " CHS[60] ,Interrupt status for logical channel 60" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CHS[59] ,Interrupt status for logical channel 59" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " CHS[58] ,Interrupt status for logical channel 58" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " CHS[57] ,Interrupt status for logical channel 57" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " CHS[56] ,Interrupt status for logical channel 56" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " CHS[55] ,Interrupt status for logical channel 55" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " CHS[54] ,Interrupt status for logical channel 54" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " CHS[53] ,Interrupt status for logical channel 53" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " CHS[52] ,Interrupt status for logical channel 52" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CHS[51] ,Interrupt status for logical channel 51" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " CHS[50] ,Interrupt status for logical channel 50" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " CHS[49] ,Interrupt status for logical channel 49" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " CHS[48] ,Interrupt status for logical channel 48" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " CHS[47] ,Interrupt status for logical channel 47" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " CHS[46] ,Interrupt status for logical channel 46" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " CHS[45] ,Interrupt status for logical channel 45" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " CHS[44] ,Interrupt status for logical channel 44" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CHS[43] ,Interrupt status for logical channel 43" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " CHS[42] ,Interrupt status for logical channel 42" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " CHS[41] ,Interrupt status for logical channel 41" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " CHS[40] ,Interrupt status for logical channel 40" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CHS[39] ,Interrupt status for logical channel 39" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " CHS[38] ,Interrupt status for logical channel 38" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " CHS[37] ,Interrupt status for logical channel 37" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " CHS[36] ,Interrupt status for logical channel 36" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CHS[35] ,Interrupt status for logical channel 35" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " CHS[34] ,Interrupt status for logical channel 34" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " CHS[33] ,Interrupt status for logical channel 33" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " CHS[32] ,Interrupt status for logical channel 32" "No interrupt,Interrupt"
|
|
line.long 0x08 "DCMR0,DMA Channel Mask 0 Register"
|
|
bitfld.long 0x08 31. " CHM[31] ,Bitwise channel mask bit 31" "Masked,Not masked"
|
|
bitfld.long 0x08 30. " CHM[30] ,Bitwise channel mask bit 30" "Masked,Not masked"
|
|
bitfld.long 0x08 29. " CHM[29] ,Bitwise channel mask bit 29" "Masked,Not masked"
|
|
bitfld.long 0x08 28. " CHM[28] ,Bitwise channel mask bit 28" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 27. " CHM[27] ,Bitwise channel mask bit 27" "Masked,Not masked"
|
|
bitfld.long 0x08 26. " CHM[26] ,Bitwise channel mask bit 26" "Masked,Not masked"
|
|
bitfld.long 0x08 25. " CHM[25] ,Bitwise channel mask bit 25" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " CHM[24] ,Bitwise channel mask bit 24" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 23. " CHM[23] ,Bitwise channel mask bit 23" "Masked,Not masked"
|
|
bitfld.long 0x08 22. " CHM[22] ,Bitwise channel mask bit 22" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " CHM[21] ,Bitwise channel mask bit 21" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " CHM[20] ,Bitwise channel mask bit 20" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " CHM[19] ,Bitwise channel mask bit 19" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " CHM[18] ,Bitwise channel mask bit 18" "Masked,Not masked"
|
|
bitfld.long 0x08 17. " CHM[17] ,Bitwise channel mask bit 17" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " CHM[16] ,Bitwise channel mask bit 16" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 15. " CHM[15] ,Bitwise channel mask bit 15" "Masked,Not masked"
|
|
bitfld.long 0x08 14. " CHM[14] ,Bitwise channel mask bit 14" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " CHM[13] ,Bitwise channel mask bit 13" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " CHM[12] ,Bitwise channel mask bit 12" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 11. " CHM[11] ,Bitwise channel mask bit 11" "Masked,Not masked"
|
|
bitfld.long 0x08 10. " CHM[10] ,Bitwise channel mask bit 10" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " CHM[9] ,Bitwise channel mask bit 9" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " CHM[8] ,Bitwise channel mask bit 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CHM[7] ,Bitwise channel mask bit 7" "Masked,Not masked"
|
|
bitfld.long 0x08 6. " CHM[6] ,Bitwise channel mask bit 6" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " CHM[5] ,Bitwise channel mask bit 5" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " CHM[4] ,Bitwise channel mask bit 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CHM[3] ,Bitwise channel mask bit 3" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " CHM[2] ,Bitwise channel mask bit 2" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " CHM[1] ,Bitwise channel mask bit 1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " CHM[0] ,Bitwise channel mask bit 0" "Masked,Not masked"
|
|
line.long 0x0C "DCMR1,DMA Channel Mask 1 Register"
|
|
bitfld.long 0x0C 31. " CHM[63] ,Bitwise channel mask bit 63" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " CHM[62] ,Bitwise channel mask bit 62" "Masked,Not masked"
|
|
bitfld.long 0x0C 29. " CHM[61] ,Bitwise channel mask bit 61" "Masked,Not masked"
|
|
bitfld.long 0x0C 28. " CHM[60] ,Bitwise channel mask bit 60" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " CHM[59] ,Bitwise channel mask bit 59" "Masked,Not masked"
|
|
bitfld.long 0x0C 26. " CHM[58] ,Bitwise channel mask bit 58" "Masked,Not masked"
|
|
bitfld.long 0x0C 25. " CHM[57] ,Bitwise channel mask bit 57" "Masked,Not masked"
|
|
bitfld.long 0x0C 24. " CHM[56] ,Bitwise channel mask bit 56" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " CHM[55] ,Bitwise channel mask bit 55" "Masked,Not masked"
|
|
bitfld.long 0x0C 22. " CHM[54] ,Bitwise channel mask bit 54" "Masked,Not masked"
|
|
bitfld.long 0x0C 21. " CHM[53] ,Bitwise channel mask bit 53" "Masked,Not masked"
|
|
bitfld.long 0x0C 20. " CHM[52] ,Bitwise channel mask bit 52" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CHM[51] ,Bitwise channel mask bit 51" "Masked,Not masked"
|
|
bitfld.long 0x0C 18. " CHM[50] ,Bitwise channel mask bit 50" "Masked,Not masked"
|
|
bitfld.long 0x0C 17. " CHM[49] ,Bitwise channel mask bit 49" "Masked,Not masked"
|
|
bitfld.long 0x0C 16. " CHM[48] ,Bitwise channel mask bit 48" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " CHM[47] ,Bitwise channel mask bit 47" "Masked,Not masked"
|
|
bitfld.long 0x0C 14. " CHM[46] ,Bitwise channel mask bit 46" "Masked,Not masked"
|
|
bitfld.long 0x0C 13. " CHM[45] ,Bitwise channel mask bit 45" "Masked,Not masked"
|
|
bitfld.long 0x0C 12. " CHM[44] ,Bitwise channel mask bit 44" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CHM[43] ,Bitwise channel mask bit 43" "Masked,Not masked"
|
|
bitfld.long 0x0C 10. " CHM[42] ,Bitwise channel mask bit 42" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CHM[41] ,Bitwise channel mask bit 41" "Masked,Not masked"
|
|
bitfld.long 0x0C 8. " CHM[40] ,Bitwise channel mask bit 40" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CHM[39] ,Bitwise channel mask bit 39" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CHM[38] ,Bitwise channel mask bit 38" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " CHM[37] ,Bitwise channel mask bit 37" "Masked,Not masked"
|
|
bitfld.long 0x0C 4. " CHM[36] ,Bitwise channel mask bit 36" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " CHM[35] ,Bitwise channel mask bit 35" "Masked,Not masked"
|
|
bitfld.long 0x0C 2. " CHM[34] ,Bitwise channel mask bit 34" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " CHM[33] ,Bitwise channel mask bit 33" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CHM[32] ,Bitwise channel mask bit 32" "Masked,Not masked"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "MMC/SD/SDIO (Secure Digital/Secure Digital I/O Card Interface)"
|
|
tree "MMC/SD/SDIO 0"
|
|
base ad:0x48060000
|
|
width 17.
|
|
sif !(cpuis("AM335*"))
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "SD_HL_REV,IP Revision Identifier Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
bitfld.long 0x00 11.--15. " R_RTL ,R_RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
line.long 0x04 "SD_HL_HWINFO,Hardware Configuration Register"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x04 2.--5. " MEM_SIZE ,Memory Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MERGE_MEM ,Merge memory" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 1. " MEM_SIZE ,Memory Size" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " MADMA_EN ,MADMA Enable" "Disabled,Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SD_HL_SYSCONFIG,Clock Management Configuration Register"
|
|
bitfld.long 0x00 4.--5. " STANDBYMODE ,Standby mode" "Mode0,Mode1,Mode2,Mode3"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Idle mode" "Mode0,Mode1,Mode2,Mode3"
|
|
bitfld.long 0x00 1. " FREEEMU ,Free EMU" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Soft reset" "No reset,Reset"
|
|
endif
|
|
width 17.
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "SD_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power management standby/wait control (when MADMA is enabled)" "Force-standby,No standby,Smart-standby,Smart-standby wake-up-capable"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "Inactive,Interface,Functional,Both"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle wake-up-capable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up capability enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "SD_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset status" "On-going,Done"
|
|
group.long 0x124++0x7
|
|
line.long 0x00 "SD_CSRE,Card Status Response Error Register"
|
|
width 17.
|
|
line.long 0x04 "SD_SYSTEST,System Test Register"
|
|
bitfld.long 0x04 16. " OBI ,Out of band interrupt data value input/output" "Low,High"
|
|
bitfld.long 0x04 15. " SDCD ,Card detect input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 14. " SDWP ,Write protect input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " WAKD ,Wake request input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 12. " SSB ,Set status bit" "Clear,Force"
|
|
bitfld.long 0x04 11. " D7D ,DAT7 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " D6D ,DAT6 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 9. " D5D ,DAT5 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 8. " D4D ,DAT4 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " D3D ,DAT3 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 6. " D2D ,DAT2 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 5. " D1D ,DAT1 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " D0D ,DAT0 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input"
|
|
bitfld.long 0x04 2. " CDAT ,CMD input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CDIR ,Control of the CMD pin direction" "Output,Input"
|
|
bitfld.long 0x04 0. " MCKD ,Clock input/output signal data value" "Low,High"
|
|
width 17.
|
|
group.long 0x12c++0x7
|
|
line.long 0x00 "SD_CON,Configuration Register"
|
|
bitfld.long 0x00 21. " SDMA_LNE ,Select Slave DMA Level/Edge Request" "Edge,Level"
|
|
bitfld.long 0x00 20. " DMA_MNS ,DMA Master or Slave selection(when MADMA is enabled)" "Slave,?..."
|
|
bitfld.long 0x00 19. " DDR ,Dual data rate transmission mode" "Single edge,Both"
|
|
textline " "
|
|
bitfld.long 0x00 18. " BOOT_CF0 ,Boot Status supported" "Not forced,Forced"
|
|
bitfld.long 0x00 17. " BOOT_ACK ,Boot acknowledge receive" "NO ACK,ACK"
|
|
bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained"
|
|
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
textline " "
|
|
bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines" "Not forced,Forced"
|
|
bitfld.long 0x00 12. " CEATA ,CE-ATA control mode" "Standard,CE-ATA"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTPL ,Control Power for SD_DAT1 line" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " DVAL ,Debounce period for filter SDCD" "33 us,231 us,1 ms,8.4 ms"
|
|
bitfld.long 0x00 8. " WPP ,Write protect polarity (SD and SDIO cards only)" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDP ,Card detect polarity (all cards)" "Active high,Active low"
|
|
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 6. " MIT ,MMC Interrupt Command" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DW8 ,8-bit mode select (MMC cars only)" "1-bit/4-bit,8-bit"
|
|
endif
|
|
bitfld.long 0x00 4. " MODE ,Mode select(all cards)" "Functional,SYSTEST"
|
|
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 3. " STR ,Stream command (MMC cars only)" "Block,Stream"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HR ,Broadcast host response (MMC cars only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent"
|
|
else
|
|
bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent"
|
|
endif
|
|
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 0. " OD ,Card open drain mode (MMC cars only)" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "SD_PWCNT,Power Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PWRCNT ,Power counter"
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x00 "SD_SDMASA,SDMA System Address Register"
|
|
if (((d.l(ad:0x48060000+0x20c))&0x20)==0x20)
|
|
group.long 0x204++0x3
|
|
line.long 0x00 "SD_BLK,Transfer Length Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer"
|
|
hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size"
|
|
else
|
|
group.long 0x204++0x3
|
|
line.long 0x00 "SD_BLK,Transfer Length Configuration Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size"
|
|
endif
|
|
group.long 0x208++0x7
|
|
line.long 0x00 "SD_ARG,Command Argument Register"
|
|
line.long 0x04 "SD_CMD,Command and Transfer Mode Register"
|
|
bitfld.long 0x04 24.--29. " INDEX ,Command number sent to card" "Cmd0 or acmd0,Cmd1 or acmd1,Cmd2 or acmd2,Cmd3 or acmd3,Cmd4 or acmd4,Cmd5 or acmd5,Cmd6 or acmd6,Cmd7 or acmd7,Cmd8 or acmd8,Cmd9 or acmd9,Cmd10 or acmd10,Cmd11 or acmd11,Cmd12 or acmd12,Cmd13 or acmd13,Cmd14 or acmd14,Cmd15 or acmd15,Cmd16 or acmd16,Cmd17 or acmd17,Cmd18 or acmd18,Cmd19 or acmd19,Cmd20 or acmd20,Cmd21 or acmd21,Cmd22 or acmd22,Cmd23 or acmd23,Cmd24 or acmd24,Cmd25 or acmd25,Cmd26 or acmd26,Cmd27 or acmd27,Cmd28 or acmd28,Cmd29 or acmd29,Cmd30 or acmd30,Cmd31 or acmd31,Cmd32 or acmd32,Cmd33 or acmd33,Cmd34 or acmd34,Cmd35 or acmd35,Cmd36 or acmd36,Cmd37 or acmd37,Cmd38 or acmd38,Cmd39 or acmd39,Cmd40 or acmd40,Cmd41 or acmd41,Cmd42 or acmd42,Cmd43 or acmd43,Cmd44 or acmd44,Cmd45 or acmd45,Cmd46 or acmd46,Cmd47 or acmd47,Cmd48 or acmd48,Cmd49 or acmd49,Cmd50 or acmd50,Cmd51 or acmd51,Cmd52 or acmd52,Cmd53 or acmd53,Cmd54 or acmd54,Cmd55 or acmd55,Cmd56 or acmd56,Cmd57 or acmd57,Cmd58 or acmd58,Cmd59 or acmd59,Cmd60 or acmd60,Cmd61 or acmd61,Cmd62 or acmd62,Cmd63 or acmd63"
|
|
bitfld.long 0x04 22.--23. " CMD_TYPE ,Command type" "Other,Bus suspend,Function select,I/O Abort"
|
|
bitfld.long 0x04 21. " DP ,Data present select" "No data,Present"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CICE ,Command index check enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CCCE ,Command CRC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits (busy)"
|
|
textline " "
|
|
bitfld.long 0x04 5. " MSBS ,Multi/Single block select" "Single,Multi"
|
|
bitfld.long 0x04 4. " DDIR ,Data transfer direction" "Write,Read"
|
|
bitfld.long 0x04 2. " ACEN ,Auto CMD12 Enable (SD cards only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BCE ,Block Count Enable (Multiple block transfers only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DE ,DMA Enable" "Disabled,Enabled"
|
|
rgroup.long 0x210++0xf
|
|
line.long 0x00 "SD_RSP10,Command Response 0 and 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command Response[31:16]"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command Response[15:0]"
|
|
line.long 0x04 "SD_RSP32,Command Response 2 and 3 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " RSP3 ,Command Response[63:48]"
|
|
hexmask.long.word 0x04 0.--15. 1. " RSP2 ,Command Response[47:32]"
|
|
line.long 0x08 "SD_RSP54,Command Response 4 and 5 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " RSP5 ,Command Response[95:80]"
|
|
hexmask.long.word 0x08 0.--15. 1. " RSP4 ,Command Response[79:64]"
|
|
line.long 0x0c "SD_RSP76,Command Response 6 and 7 Register"
|
|
hexmask.long.word 0x0c 16.--31. 1. " RSP7 ,Command Response[127:112]"
|
|
hexmask.long.word 0x0c 0.--15. 1. " RSP6 ,Command Response[111:96]"
|
|
width 17.
|
|
group.long 0x220++0x3
|
|
line.long 0x00 "SD_DATA,Data Register"
|
|
if (((d.l(ad:0x48060000+0x12c))&0x180)==0x180)
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "SD_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
|
|
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
|
|
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
|
|
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0"
|
|
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
|
|
bitfld.long 0x00 16. " CINS ,Detect card" "Detected,Not detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
|
|
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
|
|
elif (((d.l(ad:0x48060000+0x12c))&0x180)==0x100)
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "SD_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
|
|
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
|
|
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
|
|
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0"
|
|
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
|
|
bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
|
|
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
|
|
elif (((d.l(ad:0x48060000+0x12c))&0x180)==0x80)
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "SD_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
|
|
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
|
|
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
|
|
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0"
|
|
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
|
|
bitfld.long 0x00 16. " CI ,Detect card" "Detected,Not detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
|
|
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
|
|
else
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "SD_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
|
|
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
|
|
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
|
|
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0"
|
|
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
|
|
bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
|
|
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
|
|
endif
|
|
group.long 0x228++0x13
|
|
line.long 0x00 "SD_HCTL,Host Control Register"
|
|
bitfld.long 0x00 27. " OBWE ,Wake-up event enable for OBI" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " REM ,Wake-up event enable on SD card removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " INS ,Wake-up event enable on SD card insertion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " IWE ,Wake-up event enable on SD card interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " IBG ,Interrupt block at gap (in 4-bit mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RWC ,Read wait control (SDIO cards)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CR ,Transfer continue request" "No affect,Restart"
|
|
bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer mode,Stopped"
|
|
bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select" "Reserved,Reserved,Reserved,Reserved,Reserved,1.8V,3.0V,3.3V"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On"
|
|
bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "SDCD,CDTL"
|
|
bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " DMAS ,DMA Select" "Reserved,Reserved,32-bit ADMA2,?..."
|
|
bitfld.long 0x00 2. " HSPE ,High speed enable" "Normal,High"
|
|
bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit"
|
|
line.long 0x04 "SD_SYSCTL,SD System Control Register"
|
|
bitfld.long 0x04 26. " SRD ,Software reset for SD_DAT line" "No reset,Reset"
|
|
bitfld.long 0x04 25. " SRC ,Software reset for SD_CMD line" "No reset,Reset"
|
|
bitfld.long 0x04 24. " SRA ,Software reset for all" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCFx2^13,TCFx2^14,TCFx2^15,TCFx2^16,TCFx2^17,TCFx2^18,TCFx2^19,TCFx2^20,TCFx2^21,TCFx2^22,TCFx2^23,TCFx2^24,TCFx2^25,TCFx2^26,TCFx2^27,?..."
|
|
hexmask.long.word 0x04 6.--15. 1. " CLKD ,Clock frequency select"
|
|
bitfld.long 0x04 2. " CEN ,Clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable"
|
|
else
|
|
bitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable"
|
|
endif
|
|
bitfld.long 0x04 0. " ICE ,Internal clock enable" "Disabled,Enabled"
|
|
line.long 0x08 "SD_STAT,Interrupt Status Register"
|
|
eventfld.long 0x08 29. " BADA ,Bad access to data space interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 28. " CERR ,Card error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 25. " ADMAE ,ADMA error" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 24. " ACE ,Auto CMD12 error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 22. " DEB ,Data end bit error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 21. " DCRC ,Data CRC error" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 20. " DTO ,Data timeout error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 19. " CIE ,Command index error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 18. " CEB ,Command end bit error" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 17. " CCRC ,Command CRC error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 16. " CTO ,Command timeout error" "No interrupt,Interrupt"
|
|
sif (cpuis("DRA62*")||cpuis("AM355*"))
|
|
rbitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x08 7. " CREM ,Card removal" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " CINS ,Card insertion" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " BRR ,Buffer read ready" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 4. " BWR ,Buffer write ready" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DMA ,DMA interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " BGE ,Block gap event" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " TC ,Transfer completed" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " CC ,Command completed" "No interrupt,Interrupt"
|
|
width 17.
|
|
line.long 0x0c "SD_IE,Interrupt SD Enable Register"
|
|
bitfld.long 0x0c 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 25. " ADMA_ENABLE ,ADMA error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x0c 15. " NULL ,Null" "0,1"
|
|
else
|
|
bitfld.long 0x0c 15. " NULL ,Null" "0,1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0c 10. " BSR_ENABLE ,Boot status received interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 9. " OBI_ENABLE ,Out of band interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " CREM_ENABLE ,Card removal interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 6. " CINS_ENABLE ,Card insertion interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 3. " DMA_ENABLE ,DMA interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled"
|
|
line.long 0x10 "SD_ISE,Interrupt Signal Enable Register"
|
|
bitfld.long 0x10 29. " BADA_SIGEN ,Bad access to data space signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " CERR_SIGEN ,Card error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " ADMA_SIGEN ,ADMA error signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DEB_SIGEN ,Data end bit error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " DTO_SIGEN ,Data timeout error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 19. " CIE_SIGEN ,Command index error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " CEB_SIGEN ,Command end bit error signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " CTO_SIGEN ,Command timeout error signal status enable" "Disabled,Enabled"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x10 15. " NULL ,Null" "0,1"
|
|
else
|
|
bitfld.long 0x10 15. " NULL ,Null" "0,1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 10. " BSR_SIGEN ,Boot status received signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " OBI_SIGEN ,Out of band signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " CREM_SIGEN ,Card removal signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " CINS_SIGEN ,Card insertion signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " DMA_SIGEN ,DMA signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " BGE_SIGEN ,Block gap event signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TC_SIGEN ,Transfer completed signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " CC_SIGEN ,Command completed signal status enable" "Disabled,Enabled"
|
|
width 17.
|
|
if ((((d.l(ad:(ad:0x48060000+0x20c)))&0x4)==0x4)&&(((d.l(ad:(ad:0x48060000+0x230)))&0x1000000)==0x1000000))
|
|
rgroup.long 0x23c++0x3
|
|
line.long 0x00 "SD_AC12,AutoCMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error" "No error,Not issued"
|
|
bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error"
|
|
bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error"
|
|
bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed" "Executed,Not executed"
|
|
else
|
|
hgroup.long 0x23c++0x3
|
|
hide.long 0x00 "SD_AC12,AutoCMD12 Error Status Register"
|
|
endif
|
|
group.long 0x240++0x3
|
|
line.long 0x00 "SD_CAPA,Capabilities Register"
|
|
bitfld.long 0x00 28. " 64BIT ,64 Bit System Bus Support" "32-bit,64-bit"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V" "Not supported,Supported"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported"
|
|
rbitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
|
|
rbitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
|
|
rbitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
|
|
rbitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
|
|
bitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
|
|
bitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
|
|
bitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif (cpuis("DRA62*"))
|
|
hgroup.long 0x248++0x3
|
|
hide.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register"
|
|
else
|
|
group.long 0x248++0x3
|
|
line.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8 V"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0 V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3 V"
|
|
endif
|
|
wgroup.long 0x250++0x3
|
|
line.long 0x00 "SD_FE,Force Event Register for Error Interrupt Status"
|
|
bitfld.long 0x00 29. " FE_BADA ,Force Event bad acces to data space interrupt" "No effect,Force"
|
|
bitfld.long 0x00 28. " FE_CERR ,Force Event card error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FE_DEB ,Force Event Data end bit error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 17. " FE_CCRC ,Force Event Command CRC error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FE_CTO ,Force Event Command timeout error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by AUTOCMD12 index error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FE_ACIE ,Force Event AutoCMD12 index error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 3. " FE_ACEB ,Force Event AutoCMD12 end bit error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FE_ACCE ,Force Event AutoCMD12 CRC error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 1. " FE_ACTO ,Force Event AutoCMD12 timeout error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FE_ACNE ,Force Event AutoCMD12 not executed interrupt" "No effect,Force"
|
|
group.long 0x254++0x7
|
|
line.long 0x00 "SD_ADMAES,ADMA Error Status Register"
|
|
bitfld.long 0x00 2. " LME ,ADMA length mismatch error" "No error,Error"
|
|
bitfld.long 0x00 0.--1. " AES ,ADMA Error State" "Stop DMA,Stop DMA,Reserved,Transfer Data"
|
|
line.long 0x04 "SD_ADMASAL,ADMA System Address Low Bits Register"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register"
|
|
else
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register"
|
|
endif
|
|
rgroup.long 0x2fc++0x3
|
|
line.long 0x00 "SD_REV,Versions Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number"
|
|
bitfld.long 0x00 0. " SIS ,Slot Interrupt Status" "Low,High"
|
|
width 0xb
|
|
tree.end
|
|
tree "MMC/SD/SDIO 1"
|
|
base ad:0x481D8000
|
|
width 17.
|
|
sif !(cpuis("AM335*"))
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "SD_HL_REV,IP Revision Identifier Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
bitfld.long 0x00 11.--15. " R_RTL ,R_RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
line.long 0x04 "SD_HL_HWINFO,Hardware Configuration Register"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x04 2.--5. " MEM_SIZE ,Memory Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MERGE_MEM ,Merge memory" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 1. " MEM_SIZE ,Memory Size" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " MADMA_EN ,MADMA Enable" "Disabled,Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SD_HL_SYSCONFIG,Clock Management Configuration Register"
|
|
bitfld.long 0x00 4.--5. " STANDBYMODE ,Standby mode" "Mode0,Mode1,Mode2,Mode3"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Idle mode" "Mode0,Mode1,Mode2,Mode3"
|
|
bitfld.long 0x00 1. " FREEEMU ,Free EMU" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Soft reset" "No reset,Reset"
|
|
endif
|
|
width 17.
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "SD_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power management standby/wait control (when MADMA is enabled)" "Force-standby,No standby,Smart-standby,Smart-standby wake-up-capable"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "Inactive,Interface,Functional,Both"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle wake-up-capable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up capability enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "SD_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset status" "On-going,Done"
|
|
group.long 0x124++0x7
|
|
line.long 0x00 "SD_CSRE,Card Status Response Error Register"
|
|
width 17.
|
|
line.long 0x04 "SD_SYSTEST,System Test Register"
|
|
bitfld.long 0x04 16. " OBI ,Out of band interrupt data value input/output" "Low,High"
|
|
bitfld.long 0x04 15. " SDCD ,Card detect input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 14. " SDWP ,Write protect input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " WAKD ,Wake request input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 12. " SSB ,Set status bit" "Clear,Force"
|
|
bitfld.long 0x04 11. " D7D ,DAT7 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " D6D ,DAT6 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 9. " D5D ,DAT5 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 8. " D4D ,DAT4 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " D3D ,DAT3 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 6. " D2D ,DAT2 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 5. " D1D ,DAT1 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " D0D ,DAT0 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input"
|
|
bitfld.long 0x04 2. " CDAT ,CMD input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CDIR ,Control of the CMD pin direction" "Output,Input"
|
|
bitfld.long 0x04 0. " MCKD ,Clock input/output signal data value" "Low,High"
|
|
width 17.
|
|
group.long 0x12c++0x7
|
|
line.long 0x00 "SD_CON,Configuration Register"
|
|
bitfld.long 0x00 21. " SDMA_LNE ,Select Slave DMA Level/Edge Request" "Edge,Level"
|
|
bitfld.long 0x00 20. " DMA_MNS ,DMA Master or Slave selection(when MADMA is enabled)" "Slave,?..."
|
|
bitfld.long 0x00 19. " DDR ,Dual data rate transmission mode" "Single edge,Both"
|
|
textline " "
|
|
bitfld.long 0x00 18. " BOOT_CF0 ,Boot Status supported" "Not forced,Forced"
|
|
bitfld.long 0x00 17. " BOOT_ACK ,Boot acknowledge receive" "NO ACK,ACK"
|
|
bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained"
|
|
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
textline " "
|
|
bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines" "Not forced,Forced"
|
|
bitfld.long 0x00 12. " CEATA ,CE-ATA control mode" "Standard,CE-ATA"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTPL ,Control Power for SD_DAT1 line" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " DVAL ,Debounce period for filter SDCD" "33 us,231 us,1 ms,8.4 ms"
|
|
bitfld.long 0x00 8. " WPP ,Write protect polarity (SD and SDIO cards only)" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDP ,Card detect polarity (all cards)" "Active high,Active low"
|
|
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 6. " MIT ,MMC Interrupt Command" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DW8 ,8-bit mode select (MMC cars only)" "1-bit/4-bit,8-bit"
|
|
endif
|
|
bitfld.long 0x00 4. " MODE ,Mode select(all cards)" "Functional,SYSTEST"
|
|
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 3. " STR ,Stream command (MMC cars only)" "Block,Stream"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HR ,Broadcast host response (MMC cars only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent"
|
|
else
|
|
bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent"
|
|
endif
|
|
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 0. " OD ,Card open drain mode (MMC cars only)" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "SD_PWCNT,Power Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PWRCNT ,Power counter"
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x00 "SD_SDMASA,SDMA System Address Register"
|
|
if (((d.l(ad:0x481D8000+0x20c))&0x20)==0x20)
|
|
group.long 0x204++0x3
|
|
line.long 0x00 "SD_BLK,Transfer Length Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer"
|
|
hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size"
|
|
else
|
|
group.long 0x204++0x3
|
|
line.long 0x00 "SD_BLK,Transfer Length Configuration Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size"
|
|
endif
|
|
group.long 0x208++0x7
|
|
line.long 0x00 "SD_ARG,Command Argument Register"
|
|
line.long 0x04 "SD_CMD,Command and Transfer Mode Register"
|
|
bitfld.long 0x04 24.--29. " INDEX ,Command number sent to card" "Cmd0 or acmd0,Cmd1 or acmd1,Cmd2 or acmd2,Cmd3 or acmd3,Cmd4 or acmd4,Cmd5 or acmd5,Cmd6 or acmd6,Cmd7 or acmd7,Cmd8 or acmd8,Cmd9 or acmd9,Cmd10 or acmd10,Cmd11 or acmd11,Cmd12 or acmd12,Cmd13 or acmd13,Cmd14 or acmd14,Cmd15 or acmd15,Cmd16 or acmd16,Cmd17 or acmd17,Cmd18 or acmd18,Cmd19 or acmd19,Cmd20 or acmd20,Cmd21 or acmd21,Cmd22 or acmd22,Cmd23 or acmd23,Cmd24 or acmd24,Cmd25 or acmd25,Cmd26 or acmd26,Cmd27 or acmd27,Cmd28 or acmd28,Cmd29 or acmd29,Cmd30 or acmd30,Cmd31 or acmd31,Cmd32 or acmd32,Cmd33 or acmd33,Cmd34 or acmd34,Cmd35 or acmd35,Cmd36 or acmd36,Cmd37 or acmd37,Cmd38 or acmd38,Cmd39 or acmd39,Cmd40 or acmd40,Cmd41 or acmd41,Cmd42 or acmd42,Cmd43 or acmd43,Cmd44 or acmd44,Cmd45 or acmd45,Cmd46 or acmd46,Cmd47 or acmd47,Cmd48 or acmd48,Cmd49 or acmd49,Cmd50 or acmd50,Cmd51 or acmd51,Cmd52 or acmd52,Cmd53 or acmd53,Cmd54 or acmd54,Cmd55 or acmd55,Cmd56 or acmd56,Cmd57 or acmd57,Cmd58 or acmd58,Cmd59 or acmd59,Cmd60 or acmd60,Cmd61 or acmd61,Cmd62 or acmd62,Cmd63 or acmd63"
|
|
bitfld.long 0x04 22.--23. " CMD_TYPE ,Command type" "Other,Bus suspend,Function select,I/O Abort"
|
|
bitfld.long 0x04 21. " DP ,Data present select" "No data,Present"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CICE ,Command index check enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CCCE ,Command CRC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits (busy)"
|
|
textline " "
|
|
bitfld.long 0x04 5. " MSBS ,Multi/Single block select" "Single,Multi"
|
|
bitfld.long 0x04 4. " DDIR ,Data transfer direction" "Write,Read"
|
|
bitfld.long 0x04 2. " ACEN ,Auto CMD12 Enable (SD cards only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BCE ,Block Count Enable (Multiple block transfers only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DE ,DMA Enable" "Disabled,Enabled"
|
|
rgroup.long 0x210++0xf
|
|
line.long 0x00 "SD_RSP10,Command Response 0 and 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command Response[31:16]"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command Response[15:0]"
|
|
line.long 0x04 "SD_RSP32,Command Response 2 and 3 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " RSP3 ,Command Response[63:48]"
|
|
hexmask.long.word 0x04 0.--15. 1. " RSP2 ,Command Response[47:32]"
|
|
line.long 0x08 "SD_RSP54,Command Response 4 and 5 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " RSP5 ,Command Response[95:80]"
|
|
hexmask.long.word 0x08 0.--15. 1. " RSP4 ,Command Response[79:64]"
|
|
line.long 0x0c "SD_RSP76,Command Response 6 and 7 Register"
|
|
hexmask.long.word 0x0c 16.--31. 1. " RSP7 ,Command Response[127:112]"
|
|
hexmask.long.word 0x0c 0.--15. 1. " RSP6 ,Command Response[111:96]"
|
|
width 17.
|
|
group.long 0x220++0x3
|
|
line.long 0x00 "SD_DATA,Data Register"
|
|
if (((d.l(ad:0x481D8000+0x12c))&0x180)==0x180)
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "SD_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
|
|
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
|
|
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
|
|
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0"
|
|
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
|
|
bitfld.long 0x00 16. " CINS ,Detect card" "Detected,Not detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
|
|
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
|
|
elif (((d.l(ad:0x481D8000+0x12c))&0x180)==0x100)
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "SD_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
|
|
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
|
|
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
|
|
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0"
|
|
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
|
|
bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
|
|
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
|
|
elif (((d.l(ad:0x481D8000+0x12c))&0x180)==0x80)
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "SD_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
|
|
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
|
|
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
|
|
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0"
|
|
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
|
|
bitfld.long 0x00 16. " CI ,Detect card" "Detected,Not detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
|
|
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
|
|
else
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "SD_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
|
|
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
|
|
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
|
|
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0"
|
|
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
|
|
bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
|
|
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
|
|
endif
|
|
group.long 0x228++0x13
|
|
line.long 0x00 "SD_HCTL,Host Control Register"
|
|
bitfld.long 0x00 27. " OBWE ,Wake-up event enable for OBI" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " REM ,Wake-up event enable on SD card removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " INS ,Wake-up event enable on SD card insertion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " IWE ,Wake-up event enable on SD card interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " IBG ,Interrupt block at gap (in 4-bit mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RWC ,Read wait control (SDIO cards)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CR ,Transfer continue request" "No affect,Restart"
|
|
bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer mode,Stopped"
|
|
bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select" "Reserved,Reserved,Reserved,Reserved,Reserved,1.8V,3.0V,3.3V"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On"
|
|
bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "SDCD,CDTL"
|
|
bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " DMAS ,DMA Select" "Reserved,Reserved,32-bit ADMA2,?..."
|
|
bitfld.long 0x00 2. " HSPE ,High speed enable" "Normal,High"
|
|
bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit"
|
|
line.long 0x04 "SD_SYSCTL,SD System Control Register"
|
|
bitfld.long 0x04 26. " SRD ,Software reset for SD_DAT line" "No reset,Reset"
|
|
bitfld.long 0x04 25. " SRC ,Software reset for SD_CMD line" "No reset,Reset"
|
|
bitfld.long 0x04 24. " SRA ,Software reset for all" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCFx2^13,TCFx2^14,TCFx2^15,TCFx2^16,TCFx2^17,TCFx2^18,TCFx2^19,TCFx2^20,TCFx2^21,TCFx2^22,TCFx2^23,TCFx2^24,TCFx2^25,TCFx2^26,TCFx2^27,?..."
|
|
hexmask.long.word 0x04 6.--15. 1. " CLKD ,Clock frequency select"
|
|
bitfld.long 0x04 2. " CEN ,Clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable"
|
|
else
|
|
bitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable"
|
|
endif
|
|
bitfld.long 0x04 0. " ICE ,Internal clock enable" "Disabled,Enabled"
|
|
line.long 0x08 "SD_STAT,Interrupt Status Register"
|
|
eventfld.long 0x08 29. " BADA ,Bad access to data space interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 28. " CERR ,Card error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 25. " ADMAE ,ADMA error" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 24. " ACE ,Auto CMD12 error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 22. " DEB ,Data end bit error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 21. " DCRC ,Data CRC error" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 20. " DTO ,Data timeout error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 19. " CIE ,Command index error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 18. " CEB ,Command end bit error" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 17. " CCRC ,Command CRC error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 16. " CTO ,Command timeout error" "No interrupt,Interrupt"
|
|
sif (cpuis("DRA62*")||cpuis("AM355*"))
|
|
rbitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x08 7. " CREM ,Card removal" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " CINS ,Card insertion" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " BRR ,Buffer read ready" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 4. " BWR ,Buffer write ready" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DMA ,DMA interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " BGE ,Block gap event" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " TC ,Transfer completed" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " CC ,Command completed" "No interrupt,Interrupt"
|
|
width 17.
|
|
line.long 0x0c "SD_IE,Interrupt SD Enable Register"
|
|
bitfld.long 0x0c 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 25. " ADMA_ENABLE ,ADMA error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x0c 15. " NULL ,Null" "0,1"
|
|
else
|
|
bitfld.long 0x0c 15. " NULL ,Null" "0,1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0c 10. " BSR_ENABLE ,Boot status received interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 9. " OBI_ENABLE ,Out of band interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " CREM_ENABLE ,Card removal interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 6. " CINS_ENABLE ,Card insertion interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 3. " DMA_ENABLE ,DMA interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled"
|
|
line.long 0x10 "SD_ISE,Interrupt Signal Enable Register"
|
|
bitfld.long 0x10 29. " BADA_SIGEN ,Bad access to data space signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " CERR_SIGEN ,Card error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " ADMA_SIGEN ,ADMA error signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DEB_SIGEN ,Data end bit error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " DTO_SIGEN ,Data timeout error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 19. " CIE_SIGEN ,Command index error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " CEB_SIGEN ,Command end bit error signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " CTO_SIGEN ,Command timeout error signal status enable" "Disabled,Enabled"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x10 15. " NULL ,Null" "0,1"
|
|
else
|
|
bitfld.long 0x10 15. " NULL ,Null" "0,1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 10. " BSR_SIGEN ,Boot status received signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " OBI_SIGEN ,Out of band signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " CREM_SIGEN ,Card removal signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " CINS_SIGEN ,Card insertion signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " DMA_SIGEN ,DMA signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " BGE_SIGEN ,Block gap event signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TC_SIGEN ,Transfer completed signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " CC_SIGEN ,Command completed signal status enable" "Disabled,Enabled"
|
|
width 17.
|
|
if ((((d.l(ad:(ad:0x481D8000+0x20c)))&0x4)==0x4)&&(((d.l(ad:(ad:0x481D8000+0x230)))&0x1000000)==0x1000000))
|
|
rgroup.long 0x23c++0x3
|
|
line.long 0x00 "SD_AC12,AutoCMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error" "No error,Not issued"
|
|
bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error"
|
|
bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error"
|
|
bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed" "Executed,Not executed"
|
|
else
|
|
hgroup.long 0x23c++0x3
|
|
hide.long 0x00 "SD_AC12,AutoCMD12 Error Status Register"
|
|
endif
|
|
group.long 0x240++0x3
|
|
line.long 0x00 "SD_CAPA,Capabilities Register"
|
|
bitfld.long 0x00 28. " 64BIT ,64 Bit System Bus Support" "32-bit,64-bit"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V" "Not supported,Supported"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported"
|
|
rbitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
|
|
rbitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
|
|
rbitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
|
|
rbitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
|
|
bitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
|
|
bitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
|
|
bitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif (cpuis("DRA62*"))
|
|
hgroup.long 0x248++0x3
|
|
hide.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register"
|
|
else
|
|
group.long 0x248++0x3
|
|
line.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8 V"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0 V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3 V"
|
|
endif
|
|
wgroup.long 0x250++0x3
|
|
line.long 0x00 "SD_FE,Force Event Register for Error Interrupt Status"
|
|
bitfld.long 0x00 29. " FE_BADA ,Force Event bad acces to data space interrupt" "No effect,Force"
|
|
bitfld.long 0x00 28. " FE_CERR ,Force Event card error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FE_DEB ,Force Event Data end bit error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 17. " FE_CCRC ,Force Event Command CRC error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FE_CTO ,Force Event Command timeout error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by AUTOCMD12 index error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FE_ACIE ,Force Event AutoCMD12 index error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 3. " FE_ACEB ,Force Event AutoCMD12 end bit error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FE_ACCE ,Force Event AutoCMD12 CRC error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 1. " FE_ACTO ,Force Event AutoCMD12 timeout error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FE_ACNE ,Force Event AutoCMD12 not executed interrupt" "No effect,Force"
|
|
group.long 0x254++0x7
|
|
line.long 0x00 "SD_ADMAES,ADMA Error Status Register"
|
|
bitfld.long 0x00 2. " LME ,ADMA length mismatch error" "No error,Error"
|
|
bitfld.long 0x00 0.--1. " AES ,ADMA Error State" "Stop DMA,Stop DMA,Reserved,Transfer Data"
|
|
line.long 0x04 "SD_ADMASAL,ADMA System Address Low Bits Register"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register"
|
|
else
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register"
|
|
endif
|
|
rgroup.long 0x2fc++0x3
|
|
line.long 0x00 "SD_REV,Versions Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number"
|
|
bitfld.long 0x00 0. " SIS ,Slot Interrupt Status" "Low,High"
|
|
width 0xb
|
|
tree.end
|
|
sif (cpuis("AM387*")||cpuis("DRA62*"))
|
|
tree "MMC/SD/SDIO 2"
|
|
base ad:0x47810000
|
|
width 17.
|
|
sif !(cpuis("AM335*"))
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "SD_HL_REV,IP Revision Identifier Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
bitfld.long 0x00 11.--15. " R_RTL ,R_RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
line.long 0x04 "SD_HL_HWINFO,Hardware Configuration Register"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x04 2.--5. " MEM_SIZE ,Memory Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MERGE_MEM ,Merge memory" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 1. " MEM_SIZE ,Memory Size" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " MADMA_EN ,MADMA Enable" "Disabled,Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SD_HL_SYSCONFIG,Clock Management Configuration Register"
|
|
bitfld.long 0x00 4.--5. " STANDBYMODE ,Standby mode" "Mode0,Mode1,Mode2,Mode3"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Idle mode" "Mode0,Mode1,Mode2,Mode3"
|
|
bitfld.long 0x00 1. " FREEEMU ,Free EMU" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Soft reset" "No reset,Reset"
|
|
endif
|
|
width 17.
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "SD_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power management standby/wait control (when MADMA is enabled)" "Force-standby,No standby,Smart-standby,Smart-standby wake-up-capable"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "Inactive,Interface,Functional,Both"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle wake-up-capable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up capability enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "SD_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset status" "On-going,Done"
|
|
group.long 0x124++0x7
|
|
line.long 0x00 "SD_CSRE,Card Status Response Error Register"
|
|
width 17.
|
|
line.long 0x04 "SD_SYSTEST,System Test Register"
|
|
bitfld.long 0x04 16. " OBI ,Out of band interrupt data value input/output" "Low,High"
|
|
bitfld.long 0x04 15. " SDCD ,Card detect input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 14. " SDWP ,Write protect input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " WAKD ,Wake request input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 12. " SSB ,Set status bit" "Clear,Force"
|
|
bitfld.long 0x04 11. " D7D ,DAT7 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " D6D ,DAT6 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 9. " D5D ,DAT5 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 8. " D4D ,DAT4 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " D3D ,DAT3 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 6. " D2D ,DAT2 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 5. " D1D ,DAT1 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " D0D ,DAT0 input/output signal data value" "Low,High"
|
|
bitfld.long 0x04 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input"
|
|
bitfld.long 0x04 2. " CDAT ,CMD input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CDIR ,Control of the CMD pin direction" "Output,Input"
|
|
bitfld.long 0x04 0. " MCKD ,Clock input/output signal data value" "Low,High"
|
|
width 17.
|
|
group.long 0x12c++0x7
|
|
line.long 0x00 "SD_CON,Configuration Register"
|
|
bitfld.long 0x00 21. " SDMA_LNE ,Select Slave DMA Level/Edge Request" "Edge,Level"
|
|
bitfld.long 0x00 20. " DMA_MNS ,DMA Master or Slave selection(when MADMA is enabled)" "Slave,?..."
|
|
bitfld.long 0x00 19. " DDR ,Dual data rate transmission mode" "Single edge,Both"
|
|
textline " "
|
|
bitfld.long 0x00 18. " BOOT_CF0 ,Boot Status supported" "Not forced,Forced"
|
|
bitfld.long 0x00 17. " BOOT_ACK ,Boot acknowledge receive" "NO ACK,ACK"
|
|
bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained"
|
|
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
textline " "
|
|
bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines" "Not forced,Forced"
|
|
bitfld.long 0x00 12. " CEATA ,CE-ATA control mode" "Standard,CE-ATA"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTPL ,Control Power for SD_DAT1 line" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " DVAL ,Debounce period for filter SDCD" "33 us,231 us,1 ms,8.4 ms"
|
|
bitfld.long 0x00 8. " WPP ,Write protect polarity (SD and SDIO cards only)" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDP ,Card detect polarity (all cards)" "Active high,Active low"
|
|
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 6. " MIT ,MMC Interrupt Command" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DW8 ,8-bit mode select (MMC cars only)" "1-bit/4-bit,8-bit"
|
|
endif
|
|
bitfld.long 0x00 4. " MODE ,Mode select(all cards)" "Functional,SYSTEST"
|
|
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 3. " STR ,Stream command (MMC cars only)" "Block,Stream"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HR ,Broadcast host response (MMC cars only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent"
|
|
else
|
|
bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent"
|
|
endif
|
|
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x00 0. " OD ,Card open drain mode (MMC cars only)" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "SD_PWCNT,Power Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PWRCNT ,Power counter"
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x00 "SD_SDMASA,SDMA System Address Register"
|
|
if (((d.l(ad:0x47810000+0x20c))&0x20)==0x20)
|
|
group.long 0x204++0x3
|
|
line.long 0x00 "SD_BLK,Transfer Length Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer"
|
|
hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size"
|
|
else
|
|
group.long 0x204++0x3
|
|
line.long 0x00 "SD_BLK,Transfer Length Configuration Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size"
|
|
endif
|
|
group.long 0x208++0x7
|
|
line.long 0x00 "SD_ARG,Command Argument Register"
|
|
line.long 0x04 "SD_CMD,Command and Transfer Mode Register"
|
|
bitfld.long 0x04 24.--29. " INDEX ,Command number sent to card" "Cmd0 or acmd0,Cmd1 or acmd1,Cmd2 or acmd2,Cmd3 or acmd3,Cmd4 or acmd4,Cmd5 or acmd5,Cmd6 or acmd6,Cmd7 or acmd7,Cmd8 or acmd8,Cmd9 or acmd9,Cmd10 or acmd10,Cmd11 or acmd11,Cmd12 or acmd12,Cmd13 or acmd13,Cmd14 or acmd14,Cmd15 or acmd15,Cmd16 or acmd16,Cmd17 or acmd17,Cmd18 or acmd18,Cmd19 or acmd19,Cmd20 or acmd20,Cmd21 or acmd21,Cmd22 or acmd22,Cmd23 or acmd23,Cmd24 or acmd24,Cmd25 or acmd25,Cmd26 or acmd26,Cmd27 or acmd27,Cmd28 or acmd28,Cmd29 or acmd29,Cmd30 or acmd30,Cmd31 or acmd31,Cmd32 or acmd32,Cmd33 or acmd33,Cmd34 or acmd34,Cmd35 or acmd35,Cmd36 or acmd36,Cmd37 or acmd37,Cmd38 or acmd38,Cmd39 or acmd39,Cmd40 or acmd40,Cmd41 or acmd41,Cmd42 or acmd42,Cmd43 or acmd43,Cmd44 or acmd44,Cmd45 or acmd45,Cmd46 or acmd46,Cmd47 or acmd47,Cmd48 or acmd48,Cmd49 or acmd49,Cmd50 or acmd50,Cmd51 or acmd51,Cmd52 or acmd52,Cmd53 or acmd53,Cmd54 or acmd54,Cmd55 or acmd55,Cmd56 or acmd56,Cmd57 or acmd57,Cmd58 or acmd58,Cmd59 or acmd59,Cmd60 or acmd60,Cmd61 or acmd61,Cmd62 or acmd62,Cmd63 or acmd63"
|
|
bitfld.long 0x04 22.--23. " CMD_TYPE ,Command type" "Other,Bus suspend,Function select,I/O Abort"
|
|
bitfld.long 0x04 21. " DP ,Data present select" "No data,Present"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CICE ,Command index check enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " CCCE ,Command CRC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits (busy)"
|
|
textline " "
|
|
bitfld.long 0x04 5. " MSBS ,Multi/Single block select" "Single,Multi"
|
|
bitfld.long 0x04 4. " DDIR ,Data transfer direction" "Write,Read"
|
|
bitfld.long 0x04 2. " ACEN ,Auto CMD12 Enable (SD cards only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BCE ,Block Count Enable (Multiple block transfers only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DE ,DMA Enable" "Disabled,Enabled"
|
|
rgroup.long 0x210++0xf
|
|
line.long 0x00 "SD_RSP10,Command Response 0 and 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command Response[31:16]"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command Response[15:0]"
|
|
line.long 0x04 "SD_RSP32,Command Response 2 and 3 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " RSP3 ,Command Response[63:48]"
|
|
hexmask.long.word 0x04 0.--15. 1. " RSP2 ,Command Response[47:32]"
|
|
line.long 0x08 "SD_RSP54,Command Response 4 and 5 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " RSP5 ,Command Response[95:80]"
|
|
hexmask.long.word 0x08 0.--15. 1. " RSP4 ,Command Response[79:64]"
|
|
line.long 0x0c "SD_RSP76,Command Response 6 and 7 Register"
|
|
hexmask.long.word 0x0c 16.--31. 1. " RSP7 ,Command Response[127:112]"
|
|
hexmask.long.word 0x0c 0.--15. 1. " RSP6 ,Command Response[111:96]"
|
|
width 17.
|
|
group.long 0x220++0x3
|
|
line.long 0x00 "SD_DATA,Data Register"
|
|
if (((d.l(ad:0x47810000+0x12c))&0x180)==0x180)
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "SD_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
|
|
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
|
|
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
|
|
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0"
|
|
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
|
|
bitfld.long 0x00 16. " CINS ,Detect card" "Detected,Not detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
|
|
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
|
|
elif (((d.l(ad:0x47810000+0x12c))&0x180)==0x100)
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "SD_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
|
|
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
|
|
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
|
|
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0"
|
|
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
|
|
bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
|
|
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
|
|
elif (((d.l(ad:0x47810000+0x12c))&0x180)==0x80)
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "SD_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
|
|
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
|
|
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
|
|
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0"
|
|
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
|
|
bitfld.long 0x00 16. " CI ,Detect card" "Detected,Not detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
|
|
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
|
|
else
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "SD_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
|
|
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
|
|
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
|
|
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0"
|
|
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
|
|
bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
|
|
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
|
|
endif
|
|
group.long 0x228++0x13
|
|
line.long 0x00 "SD_HCTL,Host Control Register"
|
|
bitfld.long 0x00 27. " OBWE ,Wake-up event enable for OBI" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " REM ,Wake-up event enable on SD card removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " INS ,Wake-up event enable on SD card insertion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " IWE ,Wake-up event enable on SD card interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " IBG ,Interrupt block at gap (in 4-bit mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RWC ,Read wait control (SDIO cards)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CR ,Transfer continue request" "No affect,Restart"
|
|
bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer mode,Stopped"
|
|
bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select" "Reserved,Reserved,Reserved,Reserved,Reserved,1.8V,3.0V,3.3V"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On"
|
|
bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "SDCD,CDTL"
|
|
bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " DMAS ,DMA Select" "Reserved,Reserved,32-bit ADMA2,?..."
|
|
bitfld.long 0x00 2. " HSPE ,High speed enable" "Normal,High"
|
|
bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit"
|
|
line.long 0x04 "SD_SYSCTL,SD System Control Register"
|
|
bitfld.long 0x04 26. " SRD ,Software reset for SD_DAT line" "No reset,Reset"
|
|
bitfld.long 0x04 25. " SRC ,Software reset for SD_CMD line" "No reset,Reset"
|
|
bitfld.long 0x04 24. " SRA ,Software reset for all" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCFx2^13,TCFx2^14,TCFx2^15,TCFx2^16,TCFx2^17,TCFx2^18,TCFx2^19,TCFx2^20,TCFx2^21,TCFx2^22,TCFx2^23,TCFx2^24,TCFx2^25,TCFx2^26,TCFx2^27,?..."
|
|
hexmask.long.word 0x04 6.--15. 1. " CLKD ,Clock frequency select"
|
|
bitfld.long 0x04 2. " CEN ,Clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable"
|
|
else
|
|
bitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable"
|
|
endif
|
|
bitfld.long 0x04 0. " ICE ,Internal clock enable" "Disabled,Enabled"
|
|
line.long 0x08 "SD_STAT,Interrupt Status Register"
|
|
eventfld.long 0x08 29. " BADA ,Bad access to data space interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 28. " CERR ,Card error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 25. " ADMAE ,ADMA error" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 24. " ACE ,Auto CMD12 error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 22. " DEB ,Data end bit error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 21. " DCRC ,Data CRC error" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 20. " DTO ,Data timeout error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 19. " CIE ,Command index error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 18. " CEB ,Command end bit error" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 17. " CCRC ,Command CRC error" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 16. " CTO ,Command timeout error" "No interrupt,Interrupt"
|
|
sif (cpuis("DRA62*")||cpuis("AM355*"))
|
|
rbitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x08 7. " CREM ,Card removal" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " CINS ,Card insertion" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " BRR ,Buffer read ready" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 4. " BWR ,Buffer write ready" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DMA ,DMA interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " BGE ,Block gap event" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " TC ,Transfer completed" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " CC ,Command completed" "No interrupt,Interrupt"
|
|
width 17.
|
|
line.long 0x0c "SD_IE,Interrupt SD Enable Register"
|
|
bitfld.long 0x0c 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 25. " ADMA_ENABLE ,ADMA error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x0c 15. " NULL ,Null" "0,1"
|
|
else
|
|
bitfld.long 0x0c 15. " NULL ,Null" "0,1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0c 10. " BSR_ENABLE ,Boot status received interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 9. " OBI_ENABLE ,Out of band interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " CREM_ENABLE ,Card removal interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 6. " CINS_ENABLE ,Card insertion interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 3. " DMA_ENABLE ,DMA interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0c 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled"
|
|
line.long 0x10 "SD_ISE,Interrupt Signal Enable Register"
|
|
bitfld.long 0x10 29. " BADA_SIGEN ,Bad access to data space signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " CERR_SIGEN ,Card error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " ADMA_SIGEN ,ADMA error signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DEB_SIGEN ,Data end bit error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " DTO_SIGEN ,Data timeout error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 19. " CIE_SIGEN ,Command index error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " CEB_SIGEN ,Command end bit error signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " CTO_SIGEN ,Command timeout error signal status enable" "Disabled,Enabled"
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x10 15. " NULL ,Null" "0,1"
|
|
else
|
|
bitfld.long 0x10 15. " NULL ,Null" "0,1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 10. " BSR_SIGEN ,Boot status received signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " OBI_SIGEN ,Out of band signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " CREM_SIGEN ,Card removal signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " CINS_SIGEN ,Card insertion signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " DMA_SIGEN ,DMA signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " BGE_SIGEN ,Block gap event signal status enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TC_SIGEN ,Transfer completed signal status enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " CC_SIGEN ,Command completed signal status enable" "Disabled,Enabled"
|
|
width 17.
|
|
if ((((d.l(ad:(ad:0x47810000+0x20c)))&0x4)==0x4)&&(((d.l(ad:(ad:0x47810000+0x230)))&0x1000000)==0x1000000))
|
|
rgroup.long 0x23c++0x3
|
|
line.long 0x00 "SD_AC12,AutoCMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error" "No error,Not issued"
|
|
bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error"
|
|
bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error"
|
|
bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed" "Executed,Not executed"
|
|
else
|
|
hgroup.long 0x23c++0x3
|
|
hide.long 0x00 "SD_AC12,AutoCMD12 Error Status Register"
|
|
endif
|
|
group.long 0x240++0x3
|
|
line.long 0x00 "SD_CAPA,Capabilities Register"
|
|
bitfld.long 0x00 28. " 64BIT ,64 Bit System Bus Support" "32-bit,64-bit"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V" "Not supported,Supported"
|
|
textline " "
|
|
sif (cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported"
|
|
rbitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
|
|
rbitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
|
|
rbitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
|
|
rbitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
|
|
bitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
|
|
bitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
|
|
bitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif (cpuis("DRA62*"))
|
|
hgroup.long 0x248++0x3
|
|
hide.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register"
|
|
else
|
|
group.long 0x248++0x3
|
|
line.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8 V"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0 V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3 V"
|
|
endif
|
|
wgroup.long 0x250++0x3
|
|
line.long 0x00 "SD_FE,Force Event Register for Error Interrupt Status"
|
|
bitfld.long 0x00 29. " FE_BADA ,Force Event bad acces to data space interrupt" "No effect,Force"
|
|
bitfld.long 0x00 28. " FE_CERR ,Force Event card error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FE_DEB ,Force Event Data end bit error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 17. " FE_CCRC ,Force Event Command CRC error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FE_CTO ,Force Event Command timeout error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by AUTOCMD12 index error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FE_ACIE ,Force Event AutoCMD12 index error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 3. " FE_ACEB ,Force Event AutoCMD12 end bit error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FE_ACCE ,Force Event AutoCMD12 CRC error interrupt" "No effect,Force"
|
|
bitfld.long 0x00 1. " FE_ACTO ,Force Event AutoCMD12 timeout error interrupt" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FE_ACNE ,Force Event AutoCMD12 not executed interrupt" "No effect,Force"
|
|
group.long 0x254++0x7
|
|
line.long 0x00 "SD_ADMAES,ADMA Error Status Register"
|
|
bitfld.long 0x00 2. " LME ,ADMA length mismatch error" "No error,Error"
|
|
bitfld.long 0x00 0.--1. " AES ,ADMA Error State" "Stop DMA,Stop DMA,Reserved,Transfer Data"
|
|
line.long 0x04 "SD_ADMASAL,ADMA System Address Low Bits Register"
|
|
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register"
|
|
else
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register"
|
|
endif
|
|
rgroup.long 0x2fc++0x3
|
|
line.long 0x00 "SD_REV,Versions Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number"
|
|
bitfld.long 0x00 0. " SIS ,Slot Interrupt Status" "Low,High"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("AM387*"))
|
|
tree "PATA (Parallel ATA)"
|
|
base ad:0x481CA000
|
|
width 10.
|
|
group.word 0x0++0x3 "ATA Bus Master Interface BMI DMA Engine Registers"
|
|
line.word 0x0 "BMICP,BMI Control Register"
|
|
bitfld.word 0x0 3. " DMADIR ,DMA data transfer direction" "Read,Write"
|
|
bitfld.word 0x0 0. " DMASTART ,DMA start/stop control" "Stopped,Started"
|
|
line.word 0x2 "BMISP,BMI Status Register"
|
|
eventfld.word 0x2 3. " IORDYINT ,IORDY timeout" "No timeout,Timeout"
|
|
eventfld.word 0x2 2. " INTRSTAT ,ATA interrupt status" "Inactive,Active"
|
|
textline " "
|
|
eventfld.word 0x2 1. " DMAERROR ,DMA error" "No error,Error"
|
|
bitfld.word 0x2 0. " IDEACT ,ATA active" "Inactive,Active"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "BMIDTP,BMI PRD Table Pointer Register"
|
|
hexmask.long 0x0 2.--31. 0x4 " BMIDTP ,Descriptor base address pointer"
|
|
group.word 0x40++0x1 "ATA Configuration Registers"
|
|
line.word 0x0 "IDETIMP,ATA (IDE) Timing Register"
|
|
bitfld.word 0x0 15. " IDEEN ,ATA decode enable" "Disabled,Enabled"
|
|
sif (!cpuis("DRA6*"))
|
|
bitfld.word 0x0 6. " PREPOST1 ,Device 1 PIO prefetch and postwrite enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x0 5. " RDYSEN1 ,Device 1 IORDY sample point enable" "Disabled,Enabled"
|
|
sif (!cpuis("DRA6*"))
|
|
bitfld.word 0x0 2. " PREPOST0 ,Device 0 PIO prefetch and postwrite enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x0 1. " RDYSEN0 ,Device 0 IORDY sample point enable" "Disabled,Enabled"
|
|
rgroup.byte 0x47++0x0
|
|
line.byte 0x0 "IDESTAT,ATA Controller Status Register"
|
|
bitfld.byte 0x0 6. " ATA.DMARQ ,Exact value of the ATA.DMARQ signal line being sent from the device to the host controller" "Low,High"
|
|
bitfld.byte 0x0 5. " INTRQ ,Exact value of the INTRQ signal line being sent from the device to the host controller" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x0 4. " ATA.DMACKN ,Exact value of the ATA.DMACKN signal line being sent from the host controller to the device" "Low,High"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "UDMACTL,Ultra-DMA Control Register"
|
|
bitfld.word 0x0 1. " UDMAP1 ,Primary device 1 ultra-DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x0 0. " UDMAP0 ,Primary device 0 ultra-DMA enable" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "MISCCTL,Miscellaneous Control Register"
|
|
bitfld.long 0x0 20.--22. " HWNHLD1P ,/ATA.DIOW write data hold time for slave controller" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x0 16.--18. " HWNHLD0P ,/ATA.DIOW write data hold time for master controller" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
sif (cpuis("DRx45*")||cpuis("DRA6*")||(cpu()=="DRA442")||(cpu()=="DRA444")||(cpu()=="DRA446")||(cpu()=="DRx440")||(cpu()=="DRx442")||(cpu()=="DRx443")||(cpu()=="DRx444")||(cpu()=="DRx445")||(cpu()=="DRx446")||(cpu()=="DRx447")||(cpu()=="DRx449"))
|
|
bitfld.long 0x0 9. " RSTMODEP ,Reset mode" "Reserved,Primary controller"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 8. " RESETP ,Reset pin signal for primary controller" "Negated,Asserted"
|
|
bitfld.long 0x0 0. " TIMORIDE ,ATA interface timing control" "Internal,Override registers"
|
|
group.long 0x54++0x27
|
|
line.long 0x0 "REGSTB,Task File Register Strobe Timing Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. " REGSTB1P ,Register access slave strobe width for the controller"
|
|
hexmask.long.byte 0x0 0.--6. 1. " REGSTB0P ,Register access master strobe width for the controller"
|
|
line.long 0x4 "REGRCVR,Task File Register Recovery Timing Register"
|
|
hexmask.long.byte 0x4 8.--14. 1. " REGRCV1P ,Register access slave recovery time for the controller"
|
|
hexmask.long.byte 0x4 0.--6. 1. " REGRCV0P ,Register access master recovery time for the controller"
|
|
line.long 0x8 "DATSTB,Data Register Access PIO Strobe Timing Register"
|
|
hexmask.long.byte 0x8 8.--14. 1. " DATSTB1P ,Slave data register access strobe width for the controller"
|
|
hexmask.long.byte 0x8 0.--6. 1. " DATSTB0P ,Master data register access strobe width for the controller"
|
|
line.long 0xc "DATRCVR,Data Register Access PIO Recovery Timing Register"
|
|
hexmask.long.byte 0xc 8.--14. 1. " DMARCV1P ,Slave DMA access recovery time for the controller"
|
|
hexmask.long.byte 0xc 0.--6. 1. " DMARCV0P ,Master DMA access recovery time for the controller"
|
|
line.long 0x10 "DMASTB,Multiword-DMA Strobe Timing Register"
|
|
hexmask.long.byte 0x10 8.--14. 1. " DMASTB1P ,Slave DMA access strobe width for the controller"
|
|
hexmask.long.byte 0x10 0.--6. 1. " DMASTB0P ,Master DMA access strobe width for the controller"
|
|
line.long 0x14 "DMARCVR,Multiword-DMA Recovery Timing Register"
|
|
hexmask.long.byte 0x14 8.--14. 1. " DMARCV1P ,Slave DMA access recovery time for the controller"
|
|
hexmask.long.byte 0x14 0.--6. 1. " DMARCV0P ,Master DMA access recovery time for the controller"
|
|
line.long 0x18 "UDMASTB,Ultra-DMA Strobe Timing Register"
|
|
bitfld.long 0x18 8.--11. " UDMSTB1P ,Slave ultra-DMA access strobe width for the controller" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x18 0.--3. " UDMSTB0P ,Master ultra-DMA access strobe width for the controller" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
line.long 0x1c "UDMATRP,Ultra-DMA Ready-to-Pause Timing Register"
|
|
bitfld.long 0x1c 8.--12. " UDMTRP1P ,Slave ultra-DMA ready-to-pause time for the controller" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
bitfld.long 0x1c 0.--4. " UDMTRP0P ,Master ultra-DMA ready-to-pause time for the controller" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
line.long 0x20 "UDMATENV,Ultra-DMA Timing Envelope Register"
|
|
bitfld.long 0x20 8.--11. " UDMTNV1P ,Slave ultra-DMA tenv timing parameter for the controller" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x20 0.--3. " UDMTNV0P ,Master ultra-DMA tenv timing parameter for the controller" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
line.long 0x24 "IORDYTMP,IORDY Timer Register"
|
|
hexmask.long.tbyte 0x24 0.--17. 1. " IORDYTMP ,IORDY timeout value for the ATA controller"
|
|
sif (cpuis("DRA6*"))
|
|
rgroup.long 0x3f8++0x3
|
|
line.long 0x00 "REVISION,ATA IP Revision Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SOURCE_IP ,Source of ATA IP"
|
|
hexmask.long.word 0x00 0.--15. 1. " REV_IP ,ATA IP Revision number"
|
|
group.long 0x3fc++0x3
|
|
line.long 0x00 "PWRMGMT,ATA Power Management Register"
|
|
bitfld.long 0x00 0. "MSTANDBY,Indicate whether ATA peripheral can be placed in IDLE mode" "No,Yes"
|
|
endif
|
|
width 16.
|
|
tree "ATA Controller Registers in the Attached Device"
|
|
group.byte 0x1f0++0x0
|
|
line.byte 0x0 "DATA,PIO Read/Write Data Register Access"
|
|
rgroup.byte 0x1f1++0x0
|
|
line.byte 0x0 "ERROR,Error Register"
|
|
wgroup.byte 0x1f1++0x0
|
|
line.byte 0x0 "FEATURES,Features Register"
|
|
group.byte 0x1f2++0x4
|
|
line.byte 0x0 "SECTOR_COUNT,Sector Count Register"
|
|
line.byte 0x1 "LBA_LOW,LBA Low"
|
|
line.byte 0x2 "LBA_MID,LBA Mid"
|
|
line.byte 0x3 "LBA_HIGH,LBA High"
|
|
line.byte 0x4 "DEVICE,Device Register"
|
|
rgroup.byte 0x1f7++0x0
|
|
line.byte 0x0 "STATUS,Status Register"
|
|
wgroup.byte 0x1f7++0x0
|
|
line.byte 0x0 "COMMAND,Command Register"
|
|
wgroup.byte 0x3f6++0x0
|
|
line.byte 0x0 "ALT_STATUS,Alternate Status Register"
|
|
rgroup.byte 0x3f6++0x0
|
|
line.byte 0x0 "DEVICE_CONTROL,Device Control Register"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "PCIe (Peripheral Component Interconnect Express)"
|
|
base ad:0x51000000
|
|
width 21.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PID,Peripheral Version and ID"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID Register Format Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function code of the peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version number (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major revision code (X)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom code" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x04++0x13
|
|
line.long 0x00 "CMD_STATUS,Command Status"
|
|
bitfld.long 0x00 10.--11. " OCP_STANDBY ,OCP standby mode" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " OCP_IDLE ,OCP idle mode" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DBI_CS2 ,Enable writing to BAR mask registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " APP_RETRY_EN ,Application Request Retry Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POSTED_WR_EN ,Posted Write Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IB_XLT_EN ,Inbound Address Translation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OB_XLT_EN ,Outbound Address Translation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LTSSM_EN ,Link Transitioning Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CFG_SETUP,Config Transaction Setup"
|
|
bitfld.long 0x04 24. " CFG_TYPE ,Configuration Type for outbound configuration accesses" "Type 0,Type 1"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CFG_BUS ,PCIe Bus number for outbound configuration accesses"
|
|
textline " "
|
|
bitfld.long 0x04 8.--12. " CFG_DEVICE ,PCIe Device number for outbound configuration accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--2. " CFG_FUNC ,PCIe Function number for outbound configuration accesses" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "IOBASE,IO TLP Base"
|
|
hexmask.long.tbyte 0x08 12.--31. 1. " IOBASE ,Outgoing IO"
|
|
line.long 0x0C "TLPCFG,TLP Attribute Configuration"
|
|
bitfld.long 0x0C 1. " RELAXED ,Relaxed Ordering" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " NO_SNOOP ,No Snoop Attribute" "Disabled,Enabled"
|
|
line.long 0x10 "RSTCMD,Reset Command and Status"
|
|
bitfld.long 0x10 16. " FLUSH_N ,Bridge Flush Status" "Not pending,Pending"
|
|
bitfld.long 0x10 0. " INIT_RST ,Downstream hot reset sequence" "No effect,Reset"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "PMCMD,Power Management Command"
|
|
bitfld.long 0x00 1. " PM_XMT_TURNOFF ,PM_TURNOFF message transmit (RC mode)" "No effect,Transmit"
|
|
bitfld.long 0x00 0. " PM_XMT_PME ,PM_PME message transmit (EP mode)" "No effect,Transmit"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PMCFG,Power Management Configuration"
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rbitfld.long 0x00 2. " RDY_ENTR_L23 ,Read L2/L3 entry readiness" "Not ready,Ready"
|
|
else
|
|
bitfld.long 0x00 2. " RDY_ENTR_L23 ,Read L2/L3 entry readiness" "Not ready,Ready"
|
|
endif
|
|
bitfld.long 0x00 0. " ENTR_L23 ,L2/L3 ready state entry enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "ACT_STATUS,Activity Status"
|
|
bitfld.long 0x00 1. " OB_NOT_EMPTY ,Outbound buffers not empty" "Empty,Not Empty"
|
|
bitfld.long 0x00 0. " IB_NOT_EMPTY ,Inbound buffers not empty" "Empty,Not Empty"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "OB_SIZE,Outbound Size"
|
|
bitfld.long 0x00 0.--2. " OB_SIZE ,Outbound translation window size" "1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB"
|
|
line.long 0x04 "DIAG_CTRL,Diagnostic Control"
|
|
bitfld.long 0x04 1. " INV_ECRC ,Inversion of LSB of ECRC for next one packet" "Not forced,Forced"
|
|
bitfld.long 0x04 0. " INV_LCRC ,Inversion of LSB of LCRC for next one packet" "Not forced,Forced"
|
|
line.long 0x08 "ENDIAN,Endian Mode"
|
|
bitfld.long 0x08 0.--1. " ENDIAN ,Endian" "0,1,2,3"
|
|
line.long 0x0C "PRIORITY,CBA Transaction Priority"
|
|
bitfld.long 0x0C 16. " MST_PRIV ,Value on master transactions" "0,1"
|
|
bitfld.long 0x0C 8.--11. " MST_PRIVID ,Value on master transactions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
bitfld.long 0x0C 0.--2. " MST_PRIORITY ,Priority level for each inbound transaction on the CBA master port" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0C 0.--1. " MST_PRIORITY ,Priority level for each inbound transaction on the CBA master port" "0,1,2,3"
|
|
endif
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "IRQ_EOI,End of Interrupt"
|
|
bitfld.long 0x00 0.--1. " EOI ,End of interrupt for each interrupt" "0,1,2,3"
|
|
line.long 0x04 "MSI_IRQ,MSI Interrupt IRQ"
|
|
bitfld.long 0x04 31. " MSI_IRQ[31] ,MSI Interrupt Request [31]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " MSI_IRQ[30] ,MSI Interrupt Request [30]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " MSI_IRQ[29] ,MSI Interrupt Request [29]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 28. " MSI_IRQ[28] ,MSI Interrupt Request [28]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 27. " MSI_IRQ[27] ,MSI Interrupt Request [27]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " MSI_IRQ[26] ,MSI Interrupt Request [26]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 25. " MSI_IRQ[25] ,MSI Interrupt Request [25]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " MSI_IRQ[24] ,MSI Interrupt Request [24]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 23. " MSI_IRQ[23] ,MSI Interrupt Request [23]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 22. " MSI_IRQ[22] ,MSI Interrupt Request [22]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " MSI_IRQ[21] ,MSI Interrupt Request [21]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " MSI_IRQ[20] ,MSI Interrupt Request [20]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MSI_IRQ[19] ,MSI Interrupt Request [19]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " MSI_IRQ[18] ,MSI Interrupt Request [18]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " MSI_IRQ[17] ,MSI Interrupt Request [17]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 16. " MSI_IRQ[16] ,MSI Interrupt Request [16]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 15. " MSI_IRQ[15] ,MSI Interrupt Request [15]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " MSI_IRQ[14] ,MSI Interrupt Request [14]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " MSI_IRQ[13] ,MSI Interrupt Request [13]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " MSI_IRQ[12] ,MSI Interrupt Request [12]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " MSI_IRQ[11] ,MSI Interrupt Request [11]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MSI_IRQ[10] ,MSI Interrupt Request [10]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " MSI_IRQ[9] ,MSI Interrupt Request [9]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " MSI_IRQ[8] ,MSI Interrupt Request [8]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSI_IRQ[7] ,MSI Interrupt Request [7]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " MSI_IRQ[6] ,MSI Interrupt Request [6]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " MSI_IRQ[5] ,MSI Interrupt Request [5]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " MSI_IRQ[4] ,MSI Interrupt Request [4]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " MSI_IRQ[3] ,MSI Interrupt Request [3]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " MSI_IRQ[2] ,MSI Interrupt Request [2]" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MSI_IRQ[1] ,MSI Interrupt Request [1]" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " MSI_IRQ[0] ,MSI Interrupt Request [0]" "No interrupt,Interrupt"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "EP_IRQ_STATUS,Endpoint Interrupt Request Set"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EP_IRQ_STATUS_set/clr ,EP Interrupt Request Status set/clr" "Not asserted,Asserted"
|
|
group.long 0x70++0xF
|
|
line.long 0x0 "GPR0,General Purpose 0"
|
|
group.long 0x70++0xF
|
|
line.long 0x4 "GPR1,General Purpose 1"
|
|
group.long 0x70++0xF
|
|
line.long 0x8 "GPR2,General Purpose 2"
|
|
group.long 0x70++0xF
|
|
line.long 0xC "GPR3,General Purpose 3"
|
|
group.long 0x100++0xF
|
|
line.long 0x00 "MSI0_STATUS_RAW,MSI 0 Interrupt Raw Status"
|
|
bitfld.long 0x00 31. " MSI0_RAW_STATUS[31] ,MSI Interrupt 31 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " MSI0_RAW_STATUS[30] ,MSI Interrupt 30 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MSI0_RAW_STATUS[29] ,MSI Interrupt 29 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " MSI0_RAW_STATUS[28] ,MSI Interrupt 28 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MSI0_RAW_STATUS[27] ,MSI Interrupt 27 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " MSI0_RAW_STATUS[26] ,MSI Interrupt 26 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MSI0_RAW_STATUS[25] ,MSI Interrupt 25 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " MSI0_RAW_STATUS[24] ,MSI Interrupt 24 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MSI0_RAW_STATUS[23] ,MSI Interrupt 23 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " MSI0_RAW_STATUS[22] ,MSI Interrupt 22 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MSI0_RAW_STATUS[21] ,MSI Interrupt 21 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " MSI0_RAW_STATUS[20] ,MSI Interrupt 20 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MSI0_RAW_STATUS[19] ,MSI Interrupt 19 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " MSI0_RAW_STATUS[18] ,MSI Interrupt 18 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MSI0_RAW_STATUS[17] ,MSI Interrupt 17 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " MSI0_RAW_STATUS[16] ,MSI Interrupt 16 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSI0_RAW_STATUS[15] ,MSI Interrupt 15 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " MSI0_RAW_STATUS[14] ,MSI Interrupt 14 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MSI0_RAW_STATUS[13] ,MSI Interrupt 13 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " MSI0_RAW_STATUS[12] ,MSI Interrupt 12 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MSI0_RAW_STATUS[11] ,MSI Interrupt 11 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " MSI0_RAW_STATUS[10] ,MSI Interrupt 10 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MSI0_RAW_STATUS[9] ,MSI Interrupt 9 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " MSI0_RAW_STATUS[8] ,MSI Interrupt 8 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSI0_RAW_STATUS[7] ,MSI Interrupt 7 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " MSI0_RAW_STATUS[6] ,MSI Interrupt 6 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MSI0_RAW_STATUS[5] ,MSI Interrupt 5 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " MSI0_RAW_STATUS[4] ,MSI Interrupt 4 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSI0_RAW_STATUS[3] ,MSI Interrupt 3 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " MSI0_RAW_STATUS[2] ,MSI Interrupt 2 Raw Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSI0_RAW_STATUS[1] ,MSI Interrupt 1 Raw Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MSI0_RAW_STATUS[0] ,MSI Interrupt 0 Raw Status" "No interrupt,Interrupt"
|
|
line.long 0x04 "MSI0_IRQ_STATUS,MSI 0 Interrupt Enabled Status"
|
|
bitfld.long 0x04 31. " MSI0_IRQ_STATUS[31] ,MSI Interrupt 31 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " MSI0_IRQ_STATUS[30] ,MSI Interrupt 30 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 29. " MSI0_IRQ_STATUS[29] ,MSI Interrupt 29 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " MSI0_IRQ_STATUS[28] ,MSI Interrupt 28 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MSI0_IRQ_STATUS[27] ,MSI Interrupt 27 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " MSI0_IRQ_STATUS[26] ,MSI Interrupt 26 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 25. " MSI0_IRQ_STATUS[25] ,MSI Interrupt 25 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " MSI0_IRQ_STATUS[24] ,MSI Interrupt 24 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " MSI0_IRQ_STATUS[23] ,MSI Interrupt 23 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " MSI0_IRQ_STATUS[22] ,MSI Interrupt 22 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 21. " MSI0_IRQ_STATUS[21] ,MSI Interrupt 21 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " MSI0_IRQ_STATUS[20] ,MSI Interrupt 20 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MSI0_IRQ_STATUS[19] ,MSI Interrupt 19 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " MSI0_IRQ_STATUS[18] ,MSI Interrupt 18 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 17. " MSI0_IRQ_STATUS[17] ,MSI Interrupt 17 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " MSI0_IRQ_STATUS[16] ,MSI Interrupt 16 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MSI0_IRQ_STATUS[15] ,MSI Interrupt 15 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " MSI0_IRQ_STATUS[14] ,MSI Interrupt 14 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " MSI0_IRQ_STATUS[13] ,MSI Interrupt 13 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " MSI0_IRQ_STATUS[12] ,MSI Interrupt 12 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " MSI0_IRQ_STATUS[11] ,MSI Interrupt 11 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " MSI0_IRQ_STATUS[10] ,MSI Interrupt 10 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " MSI0_IRQ_STATUS[9] ,MSI Interrupt 9 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " MSI0_IRQ_STATUS[8] ,MSI Interrupt 8 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSI0_IRQ_STATUS[7] ,MSI Interrupt 7 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " MSI0_IRQ_STATUS[6] ,MSI Interrupt 6 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " MSI0_IRQ_STATUS[5] ,MSI Interrupt 5 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " MSI0_IRQ_STATUS[4] ,MSI Interrupt 4 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MSI0_IRQ_STATUS[3] ,MSI Interrupt 3 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " MSI0_IRQ_STATUS[2] ,MSI Interrupt 2 Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MSI0_IRQ_STATUS[1] ,MSI Interrupt 1 Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " MSI0_IRQ_STATUS[0] ,MSI Interrupt 0 Status" "No interrupt,Interrupt"
|
|
line.long 0x08 "MSI0_IRQ_ENABLE_SET,MSI 0 Interrupt Enable Set"
|
|
bitfld.long 0x08 31. " MSI0_IRQ_ENABLE_SET[31] ,MSI Interrupt 31 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " MSI0_IRQ_ENABLE_SET[30] ,MSI Interrupt 30 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " MSI0_IRQ_ENABLE_SET[29] ,MSI Interrupt 29 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " MSI0_IRQ_ENABLE_SET[28] ,MSI Interrupt 28 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " MSI0_IRQ_ENABLE_SET[27] ,MSI Interrupt 27 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " MSI0_IRQ_ENABLE_SET[26] ,MSI Interrupt 26 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " MSI0_IRQ_ENABLE_SET[25] ,MSI Interrupt 25 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " MSI0_IRQ_ENABLE_SET[24] ,MSI Interrupt 24 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " MSI0_IRQ_ENABLE_SET[23] ,MSI Interrupt 23 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " MSI0_IRQ_ENABLE_SET[22] ,MSI Interrupt 22 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " MSI0_IRQ_ENABLE_SET[21] ,MSI Interrupt 21 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " MSI0_IRQ_ENABLE_SET[20] ,MSI Interrupt 20 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " MSI0_IRQ_ENABLE_SET[19] ,MSI Interrupt 19 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " MSI0_IRQ_ENABLE_SET[18] ,MSI Interrupt 18 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " MSI0_IRQ_ENABLE_SET[17] ,MSI Interrupt 17 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " MSI0_IRQ_ENABLE_SET[16] ,MSI Interrupt 16 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " MSI0_IRQ_ENABLE_SET[15] ,MSI Interrupt 15 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " MSI0_IRQ_ENABLE_SET[14] ,MSI Interrupt 14 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " MSI0_IRQ_ENABLE_SET[13] ,MSI Interrupt 13 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " MSI0_IRQ_ENABLE_SET[12] ,MSI Interrupt 12 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " MSI0_IRQ_ENABLE_SET[11] ,MSI Interrupt 11 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " MSI0_IRQ_ENABLE_SET[10] ,MSI Interrupt 10 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " MSI0_IRQ_ENABLE_SET[9] ,MSI Interrupt 9 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " MSI0_IRQ_ENABLE_SET[8] ,MSI Interrupt 8 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSI0_IRQ_ENABLE_SET[7] ,MSI Interrupt 7 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " MSI0_IRQ_ENABLE_SET[6] ,MSI Interrupt 6 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSI0_IRQ_ENABLE_SET[5] ,MSI Interrupt 5 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " MSI0_IRQ_ENABLE_SET[4] ,MSI Interrupt 4 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " MSI0_IRQ_ENABLE_SET[3] ,MSI Interrupt 3 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " MSI0_IRQ_ENABLE_SET[2] ,MSI Interrupt 2 Set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MSI0_IRQ_ENABLE_SET[1] ,MSI Interrupt 1 Set" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " MSI0_IRQ_ENABLE_SET[0] ,MSI Interrupt 0 Set" "Disabled,Enabled"
|
|
line.long 0x0C "MSI0_IRQ_ENABLE_CLR,MSI 0 Interrupt Enable Clear"
|
|
eventfld.long 0x0C 31. " MSI0_IRQ_ENABLE_CLR[31] ,MSI Interrupt 31 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 30. " MSI0_IRQ_ENABLE_CLR[30] ,MSI Interrupt 30 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 29. " MSI0_IRQ_ENABLE_CLR[29] ,MSI Interrupt 29 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 28. " MSI0_IRQ_ENABLE_CLR[28] ,MSI Interrupt 28 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 27. " MSI0_IRQ_ENABLE_CLR[27] ,MSI Interrupt 27 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 26. " MSI0_IRQ_ENABLE_CLR[26] ,MSI Interrupt 26 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " MSI0_IRQ_ENABLE_CLR[25] ,MSI Interrupt 25 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 24. " MSI0_IRQ_ENABLE_CLR[24] ,MSI Interrupt 24 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 23. " MSI0_IRQ_ENABLE_CLR[23] ,MSI Interrupt 23 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 22. " MSI0_IRQ_ENABLE_CLR[22] ,MSI Interrupt 22 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 21. " MSI0_IRQ_ENABLE_CLR[21] ,MSI Interrupt 21 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 20. " MSI0_IRQ_ENABLE_CLR[20] ,MSI Interrupt 20 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " MSI0_IRQ_ENABLE_CLR[19] ,MSI Interrupt 19 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 18. " MSI0_IRQ_ENABLE_CLR[18] ,MSI Interrupt 18 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 17. " MSI0_IRQ_ENABLE_CLR[17] ,MSI Interrupt 17 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 16. " MSI0_IRQ_ENABLE_CLR[16] ,MSI Interrupt 16 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 15. " MSI0_IRQ_ENABLE_CLR[15] ,MSI Interrupt 15 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 14. " MSI0_IRQ_ENABLE_CLR[14] ,MSI Interrupt 14 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " MSI0_IRQ_ENABLE_CLR[13] ,MSI Interrupt 13 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 12. " MSI0_IRQ_ENABLE_CLR[12] ,MSI Interrupt 12 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 11. " MSI0_IRQ_ENABLE_CLR[11] ,MSI Interrupt 11 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 10. " MSI0_IRQ_ENABLE_CLR[10] ,MSI Interrupt 10 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 9. " MSI0_IRQ_ENABLE_CLR[9] ,MSI Interrupt 9 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 8. " MSI0_IRQ_ENABLE_CLR[8] ,MSI Interrupt 8 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " MSI0_IRQ_ENABLE_CLR[7] ,MSI Interrupt 7 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 6. " MSI0_IRQ_ENABLE_CLR[6] ,MSI Interrupt 6 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 5. " MSI0_IRQ_ENABLE_CLR[5] ,MSI Interrupt 5 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 4. " MSI0_IRQ_ENABLE_CLR[4] ,MSI Interrupt 4 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 3. " MSI0_IRQ_ENABLE_CLR[3] ,MSI Interrupt 3 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 2. " MSI0_IRQ_ENABLE_CLR[2] ,MSI Interrupt 2 Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " MSI0_IRQ_ENABLE_CLR[1] ,MSI Interrupt 1 Clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 0. " MSI0_IRQ_ENABLE_CLR[0] ,MSI Interrupt 0 Clear" "Disabled,Enabled"
|
|
group.long 0x180++0x0F
|
|
line.long 0x00 "IRQ_STATUS_RAW,Raw Interrupt Status (RC mode)"
|
|
bitfld.long 0x00 3. " INTD ,Legacy Interrupt D raw status" "No interupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTC ,Legacy Interrupt C raw status" "No interupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTB ,Legacy Interrupt B raw status" "No interupt,Interrupt"
|
|
bitfld.long 0x00 0. " INTA ,Legacy Interrupt A raw status" "No interupt,Interrupt"
|
|
line.long 0x04 "IRQ_STATUS,Interrupt Enabled Status"
|
|
bitfld.long 0x04 3. " INTD ,Legacy Interrupt D status" "No interupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTC ,Legacy Interrupt C status" "No interupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTB ,Legacy Interrupt B status" "No interupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTA ,Legacy Interrupt A status" "No interupt,Interrupt"
|
|
line.long 0x08 "IRQ_ENABLE_SET,Interrupt Enable Set"
|
|
bitfld.long 0x08 3. " INTD ,Legacy Interrupt D set" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " INTC ,Legacy Interrupt C set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " INTB ,Legacy Interrupt B set" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " INTA ,Legacy Interrupt A set" "Disabled,Enabled"
|
|
line.long 0x0C "IRQ_ENABLE_CLR,Interrupt Enable Clearr"
|
|
eventfld.long 0x0C 3. " INTD ,Legacy Interrupt D clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 2. " INTC ,Legacy Interrupt C clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " INTB ,Legacy Interrupt B clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 0. " INTA ,Legacy Interrupt A clear" "Disabled,Enabled"
|
|
group.long 0x1C0++0x1F
|
|
line.long 0x00 "ERR_IRQ_STATUS_RAW,Raw ERR Interrupt Status"
|
|
bitfld.long 0x00 5. " ERR_AER ,ECRC error raw status" "No error,Error"
|
|
bitfld.long 0x00 4. " ERR_AXI ,AXI tag lookup fatal error raw status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERR_CORR ,Correctable error raw status" "No error,Error"
|
|
bitfld.long 0x00 2. " ERR_NONFATAL ,Nonfatal error raw status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ERR_FATAL ,Fatal error raw status" "No error,Error"
|
|
bitfld.long 0x00 0. " ERR_SYS ,System Error raw status" "No error,Error"
|
|
line.long 0x04 "ERR_IRQ_STATUS,ERR Interrupt Enabled Status"
|
|
bitfld.long 0x04 5. " ERR_AER ,ECRC error status" "No error,Error"
|
|
bitfld.long 0x04 4. " ERR_AXI ,AXI tag lookup fatal error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ERR_CORR ,Correctable error status" "No error,Error"
|
|
bitfld.long 0x04 2. " ERR_NONFATAL ,Nonfatal error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ERR_FATAL ,Fatal error status" "No error,Error"
|
|
bitfld.long 0x04 0. " ERR_SYS ,System Error status" "No error,Error"
|
|
line.long 0x08 "ERR_IRQ_ENABLE_SET,ERR Interrupt Enable Set"
|
|
bitfld.long 0x08 5. " ERR_AER ,ECRC error interrupt set " "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " ERR_AXI ,AXI tag lookup fatal error interrupt set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ERR_CORR ,Correctable error interrupt set" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " ERR_NONFATAL ,Nonfatal error interrupt set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ERR_FATAL ,Fatal error interrupt set" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ERR_SYS ,System error interrupt set" "Disabled,Enabled"
|
|
line.long 0x0C "ERR_IRQ_ENABLE_CLR,ERR Interrupt Enable Clear"
|
|
eventfld.long 0x0C 5. " ERR_AER ,ECRC error interrupt clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 4. " ERR_AXI ,AXI tag lookup fatal error interrupt clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 3. " ERR_CORR ,Correctable error interrupt clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 2. " ERR_NONFATAL ,Nonfatal error interrupt clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " ERR_FATAL ,Fatal error interrupt clear" "Disabled,Enabled"
|
|
eventfld.long 0x0C 0. " ERR_SYS ,System error interrupt clear" "Disabled,Enabled"
|
|
line.long 0x10 "PMRST_IRQ_STATUS_RAW,Power Management and Reset Interrupt Status"
|
|
bitfld.long 0x10 3. " LINK_RST_REQ ,Link Request Reset interrupt raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " PM_PME ,Power Management PME message received interrupt raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PM_TO_ACK ,Power Management ACK received interrupt raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " PM_TURNOFF ,Power Management Turnoff message received raw status" "No interrupt,Interrupt"
|
|
line.long 0x14 "PMRST_IRQ_STATUS,Power Management and Reset Interrupt Enabled Status"
|
|
bitfld.long 0x14 3. " LINK_RST_REQ ,Link Request Reset interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 2. " PM_PME ,Power Management PME message received interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PM_TO_ACK ,Power Management ACK received interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 0. " PM_TURNOFF ,Power Management Turnoff message received status" "No interrupt,Interrupt"
|
|
line.long 0x18 "PMRST_ENABLE_SET,Power Management and Reset Interrupt Enable Set"
|
|
bitfld.long 0x18 3. " LINK_RST_REQ ,Link Request Reset interrupt set" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " PM_PME ,Power Management PME message received interrupt set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PM_TO_ACK ,Power Management ACK received interrupt set" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PM_TURNOFF ,Power Management Turnoff message received set" "Disabled,Enabled"
|
|
line.long 0x1C "PMRST_ENABLE_CLR,Power Management and Reset Interrupt Enable Clear"
|
|
eventfld.long 0x1C 3. " LINK_RST_REQ ,Link Request Reset interrupt clear" "Disabled,Enabled"
|
|
eventfld.long 0x1C 2. " PM_PME ,Power Management PME message received interrupt clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 1. " PM_TO_ACK ,Power Management ACK received interrupt clear" "Disabled,Enabled"
|
|
eventfld.long 0x1C 0. " PM_TURNOFF ,Power Management Turnoff message received clear" "Disabled,Enabled"
|
|
group.long 0x200++0x13F
|
|
line.long 0x0 "OB_OFFSET_INDEX0,Outbound Translation Region 0 Offset Low and Index"
|
|
hexmask.long.word 0x0 20.--31. 0x10 " OB_OFFSET0_LO ,Offset bits for translation region 0"
|
|
bitfld.long 0x0 0. " OB_ENABLE0 ,Enable translation region 0" "Disabled,Enabled"
|
|
line.long (0x0+0x04) "OB_OFFSET0_HI,OB_OFFSET0_HI Register"
|
|
line.long 0x8 "OB_OFFSET_INDEX1,Outbound Translation Region 1 Offset Low and Index"
|
|
hexmask.long.word 0x8 20.--31. 0x10 " OB_OFFSET1_LO ,Offset bits for translation region 1"
|
|
bitfld.long 0x8 0. " OB_ENABLE1 ,Enable translation region 1" "Disabled,Enabled"
|
|
line.long (0x8+0x04) "OB_OFFSET1_HI,OB_OFFSET1_HI Register"
|
|
line.long 0x10 "OB_OFFSET_INDEX2,Outbound Translation Region 2 Offset Low and Index"
|
|
hexmask.long.word 0x10 20.--31. 0x10 " OB_OFFSET2_LO ,Offset bits for translation region 2"
|
|
bitfld.long 0x10 0. " OB_ENABLE2 ,Enable translation region 2" "Disabled,Enabled"
|
|
line.long (0x10+0x04) "OB_OFFSET2_HI,OB_OFFSET2_HI Register"
|
|
line.long 0x18 "OB_OFFSET_INDEX3,Outbound Translation Region 3 Offset Low and Index"
|
|
hexmask.long.word 0x18 20.--31. 0x10 " OB_OFFSET3_LO ,Offset bits for translation region 3"
|
|
bitfld.long 0x18 0. " OB_ENABLE3 ,Enable translation region 3" "Disabled,Enabled"
|
|
line.long (0x18+0x04) "OB_OFFSET3_HI,OB_OFFSET3_HI Register"
|
|
line.long 0x20 "OB_OFFSET_INDEX4,Outbound Translation Region 4 Offset Low and Index"
|
|
hexmask.long.word 0x20 20.--31. 0x10 " OB_OFFSET4_LO ,Offset bits for translation region 4"
|
|
bitfld.long 0x20 0. " OB_ENABLE4 ,Enable translation region 4" "Disabled,Enabled"
|
|
line.long (0x20+0x04) "OB_OFFSET4_HI,OB_OFFSET4_HI Register"
|
|
line.long 0x28 "OB_OFFSET_INDEX5,Outbound Translation Region 5 Offset Low and Index"
|
|
hexmask.long.word 0x28 20.--31. 0x10 " OB_OFFSET5_LO ,Offset bits for translation region 5"
|
|
bitfld.long 0x28 0. " OB_ENABLE5 ,Enable translation region 5" "Disabled,Enabled"
|
|
line.long (0x28+0x04) "OB_OFFSET5_HI,OB_OFFSET5_HI Register"
|
|
line.long 0x30 "OB_OFFSET_INDEX6,Outbound Translation Region 6 Offset Low and Index"
|
|
hexmask.long.word 0x30 20.--31. 0x10 " OB_OFFSET6_LO ,Offset bits for translation region 6"
|
|
bitfld.long 0x30 0. " OB_ENABLE6 ,Enable translation region 6" "Disabled,Enabled"
|
|
line.long (0x30+0x04) "OB_OFFSET6_HI,OB_OFFSET6_HI Register"
|
|
line.long 0x38 "OB_OFFSET_INDEX7,Outbound Translation Region 7 Offset Low and Index"
|
|
hexmask.long.word 0x38 20.--31. 0x10 " OB_OFFSET7_LO ,Offset bits for translation region 7"
|
|
bitfld.long 0x38 0. " OB_ENABLE7 ,Enable translation region 7" "Disabled,Enabled"
|
|
line.long (0x38+0x04) "OB_OFFSET7_HI,OB_OFFSET7_HI Register"
|
|
line.long 0x40 "OB_OFFSET_INDEX8,Outbound Translation Region 8 Offset Low and Index"
|
|
hexmask.long.word 0x40 20.--31. 0x10 " OB_OFFSET8_LO ,Offset bits for translation region 8"
|
|
bitfld.long 0x40 0. " OB_ENABLE8 ,Enable translation region 8" "Disabled,Enabled"
|
|
line.long (0x40+0x04) "OB_OFFSET8_HI,OB_OFFSET8_HI Register"
|
|
line.long 0x48 "OB_OFFSET_INDEX9,Outbound Translation Region 9 Offset Low and Index"
|
|
hexmask.long.word 0x48 20.--31. 0x10 " OB_OFFSET9_LO ,Offset bits for translation region 9"
|
|
bitfld.long 0x48 0. " OB_ENABLE9 ,Enable translation region 9" "Disabled,Enabled"
|
|
line.long (0x48+0x04) "OB_OFFSET9_HI,OB_OFFSET9_HI Register"
|
|
line.long 0x50 "OB_OFFSET_INDEX10,Outbound Translation Region 10 Offset Low and Index"
|
|
hexmask.long.word 0x50 20.--31. 0x10 " OB_OFFSET10_LO ,Offset bits for translation region 10"
|
|
bitfld.long 0x50 0. " OB_ENABLE10 ,Enable translation region 10" "Disabled,Enabled"
|
|
line.long (0x50+0x04) "OB_OFFSET10_HI,OB_OFFSET10_HI Register"
|
|
line.long 0x58 "OB_OFFSET_INDEX11,Outbound Translation Region 11 Offset Low and Index"
|
|
hexmask.long.word 0x58 20.--31. 0x10 " OB_OFFSET11_LO ,Offset bits for translation region 11"
|
|
bitfld.long 0x58 0. " OB_ENABLE11 ,Enable translation region 11" "Disabled,Enabled"
|
|
line.long (0x58+0x04) "OB_OFFSET11_HI,OB_OFFSET11_HI Register"
|
|
line.long 0x60 "OB_OFFSET_INDEX12,Outbound Translation Region 12 Offset Low and Index"
|
|
hexmask.long.word 0x60 20.--31. 0x10 " OB_OFFSET12_LO ,Offset bits for translation region 12"
|
|
bitfld.long 0x60 0. " OB_ENABLE12 ,Enable translation region 12" "Disabled,Enabled"
|
|
line.long (0x60+0x04) "OB_OFFSET12_HI,OB_OFFSET12_HI Register"
|
|
line.long 0x68 "OB_OFFSET_INDEX13,Outbound Translation Region 13 Offset Low and Index"
|
|
hexmask.long.word 0x68 20.--31. 0x10 " OB_OFFSET13_LO ,Offset bits for translation region 13"
|
|
bitfld.long 0x68 0. " OB_ENABLE13 ,Enable translation region 13" "Disabled,Enabled"
|
|
line.long (0x68+0x04) "OB_OFFSET13_HI,OB_OFFSET13_HI Register"
|
|
line.long 0x70 "OB_OFFSET_INDEX14,Outbound Translation Region 14 Offset Low and Index"
|
|
hexmask.long.word 0x70 20.--31. 0x10 " OB_OFFSET14_LO ,Offset bits for translation region 14"
|
|
bitfld.long 0x70 0. " OB_ENABLE14 ,Enable translation region 14" "Disabled,Enabled"
|
|
line.long (0x70+0x04) "OB_OFFSET14_HI,OB_OFFSET14_HI Register"
|
|
line.long 0x78 "OB_OFFSET_INDEX15,Outbound Translation Region 15 Offset Low and Index"
|
|
hexmask.long.word 0x78 20.--31. 0x10 " OB_OFFSET15_LO ,Offset bits for translation region 15"
|
|
bitfld.long 0x78 0. " OB_ENABLE15 ,Enable translation region 15" "Disabled,Enabled"
|
|
line.long (0x78+0x04) "OB_OFFSET15_HI,OB_OFFSET15_HI Register"
|
|
line.long 0x80 "OB_OFFSET_INDEX16,Outbound Translation Region 16 Offset Low and Index"
|
|
hexmask.long.word 0x80 20.--31. 0x10 " OB_OFFSET16_LO ,Offset bits for translation region 16"
|
|
bitfld.long 0x80 0. " OB_ENABLE16 ,Enable translation region 16" "Disabled,Enabled"
|
|
line.long (0x80+0x04) "OB_OFFSET16_HI,OB_OFFSET16_HI Register"
|
|
line.long 0x88 "OB_OFFSET_INDEX17,Outbound Translation Region 17 Offset Low and Index"
|
|
hexmask.long.word 0x88 20.--31. 0x10 " OB_OFFSET17_LO ,Offset bits for translation region 17"
|
|
bitfld.long 0x88 0. " OB_ENABLE17 ,Enable translation region 17" "Disabled,Enabled"
|
|
line.long (0x88+0x04) "OB_OFFSET17_HI,OB_OFFSET17_HI Register"
|
|
line.long 0x90 "OB_OFFSET_INDEX18,Outbound Translation Region 18 Offset Low and Index"
|
|
hexmask.long.word 0x90 20.--31. 0x10 " OB_OFFSET18_LO ,Offset bits for translation region 18"
|
|
bitfld.long 0x90 0. " OB_ENABLE18 ,Enable translation region 18" "Disabled,Enabled"
|
|
line.long (0x90+0x04) "OB_OFFSET18_HI,OB_OFFSET18_HI Register"
|
|
line.long 0x98 "OB_OFFSET_INDEX19,Outbound Translation Region 19 Offset Low and Index"
|
|
hexmask.long.word 0x98 20.--31. 0x10 " OB_OFFSET19_LO ,Offset bits for translation region 19"
|
|
bitfld.long 0x98 0. " OB_ENABLE19 ,Enable translation region 19" "Disabled,Enabled"
|
|
line.long (0x98+0x04) "OB_OFFSET19_HI,OB_OFFSET19_HI Register"
|
|
line.long 0xA0 "OB_OFFSET_INDEX20,Outbound Translation Region 20 Offset Low and Index"
|
|
hexmask.long.word 0xA0 20.--31. 0x10 " OB_OFFSET20_LO ,Offset bits for translation region 20"
|
|
bitfld.long 0xA0 0. " OB_ENABLE20 ,Enable translation region 20" "Disabled,Enabled"
|
|
line.long (0xA0+0x04) "OB_OFFSET20_HI,OB_OFFSET20_HI Register"
|
|
line.long 0xA8 "OB_OFFSET_INDEX21,Outbound Translation Region 21 Offset Low and Index"
|
|
hexmask.long.word 0xA8 20.--31. 0x10 " OB_OFFSET21_LO ,Offset bits for translation region 21"
|
|
bitfld.long 0xA8 0. " OB_ENABLE21 ,Enable translation region 21" "Disabled,Enabled"
|
|
line.long (0xA8+0x04) "OB_OFFSET21_HI,OB_OFFSET21_HI Register"
|
|
line.long 0xB0 "OB_OFFSET_INDEX22,Outbound Translation Region 22 Offset Low and Index"
|
|
hexmask.long.word 0xB0 20.--31. 0x10 " OB_OFFSET22_LO ,Offset bits for translation region 22"
|
|
bitfld.long 0xB0 0. " OB_ENABLE22 ,Enable translation region 22" "Disabled,Enabled"
|
|
line.long (0xB0+0x04) "OB_OFFSET22_HI,OB_OFFSET22_HI Register"
|
|
line.long 0xB8 "OB_OFFSET_INDEX23,Outbound Translation Region 23 Offset Low and Index"
|
|
hexmask.long.word 0xB8 20.--31. 0x10 " OB_OFFSET23_LO ,Offset bits for translation region 23"
|
|
bitfld.long 0xB8 0. " OB_ENABLE23 ,Enable translation region 23" "Disabled,Enabled"
|
|
line.long (0xB8+0x04) "OB_OFFSET23_HI,OB_OFFSET23_HI Register"
|
|
line.long 0xC0 "OB_OFFSET_INDEX24,Outbound Translation Region 24 Offset Low and Index"
|
|
hexmask.long.word 0xC0 20.--31. 0x10 " OB_OFFSET24_LO ,Offset bits for translation region 24"
|
|
bitfld.long 0xC0 0. " OB_ENABLE24 ,Enable translation region 24" "Disabled,Enabled"
|
|
line.long (0xC0+0x04) "OB_OFFSET24_HI,OB_OFFSET24_HI Register"
|
|
line.long 0xC8 "OB_OFFSET_INDEX25,Outbound Translation Region 25 Offset Low and Index"
|
|
hexmask.long.word 0xC8 20.--31. 0x10 " OB_OFFSET25_LO ,Offset bits for translation region 25"
|
|
bitfld.long 0xC8 0. " OB_ENABLE25 ,Enable translation region 25" "Disabled,Enabled"
|
|
line.long (0xC8+0x04) "OB_OFFSET25_HI,OB_OFFSET25_HI Register"
|
|
line.long 0xD0 "OB_OFFSET_INDEX26,Outbound Translation Region 26 Offset Low and Index"
|
|
hexmask.long.word 0xD0 20.--31. 0x10 " OB_OFFSET26_LO ,Offset bits for translation region 26"
|
|
bitfld.long 0xD0 0. " OB_ENABLE26 ,Enable translation region 26" "Disabled,Enabled"
|
|
line.long (0xD0+0x04) "OB_OFFSET26_HI,OB_OFFSET26_HI Register"
|
|
line.long 0xD8 "OB_OFFSET_INDEX27,Outbound Translation Region 27 Offset Low and Index"
|
|
hexmask.long.word 0xD8 20.--31. 0x10 " OB_OFFSET27_LO ,Offset bits for translation region 27"
|
|
bitfld.long 0xD8 0. " OB_ENABLE27 ,Enable translation region 27" "Disabled,Enabled"
|
|
line.long (0xD8+0x04) "OB_OFFSET27_HI,OB_OFFSET27_HI Register"
|
|
line.long 0xE0 "OB_OFFSET_INDEX28,Outbound Translation Region 28 Offset Low and Index"
|
|
hexmask.long.word 0xE0 20.--31. 0x10 " OB_OFFSET28_LO ,Offset bits for translation region 28"
|
|
bitfld.long 0xE0 0. " OB_ENABLE28 ,Enable translation region 28" "Disabled,Enabled"
|
|
line.long (0xE0+0x04) "OB_OFFSET28_HI,OB_OFFSET28_HI Register"
|
|
line.long 0xE8 "OB_OFFSET_INDEX29,Outbound Translation Region 29 Offset Low and Index"
|
|
hexmask.long.word 0xE8 20.--31. 0x10 " OB_OFFSET29_LO ,Offset bits for translation region 29"
|
|
bitfld.long 0xE8 0. " OB_ENABLE29 ,Enable translation region 29" "Disabled,Enabled"
|
|
line.long (0xE8+0x04) "OB_OFFSET29_HI,OB_OFFSET29_HI Register"
|
|
line.long 0xF0 "OB_OFFSET_INDEX30,Outbound Translation Region 30 Offset Low and Index"
|
|
hexmask.long.word 0xF0 20.--31. 0x10 " OB_OFFSET30_LO ,Offset bits for translation region 30"
|
|
bitfld.long 0xF0 0. " OB_ENABLE30 ,Enable translation region 30" "Disabled,Enabled"
|
|
line.long (0xF0+0x04) "OB_OFFSET30_HI,OB_OFFSET30_HI Register"
|
|
line.long 0xF8 "OB_OFFSET_INDEX31,Outbound Translation Region 31 Offset Low and Index"
|
|
hexmask.long.word 0xF8 20.--31. 0x10 " OB_OFFSET31_LO ,Offset bits for translation region 31"
|
|
bitfld.long 0xF8 0. " OB_ENABLE31 ,Enable translation region 31" "Disabled,Enabled"
|
|
line.long (0xF8+0x04) "OB_OFFSET31_HI,OB_OFFSET31_HI Register"
|
|
line.long 0x100 "IB_BAR0,IInbound Translation Bar Match 0"
|
|
bitfld.long 0x100 0.--2. " IB_BAR0 ,BAR number to match for inbound translation region 0" "0,1,2,3,4,5,6,7"
|
|
line.long (0x100+0x04) "IB_START0_LO,Inbound Translation 0 Start Address Low"
|
|
hexmask.long.tbyte (0x100+0x04) 8.--31. 1. " IB_START0_LO ,Start address bits for inbound translation region 0"
|
|
line.long (0x100+0x08) "IB_START0_HI,Inbound Translation 0 Start Address High"
|
|
line.long (0x100+0x0C) "IB_OFFSET0,Inbound Translation 0 Address Offset"
|
|
hexmask.long.tbyte (0x100+0x0C) 8.--31. 1. " IB_OFFSET0 ,Offset address bits for inbound translation region 0"
|
|
line.long 0x110 "IB_BAR1,IInbound Translation Bar Match 1"
|
|
bitfld.long 0x110 0.--2. " IB_BAR1 ,BAR number to match for inbound translation region 1" "0,1,2,3,4,5,6,7"
|
|
line.long (0x110+0x04) "IB_START1_LO,Inbound Translation 1 Start Address Low"
|
|
hexmask.long.tbyte (0x110+0x04) 8.--31. 1. " IB_START1_LO ,Start address bits for inbound translation region 1"
|
|
line.long (0x110+0x08) "IB_START1_HI,Inbound Translation 1 Start Address High"
|
|
line.long (0x110+0x0C) "IB_OFFSET1,Inbound Translation 1 Address Offset"
|
|
hexmask.long.tbyte (0x110+0x0C) 8.--31. 1. " IB_OFFSET1 ,Offset address bits for inbound translation region 1"
|
|
line.long 0x120 "IB_BAR2,IInbound Translation Bar Match 2"
|
|
bitfld.long 0x120 0.--2. " IB_BAR2 ,BAR number to match for inbound translation region 2" "0,1,2,3,4,5,6,7"
|
|
line.long (0x120+0x04) "IB_START2_LO,Inbound Translation 2 Start Address Low"
|
|
hexmask.long.tbyte (0x120+0x04) 8.--31. 1. " IB_START2_LO ,Start address bits for inbound translation region 2"
|
|
line.long (0x120+0x08) "IB_START2_HI,Inbound Translation 2 Start Address High"
|
|
line.long (0x120+0x0C) "IB_OFFSET2,Inbound Translation 2 Address Offset"
|
|
hexmask.long.tbyte (0x120+0x0C) 8.--31. 1. " IB_OFFSET2 ,Offset address bits for inbound translation region 2"
|
|
line.long 0x130 "IB_BAR3,IInbound Translation Bar Match 3"
|
|
bitfld.long 0x130 0.--2. " IB_BAR3 ,BAR number to match for inbound translation region 3" "0,1,2,3,4,5,6,7"
|
|
line.long (0x130+0x04) "IB_START3_LO,Inbound Translation 3 Start Address Low"
|
|
hexmask.long.tbyte (0x130+0x04) 8.--31. 1. " IB_START3_LO ,Start address bits for inbound translation region 3"
|
|
line.long (0x130+0x08) "IB_START3_HI,Inbound Translation 3 Start Address High"
|
|
line.long (0x130+0x0C) "IB_OFFSET3,Inbound Translation 3 Address Offset"
|
|
hexmask.long.tbyte (0x130+0x0C) 8.--31. 1. " IB_OFFSET3 ,Offset address bits for inbound translation region 3"
|
|
group.long 0x380++0x07
|
|
line.long 0x00 "PCS_CFG0,PCS Configuration 0"
|
|
bitfld.long 0x00 24.--28. " PCS_SYNC ,Receiver Lock/Sync Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PCS_HOLDOFF ,Receiver Initialization Hold Off Control"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " PCS_RC_DELAY ,Rate Change Delay" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. " PCS_DET_DELAY ,Detection Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PCS_SHRT_TM ,Enable short times for debug purposes" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PCS_STAT186 ,Enable PIPE Spec 1.86 for PHY status behavior" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PCS_FIX_TERM ,Fed term output to 3'b100 during reset" "Not fed,Fed"
|
|
bitfld.long 0x00 4. " PCS_FIX_STD ,Fix std output to 2'b10" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PCS_L2_ENIDL_OFF ,Deassert ENIDL during L2 state" "Asserted,Deasserted"
|
|
bitfld.long 0x00 2. " PCS_L0S_RX_OFF ,Deassert Rx Enable in L0s state" "Asserted,Deasserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PCS_RXTX_ON ,RX and TX on during reset and TX on in P1 state" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PCS_RXTX_RST ,RX and TX on during reset" "Disabled,Enabled"
|
|
line.long 0x04 "PCS_CFG1,PCS Configuration 1"
|
|
hexmask.long.word 0x04 16.--25. 1. " PCS_ERR_BIT ,Error Bit enable"
|
|
bitfld.long 0x04 8.--9. " PCS_ERR_LN ,Error Lane enable" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " PCS_ERR_MODE ,Error Injection Mode" "0,1,2,3"
|
|
rgroup.long 0x388++0x03
|
|
line.long 0x00 "PCS_STATUS,PCS Status"
|
|
bitfld.long 0x00 12.--14. " PCS_REV ,PCS RTL Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--9. " PCS_LN_EN ,PCS Lanes enabled status" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PCS_TX_EN ,PCS Transmitters enabled status" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " PCS_RX_EN ,PCS Receivers enabled status" "0,1,2,3"
|
|
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "SERDES_STATUS,SerDes Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " STSTX ,Serdes transmit status"
|
|
hexmask.long.word 0x00 0.--15. 1. " SRSRX ,Serdes receive status"
|
|
sif (cpuis("AM387*")||cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
width 21.
|
|
group.long 0x390++0x27
|
|
line.long 0x00 "SERDES_RXCFG0,SerDes RX Config 0 Status Register"
|
|
bitfld.long 0x00 31. " LOOPBACK[1] ,Internal Digital loop back" "Disabled,Not supported"
|
|
bitfld.long 0x00 30. " LOOPBACK[0] ,Internal Analog loop back" "Disabled,Not supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RX_TRIM_BYPASS ,Trim bits generated from the calibration algorithm bypass (for calibration)" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 28. " CDR_ELV_IDLE_FIX ,CDR ELV Idle fix" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CDRAUX ,Clock/data recovery auxilliary" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " CAL_FILTER_DEPTH ,Average engine depth (for calibration)" "7 samples,15 samples,31 samples,7 samples"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ENOC ,Enable offset compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--22. " EQ ,Equalizer" "Disabled,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " CDR ,Clock/data recovery" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " LOS ,Loss of signal detection" "Disabled,Disabled,Disabled,Disabled,Enabled (without CDR override control),Disabled,Enabled (with CDR override control),Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " ALIGN ,Symbol alignment" "Disabled,Coma alignment,Alignment Jog,?..."
|
|
bitfld.long 0x00 8.--10. " TERM ,Input termination options" "Reserved,Common point set to 0.8 VDDA,Reserved,Common point floating,Common point set to VSSA,Common point set to 0.2 VDDA,Reserved,Common point floating"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INVPAIR ,Inverts polarity of RXPi and RXNi" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5.--6. " RATE ,Operating rate" "Full,Half,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " BUSWIDTH ,Parallel interface width" "10-bit,?..."
|
|
bitfld.long 0x00 1. " ENRXLDO ,Enable RXLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENRX ,Enable receiver" "Disabled,Enabled"
|
|
line.long 0x04 "SERDES_RXCFG1,SerDes RX Config 1 Status Register"
|
|
bitfld.long 0x04 30.--31. " EQ_ICM_S2 ,Trims common mode pullup current in second equalizer stage" "0,1,2,3"
|
|
bitfld.long 0x04 28.--29. " EQ_ICM_S1 ,Trims common mode pullup current in first equalizer stage" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 21.--23. " EQ_I_STAGE2 ,Trims the current in the second stage of the equalizer" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 18.--20. " EQ_I_STAGEFB ,Trims the current in the feedback stage of the equalizer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " EQ_I_STAGE1 ,Trims the current in the first stage of the equalizer" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 14. " ANALOG_LOOPBACK ,Enables analog loop back" "Disabled,Enabled"
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textline " "
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bitfld.long 0x04 13. " RXTRIM_CALIB ,RX trimming control to the calibration block" "Functional mode,eFuse training mode"
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bitfld.long 0x04 12. " RXTRIM_BYPASS_CTRL ,RXTRIM bypass control" "Disabled,Enabled"
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textline " "
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bitfld.long 0x04 7.--11. " RXTRIM_BYPASS_BITS ,Bypass bits for RXTRIM[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 6. " BYPASS_CALOUT_AVG ,Bypasses the averaging filter for the calout signal inside digital (for calibration)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x04 5. " CTG_DIG_RSVD1 ,Clock inversion for rpclk" "Disabled,Enabled"
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bitfld.long 0x04 4. " CTG_DIG_RSVD0 ,Clock inversion for fclk" "Disabled,Enabled"
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textline " "
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bitfld.long 0x04 3. " ENTEST ,Enable test" "Disabled,Enabled"
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bitfld.long 0x04 0.--2. " TESTPATT ,Enables and selects test patterns" "Reserved,Alternating 0/1 pattern with a period of 2 UI,7-bit LFSR with feedback polynomial x7+x6+1,23-bit LFSR with feedback polynomial x23+x18+1,31-bit LFSR with feedback polynomial x31+x28+1,?..."
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line.long 0x08 "SERDES_RXCFG2,SerDes RX Config 2 Status Register"
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bitfld.long 0x08 27.--31. " SAMP_BYPASS_SAD1 ,Bypass bits for SAD1[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 22.--26. " SAMP_BYPASS_SAT0 ,Bypass bits for SAT0[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x08 17.--21. " SAMP_BYPASS_SAD0 ,Bypass bits for SAD0[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 12.--16. " SAMP_BYPASS_SAT1 ,Bypass bits for SAT1[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x0c "SERDES_RXCFG3,SerDes RX Config 3 Status Register"
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bitfld.long 0x0c 31. " AMUX_EYESCAN_REF ,Connect the eyescan reference voltages to the test mux inputs" "Disabled,Enabled"
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bitfld.long 0x0c 30. " SAMP_OC_SEL ,Sampler offset correction is controlled" "TRXDIG SAT1/SAD0/SAT0/SAD1,CFG_CTRL/CFGRX_2"
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textline " "
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bitfld.long 0x0c 24.--29. " SAMP_ES_VREF_BYPASS_BITS ,Adjusts the eyescan reference voltage level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0c 20.--23. " SAMP_ESCM_RES ,Trims the pullup resistors in the eyescan common mode loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x0c 17.--19. " SAMP_ESCM_I ,Trims the current in the eyescan common mode loop" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0c 16. " SAMP_3_VREF_2_ES ,Sampler 3 VREF" "EQCM,Sampler 3"
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textline " "
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bitfld.long 0x0c 15. " SAMP_2_VREF_2_ES ,Sampler 2 VREF" "EQCM,Sampler 2"
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bitfld.long 0x0c 14. " SAMP_1_VREF_2_ES ,Sampler 1 VREF" "EQCM,Sampler 1"
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textline " "
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bitfld.long 0x0c 13. " SAMP_0_VREF_2_ES ,Sampler 0 VREF" "EQCM,Sampler 0"
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bitfld.long 0x0c 8.--12. " SAMP_IBIAS_Z ,Adjusts the current mirror ratio in the sampler bias current block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x0c 7. " SAMP_ES_VREF_BYPASS_CTRL ,Eyescan reference offset voltage control" "IEEE1500,CFGRX_3"
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bitfld.long 0x0c 3. " SAMP_EN_3_ODD ,Enable sampler 3 (odd data)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0c 2. " SAMP_EN_2_EOTR ,Enable sampler 2 (even to odd transition)" "Disabled,Enabled"
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bitfld.long 0x0c 1. " SAMP_EN_1_EVEN ,Enable sampler 1 (even data)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0c 0. " SAMP_EN_0_OETR ,Enable sampler 0 (odd to even transition)" "Disabled,Enabled"
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line.long 0x10 "SERDES_RXCFG4,SerDes RX Config 4 Status Register"
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bitfld.long 0x10 28.--29. " RCLK_SAMP ,RCLK_SAMP[1:0]" "0,1,2,3"
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bitfld.long 0x10 26.--27. " RCLK_DIG ,RCLK_DIG[1:0]" "0,1,2,3"
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textline " "
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bitfld.long 0x10 24. " DCD_EN_BUF ,DCD_EN_BUF" "Low,High"
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bitfld.long 0x10 23. " DCD_EN_CLK ,DCD_EN_CLK" "Low,High"
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textline " "
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bitfld.long 0x10 22. " DCD_EN_M ,DCD_EN_M" "Low,High"
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bitfld.long 0x10 21. " DCD_EN_P ,DCD_EN_P" "Low,High"
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textline " "
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bitfld.long 0x10 19. " PI_VCM_Z_0 ,PI_VCM_Z[0]" "Low,High"
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bitfld.long 0x10 18. " PI_VCM_1 ,PI_VCM[1]" "Low,High"
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textline " "
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bitfld.long 0x10 17. " PI_VCM_Z_2 ,PI_VCM_Z[2]" "Low,High"
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bitfld.long 0x10 16. " PI_VCM_Z_3 ,PI_VCM_Z[3]" "Low,High"
|
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textline " "
|
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bitfld.long 0x10 15. " PI_BIAS_DISABLE ,PI_BIAS_DISABLE" "No,Yes"
|
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bitfld.long 0x10 14. " PI_ED_CAL_LEVEL_DEC ,PI_ED_CAL_LEVEL_DEC" "Low,High"
|
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textline " "
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bitfld.long 0x10 13. " PI_ED_CAL_LEVEL_INC ,PI_ED_CAL_LEVEL_INC" "Low,High"
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bitfld.long 0x10 12. " PI_ED_CAL ,PI_ED_CAL" "Low,High"
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textline " "
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bitfld.long 0x10 11. " PI_ED_RESET ,PI_ED_RESET" "No reset,Reset"
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bitfld.long 0x10 10. " PI_ED_EN ,PI_ED_EN" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " PI_ED_VOUTP ,PI_ED_VOUTP" "Low,High"
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bitfld.long 0x10 8. " PI_ED_VOUTM ,PI_ED_VOUTM" "Low,High"
|
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textline " "
|
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bitfld.long 0x10 7. " PI_I50U ,PI_I50U" "Low,High"
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bitfld.long 0x10 6. " PI_I100U_Z ,PI_I100U_Z" "Low,High"
|
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textline " "
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bitfld.long 0x10 0.--5. " PI_IBIAS_Z ,PI_IBIAS_Z[5:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x14 "SERDES_TXCFG0,SerDes TX Config 0 Status Register"
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bitfld.long 0x14 28.--29. " CAL_FILTER_DEPTH ,Average engine depth (for calibration)" "7 samples,15 samples,31 samples,7 samples"
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bitfld.long 0x14 25.--26. " DET_CTL ,Receiver detect control" "0,1,2,3"
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textline " "
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bitfld.long 0x14 24. " ENIDL ,Idle Control" "Disabled,Enabled"
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bitfld.long 0x14 21. " TM_EXTRA_LOAD[2] ,Enable different extraload resistors to make driver constant current at speed" "Disabled,Enabled"
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textline " "
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bitfld.long 0x14 20. " TM_EXTRA_LOAD[1] ,Enable static dummy load during electrical idle" "Disabled,Enabled"
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bitfld.long 0x14 19. " TM_EXTRA_LOAD[0] ,Enable switching dummy load during electrical idle" "Disabled,Enabled"
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textline " "
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bitfld.long 0x14 13.--17. " DEEMP ,Selects one of output de-emphasis settings (PCIE/eSATA full rate/eSata half rate)" "0/0/0,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved"
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bitfld.long 0x14 9.--12. " SWING ,TX Output swing selection" "148 (half),148 (half),258 (half),258 (half),295 (full/half),295 (full/half),516 (full/half),516 (full/half),774 (full/half),774 (full/half),1069 (full/half),1069 (full/half),1069 (full/half),1069 (full/half),1069 (full/half),1069 (full/half)"
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textline " "
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bitfld.long 0x14 7. " INVPAIR ,Inverts polarity of TXPi and TXNi" "Not inverted,Inverted"
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bitfld.long 0x14 5.--6. " RATE ,Operating rate" "Full,Half,?..."
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textline " "
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bitfld.long 0x14 2.--4. " BUSWIDTH ,Parallel interface width" "10-bit,?..."
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bitfld.long 0x14 1. " ENTXLDO ,TX Analog LDO" "Disabled,Enabled"
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textline " "
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bitfld.long 0x14 0. " ENTX ,Enable transmiter" "Disabled,Enabled"
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line.long 0x18 "SERDES_TXCFG1,SerDes TX Config 1 Status Register"
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bitfld.long 0x18 28.--31. " TRIM_HIGH_THRESHOLD ,4-b programmable threshold (for calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 27. " TX_DISABLE_ON_THE_FLY ,Disables the pattern match (for calibration)" "No,Yes"
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textline " "
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bitfld.long 0x18 26. " TX_FORCE_UPDATE ,Forces the update to be made to the Analog trim bits without looking for any specific data pattern or electrical idle (for calibration)" "Not forced,Forced"
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bitfld.long 0x18 25. " TX_TRIM_BYPASS ,Bypasses the trim bits generated from the calibration algorithm (for calibration)" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x18 24. " TRIM_2B_MODE ,Enables 2-b data pattern detection mode for trim updates (for calibration)" "Disabled,Enabled"
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bitfld.long 0x18 21.--22. " TRIM_STEP_CHANGE ,Step change value for staircase logic (for calibration)" "1,2,4,8"
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textline " "
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bitfld.long 0x18 19.--20. " TRIM_LOW_THRESHOLD ,2-b programmable threshold (for calibration)" "diff >= 1,diff >= 2,diff >= 3,diff >= 4"
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bitfld.long 0x18 17.--18. " CALIB_WAIT_CYCLES ,2-b programmable number of wait cycles before polling the calout signal (for calibration)" "1 MHz clock,1 MHz clock,1 MHz clock,1 MHz clock"
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textline " "
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bitfld.long 0x18 16. " ENABLE_LOOP_DELAY ,Enables the additional loop delay of 40 clock cycles before sweeping the trim code during the calibration (for calibration)" "Disabled,Enabled"
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bitfld.long 0x18 15. " BYPASS_CALOUT_AVG ,Bypasses the averaging filter for the callout signal inside digital (for calibration)" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x18 14. " NOLCKRST ,Reset override bit during PLL unlock" "No reset,Reset"
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bitfld.long 0x18 13. " ENBSPLS ,Receiver pulse boundary scan" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 12. " ENBSRX ,Enables IEEE 1149.6 boundary scan control of RXP and RXN" "Disabled,Enabled"
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bitfld.long 0x18 11. " ENBSTX ,Enables IEEE 1149.6 boundary scan control of TXP and TXN" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 10. " BSINITCLK ,BS initialization clock" "Disabled,Enabled"
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bitfld.long 0x18 9. " BSINRXN ,Boundary scan initialization for RXN" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 8. " BSINRXP ,Boundary scan initialization for RXP" "Disabled,Enabled"
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bitfld.long 0x18 7. " TSYNC_ENABLE ,Tsync Enable" "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x18 6. " ENTEST ,Enable test" "Disabled,Enabled"
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bitfld.long 0x18 5. " BSTX ,Boundary scan data" "Low,High"
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textline " "
|
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bitfld.long 0x18 1. " USE_STAIRCASE ,Staircase logic for trim code change (for calibration)" "Disabled,Enabled"
|
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line.long 0x1c "SERDES_TXCFG2,SerDes TX Config 2 Status Register"
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bitfld.long 0x1c 29.--30. " TM_DUMMY2IDLE ,Control ldo dummy digital load" "Disabled,1.5 mA,1.5 mA,3 mA"
|
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bitfld.long 0x1c 27.--28. " TM_DUMMY1IDLE ,Control ldo dummy resistor load" "Disabled,6 mA,9.6 mA,15 mA"
|
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textline " "
|
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bitfld.long 0x1c 25.--26. " TM_TEXTRALOAD ,Driver dummy current controlled by tx_extraload" "Disabled,1 mA,2 mA,3 mA"
|
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bitfld.long 0x1c 23. " DISABLE_FB1_TM_SRCONTROL ,TM_SRCONTROL disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x1c 21.--22. " SC_SATA ,Control for SATA slew-control" "0,1,2,3"
|
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bitfld.long 0x1c 19.--20. " SC_PCIE ,Control for PCIe slew-control" "0,1,2,3"
|
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textline " "
|
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bitfld.long 0x1c 18. " DISABLE_PCIE_SC ,Disable PCIE SC" "No,Yes"
|
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bitfld.long 0x1c 17. " DISABLE_SATA_SC ,Disable SATA SC" "No,Yes"
|
|
textline " "
|
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bitfld.long 0x1c 14. " TXDCC_PWRDN ,TX clock duty-cycle correction bypass" "Disabled,Enabled"
|
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bitfld.long 0x1c 4.--8. " TMTRIM ,Termination resistor calibration code for grounded resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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textline " "
|
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bitfld.long 0x1c 3. " TRIMBYPASS ,Digital control of termination resistor bypass" "Disabled,Enabled"
|
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bitfld.long 0x1c 1.--2. " RDTCT_VTMODE ,Receive detect test mode to program threshold" ".285V,0.3V,.27V,0.35V"
|
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line.long 0x20 "SERDES_TXCFG3,SerDes TX Config 3 Status Register"
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bitfld.long 0x20 24.--27. " RXLDO_CTRL[15:13] ,LDO loop compensation control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 23. " RXLDO_CTRL[12] ,Force LDO UP signal high" "Not forced,Forced"
|
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textline " "
|
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bitfld.long 0x20 22. " RXLDO_CTRL[11] ,Low dropout mode" "Disabled,Enabled"
|
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bitfld.long 0x20 21. " RXLDO_CTRL[10] ,Vref magnitude selection" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x20 20. " RXLDO_CTRL[9] ,Iref magnitude selection" "Disabled,Enabled"
|
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bitfld.long 0x20 18.--19. " RXLDO_CTRL[8:7] ,Quiescent current programmability" "0,1,2,3"
|
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textline " "
|
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bitfld.long 0x20 17. " RXLDO_CTRL[6] ,Overshoot control block" "Disabled,Enabled"
|
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bitfld.long 0x20 12.--16. " RXLDO_CTRL[5:0] ,Trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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textline " "
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bitfld.long 0x20 11. " RXLDO_HITRAN_UNUSED ,RX LDO transient improvement" "Disabled,Enabled"
|
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bitfld.long 0x20 7.--10. " TXLDO_CTRL[9:6] ,LDO loop compensation control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x20 6. " TXLDO_CTRL[5] ,Force LDO UP signal high" "Not forced,Forced"
|
|
bitfld.long 0x20 5. " TXLDO_CTRL[4] ,Low dropout mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " TXLDO_CTRL[3] ,Vref magnitude selection" "Disabled,Enabled"
|
|
bitfld.long 0x20 3. " TXLDO_CTRL[2] ,Iref magnitude selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 1.--2. " TXLDO_CTRL[1:0] ,Quiescent current programmability" "0,1,2,3"
|
|
bitfld.long 0x20 0. " TXLDO_DISABLE_OVERSHOOT ,TX LDO disable overshoot control" "No,Yes"
|
|
line.long 0x24 "SERDES_TXCFG4,SerDes TX Config 4 Status Register"
|
|
bitfld.long 0x24 4. " TM_BIASCTR ,TM_BIASCTR used in DCC" "Disabled,Enabled"
|
|
bitfld.long 0x24 1.--3. " TRIM_MODE ,TRIM_MODE[2:0]" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x24 0. " HYST_DISABLE ,HYST_DISABLE_Z and CALOUT_TX" "No,Yes"
|
|
else
|
|
group.long 0x390++0x1F
|
|
line.long 0x0 "SERDES_RXCFG0,SerDes RX Config 0 Register"
|
|
line.long 0x4 "SERDES_RXCFG1,SerDes RX Config 1 Register"
|
|
line.long 0x8 "SERDES_RXCFG2,SerDes RX Config 2 Register"
|
|
line.long 0xC "SERDES_RXCFG3,SerDes RX Config 3 Register"
|
|
line.long 0x10 "SERDES_TXCFG0,SerDes TX Config 0 Register"
|
|
line.long 0x14 "SERDES_TXCFG1,SerDes TX Config 1 Register"
|
|
line.long 0x18 "SERDES_TXCFG2,SerDes TX Config 2 Register"
|
|
line.long 0x1C "SERDES_TXCFG3,SerDes TX Config 3 Register"
|
|
endif
|
|
else
|
|
group.long 0x390++0x07
|
|
line.long 0x0 "SERDES_CFG0,SerDes Configuration for Lane 0"
|
|
bitfld.long 0x0 19.--20. " TX_LOOPBACK ,Enable TX loopback" "Disabled,Disabled,Disabled,Enabled"
|
|
bitfld.long 0x0 18. " TX_MSYNC ,Master mode for synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 17. " TX_CM ,Enable common mode adjustment" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " TX_INVPAIR ,Invert TX pair polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " RX_LOOPBACK ,Enable RX loopback" "Disabled,Disabled,Disabled,Enabled"
|
|
bitfld.long 0x0 13. " RX_ENOC ,Enable RX offset compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9.--12. " RX_EQ ,Enable RX adaptive equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 6.--8. " RX_CDR ,Enable RX clock data recovery" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 3.--5. " RX_LOS ,Enable RX loss of signal detection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 1.--2. " RX_ALIGN ,Enable RX symbol alignment" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RX_INVPAIR ,Invert RX pair polarity" "Not inverted,Inverted"
|
|
line.long 0x4 "SERDES_CFG1,SerDes Configuration for Lane 1"
|
|
bitfld.long 0x4 19.--20. " TX_LOOPBACK ,Enable TX loopback" "Disabled,Disabled,Disabled,Enabled"
|
|
bitfld.long 0x4 18. " TX_MSYNC ,Master mode for synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 17. " TX_CM ,Enable common mode adjustment" "Disabled,Enabled"
|
|
bitfld.long 0x4 16. " TX_INVPAIR ,Invert TX pair polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x4 14.--15. " RX_LOOPBACK ,Enable RX loopback" "Disabled,Disabled,Disabled,Enabled"
|
|
bitfld.long 0x4 13. " RX_ENOC ,Enable RX offset compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9.--12. " RX_EQ ,Enable RX adaptive equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 6.--8. " RX_CDR ,Enable RX clock data recovery" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 3.--5. " RX_LOS ,Enable RX loss of signal detection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 1.--2. " RX_ALIGN ,Enable RX symbol alignment" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x4 0. " RX_INVPAIR ,Invert RX pair polarity" "Not inverted,Inverted"
|
|
endif
|
|
width 11.
|
|
tree.end
|
|
sif (!cpuis("DRA62*"))
|
|
tree "SATA (Serial ATA)"
|
|
base ad:0x4A140000
|
|
width 9.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CAP,HBA Capabilities Register"
|
|
bitfld.long 0x00 31. " S64A ,Indicates Support for 64-Bit Addressing" "32bit,?..."
|
|
bitfld.long 0x00 30. " SNCQ ,Supports Native Command Queuing" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SSNTF ,Supports SNotification Register" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " SMPS ,Supports Mechanical Presence Switch" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SSS ,Supports Staggered Spin-Up" "Not supported,Supported"
|
|
bitfld.long 0x00 26. " SALP ,Supports Aggressive Link Power Management" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SAL ,Supports Activity LED" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " SCLO ,Supports Command List Override" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ISS ,Interface Speed Support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. " SNZO ,Supports Non-Zero DMA Offsets" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SAM ,Supports AHCI Mode Only" "Not supported,Supported"
|
|
bitfld.long 0x00 17. " SPM ,Supports Port Multiplier" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PMD ,PIO Multiple DRQ Block" "Not supported,Supported"
|
|
bitfld.long 0x00 14. " SSC ,Slumber State Capable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PSC ,Partial State Capable" "Low,High"
|
|
bitfld.long 0x00 8.--12. " NCS ,Number of Command Slots" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CCCS ,Command Completion Coalescing Supported" "Not supported,Supported"
|
|
bitfld.long 0x00 6. " EMS ,Enclosure Management Supported" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SXS ,Supports External SATA" "Not supported,Supported"
|
|
sif ((cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 0.--4. " NP ,Number of Ports" "1,2,?..."
|
|
elif (cpu()=="AM1810")||(cpu()=="AM1808")
|
|
bitfld.long 0x00 0.--4. " NP ,Number of Ports" "1 port,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " NP ,Number of Ports" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
endif
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "GHC,Global HBA Control Register"
|
|
bitfld.long 0x00 31. " AE ,AHCI Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HR ,HBA Reset" "No reset,Reset"
|
|
line.long 0x04 "IS,Interrupt Status Register"
|
|
eventfld.long 0x04 1. " IPS1 ,Interrupt Pending Status" "No pending,Pending"
|
|
eventfld.long 0x04 0. " IPS0 ,Interrupt Pending Status" "No pending,Pending"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "PI,Ports Implemented Register"
|
|
bitfld.long 0x00 1. " PI1 ,Ports 1 Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " PI0 ,Ports 0 Implemented" "Not implemented,Implemented"
|
|
line.long 0x04 "VS,AHCI Version Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " MJR ,Major Revision Number"
|
|
hexmask.long.word 0x04 0.--15. 1. " MNR ,Minor Revision Number"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "CCC_CTL,Command Completion Coalescing Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TV ,Time-out value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CC ,Command Completions"
|
|
textline " "
|
|
bitfld.long 0x00 3.--7. " INT ,Specifies the interrupt used by the CCC feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " EN ,CCC feature enable" "Disabled,Enabled"
|
|
width 9.
|
|
line.long 0x04 "CCC_PORTS,Command Completion Coalescing Ports Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1810"&&cpu()!="AM1808")
|
|
bitfld.long 0x04 31. " PRT[31] ,Ports 31 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 30. " PRT[30] ,Ports 30 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 29. " PRT[29] ,Ports 29 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
textline " "
|
|
bitfld.long 0x04 28. " PRT[28] ,Ports 28 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 27. " PRT[27] ,Ports 27 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 26. " PRT[26] ,Ports 26 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
textline " "
|
|
bitfld.long 0x04 25. " PRT[25] ,Ports 25 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 24. " PRT[24] ,Ports 24 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 23. " PRT[23] ,Ports 23 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
textline " "
|
|
bitfld.long 0x04 22. " PRT[22] ,Ports 22 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 21. " PRT[21] ,Ports 21 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 20. " PRT[20] ,Ports 20 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PRT[19] ,Ports 19 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 18. " PRT[18] ,Ports 18 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 17. " PRT[17] ,Ports 17 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PRT[16] ,Ports 16 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 15. " PRT[15] ,Ports 15 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 14. " PRT[14] ,Ports 14 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PRT[13] ,Ports 13 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 12. " PRT[12] ,Ports 12 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 11. " PRT[11] ,Ports 11 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
textline " "
|
|
bitfld.long 0x04 10. " PRT[10] ,Ports 10 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 9. " PRT[9] ,Ports 9 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 8. " PRT[8] ,Ports 8 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PRT[7] ,Ports 7 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 6. " PRT[6] ,Ports 6 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 5. " PRT[5] ,Ports 5 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PRT[4] ,Ports 4 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 3. " PRT[3] ,Ports 3 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
bitfld.long 0x04 2. " PRT[2] ,Ports 2 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="AM1810"&&cpu()!="AM1808")
|
|
bitfld.long 0x04 1. " PRT[1] ,Port 1 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " PRT[0] ,Port 0 command completion coalescing (CCC) feature" "Not CCC,CCC"
|
|
rgroup.long 0xA0++0x03
|
|
width 9.
|
|
line.long 0x00 "BISTAFR,BIST Active FIS Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NCP ,Non-Compliant Pattern"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PD ,Pattern Definition"
|
|
group.long 0xA4++0x0B
|
|
line.long 0x00 "BISTCR,BIST Control Register"
|
|
bitfld.long 0x00 18. " TXO ,Transmit Only" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CNTCLR ,Counter Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 16. " NEALB ,Near-end Analog Loopback" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LLC_RPD ,Repeat primitive drop" "Disabled(Normal)/Enabled(BIST),Enabled(Normal)/Disabled(BIST)"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LLC_DESCRAM ,Descrambler" "Disabled(Normal)/Enabled(BIST),Enabled(Normal)/Disabled(BIST)"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LLC_SCRAM ,Scrambler" "Disabled(Normal)/Enabled(BIST),Enabled(Normal)/Disabled(BIST)"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ERREN ,Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLIP ,Flip Disparity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PV ,Pattern Version" "Short,Long"
|
|
bitfld.long 0x00 0.--3. " PATTERN ,Defines one of the following SATA compliant patterns" "Simultaneous switching outputs pattern (SSOP),High-transition density pattern,Low-transition density pattern,Low-frequency spectral component pattern (LFSCP),Composite pattern (COMP),Lone bit pattern (LBP),Mid-frequency test pattern (MFTP),High-frequency test pattern (HFTP),Low-frequency test pattern (LFTP),?..."
|
|
width 9.
|
|
line.long 0x04 "BISTFCTR,BIST FIS Count Register"
|
|
line.long 0x08 "BISTSR,BIST Status Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " BRSTERR ,Burst Error"
|
|
hexmask.long.word 0x08 0.--15. 1. " FRAMERR ,Frame Error"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "BISTDECR,BIST DWORD Error Count Register"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TIMER1MS,BIST DWORD Error Count Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " TIMV ,1ms Timer Value"
|
|
rgroup.long 0xE8++0x0B
|
|
line.long 0x00 "GPARAM1R,Global Parameter 1 Register"
|
|
bitfld.long 0x00 31. " ALIGN_M ,Rx Data Alignment" "Not aligned,Aligned"
|
|
bitfld.long 0x00 30. " RX_BUFFER ,Rx Data Buffer" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " PHY_DATA ,PHY Data Width" "0,1,2,3"
|
|
bitfld.long 0x00 27. " PHY_RST ,PHY Reset Mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21.--26. " PHY_CTRL ,PHY Control Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--20. " PHY_STAT ,PHY Status Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LATCH_M ,Latch Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BIST_M ,BIST Loopback Checking Depth" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PHY_TYPE ,PHY Interface Type" "Non-Synopsis,Synopsis"
|
|
bitfld.long 0x00 10. " RETURN_ERR ,AHB Error Response" "Not returned,Returned"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " AHB_ENDIAN ,Bus Endianness" "0,1,2,3"
|
|
bitfld.long 0x00 7. " S_HADDR ,Slave address bus width" "32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " M_HADDR ,Master address bus width" "32-bit,?..."
|
|
bitfld.long 0x00 3.--5. " S_HDATA ,Slave Data Bus Width" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " M_HDATA ,Master Data Bus Width" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "GPARAM2R,Global Parameter 2 Register"
|
|
bitfld.long 0x04 14. " DEV_CP ,Cold Presence Detect" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " DEV_MP ,Cold Presence Detect" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 12. " ENCODE_M ,8b/10b Encoding/Decoding" "8-bit,10-bit"
|
|
bitfld.long 0x04 11. " RXOOB_CLK_M ,Rx OOB Clock Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " RX_OOB_M ,Rx OOB Mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TX_OOB_M ,Tx OOB Mode" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--8. 1. " RXOOB_CLK ,Rx OOB Clock Frequency"
|
|
line.long 0x08 "PPARAMR,Port Parameter Register"
|
|
bitfld.long 0x08 9. " TX_MEM_M ,Tx FIFO Memory Read Port Type" "Synchronous,Asynchronous"
|
|
bitfld.long 0x08 8. " TX_MEM_S ,Tx FIFO Memory Type" "Inside,Outside"
|
|
textline " "
|
|
bitfld.long 0x08 7. " RX_MEM_M ,Rx FIFO Memory Read Port Type" "Synchronous,Asynchronous"
|
|
bitfld.long 0x08 6. " RX_MEM_S ,Rx FIFO Memory Type" "Inside,Outside"
|
|
textline " "
|
|
bitfld.long 0x08 3.--5. " TX_FIFO_DEPTH ,Tx FIFO Depth" "32,64,128,256,512,1024,2048,4096"
|
|
bitfld.long 0x08 0.--2. " RX_FIFO_DEPTH ,Rx FIFO Depth" "32,64,128,256,512,1024,2048,4096"
|
|
sif (!(cpuis("AM387*")))
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TESTR,Test Register"
|
|
bitfld.long 0x00 16.--18. " PSEL ,Port Select" "0,1,..."
|
|
bitfld.long 0x00 0. " TEST_IF ,Test Interface" "Normal,Test"
|
|
endif
|
|
rgroup.long 0xF8++0x07
|
|
line.long 0x00 "VERSIONR,Version Register"
|
|
line.long 0x04 "IDR,ID register"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "P0CLB,Port Command List Base Address Register"
|
|
hexmask.long 0x00 10.--31. 0x400 " CLB ,Command List Base Address"
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "P0FB,Port FIS Base Address Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " FB ,FIS Base Address"
|
|
group.long (0x100+0x10)++0x0B
|
|
line.long 0x00 "P0IS,Port Interrupt Status Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
eventfld.long 0x00 31. " CPDS ,Cold Port Detect Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 30. " TFES ,Task File Error Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " HBFS ,Host Bus Fatal Error Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 28. " HBDS ,Host Bus Data Error Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IFS ,Interface Fatal Error Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 26. " INFS ,Interface Non-fatal Error Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 24. " OFS ,Overflow Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IPMS ,Incorrect Port Multiplier Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PRCS ,PHYReady Change Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " DMPS ,Device Mechanical Presence Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PCS ,Port Connect Change Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " DPS ,Descriptor Processed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFS ,Unknown FIS Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " SDBS ,Set Device Bits Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DSS ,DMA Setup FIS Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PSS ,PIO Setup FIS Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " DHRS ,Device to Host Register FIS Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "P0IE,Port Interrupt Enable Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
bitfld.long 0x04 31. " CPDE ,Cold Port Detect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 30. " TFEE ,Task File Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " HBFE ,Host Bus Fatal Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " HBDE ,Host Bus Data Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " IFE ,Interface Fatal Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 26. " INFE ,Interface Non-fatal Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " OFE ,Overflow Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IPME ,Incorrect Port Multiplier Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " PRCE ,PHYReady Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DMPE ,Device Mechanical Presence Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PCE ,Port Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DPE ,Descriptor Processed Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " UFE ,Unknown FIS Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SDBE ,Set Device Bits FIS Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DSE ,DMA Setup FIS Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PSE ,PIO Setup FIS Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DHRE ,Device Host Register FIS Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x08 "P0CMD,Port Command Register"
|
|
bitfld.long 0x08 28.--31. " ICC ,Interface Communication Control" "No-Op/ Idle,Active,Partial,Reserved,Reserved,Reserved,Slumber,?..."
|
|
textline " "
|
|
bitfld.long 0x08 27. " ASP ,Aggressive Slumber/Partial" "Partial,Slumber"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ALPE ,Aggressive Link Power Management Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " DLAE ,Drive LED on ATAPI Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " ATAPI ,Device is ATAPI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " ESP ,External SATA Port" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
bitfld.long 0x08 20. " CPD ,Cold Presence Detection" "Not supported,Supported"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 19. " MPSP ,Mechanical Presence Switch Attached to Port" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 18. " HPCP ,Hot Plug" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " PMA ,Port Multiplier Attached" "Not attached,Attached"
|
|
textline " "
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
bitfld.long 0x08 16. " CPS ,Cold Presence State" "Not attached,Attached"
|
|
else
|
|
bitfld.long 0x08 16. " CPD ,Cold Presence Detection" "Not supported,Supported"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 15. " CR ,Command List Running" "Stop,Running"
|
|
textline " "
|
|
bitfld.long 0x08 14. " FR ,FIS Receive Running" "Stop,Running"
|
|
textline " "
|
|
bitfld.long 0x08 13. " MPSS ,Mechanical Presence Switch State" "Closed,Open"
|
|
textline " "
|
|
bitfld.long 0x08 8.--12. " CCS ,Current Command Slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 4. " FRE ,FIS Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CLO ,Command List Override" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 2. " POD ,Power On Device" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SUD ,Spin-Up Device" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ST ,Start" "Not forced,Forced"
|
|
rgroup.long (0x100+0x20)++0x0B
|
|
line.long 0x00 "P0TFD,Port Task File Data Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ERR ,Contains the latest copy of the task file error register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " STS ,Contains the latest copy of the task file status register"
|
|
line.long 0x04 "P0SIG,Port Signature Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " LBA_HIGH ,LBA High (Cylinder High) Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LBA_MID ,LBA Mid (Cylinder Low) Register"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " LBA_LOW ,LBA Low (Sector Number) Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCR ,Sector Count Register"
|
|
width 9.
|
|
line.long 0x08 "P0SSTS,Port Serial ATA Status Register"
|
|
bitfld.long 0x08 8.--11. " IPM ,Interface Power Management" "Not present/Not established,Interface in active state,Partial,Reserved,Reserved,Reserved,Slumber,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " SPD ,Current Interface Speed" "Not present/Not established,1.5 Gbps,3 Gbps,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " DET ,Device Detection" "No detected/not established,Detected/Not established,Reserved,Detected/Established,0ffline mode/Disabled /BIST loopback mode,?..."
|
|
group.long (0x100+0x2C)++0x13
|
|
line.long 0x00 "P0SCTL,Port Serial ATA Control Register"
|
|
bitfld.long 0x00 8.--11. " IPM ,Interface Power Management Transitions Allowed" "No interface power management state restrictions,Transitions to the Partial state are disabled,Transitions to the Slumber state are disabled,Transitions to both Partial and Slumber states are disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SPD ,Speed Allowed" "No speed negotiation restrictions,1.5 Gbps,3 Gbps,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DET ,Device Detection Initialization" "No device detection /Requested,Interface initialization sequence,Reserved,Reserved,Disabled/Offline mode,?..."
|
|
width 9.
|
|
line.long 0x04 "P0SERR,Port Serial ATA Error Register"
|
|
eventfld.long 0x04 26. " DIAG_X ,Exchanged" "No error,Error"
|
|
eventfld.long 0x04 25. " DIAG_F ,Unknown FIS Type" "No error,Error"
|
|
eventfld.long 0x04 24. " DIAG_T ,Transport State Transition Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 23. " DIAG_S ,Link Sequence Error" "No error,Error"
|
|
eventfld.long 0x04 22. " DIAG_H ,Handshake Error" "No error,Error"
|
|
eventfld.long 0x04 21. " DIAG_C ,CRC Error" "No error,Error"
|
|
textline " "
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("AM387*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1810"&&cpu()!="AM1808")
|
|
eventfld.long 0x04 20. " DIAG_D ,Disparity Error" "No error,Error"
|
|
else
|
|
bitfld.long 0x04 20. " DIAG_D ,Disparity Error" "No error,Error"
|
|
endif
|
|
eventfld.long 0x04 19. " DIAG_B ,10B to 8B Decode Error" "No error,Error"
|
|
eventfld.long 0x04 18. " DIAG_W ,Comm Wake" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 17. " DIAG_I ,PHY Internal Error" "No error,Error"
|
|
eventfld.long 0x04 16. " DIAG_N ,PHY Ready Change" "No error,Error"
|
|
eventfld.long 0x04 11. " ERR_E ,Internal Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 10. " ERR_P ,Protocol Error" "No error,Error"
|
|
eventfld.long 0x04 9. " ERR_C ,Non-recovered Persistent Communication Error" "No error,Error"
|
|
eventfld.long 0x04 8. " ERR_T ,Non-recovered Transient Data Integrity Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 1. " ERR_M ,Recovered Communication Error" "No error,Error"
|
|
eventfld.long 0x04 0. " ERR_I ,Recovered Data Integrity" "No error,Error"
|
|
line.long 0x08 "P0SACT,Port Serial ATA Active Register"
|
|
bitfld.long 0x08 31. " DS[31] ,Bit 31 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 30. " DS[30] ,Bit 30 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 29. " DS[29] ,Bit 29 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 28. " DS[28] ,Bit 28 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 27. " DS[27] ,Bit 27 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 26. " DS[26] ,Bit 26 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 25. " DS[25] ,Bit 25 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 24. " DS[24] ,Bit 24 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 23. " DS[23] ,Bit 23 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 22. " DS[22] ,Bit 22 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 21. " DS[21] ,Bit 21 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 20. " DS[20] ,Bit 20 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 19. " DS[19] ,Bit 19 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 18. " DS[18] ,Bit 18 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 17. " DS[17] ,Bit 17 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DS[16] ,Bit 16 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 15. " DS[15] ,Bit 15 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 14. " DS[14] ,Bit 14 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DS[13] ,Bit 13 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 12. " DS[12] ,Bit 12 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 11. " DS[11] ,Bit 11 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DS[10] ,Bit 10 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 9. " DS[9] ,Bit 9 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 8. " DS[8] ,Bit 8 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DS[7] ,Bit 7 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 6. " DS[6] ,Bit 6 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 5. " DS[5] ,Bit 5 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 4. " DS[4] ,Bit 4 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 3. " DS[3] ,Bit 3 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 2. " DS[2] ,Bit 2 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DS[1] ,Bit 1 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 0. " DS[0] ,Bit 0 corresponds to the TAG" "Low,High"
|
|
line.long 0x0C "P0CI,Port Command Issue Register"
|
|
bitfld.long 0x0C 31. " CI[31] ,Bit 31 corresponds to a command slot 31" "Low,High"
|
|
bitfld.long 0x0C 30. " CI[30] ,Bit 30 corresponds to a command slot 30" "Low,High"
|
|
bitfld.long 0x0C 29. " CI[29] ,Bit 29 corresponds to a command slot 29" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " CI[28] ,Bit 28 corresponds to a command slot 28" "Low,High"
|
|
bitfld.long 0x0C 27. " CI[27] ,Bit 27 corresponds to a command slot 27" "Low,High"
|
|
bitfld.long 0x0C 26. " CI[26] ,Bit 26 corresponds to a command slot 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " CI[25] ,Bit 25 corresponds to a command slot 25" "Low,High"
|
|
bitfld.long 0x0C 24. " CI[24] ,Bit 24 corresponds to a command slot 24" "Low,High"
|
|
bitfld.long 0x0C 23. " CI[23] ,Bit 23 corresponds to a command slot 23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " CI[22] ,Bit 22 corresponds to a command slot 22" "Low,High"
|
|
bitfld.long 0x0C 21. " CI[21] ,Bit 21 corresponds to a command slot 21" "Low,High"
|
|
bitfld.long 0x0C 20. " CI[20] ,Bit 20 corresponds to a command slot 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CI[19] ,Bit 19 corresponds to a command slot 19" "Low,High"
|
|
bitfld.long 0x0C 18. " CI[18] ,Bit 18 corresponds to a command slot 18" "Low,High"
|
|
bitfld.long 0x0C 17. " CI[17] ,Bit 17 corresponds to a command slot 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " CI[16] ,Bit 16 corresponds to a command slot 16" "Low,High"
|
|
bitfld.long 0x0C 15. " CI[15] ,Bit 15 corresponds to a command slot 15" "Low,High"
|
|
bitfld.long 0x0C 14. " CI[14] ,Bit 14 corresponds to a command slot 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CI[13] ,Bit 13 corresponds to a command slot 13" "Low,High"
|
|
bitfld.long 0x0C 12. " CI[12] ,Bit 12 corresponds to a command slot 12" "Low,High"
|
|
bitfld.long 0x0C 11. " CI[11] ,Bit 11 corresponds to a command slot 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CI[10] ,Bit 10 corresponds to a command slot 10" "Low,High"
|
|
bitfld.long 0x0C 9. " CI[9] ,Bit 9 corresponds to a command slot 9" "Low,High"
|
|
bitfld.long 0x0C 8. " CI[8] ,Bit 8 corresponds to a command slot 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CI[7] ,Bit 7 corresponds to a command slot 7" "Low,High"
|
|
bitfld.long 0x0C 6. " CI[6] ,Bit 6 corresponds to a command slot 6" "Low,High"
|
|
bitfld.long 0x0C 5. " CI[5] ,Bit 5 corresponds to a command slot 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CI[4] ,Bit 4 corresponds to a command slot 4" "Low,High"
|
|
bitfld.long 0x0C 3. " CI[3] ,Bit 3 corresponds to a command slot 3" "Low,High"
|
|
bitfld.long 0x0C 2. " CI[2] ,Bit 2 corresponds to a command slot 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CI[1] ,Bit 1 corresponds to a command slot 1" "Low,High"
|
|
bitfld.long 0x0C 0. " CI[0] ,Bit 0 corresponds to a command slot 0" "Low,High"
|
|
line.long 0x10 "P0SNTF,Port Serial ATA Notification Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1810"&&cpu()!="AM1808")
|
|
eventfld.long 0x10 15. " PMN[15] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 14. " PMN[14] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 13. " PMN[13] ,PM Notify" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x10 12. " PMN[12] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 11. " PMN[11] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 10. " PMN[10] ,PM Notify" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x10 9. " PMN[9] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 8. " PMN[8] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 7. " PMN[7] ,PM Notify" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x10 6. " PMN[6] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 5. " PMN[5] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 4. " PMN[4] ,PM Notify" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x10 3. " PMN[3] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 2. " PMN[2] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 1. " PMN[1] ,PM Notify" "Low,High"
|
|
else
|
|
sif (cpu()!="AM1810"&&cpu()!="AM1808")
|
|
eventfld.long 0x10 1. " PMN[1] ,PM Notify" "Low,High"
|
|
endif
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x10 0. " PMN[0] ,PM Notify" "Low,High"
|
|
width 9.
|
|
group.long (0x100+0x70)++0x03
|
|
line.long 0x00 "P0DMACR,Port DMA Control Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
bitfld.long 0x00 12.--15. " RXABL ,Receive Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
|
|
bitfld.long 0x00 8.--11. " TXABL ,Transmit Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " RXTS ,Receive Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDs,512 DWORDs,1024 DWORDs,?..."
|
|
bitfld.long 0x00 0.--3. " TXTS ,Transmit Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDs,512 DWORDs,1024 DWORDs,?..."
|
|
else
|
|
bitfld.long 0x00 12.--15. " RXABL ,Receive Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,Reserved,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
|
|
bitfld.long 0x00 8.--11. " TXABL ,Transmit Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,Reserved,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " RXTS ,Receive Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,?..."
|
|
bitfld.long 0x00 0.--3. " TXTS ,Transmit Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,?..."
|
|
endif
|
|
sif (!(cpuis("AM387*")))
|
|
group.long (0x100+0x78)++0x03
|
|
line.long 0x00 "P0PHYCR,Port PHY Control Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
bitfld.long 0x00 31. " ENPLL ,Enable Phy PLL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 30. " OVERRIDE ,Override for Clock Stopping" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXDE ,Transmitter De-Emphasis" "0%,4.76%,9.52%,14.28%,19.04%,23.8%,28.56%,33.32%,38.08%,42.85%,47.61%,52.38%,57.14%,61.9%,66.66%,71.42%"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TXSWING ,Transmitter Output Swing" "125,250,500,625,750,1000,1250,1375"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TXCM ,Transmitter Common Mode" "Normal,Raised"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TXINVPAIR ,Transmitter Invert Polarity" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13.--16. " RXEQ ,Receiver Equalizer" "-,Adaptive,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,365 MHz,275 MHz,195 MHz,140 MHz,105 MHz,75 MHz,55 MHz,50 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " RXCDR ,Receiver Clock/data Recovery" "First order/Threshold of 1,First order/Threshold of 16,Second order/High precision/Threshold of 1,Second order/High precision/Threshold of 16,Second order/Low precision/Threshold of 1,Second order/Low precision/Threshold of 16,First order/Threshold of 1 with fast lock,Second order/Low precision with fast lock"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RXTERM ,Receiver Termination" "V_SSA,0.8 V_DDA,0.2 V_DDA,Wide common mode range"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXINVPAIR ,Receiver Invert Polarity" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOS ,Loss of Signal Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " LB ,Loop Bandwidth" "Medium,Ultra High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MPY ,PLL Multiply" "Reserved,5x,6x,Reserved,8x,10x,12x,12.5x,15x,20x,25x,?..."
|
|
else
|
|
bitfld.long 0x00 27.--31. " TXDE ,Transmitter De-Emphasis" "0%,4.76%,9.52%,14.28%,19.04%,23.8%,28.56%,33.32%,38.08%,42.85%,47.61%,52.38%,57.14%,61.9%,66.66%,71.42%,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--26. " TXSWING ,Transmitter Output Swing" "100,1,2,3,4,5,6,7,8,9,10,11,12,13,14,1000"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXCM ,Transmitter Common Mode" "Normal,Raised"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TXINVPAIR ,Transmitter Invert Polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RXENOC ,Receiver Offset Compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RXEQ ,Receiver Equalizer Configuration (Low Frequency Gain/Zero Frequency)" "Max/-,Adaptive,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Adaptive/365 MHz,Adaptive/275 MHz,Adaptive/195 MHz,Adaptive/140 MHz,Adaptive/105 MHz,Adaptive/75 MHz,Adaptive/55 MHz,Adaptive/50 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " RXCDR ,Receiver Clock/data Recovery" "First order/Threshold of 1,First order/Threshold of 17,Second order/High precision/Threshold of 1,Second order/High precision/Threshold of 1,Second order/Low precision/Threshold of 1,Second order/Low precision/Threshold of 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " RXLOS ,Loss of Signal Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " LOOPBACK ,Transmitter(T) and Receiver(R) Loopback(LB) Selection" "T/R-Disabled,Reserved,T-LB/R-N/A,T/R-LB"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RXINVPAIR ,Receiver Invert Polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " CLKBYP ,Clock Bypass" "Not bypassed,Reserved,Functional,REFCLK observe"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " LB ,Loopback enable" "Disabled,Reserved,Inner/CML-disabled,Inner/CML-enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " MPY ,PLL Multiply" "4x,5x,6x,8x,8.25x,10x,12x,12.5x,15x,16x,16.5x,20x,22x,25x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENPLL ,Enable PHY PLL" "Disabled,Enabled"
|
|
endif
|
|
width 9.
|
|
rgroup.long (0x100+0x7C)++0x03
|
|
line.long 0x00 "P0PHYSR,Port PHY Status Register"
|
|
bitfld.long 0x00 1. " SIGDET ,Signal Detect" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " LOCK ,PLL Lock" "Not locked,Locked"
|
|
endif
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "P1CLB,Port Command List Base Address Register"
|
|
hexmask.long 0x00 10.--31. 0x400 " CLB ,Command List Base Address"
|
|
group.long (0x180+0x08)++0x03
|
|
line.long 0x00 "P1FB,Port FIS Base Address Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " FB ,FIS Base Address"
|
|
group.long (0x180+0x10)++0x0B
|
|
line.long 0x00 "P1IS,Port Interrupt Status Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
eventfld.long 0x00 31. " CPDS ,Cold Port Detect Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 30. " TFES ,Task File Error Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " HBFS ,Host Bus Fatal Error Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 28. " HBDS ,Host Bus Data Error Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IFS ,Interface Fatal Error Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 26. " INFS ,Interface Non-fatal Error Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 24. " OFS ,Overflow Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IPMS ,Incorrect Port Multiplier Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PRCS ,PHYReady Change Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " DMPS ,Device Mechanical Presence Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PCS ,Port Connect Change Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " DPS ,Descriptor Processed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFS ,Unknown FIS Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " SDBS ,Set Device Bits Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DSS ,DMA Setup FIS Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PSS ,PIO Setup FIS Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " DHRS ,Device to Host Register FIS Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "P1IE,Port Interrupt Enable Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
bitfld.long 0x04 31. " CPDE ,Cold Port Detect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 30. " TFEE ,Task File Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " HBFE ,Host Bus Fatal Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " HBDE ,Host Bus Data Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " IFE ,Interface Fatal Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 26. " INFE ,Interface Non-fatal Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " OFE ,Overflow Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IPME ,Incorrect Port Multiplier Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " PRCE ,PHYReady Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DMPE ,Device Mechanical Presence Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PCE ,Port Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DPE ,Descriptor Processed Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " UFE ,Unknown FIS Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SDBE ,Set Device Bits FIS Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DSE ,DMA Setup FIS Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PSE ,PIO Setup FIS Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DHRE ,Device Host Register FIS Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x08 "P1CMD,Port Command Register"
|
|
bitfld.long 0x08 28.--31. " ICC ,Interface Communication Control" "No-Op/ Idle,Active,Partial,Reserved,Reserved,Reserved,Slumber,?..."
|
|
textline " "
|
|
bitfld.long 0x08 27. " ASP ,Aggressive Slumber/Partial" "Partial,Slumber"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ALPE ,Aggressive Link Power Management Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " DLAE ,Drive LED on ATAPI Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " ATAPI ,Device is ATAPI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " ESP ,External SATA Port" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
bitfld.long 0x08 20. " CPD ,Cold Presence Detection" "Not supported,Supported"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 19. " MPSP ,Mechanical Presence Switch Attached to Port" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 18. " HPCP ,Hot Plug" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " PMA ,Port Multiplier Attached" "Not attached,Attached"
|
|
textline " "
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
bitfld.long 0x08 16. " CPS ,Cold Presence State" "Not attached,Attached"
|
|
else
|
|
bitfld.long 0x08 16. " CPD ,Cold Presence Detection" "Not supported,Supported"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 15. " CR ,Command List Running" "Stop,Running"
|
|
textline " "
|
|
bitfld.long 0x08 14. " FR ,FIS Receive Running" "Stop,Running"
|
|
textline " "
|
|
bitfld.long 0x08 13. " MPSS ,Mechanical Presence Switch State" "Closed,Open"
|
|
textline " "
|
|
bitfld.long 0x08 8.--12. " CCS ,Current Command Slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 4. " FRE ,FIS Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CLO ,Command List Override" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 2. " POD ,Power On Device" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SUD ,Spin-Up Device" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ST ,Start" "Not forced,Forced"
|
|
rgroup.long (0x180+0x20)++0x0B
|
|
line.long 0x00 "P1TFD,Port Task File Data Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ERR ,Contains the latest copy of the task file error register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " STS ,Contains the latest copy of the task file status register"
|
|
line.long 0x04 "P1SIG,Port Signature Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " LBA_HIGH ,LBA High (Cylinder High) Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LBA_MID ,LBA Mid (Cylinder Low) Register"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " LBA_LOW ,LBA Low (Sector Number) Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCR ,Sector Count Register"
|
|
width 9.
|
|
line.long 0x08 "P1SSTS,Port Serial ATA Status Register"
|
|
bitfld.long 0x08 8.--11. " IPM ,Interface Power Management" "Not present/Not established,Interface in active state,Partial,Reserved,Reserved,Reserved,Slumber,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " SPD ,Current Interface Speed" "Not present/Not established,1.5 Gbps,3 Gbps,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " DET ,Device Detection" "No detected/not established,Detected/Not established,Reserved,Detected/Established,0ffline mode/Disabled /BIST loopback mode,?..."
|
|
group.long (0x180+0x2C)++0x13
|
|
line.long 0x00 "P1SCTL,Port Serial ATA Control Register"
|
|
bitfld.long 0x00 8.--11. " IPM ,Interface Power Management Transitions Allowed" "No interface power management state restrictions,Transitions to the Partial state are disabled,Transitions to the Slumber state are disabled,Transitions to both Partial and Slumber states are disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SPD ,Speed Allowed" "No speed negotiation restrictions,1.5 Gbps,3 Gbps,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DET ,Device Detection Initialization" "No device detection /Requested,Interface initialization sequence,Reserved,Reserved,Disabled/Offline mode,?..."
|
|
width 9.
|
|
line.long 0x04 "P1SERR,Port Serial ATA Error Register"
|
|
eventfld.long 0x04 26. " DIAG_X ,Exchanged" "No error,Error"
|
|
eventfld.long 0x04 25. " DIAG_F ,Unknown FIS Type" "No error,Error"
|
|
eventfld.long 0x04 24. " DIAG_T ,Transport State Transition Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 23. " DIAG_S ,Link Sequence Error" "No error,Error"
|
|
eventfld.long 0x04 22. " DIAG_H ,Handshake Error" "No error,Error"
|
|
eventfld.long 0x04 21. " DIAG_C ,CRC Error" "No error,Error"
|
|
textline " "
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("AM387*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1810"&&cpu()!="AM1808")
|
|
eventfld.long 0x04 20. " DIAG_D ,Disparity Error" "No error,Error"
|
|
else
|
|
bitfld.long 0x04 20. " DIAG_D ,Disparity Error" "No error,Error"
|
|
endif
|
|
eventfld.long 0x04 19. " DIAG_B ,10B to 8B Decode Error" "No error,Error"
|
|
eventfld.long 0x04 18. " DIAG_W ,Comm Wake" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 17. " DIAG_I ,PHY Internal Error" "No error,Error"
|
|
eventfld.long 0x04 16. " DIAG_N ,PHY Ready Change" "No error,Error"
|
|
eventfld.long 0x04 11. " ERR_E ,Internal Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 10. " ERR_P ,Protocol Error" "No error,Error"
|
|
eventfld.long 0x04 9. " ERR_C ,Non-recovered Persistent Communication Error" "No error,Error"
|
|
eventfld.long 0x04 8. " ERR_T ,Non-recovered Transient Data Integrity Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 1. " ERR_M ,Recovered Communication Error" "No error,Error"
|
|
eventfld.long 0x04 0. " ERR_I ,Recovered Data Integrity" "No error,Error"
|
|
line.long 0x08 "P1SACT,Port Serial ATA Active Register"
|
|
bitfld.long 0x08 31. " DS[31] ,Bit 31 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 30. " DS[30] ,Bit 30 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 29. " DS[29] ,Bit 29 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 28. " DS[28] ,Bit 28 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 27. " DS[27] ,Bit 27 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 26. " DS[26] ,Bit 26 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 25. " DS[25] ,Bit 25 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 24. " DS[24] ,Bit 24 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 23. " DS[23] ,Bit 23 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 22. " DS[22] ,Bit 22 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 21. " DS[21] ,Bit 21 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 20. " DS[20] ,Bit 20 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 19. " DS[19] ,Bit 19 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 18. " DS[18] ,Bit 18 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 17. " DS[17] ,Bit 17 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DS[16] ,Bit 16 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 15. " DS[15] ,Bit 15 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 14. " DS[14] ,Bit 14 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DS[13] ,Bit 13 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 12. " DS[12] ,Bit 12 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 11. " DS[11] ,Bit 11 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DS[10] ,Bit 10 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 9. " DS[9] ,Bit 9 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 8. " DS[8] ,Bit 8 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DS[7] ,Bit 7 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 6. " DS[6] ,Bit 6 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 5. " DS[5] ,Bit 5 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 4. " DS[4] ,Bit 4 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 3. " DS[3] ,Bit 3 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 2. " DS[2] ,Bit 2 corresponds to the TAG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DS[1] ,Bit 1 corresponds to the TAG" "Low,High"
|
|
bitfld.long 0x08 0. " DS[0] ,Bit 0 corresponds to the TAG" "Low,High"
|
|
line.long 0x0C "P1CI,Port Command Issue Register"
|
|
bitfld.long 0x0C 31. " CI[31] ,Bit 31 corresponds to a command slot 31" "Low,High"
|
|
bitfld.long 0x0C 30. " CI[30] ,Bit 30 corresponds to a command slot 30" "Low,High"
|
|
bitfld.long 0x0C 29. " CI[29] ,Bit 29 corresponds to a command slot 29" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " CI[28] ,Bit 28 corresponds to a command slot 28" "Low,High"
|
|
bitfld.long 0x0C 27. " CI[27] ,Bit 27 corresponds to a command slot 27" "Low,High"
|
|
bitfld.long 0x0C 26. " CI[26] ,Bit 26 corresponds to a command slot 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " CI[25] ,Bit 25 corresponds to a command slot 25" "Low,High"
|
|
bitfld.long 0x0C 24. " CI[24] ,Bit 24 corresponds to a command slot 24" "Low,High"
|
|
bitfld.long 0x0C 23. " CI[23] ,Bit 23 corresponds to a command slot 23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " CI[22] ,Bit 22 corresponds to a command slot 22" "Low,High"
|
|
bitfld.long 0x0C 21. " CI[21] ,Bit 21 corresponds to a command slot 21" "Low,High"
|
|
bitfld.long 0x0C 20. " CI[20] ,Bit 20 corresponds to a command slot 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CI[19] ,Bit 19 corresponds to a command slot 19" "Low,High"
|
|
bitfld.long 0x0C 18. " CI[18] ,Bit 18 corresponds to a command slot 18" "Low,High"
|
|
bitfld.long 0x0C 17. " CI[17] ,Bit 17 corresponds to a command slot 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " CI[16] ,Bit 16 corresponds to a command slot 16" "Low,High"
|
|
bitfld.long 0x0C 15. " CI[15] ,Bit 15 corresponds to a command slot 15" "Low,High"
|
|
bitfld.long 0x0C 14. " CI[14] ,Bit 14 corresponds to a command slot 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CI[13] ,Bit 13 corresponds to a command slot 13" "Low,High"
|
|
bitfld.long 0x0C 12. " CI[12] ,Bit 12 corresponds to a command slot 12" "Low,High"
|
|
bitfld.long 0x0C 11. " CI[11] ,Bit 11 corresponds to a command slot 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CI[10] ,Bit 10 corresponds to a command slot 10" "Low,High"
|
|
bitfld.long 0x0C 9. " CI[9] ,Bit 9 corresponds to a command slot 9" "Low,High"
|
|
bitfld.long 0x0C 8. " CI[8] ,Bit 8 corresponds to a command slot 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CI[7] ,Bit 7 corresponds to a command slot 7" "Low,High"
|
|
bitfld.long 0x0C 6. " CI[6] ,Bit 6 corresponds to a command slot 6" "Low,High"
|
|
bitfld.long 0x0C 5. " CI[5] ,Bit 5 corresponds to a command slot 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CI[4] ,Bit 4 corresponds to a command slot 4" "Low,High"
|
|
bitfld.long 0x0C 3. " CI[3] ,Bit 3 corresponds to a command slot 3" "Low,High"
|
|
bitfld.long 0x0C 2. " CI[2] ,Bit 2 corresponds to a command slot 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CI[1] ,Bit 1 corresponds to a command slot 1" "Low,High"
|
|
bitfld.long 0x0C 0. " CI[0] ,Bit 0 corresponds to a command slot 0" "Low,High"
|
|
line.long 0x10 "P1SNTF,Port Serial ATA Notification Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1810"&&cpu()!="AM1808")
|
|
eventfld.long 0x10 15. " PMN[15] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 14. " PMN[14] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 13. " PMN[13] ,PM Notify" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x10 12. " PMN[12] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 11. " PMN[11] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 10. " PMN[10] ,PM Notify" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x10 9. " PMN[9] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 8. " PMN[8] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 7. " PMN[7] ,PM Notify" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x10 6. " PMN[6] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 5. " PMN[5] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 4. " PMN[4] ,PM Notify" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x10 3. " PMN[3] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 2. " PMN[2] ,PM Notify" "Low,High"
|
|
eventfld.long 0x10 1. " PMN[1] ,PM Notify" "Low,High"
|
|
else
|
|
sif (cpu()!="AM1810"&&cpu()!="AM1808")
|
|
eventfld.long 0x10 1. " PMN[1] ,PM Notify" "Low,High"
|
|
endif
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x10 0. " PMN[0] ,PM Notify" "Low,High"
|
|
width 9.
|
|
group.long (0x180+0x70)++0x03
|
|
line.long 0x00 "P1DMACR,Port DMA Control Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
bitfld.long 0x00 12.--15. " RXABL ,Receive Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
|
|
bitfld.long 0x00 8.--11. " TXABL ,Transmit Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " RXTS ,Receive Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDs,512 DWORDs,1024 DWORDs,?..."
|
|
bitfld.long 0x00 0.--3. " TXTS ,Transmit Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDs,512 DWORDs,1024 DWORDs,?..."
|
|
else
|
|
bitfld.long 0x00 12.--15. " RXABL ,Receive Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,Reserved,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
|
|
bitfld.long 0x00 8.--11. " TXABL ,Transmit Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,Reserved,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " RXTS ,Receive Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,?..."
|
|
bitfld.long 0x00 0.--3. " TXTS ,Transmit Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,?..."
|
|
endif
|
|
sif (!(cpuis("AM387*")))
|
|
group.long (0x180+0x78)++0x03
|
|
line.long 0x00 "P1PHYCR,Port PHY Control Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
bitfld.long 0x00 31. " ENPLL ,Enable Phy PLL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 30. " OVERRIDE ,Override for Clock Stopping" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXDE ,Transmitter De-Emphasis" "0%,4.76%,9.52%,14.28%,19.04%,23.8%,28.56%,33.32%,38.08%,42.85%,47.61%,52.38%,57.14%,61.9%,66.66%,71.42%"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TXSWING ,Transmitter Output Swing" "125,250,500,625,750,1000,1250,1375"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TXCM ,Transmitter Common Mode" "Normal,Raised"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TXINVPAIR ,Transmitter Invert Polarity" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13.--16. " RXEQ ,Receiver Equalizer" "-,Adaptive,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,365 MHz,275 MHz,195 MHz,140 MHz,105 MHz,75 MHz,55 MHz,50 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " RXCDR ,Receiver Clock/data Recovery" "First order/Threshold of 1,First order/Threshold of 16,Second order/High precision/Threshold of 1,Second order/High precision/Threshold of 16,Second order/Low precision/Threshold of 1,Second order/Low precision/Threshold of 16,First order/Threshold of 1 with fast lock,Second order/Low precision with fast lock"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RXTERM ,Receiver Termination" "V_SSA,0.8 V_DDA,0.2 V_DDA,Wide common mode range"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXINVPAIR ,Receiver Invert Polarity" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOS ,Loss of Signal Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " LB ,Loop Bandwidth" "Medium,Ultra High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MPY ,PLL Multiply" "Reserved,5x,6x,Reserved,8x,10x,12x,12.5x,15x,20x,25x,?..."
|
|
else
|
|
bitfld.long 0x00 27.--31. " TXDE ,Transmitter De-Emphasis" "0%,4.76%,9.52%,14.28%,19.04%,23.8%,28.56%,33.32%,38.08%,42.85%,47.61%,52.38%,57.14%,61.9%,66.66%,71.42%,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--26. " TXSWING ,Transmitter Output Swing" "100,1,2,3,4,5,6,7,8,9,10,11,12,13,14,1000"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXCM ,Transmitter Common Mode" "Normal,Raised"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TXINVPAIR ,Transmitter Invert Polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RXENOC ,Receiver Offset Compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RXEQ ,Receiver Equalizer Configuration (Low Frequency Gain/Zero Frequency)" "Max/-,Adaptive,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Adaptive/365 MHz,Adaptive/275 MHz,Adaptive/195 MHz,Adaptive/140 MHz,Adaptive/105 MHz,Adaptive/75 MHz,Adaptive/55 MHz,Adaptive/50 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " RXCDR ,Receiver Clock/data Recovery" "First order/Threshold of 1,First order/Threshold of 17,Second order/High precision/Threshold of 1,Second order/High precision/Threshold of 1,Second order/Low precision/Threshold of 1,Second order/Low precision/Threshold of 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " RXLOS ,Loss of Signal Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " LOOPBACK ,Transmitter(T) and Receiver(R) Loopback(LB) Selection" "T/R-Disabled,Reserved,T-LB/R-N/A,T/R-LB"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RXINVPAIR ,Receiver Invert Polarity" "Not inverted,Inverted"
|
|
endif
|
|
width 9.
|
|
rgroup.long (0x180+0x7C)++0x03
|
|
line.long 0x00 "P1PHYSR,Port PHY Status Register"
|
|
bitfld.long 0x00 1. " SIGDET ,Signal Detect" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " LOCK ,PLL Lock" "Not locked,Locked"
|
|
endif
|
|
sif ((cpuis("AM389*"))||((cpuis("AM387*")))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpu()=="AM3874")||(cpu()=="AM3872")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
width 9.
|
|
group.long 0x1100++0x07
|
|
line.long 0x00 "IDLE,Idle Register"
|
|
bitfld.long 0x00 17. " OVERRIDE1 ,Override for Clock Stopping" "Normal,Override"
|
|
bitfld.long 0x00 16. " OVERRIDE0 ,Override for Clock Stopping" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " STANDBYMODE ,Standby_mode controle" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " IDLEMODE ,Idle_mode controle" "0,1,2,3"
|
|
sif cpuis("AM387*")
|
|
line.long 0x04 "CFGRX0,PHY Configuration Receive 0 Register"
|
|
bitfld.long 0x04 31. " LOOPBACK[1] ,Internal Digital loop back" "Disabled,Not supported"
|
|
bitfld.long 0x04 30. " LOOPBACK[0] ,Internal Analog loop back" "Disabled,Not supported"
|
|
textline " "
|
|
bitfld.long 0x04 29. " RX_TRIM_BYPASS ,Trim bits generated from the calibration algorithm bypass (for calibration)" "Not bypassed,Bypassed"
|
|
bitfld.long 0x04 28. " CDR_ELV_IDLE_FIX ,CDR ELV Idle fix" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " CDRAUX ,Clock/data recovery auxilliary" "0,1,2,3"
|
|
bitfld.long 0x04 24.--25. " CAL_FILTER_DEPTH ,Average engine depth (for calibration)" "7 samples,15 samples,31 samples,7 samples"
|
|
textline " "
|
|
bitfld.long 0x04 23. " ENOC ,Enable offset compensation" "Disabled,Enabled"
|
|
bitfld.long 0x04 19.--22. " EQ ,Equalizer" "Disabled,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " CDR ,Clock/data recovery" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 13.--15. " LOS ,Enables loss of signal detection" "Disabled,Enabled (without CDR override control),Enabled (with CDR override control),Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 11.--12. " ALIGN ,Symbol alignment" "Disabled,Coma alignment,Alignment Jog,?..."
|
|
bitfld.long 0x04 8.--10. " TERM ,Selects input termination options" "Reserved,Common point set to 0.8 VDDA,Reserved,Common point floating,Common point set to VSSA,Common point set to 0.2 VDDA,Reserved,Common point floating"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INVPAIR ,Inverts polarity of RXPi and RXNi" "Not inverted,Inverted"
|
|
bitfld.long 0x04 5.--6. " RATE ,Value being driven to the phy's RATE field" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 2.--4. " BUSWIDTH ,Parallel interface width" "10-bit,?..."
|
|
bitfld.long 0x04 1. " ENRXLDO ,Enables RXLDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENRX ,Reflects the ENRX of the phy" "Not received,Received"
|
|
else
|
|
line.long 0x04 "PHYCFGR2,PHY Configuration Register 2"
|
|
bitfld.long 0x04 8.--9. " P1ALIGN ,Port 1 Comma Alignment Enable" "Disabled,Enabled,Jog,?..."
|
|
bitfld.long 0x04 6.--7. " P0ALIGN ,Port 0 Comma Alignment Enable" "Disabled,Enabled,Jog,?..."
|
|
textline " "
|
|
bitfld.long 0x04 3.--5. " P1LOS ,Port 1 Loss-of-Signal Configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " P0LOS ,Port 0 Loss-of-Signal Configuration" "0,1,2,3,4,5,6,7"
|
|
endif
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endif
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sif cpuis("AM387*")
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width 11.
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group.long 0x1108++0x2b
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line.long 0x00 "CFGRX1,PHY Configuration Receive 1 Register"
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bitfld.long 0x00 30.--31. " EQ_ICM_S2 ,Trims common mode pullup current in second equalizer stage" "0,1,2,3"
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bitfld.long 0x00 28.--29. " EQ_ICM_S1 ,Trims common mode pullup current in first equalizer stage" "0,1,2,3"
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textline " "
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bitfld.long 0x00 21.--23. " EQ_I_STAGE2 ,Trims the current in the second stage of the equalizer" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 18.--20. " EQ_I_STAGEFB ,Trims the current in the feedback stage of the equalizer" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 15.--17. " EQ_I_STAGE1 ,Trims the current in the first stage of the equalizer" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 14. " ANALOG_LOOPBACK ,Enables analog loop back" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 13. " RXTRIM_CALIB ,RX trimming control to the calibration block" "Functional mode,eFuse training mode"
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bitfld.long 0x00 12. " RXTRIM_BYPASS_CTRL ,RXTRIM bypass control" "Fuse/calib,Cfg_ctrl"
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textline " "
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bitfld.long 0x00 7.--11. " RXTRIM_BYPASS_BITS ,Bypass bits for RXTRIM[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6. " BYPASS_CALOUT_AVG ,Bypasses the averaging filter for the calout signal inside digital (for calibration)" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x00 5. " CTG_DIG_RSVD1 ,Clock inversion for rpclk" "Not inverted,Inverted"
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bitfld.long 0x00 4. " CTG_DIG_RSVD0 ,Clock inversion for fclk" "Not inverted,Inverted"
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textline " "
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bitfld.long 0x00 3. " ENTEST ,Value on the serdes_testpatt_p0_entestrx input" "Low,High"
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bitfld.long 0x00 0.--2. " TESTPATT ,Value on the serdes_testpatt_p0_testpatt input" "0,1,2,3,4,5,6,7"
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line.long 0x04 "CFGRX2,PHY Configuration Receive 2 Register"
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bitfld.long 0x04 27.--31. " SAMP_BYPASS_SAD1 ,Bypass bits for SAD1[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 22.--26. " SAMP_BYPASS_SAT0 ,Bypass bits for SAT0[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x04 17.--21. " SAMP_BYPASS_SAD0 ,Bypass bits for SAD0[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 12.--16. " SAMP_BYPASS_SAT1 ,Bypass bits for SAT1[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x08 "CFGRX3,PHY Configuration Receive 3 Register"
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bitfld.long 0x08 31. " AMUX_EYESCAN_REF ,Connect the eyescan reference voltages to the test mux inputs" "Low,High"
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bitfld.long 0x08 30. " SAMP_OC_SEL ,Sampler offset correction is controlled" "TRXDIG SAT1/SAD0/SAT0/SAD1,CFG_CTRL/CFGRX_2"
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textline " "
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bitfld.long 0x08 24.--29. " SAMP_ES_VREF_BYPASS_BITS ,Adjusts the eyescan reference voltage level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 20.--23. " SAMP_ESCM_RES ,Trims the pullup resistors in the eyescan common mode loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x08 17.--19. " SAMP_ESCM_I ,Trims the current in the eyescan common mode loop" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16. " SAMP_3_VREF_2_ES ,Sampler 3 VREF" "EQCM,Sampler 3"
|
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textline " "
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bitfld.long 0x08 15. " SAMP_2_VREF_2_ES ,Sampler 2 VREF" "EQCM,Sampler 2"
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bitfld.long 0x08 14. " SAMP_1_VREF_2_ES ,Sampler 1 VREF" "EQCM,Sampler 1"
|
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textline " "
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|
bitfld.long 0x08 13. " SAMP_0_VREF_2_ES ,Sampler 0 VREF" "EQCM,Sampler 0"
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bitfld.long 0x08 8.--12. " SAMP_IBIAS_Z ,Sampler bias" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x08 7. " SAMP_ES_VREF_BYPASS_CTRL ,Eyescan reference offset voltage control" "IEEE1500,CFGRX_3"
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bitfld.long 0x08 3. " SAMP_EN_3_ODD ,Samapler 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SAMP_EN_2_EOTR ,Sampler 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " SAMP_EN_1_EVEN ,Sampler 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SAMP_EN_0_OETR ,Sampler 0" "Disabled,Enabled"
|
|
line.long 0x0c "CFGRX4,PHY Configuration Receive 4 Register"
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bitfld.long 0x0c 28.--29. " RCLK_SAMP ,RCLK_SAMP[1:0]" "0,1,2,3"
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bitfld.long 0x0c 26.--27. " RCLK_DIG ,RCLK_DIG[1:0]" "0,1,2,3"
|
|
textline " "
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bitfld.long 0x0c 24. " DCD_EN_BUF ,DCD_EN_BUF" "Disabled,Enabled"
|
|
bitfld.long 0x0c 23. " DCD_EN_CLK ,DCD_EN_CLK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " DCD_EN_M ,DCD_EN_M" "Disabled,Enabled"
|
|
bitfld.long 0x0c 21. " DCD_EN_P ,DCD_EN_P" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " PI_VCM_Z_0 ,PI_VCM_Z[0]" "Low,High"
|
|
bitfld.long 0x0c 18. " PI_VCM_1 ,PI_VCM[1]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " PI_VCM_Z_2 ,PI_VCM_Z[2]" "Low,High"
|
|
bitfld.long 0x0c 16. " PI_VCM_Z_3 ,PI_VCM_Z[3]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " PI_BIAS_DISABLE ,PI_BIAS_DISABLE" "No,Yes"
|
|
bitfld.long 0x0c 14. " PI_ED_CAL_LEVEL_DEC ,PI_ED_CAL_LEVEL_DEC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " PI_ED_CAL_LEVEL_INC ,PI_ED_CAL_LEVEL_INC" "Low,High"
|
|
bitfld.long 0x0c 12. " PI_ED_CAL ,PI_ED_CAL" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " PI_ED_RESET ,PI_ED_RESET" "Low,High"
|
|
bitfld.long 0x0c 10. " PI_ED_EN ,PI_ED_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " PI_ED_VOUTP ,PI_ED_VOUTP" "Low,High"
|
|
bitfld.long 0x0c 8. " PI_ED_VOUTM ,PI_ED_VOUTM" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " PI_I50U ,PI_I50U" "Low,High"
|
|
bitfld.long 0x0c 6. " PI_I100U_Z ,PI_I100U_Z" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 0.--5. " PI_IBIAS_Z ,PI_IBIAS_Z[5:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x10 "PHY_STSRX,Receive Bus PHY-to-Controller Status Register"
|
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bitfld.long 0x10 11.--15. " RX_RTRIM ,Trim bits for RX resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 10. " RX_CALOUT_D ,CalOut after the digital filter" "Low,High"
|
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textline " "
|
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bitfld.long 0x10 9. " RX_CALOUT_A ,CalOut coming from analog" "Low,High"
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bitfld.long 0x10 6. " OCIP ,Offset Compensation in Progres. Driven high asynchronously during offset compensation" "Not in progres,In progres"
|
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textline " "
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bitfld.long 0x10 5. " BSRXN ,Boundary scan data" "Low,High"
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bitfld.long 0x10 4. " BSRXP ,Boundary scan data" "Low,High"
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textline " "
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bitfld.long 0x10 3. " LOSDTCT ,Loss of Signal detect" "Not detected,Detected"
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bitfld.long 0x10 2. " ODDCG ,Odd code group" "Not odd,Odd"
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textline " "
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bitfld.long 0x10 1. " SYNC ,Symbol alignment" "No alignment,Alignment"
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bitfld.long 0x10 0. " TESTFAIL ,Test failure" "Not failed,Failed"
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line.long 0x14 "CFGTX0,PHY Configuration Transmit 0 Register"
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bitfld.long 0x14 28.--29. " CAL_FILTER_DEPTH ,Average engine depth (for calibration)" "7 samples,15 samples,31 samples,7 samples"
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bitfld.long 0x14 25.--26. " DET_CTL ,Receiver detect control" "0,1,2,3"
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textline " "
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bitfld.long 0x14 24. " ENIDL ,Value of ENIDL field" "Normal,Idle"
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bitfld.long 0x14 21. " TM_EXTRA_LOAD[2] ,Enable different extraload resistors to make driver constant current at speed" "Disabled,Enabled"
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textline " "
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bitfld.long 0x14 20. " TM_EXTRA_LOAD[1] ,Enable static dummy load during electrical idle" "Disabled,Enabled"
|
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bitfld.long 0x14 19. " TM_EXTRA_LOAD[0] ,Enable switching dummy load during electrical idle" "Disabled,Enabled"
|
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textline " "
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|
bitfld.long 0x14 13.--17. " DEEMP ,Selects one of output de-emphasis settings (PCIE/eSATA full rate/eSata half rate)" "0/0/0,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved"
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bitfld.long 0x14 9.--12. " SWING ,TX Output swing selection" "148 (half),148 (half),258 (half),258 (half),295 (full/half),295 (full/half),516 (full/half),516 (full/half),774 (full/half),774 (full/half),1069 (full/half),1069 (full/half),1069 (full/half),1069 (full/half),1069 (full/half),1069 (full/half)"
|
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textline " "
|
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bitfld.long 0x14 7. " INVPAIR ,Inverts polarity of TXPi and TXNi" "Not inverted,Inverted"
|
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bitfld.long 0x14 5.--6. " RATE ,Value of the phy's RATE field" "0,1,2,3"
|
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textline " "
|
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bitfld.long 0x14 2.--4. " BUSWIDTH ,Selects the parallel interface width" "10-bit operation,?..."
|
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bitfld.long 0x14 1. " ENTXLDO ,Enables TX Analog LDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ENTX ,Value of the ENTX of the phy" "Reset/slumber,Enabled"
|
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line.long 0x18 "CFGTX1,PHY Configuration Transmit 1 Register"
|
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bitfld.long 0x18 28.--31. " TRIM_HIGH_THRESHOLD ,4-b programmable threshold (for calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 27. " TX_DISABLE_ON_THE_FLY ,Disables the pattern match (for calibration)" "No,Yes"
|
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textline " "
|
|
bitfld.long 0x18 26. " TX_FORCE_UPDATE ,Forces the update to be made to the Analog trim bits without looking for any specific data pattern or electrical idle (for calibration)" "Disabled,Enabled"
|
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bitfld.long 0x18 25. " TX_TRIM_BYPASS ,Bypasses the trim bits generated from the calibration algorithm (for calibration)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 24. " TRIM_2B_MODE ,Enables 2-b data pattern detection mode for trim updates (for calibration)" "Disabled,Enabled"
|
|
bitfld.long 0x18 21.--22. " TRIM_STEP_CHANGE ,Step change value for staircase logic (for calibration)" "1,2,4,8"
|
|
textline " "
|
|
bitfld.long 0x18 19.--20. " TRIM_LOW_THRESHOLD ,2-b programmable threshold (for calibration)" "Diff >= 1,Diff >= 2,Diff >= 3,Diff >= 4"
|
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bitfld.long 0x18 17.--18. " CALIB_WAIT_CYCLES ,2-b programmable number of wait cycles before polling the calout signal (for calibration)" "1 MHz clock,1 MHz clock,1 MHz clock,1 MHz clock"
|
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textline " "
|
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bitfld.long 0x18 16. " ENABLE_LOOP_DELAY ,Enables the additional loop delay of 40 clock cycles before sweeping the trim code during the calibration (for calibration)" "Disabled,Enabled"
|
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bitfld.long 0x18 15. " BYPASS_CALOUT_AVG ,Bypasses the averaging filter for the callout signal inside digital (for calibration)" "Not bypassed,Bypassed"
|
|
textline " "
|
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bitfld.long 0x18 13. " ENBSPLS ,Value of the serdes_bscan_ctrl_p0_enbspt input" "Low,High"
|
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bitfld.long 0x18 12. " ENBSRX ,Value of the serdes_bscan_ctrl_p0_enbsrx input" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 11. " ENBSTX ,Value of the serdes_bscan_ctrl_p0_enbstx input" "Low,High"
|
|
bitfld.long 0x18 10. " BSINITCLK ,Value of the serdes_bscan_clk_p0_bsinitclk input" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 9. " BSINRXN ,Value of the serdes_bscan_p0_bsinrxn input" "Low,High"
|
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bitfld.long 0x18 8. " BSINRXP ,Value of the serdes_bscan_p0_bsinrxp input" "Low,High"
|
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textline " "
|
|
bitfld.long 0x18 7. " TSYNC_ENABLE ,Tsync Enable" "Disabled,Enabled"
|
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bitfld.long 0x18 6. " ENTEST ,Value of the serdes_testpatt_p0_entesttx input" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 5. " BSTX ,Value of the serdes_bscan_p0_bstx input" "Low,High"
|
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bitfld.long 0x18 1. " USE_STAIRCASE ,Staircase logic for trim code change (for calibration)" "Disabled,Enabled"
|
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line.long 0x1c "CFGTX2,PHY Configuration Transmit 2 Register"
|
|
bitfld.long 0x1c 29.--30. " TM_DUMMY2IDLE ,Control ldo dummy digital load" "Disabled,1.5 mA,1.5 mA,3 mA"
|
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bitfld.long 0x1c 27.--28. " TM_DUMMY1IDLE ,Control ldo dummy resistor load" "Disabled,6 mA,9.6 mA,15 mA"
|
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textline " "
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bitfld.long 0x1c 25.--26. " TM_TEXTRALOAD ,Driver dummy current controlled by tx_extraload" "Disabled,1 mA,2 mA,3 mA"
|
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bitfld.long 0x1c 23. " DISABLE_FB1_TM_SRCONTROL ,DISABLE_FB1_TM_SRCONTROL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x1c 21.--22. " SC_SATA ,Control for SATA slew-control" "0,1,2,3"
|
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bitfld.long 0x1c 19.--20. " SC_PCIE ,Control for PCIe slew-control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x1c 18. " DISABLE_PCIE_SC ,Output divider slew-rate control for PCIe mode" "No,Yes"
|
|
bitfld.long 0x1c 17. " DISABLE_SATA_SC ,Output driver slew-rate control for SATA mode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x1c 14. " TXDCC_PWRDN ,TX clock will duty-cycle correction" "Disabled,Enabled"
|
|
bitfld.long 0x1c 4.--8. " TMTRIM ,Termination resistor calibration code for grounded resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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textline " "
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bitfld.long 0x1c 3. " TRIMBYPASS ,Digital control of termination resistor" "Not bypassed,Bypassed"
|
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bitfld.long 0x1c 1.--2. " RDTCT_VTMODE ,Receive detect test mode to program threshold" ".285V,0.3V,.27V,0.35V"
|
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line.long 0x20 "CFGTX3,PHY Configuration Transmit 3 Register"
|
|
bitfld.long 0x20 24.--27. " RXLDO_CTRL[15:13] ,LDO loop compensation control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x20 23. " RXLDO_CTRL[12] ,Force LDO UP signal high" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x20 22. " RXLDO_CTRL[11] ,Low dropout mode" "Disabled,Enabled"
|
|
bitfld.long 0x20 21. " RXLDO_CTRL[10] ,Vref magnitude selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x20 20. " RXLDO_CTRL[9] ,Iref magnitude selection" "Not selected,Selected"
|
|
bitfld.long 0x20 18.--19. " RXLDO_CTRL[8:7] ,Quiescent current programmability" "0,1,2,3"
|
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textline " "
|
|
bitfld.long 0x20 17. " RXLDO_CTRL[6] ,Overshoot control block" "Disabled,Enabled"
|
|
bitfld.long 0x20 12.--16. " RXLDO_CTRL[5:0] ,Trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
|
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bitfld.long 0x20 11. " RXLDO_HITRAN_UNUSED ,RX LDO transient improvement" "Low,High"
|
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bitfld.long 0x20 7.--10. " TXLDO_CTRL[9:6] ,LDO loop compensation control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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textline " "
|
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bitfld.long 0x20 6. " TXLDO_CTRL[5] ,Force LDO UP signal high" "Not forced,Forced"
|
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bitfld.long 0x20 5. " TXLDO_CTRL[4] ,Low dropout mode" "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x20 4. " TXLDO_CTRL[3] ,Vref magnitude selection" "Not selected,Selected"
|
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bitfld.long 0x20 3. " TXLDO_CTRL[2] ,Iref magnitude selection" "Not selected,Selected"
|
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textline " "
|
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bitfld.long 0x20 1.--2. " TXLDO_CTRL[1:0] ,Quiescent current programmability" "0,1,2,3"
|
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bitfld.long 0x20 0. " TXLDO_DISABLE_OVERSHOOT ,TX LDO disable overshoot control" "No,Yes"
|
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line.long 0x24 "CFGTX4,PHY Configuration Transmit 4 Register"
|
|
bitfld.long 0x24 4. " TM_BIASCTR ,TM_BIASCTR used in DCC" "Disabled,Enabled"
|
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bitfld.long 0x24 1.--3. " TRIM_MODE ,TRIM_MODE[2:0]" "0,1,2,3,4,5,6,7"
|
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textline " "
|
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bitfld.long 0x24 0. " HYST_DISABLE ,HYST_DISABLE_Z and CALOUT_TX" "No,Yes"
|
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line.long 0x28 "STSRX_PHY,Transmit Bus Controller-to-PHY Status Register"
|
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bitfld.long 0x28 9. " TX_CALOUT_D ,CalOut after the digital filter" "Low,High"
|
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bitfld.long 0x28 8. " TX_CALOUT_A ,CalOut coming from analog" "Low,High"
|
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textline " "
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bitfld.long 0x28 3.--7. " TX_RTRIM ,Trim bits for TX resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x28 1. " RDTCTIP ,Receiver detect in progress" "Not in progress,In progress"
|
|
textline " "
|
|
bitfld.long 0x28 0. " TESTFAIL ,Test failure" "Not failed,Failed"
|
|
endif
|
|
width 0xb
|
|
sif (cpuis("AM387*"))
|
|
base ad:0x48140000
|
|
width 16.
|
|
tree "SATA PLL Registers"
|
|
group.long 0x720++0x13
|
|
line.long 0x00 "SATA_PLLCFG0,SATA PLL Configuration 0 Register"
|
|
bitfld.long 0x00 31. " SEL_IN_FREQ ,Select input frequency" "100MHz,20MHz"
|
|
bitfld.long 0x00 30. " DIGCLRZ ,Used to reset flops and state machines" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AMUXSEL ,AMUX select" "KVCO,VRTRIM"
|
|
bitfld.long 0x00 26. " TESTCLKMUXSEL ,Selects test clock mux" "REF Clock,Divided clock"
|
|
textline " "
|
|
bitfld.long 0x00 20.--25. " APLL_MISC_CTRL ,Used by APLL DIG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19. " DIS_REFCLK ,DIS_REFCLK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EN_3P ,EN_3P" "No effect,Generate"
|
|
bitfld.long 0x00 17. " PFD_CLR ,Reset for phase-frequency detector" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CLK_FLIP ,Output clock phase flip" "Not flipped,Flipped"
|
|
bitfld.long 0x00 15. " EN_RTRIM ,Enable resistor calibration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EN_MEAS ,Enable measurement circuit inside APLL ANA" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " EN_LATCH ,Enable output latch in differential ring" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CP_CTRL ,Charge pump control bit +- 50 %" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. " RESVALUE ,Sets loop filter resistor value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 5. " C1_2X ,Increase filter capacitance by 2x in low reference (20 MHz) clock" "Low,High"
|
|
bitfld.long 0x00 4. " ENDIGLDO ,Enable DIG LDO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SELSC ,SELSC" "Low,High"
|
|
bitfld.long 0x00 2. " ENBGSC_REF ,ENBGSC_REF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENPLLDO ,Enable PLL LDO" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENPLL ,Enable PLL" "Disabled,Enabled"
|
|
line.long 0x04 "SATA_PLLCFG1,SATA PLL Configuration 1 Register"
|
|
bitfld.long 0x04 31. " ENSATAMODE ,Mode select" "PCIe (2.5 GHz),SATA (1.5 GHz)"
|
|
bitfld.long 0x04 30. " PLLREFSEL ,Chose reference clock value" "100 MHz,20 MHz"
|
|
textline " "
|
|
bitfld.long 0x04 26.--29. " NP1_DIV_INT ,Integer value of N+1 divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 18.--25. 1. " MDIVINT ,8-bit value, which is used as integer portion of feedback divider"
|
|
textline " "
|
|
hexmask.long.word 0x04 6.--17. 1. " MDIVFRAC ,12-bit value, which is used as fractional portion of feedback divider"
|
|
bitfld.long 0x04 5. " EN_CLKAUX ,Enable for spectrum clock (testclk)" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 4. " EN_CLK125M ,Enable for 125MHz clock" "Disable,Enable"
|
|
bitfld.long 0x04 3. " EN_CLK100M ,Enable for 100MHz clock" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EN_CLK50M ,Enable for 50MHz clock" "Disable,Enable"
|
|
bitfld.long 0x04 1. " ENSSC ,Enable spread spectrum support" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MDIVPULSE ,Update M div when pulse is high" "Disable,Enable"
|
|
line.long 0x08 "SATA_PLLCFG2,SATA PLL Configuration 2 Register"
|
|
bitfld.long 0x08 31. " SSCDNSPREAD ,SSC downspread" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 24.--30. 1. " SSCMANT ,Mantesa portion of the modified frequency in SSC operation"
|
|
textline " "
|
|
bitfld.long 0x08 21.--23. " SSCEXPO ,Exponent portion of the modified frequency in SSC operation" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x08 0.--20. 1. " STS_TX ,SSC frequency spread"
|
|
line.long 0x0c "SATA_PLLCFG3,SATA PLL Configuration 3 Register"
|
|
bitfld.long 0x0c 26. " DIGLDO_PULLDOWNZ ,DIGLDO_PULLDOWNZ" "Low,High"
|
|
bitfld.long 0x0c 25. " DIGLDO_ENFUNC5 ,DIGLDO_ENFUNC5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 24. " DIGLDO_ENFUNC4 ,DIGLDO_ENFUNC4" "Low,High"
|
|
bitfld.long 0x0c 23. " DIGLDO_ENFUNC3 ,DIGLDO_ENFUNC3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " DIGLDO_ENFUNC2 ,DIGLDO_ENFUNC2" "Low,High"
|
|
bitfld.long 0x0c 21. " DIGLDO_ENFUNC1 ,DIGLDO_ENFUNC1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--20. " DIGLDO_VSET ,DIGLDO_VSET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x0c 0.--12. 1. " PLLLDO_CTRL ,PLLLDO_CTRL"
|
|
line.long 0x10 "SATA_PLLCFG4,SATA PLL Configuration 4 Register"
|
|
bitfld.long 0x10 25. " AUX_CLK_SEL ,Auxiliary clock select" "Divided,Ref clk"
|
|
bitfld.long 0x10 20.--24. " AUX_DIV ,Auxiliary divider control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x10 18.--19. " RTRIM_RANGE ,Range for rtrim" "0.9-0.8,1.0-0.9,1.1-1.0,1.1-0.9"
|
|
bitfld.long 0x10 17. " RTRIM_EXT_EN ,Select loop starting point" "Mid-code,External input"
|
|
textline " "
|
|
bitfld.long 0x10 16. " RTRIM_SPEED ,Selection on wait for # REFCLKs after previous update" "128,256"
|
|
bitfld.long 0x10 14.--15. " RTRIM_MODE ,Loop mode" "Disabled,Reserved,Freeze,Continuous"
|
|
textline " "
|
|
bitfld.long 0x10 10.--13. " RTRIM_EXT_VAL ,2's compliment vtune control loop value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--9. " VTUNE_RANGE ,Range for Vtune" "0.9-0.8,1.0-0.9,1.1-1.0,1.1-0.9"
|
|
textline " "
|
|
bitfld.long 0x10 7. " VTUNE_EXT_EN ,Select loop starting point" "Mid-code,External input"
|
|
bitfld.long 0x10 6. " VTUNE_SPEED ,Selection on wait for # REFCLKs after previous update" "128,256"
|
|
textline " "
|
|
bitfld.long 0x10 4.--5. " VTUNE_MODE ,Loop mode" "Disabled,Reserved,Freeze,Continuous"
|
|
bitfld.long 0x10 0.--3. " VTUNE_EXT_VAL ,2's compliment vtune control loop value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x734++0x0b
|
|
line.long 0x00 "SATA_PLLSTATUS,SATA PLL Status"
|
|
bitfld.long 0x00 8.--11. " RTRIMSTS ,Value of the rtrim loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " VTUNESTS ,Value of the vtune control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " APLLDIGSTS1 ,SSC engaged" "Not engaged,Engaged"
|
|
bitfld.long 0x00 0. " APLLDIGSTS0 ,APLL lock" "Not locked,Locked"
|
|
line.long 0x04 "SATA_RXSTATUS,SATA Receive Status"
|
|
bitfld.long 0x04 0. " TESTFAIL ,Test failure" "Not failed,Failed"
|
|
line.long 0x08 "SATA_TXSTATUS,SATA Transmit Status"
|
|
bitfld.long 0x08 0. " TESTFAIL ,Test failure" "Not failed,Failed"
|
|
group.long 0x740++0x03
|
|
line.long 0x00 "SATA_TESTCFG,SATA TEST Configuration"
|
|
bitfld.long 0x00 0.--2. " RX_TESTPATT ,Enables and selects test patterns" "Reserved,An alternating 0/1 pattern with a period of 2 UI,Uses a 7-bit LFSR with feedback polynomial x7+x6+1,Uses a 23-bit LFSR with feedback polynomial x23+x18+1,Uses a 31-bit LFSR with feedback polynomial x31+x28+1,?..."
|
|
tree.end
|
|
tree "SATA Subsystem Registers"
|
|
base ad:0x48180000
|
|
width 29.
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "CM_DEFAULT_L3_MED_CLKSTCTRL,Clock Domain Power Control Register"
|
|
bitfld.long 0x00 8. " CLKACTIVITY_L3_MED_GCLK ,state of the L3_SLOW_GCLK clock in the domain" "Gated,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3_MED clock domain in DEFAULT power domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "CM_ALWON2_SATA_CLKCTRL,Clock Domain SATA Control Register"
|
|
bitfld.long 0x00 18. " STBYST ,Module standby status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Fully functional,Performing transition,Idle mode,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODULEMODE ,Controls the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..."
|
|
tree.end
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.open "McSPI (Multichannel Serial Port Interface)"
|
|
tree "SPI 0"
|
|
base ad:0x48030000
|
|
width 20.
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "MCSPI_HL_REV,MCSPI IP Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Identifies scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Indicates a software compatible module family"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision (X)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision (Y)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "MCSPI_HL_HWINFO,MCSPI IP hardware information register"
|
|
bitfld.long 0x04 1.--5. " FFNBYTE ,FIFO number of byte generic parameter" "Reserved,16 bytes,32 bytes,Reserved,64 bytes,Reserved,Reserved,Reserved,128 bytes,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,256 bytes,?..."
|
|
bitfld.long 0x04 0. " USEFIFO ,Use of a FIFO enable" "Disabled,Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCSPI_HL_SYSCONFIG,MCSPI IP system configuration register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle/wakeup-capable"
|
|
bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal" "Sensitive,Not sensitive"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "MCSPI_REVISION,MCSPI revision register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Identifies revision of peripheral"
|
|
endif
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "MCSPI_SYSCONFIG,MCSPI System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Software reset" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "MCSPI_SYSSTATUS,MCSPI System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x118++0x7
|
|
line.long 0x00 "MCSPI_IRQSTATUS,MCSPI Interrupt Status Register"
|
|
eventfld.long 0x00 17. " EOW ,End of word count event" "False,Pending"
|
|
eventfld.long 0x00 14. " RX3_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RX2_FULL ,Receiver register full" "False,Pending"
|
|
eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty" "False,Pending"
|
|
eventfld.long 0x00 6. " RX1_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow" "False,Pending"
|
|
eventfld.long 0x00 2. " RX0_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty" "False,Pending"
|
|
line.long 0x04 "MCSPI_IRQENABLE,MCSPI Interrupt Enable/Disable Register"
|
|
bitfld.long 0x04 17. " EOWKE ,End of word count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RX3_FULL_ENABLE ,Receiver register full Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " TX3_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " RX2_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TX2_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RX1_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TX1_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX0_OVERFLOW_ENABLE ,Receiver register overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RX0_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TX0_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "MCSPI_WAKEUPENABLE,MCSPI Wakeup Enable Register"
|
|
bitfld.long 0x00 0. " WKEN ,Wakeup functionality in slave mode" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MCSPI_SYST,MCSPI System Test Register"
|
|
bitfld.long 0x00 11. " SSB ,Set status" "No action,Set"
|
|
bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0] lines and SPICLK line" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input"
|
|
bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPICLK ,SPICLK line" "Low,High"
|
|
bitfld.long 0x00 5. " SPIDAT_1 ,SPIDAT[1] line" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIDAT_0 ,SPIDAT[0] line" "Low,High"
|
|
bitfld.long 0x00 3. " SPIEN_3 ,SPIEN[3] line" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SPIEN_2 ,SPIEN[2] line" "Low,High"
|
|
bitfld.long 0x00 1. " SPIEN_1 ,SPIEN[1] line" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN_0 ,SPIEN[0] line" "Low,High"
|
|
if (((d.l((ad:0x48030000+0x128)))&0x4)==0x4)
|
|
;slave
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI_TX(i)/MCSPI_RX(i),MCSPI_DAFTX/MCSPI_DAFRX"
|
|
bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " INITDLY ,>Initial SPI delay for first transfer (SPI bus clocks)" "No delay,4,8,16,32,?..."
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
bitfld.long 0x00 1. " PIN34 ,Pin mode selection (SPIEN)" "Chip select,Unused"
|
|
else
|
|
;master
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI_TX(i)/MCSPI_RX(i),MCSPI_DAFTX/MCSPI_DAFRX"
|
|
bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " INITDLY ,Initial SPI delay for first transfer" "No delay,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
bitfld.long 0x00 1. " PIN34 ,Pin mode selection (SPIEN)" "Chip select,Unused"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel" "Multi,Single"
|
|
endif
|
|
group.long 0x12C++0x3 "Channel 0"
|
|
line.long 0x00 "MCSPI_CH0CONF,MCSPI Channel 0 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 0" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x12C+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH0STAT,MCSPI Channel 0 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 0 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full"
|
|
group.long (0x12C+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH0CTRL,MCSPI Channel 0 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX0,MCSPI Channel 0 Transmit Register"
|
|
hgroup.long (0x12C+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX0,MCSPI Channel 0 Receive Register"
|
|
in
|
|
group.long 0x140++0x3 "Channel 1"
|
|
line.long 0x00 "MCSPI_CH1CONF,MCSPI Channel 1 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x140+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH1STAT,MCSPI Channel 1 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 1 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 1 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 1 receiver register status" "Empty,Full"
|
|
group.long (0x140+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH1CTRL,MCSPI Channel 1 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 1 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX1,MCSPI Channel 1 Transmit Register"
|
|
hgroup.long (0x140+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX1,MCSPI Channel 1 Receive Register"
|
|
in
|
|
group.long 0x154++0x3 "Channel 2"
|
|
line.long 0x00 "MCSPI_CH2CONF,MCSPI Channel 2 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 2" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x154+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH2STAT,MCSPI Channel 2 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 2 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 2 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 2 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 2 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 2 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 2 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 2 receiver register status" "Empty,Full"
|
|
group.long (0x154+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH2CTRL,MCSPI Channel 2 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 2 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX2,MCSPI Channel 2 Transmit Register"
|
|
hgroup.long (0x154+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX2,MCSPI Channel 2 Receive Register"
|
|
in
|
|
group.long 0x168++0x3 "Channel 3"
|
|
line.long 0x00 "MCSPI_CH3CONF,MCSPI Channel 3 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x168+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH3STAT,MCSPI Channel 3 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 3 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 3 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 3 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 3 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 3 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 3 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 3 receiver register status" "Empty,Full"
|
|
group.long (0x168+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH3CTRL,MCSPI Channel 3 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 3 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX3,MCSPI Channel 3 Transmit Register"
|
|
hgroup.long (0x168+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX3,MCSPI Channel 3 Receive Register"
|
|
in
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.long 0x17C++0x3 ""
|
|
line.long 0x00 "MCSPI_XFERLEVEL,McSPI Transfer Levels Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty"
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "MCSPI_DAFTX,DMA Address Aligned FIFO Transmitter Register"
|
|
hgroup.long 0x1A0++0x3
|
|
hide.long 0x00 "MCSPI_DAFRX,DMA Address Aligned FIFO Receiver Register"
|
|
in
|
|
else
|
|
group.long 0x7C++0x3 ""
|
|
line.long 0x00 "MCSPI_XFERLEVEL,McSPI Transfer Levels Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty"
|
|
endif
|
|
width 11.
|
|
tree.end
|
|
tree "SPI 1"
|
|
base ad:0x481A0000
|
|
width 20.
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "MCSPI_HL_REV,MCSPI IP Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Identifies scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Indicates a software compatible module family"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision (X)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision (Y)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "MCSPI_HL_HWINFO,MCSPI IP hardware information register"
|
|
bitfld.long 0x04 1.--5. " FFNBYTE ,FIFO number of byte generic parameter" "Reserved,16 bytes,32 bytes,Reserved,64 bytes,Reserved,Reserved,Reserved,128 bytes,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,256 bytes,?..."
|
|
bitfld.long 0x04 0. " USEFIFO ,Use of a FIFO enable" "Disabled,Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCSPI_HL_SYSCONFIG,MCSPI IP system configuration register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle/wakeup-capable"
|
|
bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal" "Sensitive,Not sensitive"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "MCSPI_REVISION,MCSPI revision register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Identifies revision of peripheral"
|
|
endif
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "MCSPI_SYSCONFIG,MCSPI System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Software reset" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "MCSPI_SYSSTATUS,MCSPI System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x118++0x7
|
|
line.long 0x00 "MCSPI_IRQSTATUS,MCSPI Interrupt Status Register"
|
|
eventfld.long 0x00 17. " EOW ,End of word count event" "False,Pending"
|
|
eventfld.long 0x00 14. " RX3_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RX2_FULL ,Receiver register full" "False,Pending"
|
|
eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty" "False,Pending"
|
|
eventfld.long 0x00 6. " RX1_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow" "False,Pending"
|
|
eventfld.long 0x00 2. " RX0_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty" "False,Pending"
|
|
line.long 0x04 "MCSPI_IRQENABLE,MCSPI Interrupt Enable/Disable Register"
|
|
bitfld.long 0x04 17. " EOWKE ,End of word count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RX3_FULL_ENABLE ,Receiver register full Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " TX3_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " RX2_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TX2_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RX1_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TX1_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX0_OVERFLOW_ENABLE ,Receiver register overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RX0_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TX0_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "MCSPI_WAKEUPENABLE,MCSPI Wakeup Enable Register"
|
|
bitfld.long 0x00 0. " WKEN ,Wakeup functionality in slave mode" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MCSPI_SYST,MCSPI System Test Register"
|
|
bitfld.long 0x00 11. " SSB ,Set status" "No action,Set"
|
|
bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0] lines and SPICLK line" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input"
|
|
bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPICLK ,SPICLK line" "Low,High"
|
|
bitfld.long 0x00 5. " SPIDAT_1 ,SPIDAT[1] line" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIDAT_0 ,SPIDAT[0] line" "Low,High"
|
|
bitfld.long 0x00 3. " SPIEN_3 ,SPIEN[3] line" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SPIEN_2 ,SPIEN[2] line" "Low,High"
|
|
bitfld.long 0x00 1. " SPIEN_1 ,SPIEN[1] line" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN_0 ,SPIEN[0] line" "Low,High"
|
|
if (((d.l((ad:0x481A0000+0x128)))&0x4)==0x4)
|
|
;slave
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI_TX(i)/MCSPI_RX(i),MCSPI_DAFTX/MCSPI_DAFRX"
|
|
bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " INITDLY ,>Initial SPI delay for first transfer (SPI bus clocks)" "No delay,4,8,16,32,?..."
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
bitfld.long 0x00 1. " PIN34 ,Pin mode selection (SPIEN)" "Chip select,Unused"
|
|
else
|
|
;master
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI_TX(i)/MCSPI_RX(i),MCSPI_DAFTX/MCSPI_DAFRX"
|
|
bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " INITDLY ,Initial SPI delay for first transfer" "No delay,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
bitfld.long 0x00 1. " PIN34 ,Pin mode selection (SPIEN)" "Chip select,Unused"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel" "Multi,Single"
|
|
endif
|
|
group.long 0x12C++0x3 "Channel 0"
|
|
line.long 0x00 "MCSPI_CH0CONF,MCSPI Channel 0 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 0" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x12C+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH0STAT,MCSPI Channel 0 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 0 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full"
|
|
group.long (0x12C+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH0CTRL,MCSPI Channel 0 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX0,MCSPI Channel 0 Transmit Register"
|
|
hgroup.long (0x12C+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX0,MCSPI Channel 0 Receive Register"
|
|
in
|
|
group.long 0x140++0x3 "Channel 1"
|
|
line.long 0x00 "MCSPI_CH1CONF,MCSPI Channel 1 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x140+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH1STAT,MCSPI Channel 1 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 1 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 1 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 1 receiver register status" "Empty,Full"
|
|
group.long (0x140+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH1CTRL,MCSPI Channel 1 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 1 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX1,MCSPI Channel 1 Transmit Register"
|
|
hgroup.long (0x140+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX1,MCSPI Channel 1 Receive Register"
|
|
in
|
|
group.long 0x154++0x3 "Channel 2"
|
|
line.long 0x00 "MCSPI_CH2CONF,MCSPI Channel 2 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 2" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x154+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH2STAT,MCSPI Channel 2 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 2 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 2 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 2 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 2 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 2 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 2 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 2 receiver register status" "Empty,Full"
|
|
group.long (0x154+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH2CTRL,MCSPI Channel 2 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 2 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX2,MCSPI Channel 2 Transmit Register"
|
|
hgroup.long (0x154+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX2,MCSPI Channel 2 Receive Register"
|
|
in
|
|
group.long 0x168++0x3 "Channel 3"
|
|
line.long 0x00 "MCSPI_CH3CONF,MCSPI Channel 3 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x168+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH3STAT,MCSPI Channel 3 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 3 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 3 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 3 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 3 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 3 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 3 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 3 receiver register status" "Empty,Full"
|
|
group.long (0x168+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH3CTRL,MCSPI Channel 3 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 3 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX3,MCSPI Channel 3 Transmit Register"
|
|
hgroup.long (0x168+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX3,MCSPI Channel 3 Receive Register"
|
|
in
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.long 0x17C++0x3 ""
|
|
line.long 0x00 "MCSPI_XFERLEVEL,McSPI Transfer Levels Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty"
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "MCSPI_DAFTX,DMA Address Aligned FIFO Transmitter Register"
|
|
hgroup.long 0x1A0++0x3
|
|
hide.long 0x00 "MCSPI_DAFRX,DMA Address Aligned FIFO Receiver Register"
|
|
in
|
|
else
|
|
group.long 0x7C++0x3 ""
|
|
line.long 0x00 "MCSPI_XFERLEVEL,McSPI Transfer Levels Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty"
|
|
endif
|
|
width 11.
|
|
tree.end
|
|
tree "SPI 2"
|
|
base ad:0x481A2000
|
|
width 20.
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "MCSPI_HL_REV,MCSPI IP Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Identifies scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Indicates a software compatible module family"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision (X)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision (Y)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "MCSPI_HL_HWINFO,MCSPI IP hardware information register"
|
|
bitfld.long 0x04 1.--5. " FFNBYTE ,FIFO number of byte generic parameter" "Reserved,16 bytes,32 bytes,Reserved,64 bytes,Reserved,Reserved,Reserved,128 bytes,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,256 bytes,?..."
|
|
bitfld.long 0x04 0. " USEFIFO ,Use of a FIFO enable" "Disabled,Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCSPI_HL_SYSCONFIG,MCSPI IP system configuration register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle/wakeup-capable"
|
|
bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal" "Sensitive,Not sensitive"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "MCSPI_REVISION,MCSPI revision register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Identifies revision of peripheral"
|
|
endif
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "MCSPI_SYSCONFIG,MCSPI System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Software reset" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "MCSPI_SYSSTATUS,MCSPI System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x118++0x7
|
|
line.long 0x00 "MCSPI_IRQSTATUS,MCSPI Interrupt Status Register"
|
|
eventfld.long 0x00 17. " EOW ,End of word count event" "False,Pending"
|
|
eventfld.long 0x00 14. " RX3_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RX2_FULL ,Receiver register full" "False,Pending"
|
|
eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty" "False,Pending"
|
|
eventfld.long 0x00 6. " RX1_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow" "False,Pending"
|
|
eventfld.long 0x00 2. " RX0_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty" "False,Pending"
|
|
line.long 0x04 "MCSPI_IRQENABLE,MCSPI Interrupt Enable/Disable Register"
|
|
bitfld.long 0x04 17. " EOWKE ,End of word count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RX3_FULL_ENABLE ,Receiver register full Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " TX3_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " RX2_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TX2_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RX1_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TX1_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX0_OVERFLOW_ENABLE ,Receiver register overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RX0_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TX0_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "MCSPI_WAKEUPENABLE,MCSPI Wakeup Enable Register"
|
|
bitfld.long 0x00 0. " WKEN ,Wakeup functionality in slave mode" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MCSPI_SYST,MCSPI System Test Register"
|
|
bitfld.long 0x00 11. " SSB ,Set status" "No action,Set"
|
|
bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0] lines and SPICLK line" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input"
|
|
bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPICLK ,SPICLK line" "Low,High"
|
|
bitfld.long 0x00 5. " SPIDAT_1 ,SPIDAT[1] line" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIDAT_0 ,SPIDAT[0] line" "Low,High"
|
|
bitfld.long 0x00 3. " SPIEN_3 ,SPIEN[3] line" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SPIEN_2 ,SPIEN[2] line" "Low,High"
|
|
bitfld.long 0x00 1. " SPIEN_1 ,SPIEN[1] line" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN_0 ,SPIEN[0] line" "Low,High"
|
|
if (((d.l((ad:0x481A2000+0x128)))&0x4)==0x4)
|
|
;slave
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI_TX(i)/MCSPI_RX(i),MCSPI_DAFTX/MCSPI_DAFRX"
|
|
bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " INITDLY ,>Initial SPI delay for first transfer (SPI bus clocks)" "No delay,4,8,16,32,?..."
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
bitfld.long 0x00 1. " PIN34 ,Pin mode selection (SPIEN)" "Chip select,Unused"
|
|
else
|
|
;master
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI_TX(i)/MCSPI_RX(i),MCSPI_DAFTX/MCSPI_DAFRX"
|
|
bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " INITDLY ,Initial SPI delay for first transfer" "No delay,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
bitfld.long 0x00 1. " PIN34 ,Pin mode selection (SPIEN)" "Chip select,Unused"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel" "Multi,Single"
|
|
endif
|
|
group.long 0x12C++0x3 "Channel 0"
|
|
line.long 0x00 "MCSPI_CH0CONF,MCSPI Channel 0 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 0" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x12C+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH0STAT,MCSPI Channel 0 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 0 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full"
|
|
group.long (0x12C+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH0CTRL,MCSPI Channel 0 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX0,MCSPI Channel 0 Transmit Register"
|
|
hgroup.long (0x12C+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX0,MCSPI Channel 0 Receive Register"
|
|
in
|
|
group.long 0x140++0x3 "Channel 1"
|
|
line.long 0x00 "MCSPI_CH1CONF,MCSPI Channel 1 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x140+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH1STAT,MCSPI Channel 1 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 1 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 1 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 1 receiver register status" "Empty,Full"
|
|
group.long (0x140+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH1CTRL,MCSPI Channel 1 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 1 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX1,MCSPI Channel 1 Transmit Register"
|
|
hgroup.long (0x140+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX1,MCSPI Channel 1 Receive Register"
|
|
in
|
|
group.long 0x154++0x3 "Channel 2"
|
|
line.long 0x00 "MCSPI_CH2CONF,MCSPI Channel 2 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 2" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x154+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH2STAT,MCSPI Channel 2 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 2 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 2 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 2 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 2 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 2 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 2 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 2 receiver register status" "Empty,Full"
|
|
group.long (0x154+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH2CTRL,MCSPI Channel 2 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 2 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX2,MCSPI Channel 2 Transmit Register"
|
|
hgroup.long (0x154+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX2,MCSPI Channel 2 Receive Register"
|
|
in
|
|
group.long 0x168++0x3 "Channel 3"
|
|
line.long 0x00 "MCSPI_CH3CONF,MCSPI Channel 3 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x168+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH3STAT,MCSPI Channel 3 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 3 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 3 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 3 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 3 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 3 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 3 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 3 receiver register status" "Empty,Full"
|
|
group.long (0x168+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH3CTRL,MCSPI Channel 3 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 3 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX3,MCSPI Channel 3 Transmit Register"
|
|
hgroup.long (0x168+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX3,MCSPI Channel 3 Receive Register"
|
|
in
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.long 0x17C++0x3 ""
|
|
line.long 0x00 "MCSPI_XFERLEVEL,McSPI Transfer Levels Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty"
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "MCSPI_DAFTX,DMA Address Aligned FIFO Transmitter Register"
|
|
hgroup.long 0x1A0++0x3
|
|
hide.long 0x00 "MCSPI_DAFRX,DMA Address Aligned FIFO Receiver Register"
|
|
in
|
|
else
|
|
group.long 0x7C++0x3 ""
|
|
line.long 0x00 "MCSPI_XFERLEVEL,McSPI Transfer Levels Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty"
|
|
endif
|
|
width 11.
|
|
tree.end
|
|
tree "SPI 3"
|
|
base ad:0x481A4000
|
|
width 20.
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "MCSPI_HL_REV,MCSPI IP Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Identifies scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Indicates a software compatible module family"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision (X)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision (Y)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "MCSPI_HL_HWINFO,MCSPI IP hardware information register"
|
|
bitfld.long 0x04 1.--5. " FFNBYTE ,FIFO number of byte generic parameter" "Reserved,16 bytes,32 bytes,Reserved,64 bytes,Reserved,Reserved,Reserved,128 bytes,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,256 bytes,?..."
|
|
bitfld.long 0x04 0. " USEFIFO ,Use of a FIFO enable" "Disabled,Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCSPI_HL_SYSCONFIG,MCSPI IP system configuration register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle/wakeup-capable"
|
|
bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal" "Sensitive,Not sensitive"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "MCSPI_REVISION,MCSPI revision register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Identifies revision of peripheral"
|
|
endif
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "MCSPI_SYSCONFIG,MCSPI System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
textline " "
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Software reset" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "MCSPI_SYSSTATUS,MCSPI System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x118++0x7
|
|
line.long 0x00 "MCSPI_IRQSTATUS,MCSPI Interrupt Status Register"
|
|
eventfld.long 0x00 17. " EOW ,End of word count event" "False,Pending"
|
|
eventfld.long 0x00 14. " RX3_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RX2_FULL ,Receiver register full" "False,Pending"
|
|
eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty" "False,Pending"
|
|
eventfld.long 0x00 6. " RX1_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow" "False,Pending"
|
|
eventfld.long 0x00 2. " RX0_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty" "False,Pending"
|
|
line.long 0x04 "MCSPI_IRQENABLE,MCSPI Interrupt Enable/Disable Register"
|
|
bitfld.long 0x04 17. " EOWKE ,End of word count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RX3_FULL_ENABLE ,Receiver register full Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " TX3_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " RX2_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TX2_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RX1_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TX1_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX0_OVERFLOW_ENABLE ,Receiver register overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RX0_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TX0_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "MCSPI_WAKEUPENABLE,MCSPI Wakeup Enable Register"
|
|
bitfld.long 0x00 0. " WKEN ,Wakeup functionality in slave mode" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MCSPI_SYST,MCSPI System Test Register"
|
|
bitfld.long 0x00 11. " SSB ,Set status" "No action,Set"
|
|
bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0] lines and SPICLK line" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input"
|
|
bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPICLK ,SPICLK line" "Low,High"
|
|
bitfld.long 0x00 5. " SPIDAT_1 ,SPIDAT[1] line" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIDAT_0 ,SPIDAT[0] line" "Low,High"
|
|
bitfld.long 0x00 3. " SPIEN_3 ,SPIEN[3] line" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SPIEN_2 ,SPIEN[2] line" "Low,High"
|
|
bitfld.long 0x00 1. " SPIEN_1 ,SPIEN[1] line" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN_0 ,SPIEN[0] line" "Low,High"
|
|
if (((d.l((ad:0x481A4000+0x128)))&0x4)==0x4)
|
|
;slave
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI_TX(i)/MCSPI_RX(i),MCSPI_DAFTX/MCSPI_DAFRX"
|
|
bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " INITDLY ,>Initial SPI delay for first transfer (SPI bus clocks)" "No delay,4,8,16,32,?..."
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
bitfld.long 0x00 1. " PIN34 ,Pin mode selection (SPIEN)" "Chip select,Unused"
|
|
else
|
|
;master
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI_TX(i)/MCSPI_RX(i),MCSPI_DAFTX/MCSPI_DAFRX"
|
|
bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " INITDLY ,Initial SPI delay for first transfer" "No delay,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
bitfld.long 0x00 1. " PIN34 ,Pin mode selection (SPIEN)" "Chip select,Unused"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel" "Multi,Single"
|
|
endif
|
|
group.long 0x12C++0x3 "Channel 0"
|
|
line.long 0x00 "MCSPI_CH0CONF,MCSPI Channel 0 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 0" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x12C+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH0STAT,MCSPI Channel 0 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 0 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full"
|
|
group.long (0x12C+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH0CTRL,MCSPI Channel 0 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX0,MCSPI Channel 0 Transmit Register"
|
|
hgroup.long (0x12C+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX0,MCSPI Channel 0 Receive Register"
|
|
in
|
|
group.long 0x140++0x3 "Channel 1"
|
|
line.long 0x00 "MCSPI_CH1CONF,MCSPI Channel 1 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x140+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH1STAT,MCSPI Channel 1 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 1 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 1 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 1 receiver register status" "Empty,Full"
|
|
group.long (0x140+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH1CTRL,MCSPI Channel 1 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 1 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX1,MCSPI Channel 1 Transmit Register"
|
|
hgroup.long (0x140+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX1,MCSPI Channel 1 Receive Register"
|
|
in
|
|
group.long 0x154++0x3 "Channel 2"
|
|
line.long 0x00 "MCSPI_CH2CONF,MCSPI Channel 2 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 2" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x154+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH2STAT,MCSPI Channel 2 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 2 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 2 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 2 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 2 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 2 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 2 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 2 receiver register status" "Empty,Full"
|
|
group.long (0x154+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH2CTRL,MCSPI Channel 2 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 2 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX2,MCSPI Channel 2 Transmit Register"
|
|
hgroup.long (0x154+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX2,MCSPI Channel 2 Receive Register"
|
|
in
|
|
group.long 0x168++0x3 "Channel 3"
|
|
line.long 0x00 "MCSPI_CH3CONF,MCSPI Channel 3 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
|
|
rgroup.long (0x168+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH3STAT,MCSPI Channel 3 Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 3 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 3 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 3 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 3 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 3 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 3 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 3 receiver register status" "Empty,Full"
|
|
group.long (0x168+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH3CTRL,MCSPI Channel 3 Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel 3 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX3,MCSPI Channel 3 Transmit Register"
|
|
hgroup.long (0x168+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX3,MCSPI Channel 3 Receive Register"
|
|
in
|
|
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.long 0x17C++0x3 ""
|
|
line.long 0x00 "MCSPI_XFERLEVEL,McSPI Transfer Levels Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty"
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "MCSPI_DAFTX,DMA Address Aligned FIFO Transmitter Register"
|
|
hgroup.long 0x1A0++0x3
|
|
hide.long 0x00 "MCSPI_DAFRX,DMA Address Aligned FIFO Receiver Register"
|
|
in
|
|
else
|
|
group.long 0x7C++0x3 ""
|
|
line.long 0x00 "MCSPI_XFERLEVEL,McSPI Transfer Levels Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty"
|
|
endif
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree.open "Timers"
|
|
tree "Timer 1"
|
|
base ad:0x4802E000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIDR,Identification Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
|
|
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
|
|
else
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
|
|
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
|
|
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
|
|
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCLR,Timer Control Register"
|
|
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
|
|
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
|
|
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
|
|
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TCRR,Timer Counter Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TLDR,Timer Load Register"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TTGR,Timer Trigger Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TWPS,Timer Write Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TMAR,Timer Match Register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TCAR1,Timer Capture Register 1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCAR2,Timer Capture Register 2"
|
|
width 0xb
|
|
tree.end
|
|
tree "Timer 2"
|
|
base ad:0x48040000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIDR,Identification Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
|
|
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
|
|
else
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
|
|
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
|
|
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
|
|
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCLR,Timer Control Register"
|
|
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
|
|
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
|
|
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
|
|
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TCRR,Timer Counter Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TLDR,Timer Load Register"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TTGR,Timer Trigger Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TWPS,Timer Write Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TMAR,Timer Match Register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TCAR1,Timer Capture Register 1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCAR2,Timer Capture Register 2"
|
|
width 0xb
|
|
tree.end
|
|
tree "Timer 3"
|
|
base ad:0x48042000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIDR,Identification Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
|
|
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
|
|
else
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
|
|
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
|
|
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
|
|
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCLR,Timer Control Register"
|
|
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
|
|
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
|
|
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
|
|
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TCRR,Timer Counter Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TLDR,Timer Load Register"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TTGR,Timer Trigger Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TWPS,Timer Write Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TMAR,Timer Match Register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TCAR1,Timer Capture Register 1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCAR2,Timer Capture Register 2"
|
|
width 0xb
|
|
tree.end
|
|
tree "Timer 4"
|
|
base ad:0x48044000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIDR,Identification Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
|
|
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
|
|
else
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
|
|
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
|
|
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
|
|
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCLR,Timer Control Register"
|
|
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
|
|
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
|
|
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
|
|
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TCRR,Timer Counter Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TLDR,Timer Load Register"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TTGR,Timer Trigger Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TWPS,Timer Write Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TMAR,Timer Match Register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TCAR1,Timer Capture Register 1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCAR2,Timer Capture Register 2"
|
|
width 0xb
|
|
tree.end
|
|
tree "Timer 5"
|
|
base ad:0x48046000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIDR,Identification Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
|
|
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
|
|
else
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
|
|
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
|
|
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
|
|
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCLR,Timer Control Register"
|
|
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
|
|
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
|
|
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
|
|
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TCRR,Timer Counter Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TLDR,Timer Load Register"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TTGR,Timer Trigger Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TWPS,Timer Write Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TMAR,Timer Match Register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TCAR1,Timer Capture Register 1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCAR2,Timer Capture Register 2"
|
|
width 0xb
|
|
tree.end
|
|
tree "Timer 6"
|
|
base ad:0x48048000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIDR,Identification Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
|
|
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
|
|
else
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
|
|
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
|
|
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
|
|
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCLR,Timer Control Register"
|
|
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
|
|
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
|
|
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
|
|
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TCRR,Timer Counter Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TLDR,Timer Load Register"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TTGR,Timer Trigger Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TWPS,Timer Write Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TMAR,Timer Match Register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TCAR1,Timer Capture Register 1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCAR2,Timer Capture Register 2"
|
|
width 0xb
|
|
tree.end
|
|
tree "Timer 7"
|
|
base ad:0x4804A000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIDR,Identification Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
|
|
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
|
|
else
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
|
|
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
|
|
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
|
|
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCLR,Timer Control Register"
|
|
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
|
|
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
|
|
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
|
|
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TCRR,Timer Counter Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TLDR,Timer Load Register"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TTGR,Timer Trigger Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TWPS,Timer Write Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TMAR,Timer Match Register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TCAR1,Timer Capture Register 1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCAR2,Timer Capture Register 2"
|
|
width 0xb
|
|
tree.end
|
|
tree "Timer 8"
|
|
base ad:0x481C1000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIDR,Identification Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
|
|
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
|
|
else
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
|
|
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
|
|
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
|
|
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCLR,Timer Control Register"
|
|
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
|
|
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
|
|
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
|
|
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TCRR,Timer Counter Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TLDR,Timer Load Register"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TTGR,Timer Trigger Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TWPS,Timer Write Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TMAR,Timer Match Register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TCAR1,Timer Capture Register 1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCAR2,Timer Capture Register 2"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "WDOG (Watchdog Timer)"
|
|
base ad:0x481C7000
|
|
width 17.
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "WDT_WIDR,IP revision identifier"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "WDT_WDSC,OCP interface parameters"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset (Optional)" "Reset,No reset"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "WDT_WDST,Status information"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal module reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "WDT_WISR,Interrupt events pending"
|
|
eventfld.long 0x00 1. " DLY_IT_FLAG ,Pending delay interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "WDT_WIER,Interrupt events control"
|
|
bitfld.long 0x04 1. " DLY_IT_ENA ,Delay interrupt enable/disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " OVF_IT_ENA ,Overflow interrupt enable/disable" "Disabled,Enabled"
|
|
sif (cpuis("DRA62*"))
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "WDT_WWER,Wake-up events control"
|
|
bitfld.long 0x00 1. " DLY_WK_ENA ,Delay wake-up enable/disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OVF_WK_ENA ,Overflow wake-up enable/disable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "WDT_WCLR,Counter prescaler control"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable/disable configuration" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " PTV ,Prescaler value" "0,1,2,3,4,5,6,7"
|
|
group.long 0x28++0xB
|
|
line.long 0x00 "WDT_WCRR,Internal counter value"
|
|
line.long 0x04 "WDT_WLDR,Timer load value"
|
|
line.long 0x08 "WDT_WTGR,Watchdog counter reload"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "WDT_WWPS,Write posting bits"
|
|
bitfld.long 0x00 5. " W_PEND_WDLY ,Write pending for register WDLY" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR" "Not pending,Pending"
|
|
group.long 0x44++0x7
|
|
line.long 0x00 "WDT_WDLY,Event detection delay value"
|
|
line.long 0x04 "WDT_WSPR,Start-stop value"
|
|
group.long 0x54++0xF
|
|
line.long 0x00 "WDT_WIRQSTATRAW,IRQ unmasked status"
|
|
bitfld.long 0x00 1. " EVENT_DLY ,Settable raw status for delay event" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " EVENT_OVF ,Settable raw status for overflow event" "Not pending,Pending"
|
|
line.long 0x04 "WDT_WIRQSTAT,IRQ masked status"
|
|
eventfld.long 0x04 1. " EVENT_DLY ,Clearable enabled status for delay event" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " EVENT_OVF ,Clearable enabled status for overflow event" "Not pending,Pending"
|
|
line.long 0x08 "WDT_WIRQENSET,IRQ enable"
|
|
bitfld.long 0x08 1. " ENABLE_DLY ,Enable for delay event" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLE_OVF ,Enable for overflow event" "Disabled,Enabled"
|
|
line.long 0x0C "WDT_WIRQENCLR,IRQ enable clear"
|
|
eventfld.long 0x0C 1. " ENABLE_DLY ,Enable (Clear) for delay event" "Disabled,Enabled"
|
|
eventfld.long 0x0C 0. " ENABLE_OVF ,Enable (Clear) for overflow event" "Disabled,Enabled"
|
|
sif (cpuis("DRA62*"))
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "WDT_WIRQWAKEEN,Wake-up events control"
|
|
bitfld.long 0x00 1. " DLY_WK_ENA ,Delay wake-up enable/disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OVF_WK_ENA ,Overflow wake-up enable/disable" "Disabled,Enabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
sif (cpuis("DRA62*"))
|
|
tree.open "VCP (Viterbi-Decoder Coprocessor)"
|
|
tree "VCP Data Registers - EDMA Access"
|
|
base ad:0x47800000
|
|
width 0xa
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "VCPIC0,VCP2 Input Configuration Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " POLY3 ,Polynomial generator G3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " POLY2 ,Polynomial generator G2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " POLY1 ,Polynomial generator G1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " POLY0 ,Polynomial generator G0"
|
|
line.long 0x4 "VCPIC1,VCP2 Input Configuration Register 1"
|
|
bitfld.long 0x4 28. " YAMEN ,Yamamoto algorithm enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x4 16.--27. 1. " YAMT ,Yamamoto threshold value bits"
|
|
line.long 0x8 "VCPIC2,VCP2 Input Configuration Register 2"
|
|
hexmask.long.word 0x8 16.--31. 1. " R ,Reliability length"
|
|
hexmask.long.word 0x8 0.--15. 1. " F ,Frame length"
|
|
line.long 0xc "VCPIC3,VCP2 Input Configuration Register 3"
|
|
bitfld.long 0xc 28. " OUT_ORDER ,Order of VCP output for decoded data" "0->31,31->0"
|
|
bitfld.long 0xc 24. " ITBEN ,Traceback state index enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0xc 16.--23. 1. " ITBI ,Traceback state index"
|
|
textline " "
|
|
hexmask.long.word 0xc 0.--15. 1. " C ,Convergence distance"
|
|
line.long 0x10 "VCPIC4,VCP2 Input Configuration Register 4"
|
|
hexmask.long.word 0x10 16.--28. 1. " IMINS ,Minimum initial state metric value"
|
|
hexmask.long.word 0x10 0.--12. 1. " IMAXS ,Maximum initial state metric value"
|
|
line.long 0x14 "VCPIC5,VCP2 Input Configuration Register 5"
|
|
bitfld.long 0x14 31. " SDHD ,Output decision type select" "Hard,Soft"
|
|
bitfld.long 0x14 30. " OUTF ,Output parameters read flag" "Not generated,Generated"
|
|
bitfld.long 0x14 28.--29. " TB ,Traceback mode select" "Not allowed,Tailed,Convergent,Mixed"
|
|
textline " "
|
|
bitfld.long 0x14 20.--24. " SYMR ,Decision buffer length in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x14 16.--19. " SYMX ,Branch metrics buffer length in input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x14 0.--7. 1. " IMAXI ,Maximum initial state metric value"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x00 "VCPOUT0,VCP Output Register 0"
|
|
hexmask.long.word 0x00 16.--28. 1. " FMINS ,Minimum initial state metric value for the final trellis stage"
|
|
hexmask.long.word 0x00 0.--12. 1. " FMAXS ,Maximum state metric value for the final trellis stage"
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "VCPOUT1,VCP Output Register 1"
|
|
bitfld.long 0x00 16. " YAM ,Yamamoto bit result" "Poor quality,Good quality"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FMAXI ,State index for the state with the final maximum state metric"
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "VCPWBM,VCP Branch Metrics Write Register"
|
|
in
|
|
hgroup.long 0xC0++0x3
|
|
hide.long 0x00 "VCPRDECS,VCP Decisions Read Register"
|
|
in
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "BM,Branch Metrics"
|
|
button "BM" "d ad:(0x47800000+0x1000)--ad:(0x47800000+0x11FF) /long"
|
|
group.long 0x2000++0x03
|
|
line.long 0x00 "SM,State Metric"
|
|
button "SM" "d ad:(0x47800000+0x2000)--ad:(0x47800000+0x21BF) /long"
|
|
group.long 0x3000++0x03
|
|
line.long 0x00 "TBHD,Traceback Hard Decision"
|
|
button "TBHD" "d ad:(0x47800000+0x3000)--ad:(0x47800000+0x3FFF) /long"
|
|
group.long 0x6000++0x03
|
|
line.long 0x00 "TBSD,Traceback Soft Decision"
|
|
button "TBSD" "d ad:(0x47800000+0x6000)--ad:(0x47800000+0x9FFF) /long"
|
|
group.long 0x3000++0x03
|
|
line.long 0x00 "IO,Decoded Bits"
|
|
button "IO" "d ad:(0x47800000+0xF000)--ad:(0x47800000+0xF1FF) /long"
|
|
width 0xb
|
|
tree.end
|
|
tree "VCP Configuration Registers - Peripheral Bus Access"
|
|
base ad:0x4A1B3000
|
|
width 0xa
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "VCPEXE,VCP Execution Register"
|
|
bitfld.long 0x00 0.--3. " COMMAND ,VCP command select" "Reserved,Start,Pause,Restart/SW process,Restart,Stop,?..."
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "VCPEND,VCP Endian Mode Register"
|
|
bitfld.long 0x00 9. " SLPZVSS_EN ,Sleep mode for Slpzvss_en" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLPZVDD_EN ,Sleep mode for slpzvdd_en" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SD ,Soft-decisions memory format select" "32-bit,8-bit"
|
|
bitfld.long 0x00 0. " BM ,Branch metrics memory format select" "32-bit,8-bit"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "VCPSTAT0,VCP Status Register 0"
|
|
hexmask.long.tbyte 0x00 12.--28. 1. " NSYMPROC ,Number of symbols processed"
|
|
bitfld.long 0x00 6. " Emuhalt ,Emulation halt status" "No halt,Halt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OFFUL ,Output FIFO buffer full status" "Not full,Full"
|
|
bitfld.long 0x00 4. " IFEMP ,Input FIFO buffer empty status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WIC ,Waiting for input configuration" "Not waiting,Waiting"
|
|
bitfld.long 0x00 2. " ERR ,VCP error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUN ,VCP running status" "Not running,Running"
|
|
bitfld.long 0x00 0. " PAUS ,VCP pause status" "Not paused,Paused"
|
|
rgroup.long 0x144++0x3
|
|
line.long 0x0 "VCPSTAT1,VCP Status Register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. " NSYMOF ,Number of symbols in the output FIFO buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. " NSYMIF ,Number of symbols in the input FIFO buffer"
|
|
rgroup.long 0x150++0x3
|
|
line.long 0x00 "VCPERR,VCP Error Register"
|
|
bitfld.long 0x00 6. " E_SYMR ,Error for SMAR" "No error,Error"
|
|
bitfld.long 0x00 5. " E_SYMX ,Error for SMAX" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MAXIMINERR ,Maxs / Iminis error" "No error,Error"
|
|
bitfld.long 0x00 3. " FCTLERR ,r / c too large error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FTLERR ,F too large error" "No error,Error"
|
|
bitfld.long 0x00 1. " TBNAERR ,Traceback mode not allowed error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ERROR ,Error detection" "No error,Error"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "VCPEMU,VCP2 Emulation Control Register"
|
|
bitfld.long 0x00 1. " SOFT ,Soft bit" "Immediately,After finish"
|
|
bitfld.long 0x00 0. " FREE ,Free bit" "Soft bit select,Free run"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x0 "REVISION,VCP2_IP Revision Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " Source_IP ,Source of VCP IP"
|
|
hexmask.long.word 0x00 0.--15. 1. " Rev_IP ,VCP IP Revision number"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SYSCONFIG,VCP2 System Configuration Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Idle mode bit" "Unconditional,Inactive,Busy,?..."
|
|
bitfld.long 0x00 0. " RESET_DONE ,Status of the reset from the idle command" "No reset,Reset"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "IRQSTATUS,VCP2 System Configuration Register"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " STATUS_set/clr ,VCP IRQ enable status" "Disabled,Enabled"
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "DEBUG,VCP2 System Configuration Register"
|
|
bitfld.long 0x00 3. " EMUSUSP ,Status of the emulation suspend mode request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " DMA_X_REQ ,Status of the VCP tranmit event (VCPXEVT)" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA_R_REQ ,Status of the VCP receive event (VCPREVT)" "Not pending,Pending"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.open "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "UART 0"
|
|
base ad:0x48020000
|
|
width 15.
|
|
if (((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x6))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "IER,Interrupt Enable Register"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "LCR,Line Control Register"
|
|
bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced"
|
|
bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits"
|
|
if (((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low"
|
|
bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "LSR,Line Status Register"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x10)))&0x40)==0x0))
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "MSR,Modem Status Register"
|
|
in
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x48020000+0x10)))&0x40)==0x0))
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "XOFF1,XOFF1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)"
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "XOFF2,XOFF2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
endif
|
|
if (((d.w((ad:0x48020000+0x20)))&0x7)==(0x4||0x5))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x48020000+0x20)))&0x7)==0x1)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x48020000+0x20)))&0x7)==0x6)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles"
|
|
elif (((d.w((ad:0x48020000+0x20)))&0x7)==(0x0||0x2||0x3))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
hgroup.word 0x24++0x01
|
|
hide.word 0x00 "MDR2,Mode Definition Register 2"
|
|
endif
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "SFLSR,Status FIFO Line Status Register"
|
|
bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error"
|
|
bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected"
|
|
bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error"
|
|
wgroup.word 0x28++0x01
|
|
line.word 0x00 "TXFLL,Transmit Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs"
|
|
rgroup.word 0x2c++0x01
|
|
line.word 0x00 "RESUME,Resume register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX"
|
|
wgroup.word 0x2c++0x01
|
|
line.word 0x00 "TXFLH,Transmit Frame Length High Register"
|
|
hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SFREGL,Status FIFO Register Low"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "RXFLL,Received Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "SFREGH,Status FIFO Register High"
|
|
bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.word 0x34++0x01
|
|
line.word 0x00 "RXFLH,Received Frame Length High Register"
|
|
bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "BLR,BOF Control Register"
|
|
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
else
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "UASR,UART Autobauding Status Register"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..."
|
|
endif
|
|
if (((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred"
|
|
else
|
|
hgroup.word 0x3c++0x01
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
endif
|
|
width 15.
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
|
|
width 15.
|
|
if ((((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags"
|
|
elif ((((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x6))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt"
|
|
else
|
|
hgroup.word 0x48++0x01
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "MVR,Module Version Register"
|
|
hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
|
|
hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "SYSC,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup"
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
rgroup.word 0x58++0x01
|
|
line.word 0x00 "SYSS,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x01
|
|
line.word 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed"
|
|
bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
if (((d.w((ad:0x48020000+0x20)))&0x7)==0x6)
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler"
|
|
else
|
|
hgroup.word 0x60++0x01
|
|
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
endif
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "MDR3,Mode Definition Register 3"
|
|
bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different"
|
|
bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault"
|
|
bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable"
|
|
endif
|
|
sif (cpuis("AM335*"))
|
|
width 18.
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh."
|
|
hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "UART 1"
|
|
base ad:0x48022000
|
|
width 15.
|
|
if (((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x6))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "IER,Interrupt Enable Register"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "LCR,Line Control Register"
|
|
bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced"
|
|
bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits"
|
|
if (((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low"
|
|
bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "LSR,Line Status Register"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x10)))&0x40)==0x0))
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "MSR,Modem Status Register"
|
|
in
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x48022000+0x10)))&0x40)==0x0))
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "XOFF1,XOFF1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)"
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "XOFF2,XOFF2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
endif
|
|
if (((d.w((ad:0x48022000+0x20)))&0x7)==(0x4||0x5))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x48022000+0x20)))&0x7)==0x1)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x48022000+0x20)))&0x7)==0x6)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles"
|
|
elif (((d.w((ad:0x48022000+0x20)))&0x7)==(0x0||0x2||0x3))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
hgroup.word 0x24++0x01
|
|
hide.word 0x00 "MDR2,Mode Definition Register 2"
|
|
endif
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "SFLSR,Status FIFO Line Status Register"
|
|
bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error"
|
|
bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected"
|
|
bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error"
|
|
wgroup.word 0x28++0x01
|
|
line.word 0x00 "TXFLL,Transmit Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs"
|
|
rgroup.word 0x2c++0x01
|
|
line.word 0x00 "RESUME,Resume register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX"
|
|
wgroup.word 0x2c++0x01
|
|
line.word 0x00 "TXFLH,Transmit Frame Length High Register"
|
|
hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SFREGL,Status FIFO Register Low"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "RXFLL,Received Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "SFREGH,Status FIFO Register High"
|
|
bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.word 0x34++0x01
|
|
line.word 0x00 "RXFLH,Received Frame Length High Register"
|
|
bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "BLR,BOF Control Register"
|
|
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
else
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "UASR,UART Autobauding Status Register"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..."
|
|
endif
|
|
if (((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred"
|
|
else
|
|
hgroup.word 0x3c++0x01
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
endif
|
|
width 15.
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
|
|
width 15.
|
|
if ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags"
|
|
elif ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x6))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt"
|
|
else
|
|
hgroup.word 0x48++0x01
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "MVR,Module Version Register"
|
|
hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
|
|
hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "SYSC,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup"
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
rgroup.word 0x58++0x01
|
|
line.word 0x00 "SYSS,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x01
|
|
line.word 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed"
|
|
bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
if (((d.w((ad:0x48022000+0x20)))&0x7)==0x6)
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler"
|
|
else
|
|
hgroup.word 0x60++0x01
|
|
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
endif
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "MDR3,Mode Definition Register 3"
|
|
bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different"
|
|
bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault"
|
|
bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable"
|
|
endif
|
|
sif (cpuis("AM335*"))
|
|
width 18.
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh."
|
|
hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "UART 2"
|
|
base ad:0x48024000
|
|
width 15.
|
|
if (((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x6))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "IER,Interrupt Enable Register"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "LCR,Line Control Register"
|
|
bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced"
|
|
bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits"
|
|
if (((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low"
|
|
bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "LSR,Line Status Register"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x10)))&0x40)==0x0))
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "MSR,Modem Status Register"
|
|
in
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x48024000+0x10)))&0x40)==0x0))
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "XOFF1,XOFF1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)"
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "XOFF2,XOFF2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
endif
|
|
if (((d.w((ad:0x48024000+0x20)))&0x7)==(0x4||0x5))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x48024000+0x20)))&0x7)==0x1)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x48024000+0x20)))&0x7)==0x6)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles"
|
|
elif (((d.w((ad:0x48024000+0x20)))&0x7)==(0x0||0x2||0x3))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
hgroup.word 0x24++0x01
|
|
hide.word 0x00 "MDR2,Mode Definition Register 2"
|
|
endif
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "SFLSR,Status FIFO Line Status Register"
|
|
bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error"
|
|
bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected"
|
|
bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error"
|
|
wgroup.word 0x28++0x01
|
|
line.word 0x00 "TXFLL,Transmit Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs"
|
|
rgroup.word 0x2c++0x01
|
|
line.word 0x00 "RESUME,Resume register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX"
|
|
wgroup.word 0x2c++0x01
|
|
line.word 0x00 "TXFLH,Transmit Frame Length High Register"
|
|
hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SFREGL,Status FIFO Register Low"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "RXFLL,Received Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "SFREGH,Status FIFO Register High"
|
|
bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.word 0x34++0x01
|
|
line.word 0x00 "RXFLH,Received Frame Length High Register"
|
|
bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "BLR,BOF Control Register"
|
|
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
else
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "UASR,UART Autobauding Status Register"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..."
|
|
endif
|
|
if (((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred"
|
|
else
|
|
hgroup.word 0x3c++0x01
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
endif
|
|
width 15.
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
|
|
width 15.
|
|
if ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags"
|
|
elif ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x6))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt"
|
|
else
|
|
hgroup.word 0x48++0x01
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "MVR,Module Version Register"
|
|
hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
|
|
hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "SYSC,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup"
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
rgroup.word 0x58++0x01
|
|
line.word 0x00 "SYSS,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x01
|
|
line.word 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed"
|
|
bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
if (((d.w((ad:0x48024000+0x20)))&0x7)==0x6)
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler"
|
|
else
|
|
hgroup.word 0x60++0x01
|
|
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
endif
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "MDR3,Mode Definition Register 3"
|
|
bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different"
|
|
bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault"
|
|
bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable"
|
|
endif
|
|
sif (cpuis("AM335*"))
|
|
width 18.
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh."
|
|
hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "UART 3"
|
|
base ad:0x481A6000
|
|
width 15.
|
|
if (((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x6))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "IER,Interrupt Enable Register"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "LCR,Line Control Register"
|
|
bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced"
|
|
bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits"
|
|
if (((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low"
|
|
bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "LSR,Line Status Register"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x10)))&0x40)==0x0))
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "MSR,Modem Status Register"
|
|
in
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x481A6000+0x10)))&0x40)==0x0))
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "XOFF1,XOFF1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)"
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "XOFF2,XOFF2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
endif
|
|
if (((d.w((ad:0x481A6000+0x20)))&0x7)==(0x4||0x5))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x481A6000+0x20)))&0x7)==0x1)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x481A6000+0x20)))&0x7)==0x6)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles"
|
|
elif (((d.w((ad:0x481A6000+0x20)))&0x7)==(0x0||0x2||0x3))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
hgroup.word 0x24++0x01
|
|
hide.word 0x00 "MDR2,Mode Definition Register 2"
|
|
endif
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "SFLSR,Status FIFO Line Status Register"
|
|
bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error"
|
|
bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected"
|
|
bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error"
|
|
wgroup.word 0x28++0x01
|
|
line.word 0x00 "TXFLL,Transmit Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs"
|
|
rgroup.word 0x2c++0x01
|
|
line.word 0x00 "RESUME,Resume register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX"
|
|
wgroup.word 0x2c++0x01
|
|
line.word 0x00 "TXFLH,Transmit Frame Length High Register"
|
|
hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SFREGL,Status FIFO Register Low"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "RXFLL,Received Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "SFREGH,Status FIFO Register High"
|
|
bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.word 0x34++0x01
|
|
line.word 0x00 "RXFLH,Received Frame Length High Register"
|
|
bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "BLR,BOF Control Register"
|
|
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
else
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "UASR,UART Autobauding Status Register"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..."
|
|
endif
|
|
if (((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred"
|
|
else
|
|
hgroup.word 0x3c++0x01
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
endif
|
|
width 15.
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
|
|
width 15.
|
|
if ((((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags"
|
|
elif ((((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x6))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt"
|
|
else
|
|
hgroup.word 0x48++0x01
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "MVR,Module Version Register"
|
|
hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
|
|
hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "SYSC,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup"
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
rgroup.word 0x58++0x01
|
|
line.word 0x00 "SYSS,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x01
|
|
line.word 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed"
|
|
bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
if (((d.w((ad:0x481A6000+0x20)))&0x7)==0x6)
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler"
|
|
else
|
|
hgroup.word 0x60++0x01
|
|
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
endif
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "MDR3,Mode Definition Register 3"
|
|
bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different"
|
|
bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault"
|
|
bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable"
|
|
endif
|
|
sif (cpuis("AM335*"))
|
|
width 18.
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh."
|
|
hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "UART 4"
|
|
base ad:0x481A8000
|
|
width 15.
|
|
if (((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x6))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "IER,Interrupt Enable Register"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "LCR,Line Control Register"
|
|
bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced"
|
|
bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits"
|
|
if (((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low"
|
|
bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "LSR,Line Status Register"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x10)))&0x40)==0x0))
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "MSR,Modem Status Register"
|
|
in
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x481A8000+0x10)))&0x40)==0x0))
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "XOFF1,XOFF1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)"
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "XOFF2,XOFF2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
endif
|
|
if (((d.w((ad:0x481A8000+0x20)))&0x7)==(0x4||0x5))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x481A8000+0x20)))&0x7)==0x1)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x481A8000+0x20)))&0x7)==0x6)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles"
|
|
elif (((d.w((ad:0x481A8000+0x20)))&0x7)==(0x0||0x2||0x3))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
hgroup.word 0x24++0x01
|
|
hide.word 0x00 "MDR2,Mode Definition Register 2"
|
|
endif
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "SFLSR,Status FIFO Line Status Register"
|
|
bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error"
|
|
bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected"
|
|
bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error"
|
|
wgroup.word 0x28++0x01
|
|
line.word 0x00 "TXFLL,Transmit Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs"
|
|
rgroup.word 0x2c++0x01
|
|
line.word 0x00 "RESUME,Resume register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX"
|
|
wgroup.word 0x2c++0x01
|
|
line.word 0x00 "TXFLH,Transmit Frame Length High Register"
|
|
hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SFREGL,Status FIFO Register Low"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "RXFLL,Received Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "SFREGH,Status FIFO Register High"
|
|
bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.word 0x34++0x01
|
|
line.word 0x00 "RXFLH,Received Frame Length High Register"
|
|
bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "BLR,BOF Control Register"
|
|
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
else
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "UASR,UART Autobauding Status Register"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..."
|
|
endif
|
|
if (((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred"
|
|
else
|
|
hgroup.word 0x3c++0x01
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
endif
|
|
width 15.
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
|
|
width 15.
|
|
if ((((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags"
|
|
elif ((((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x6))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt"
|
|
else
|
|
hgroup.word 0x48++0x01
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "MVR,Module Version Register"
|
|
hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
|
|
hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "SYSC,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup"
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
rgroup.word 0x58++0x01
|
|
line.word 0x00 "SYSS,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x01
|
|
line.word 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed"
|
|
bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
if (((d.w((ad:0x481A8000+0x20)))&0x7)==0x6)
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler"
|
|
else
|
|
hgroup.word 0x60++0x01
|
|
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
endif
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "MDR3,Mode Definition Register 3"
|
|
bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different"
|
|
bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault"
|
|
bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable"
|
|
endif
|
|
sif (cpuis("AM335*"))
|
|
width 18.
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh."
|
|
hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "UART 5"
|
|
base ad:0x481AA000
|
|
width 15.
|
|
if (((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x6))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "IER,Interrupt Enable Register"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "LCR,Line Control Register"
|
|
bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced"
|
|
bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits"
|
|
if (((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low"
|
|
bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "LSR,Line Status Register"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x10)))&0x40)==0x0))
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "MSR,Modem Status Register"
|
|
in
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x481AA000+0x10)))&0x40)==0x0))
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "XOFF1,XOFF1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)"
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "XOFF2,XOFF2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
endif
|
|
if (((d.w((ad:0x481AA000+0x20)))&0x7)==(0x4||0x5))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x481AA000+0x20)))&0x7)==0x1)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x481AA000+0x20)))&0x7)==0x6)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles"
|
|
elif (((d.w((ad:0x481AA000+0x20)))&0x7)==(0x0||0x2||0x3))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
hgroup.word 0x24++0x01
|
|
hide.word 0x00 "MDR2,Mode Definition Register 2"
|
|
endif
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "SFLSR,Status FIFO Line Status Register"
|
|
bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error"
|
|
bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected"
|
|
bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error"
|
|
wgroup.word 0x28++0x01
|
|
line.word 0x00 "TXFLL,Transmit Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs"
|
|
rgroup.word 0x2c++0x01
|
|
line.word 0x00 "RESUME,Resume register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX"
|
|
wgroup.word 0x2c++0x01
|
|
line.word 0x00 "TXFLH,Transmit Frame Length High Register"
|
|
hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SFREGL,Status FIFO Register Low"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "RXFLL,Received Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "SFREGH,Status FIFO Register High"
|
|
bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.word 0x34++0x01
|
|
line.word 0x00 "RXFLH,Received Frame Length High Register"
|
|
bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "BLR,BOF Control Register"
|
|
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
else
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "UASR,UART Autobauding Status Register"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..."
|
|
endif
|
|
if (((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred"
|
|
else
|
|
hgroup.word 0x3c++0x01
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
endif
|
|
width 15.
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
|
|
width 15.
|
|
if ((((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags"
|
|
elif ((((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x6))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt"
|
|
else
|
|
hgroup.word 0x48++0x01
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "MVR,Module Version Register"
|
|
hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
|
|
hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "SYSC,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup"
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
rgroup.word 0x58++0x01
|
|
line.word 0x00 "SYSS,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x01
|
|
line.word 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed"
|
|
bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
if (((d.w((ad:0x481AA000+0x20)))&0x7)==0x6)
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler"
|
|
else
|
|
hgroup.word 0x60++0x01
|
|
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
endif
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "MDR3,Mode Definition Register 3"
|
|
bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different"
|
|
bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault"
|
|
bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable"
|
|
endif
|
|
sif (cpuis("AM335*"))
|
|
width 18.
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh."
|
|
hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
sif (cpuis("DRA62*"))
|
|
tree "UART 6"
|
|
base ad:0x48440000
|
|
width 15.
|
|
if (((d.w((ad:0x48440000+0x0c)))&0x80)==0x00)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x48440000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48440000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48440000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48440000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48440000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48440000+0x20)))&0x7)==0x6))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48440000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48440000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "IER,Interrupt Enable Register"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x48440000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48440000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48440000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48440000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48440000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48440000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48440000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48440000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "LCR,Line Control Register"
|
|
bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced"
|
|
bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits"
|
|
if (((d.w((ad:0x48440000+0x0c)))&0xff)!=0xbf)
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low"
|
|
bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x48440000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48440000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48440000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48440000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48440000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48440000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48440000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48440000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "LSR,Line Status Register"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x48440000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48440000+0x10)))&0x40)==0x0))
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "MSR,Modem Status Register"
|
|
in
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x48440000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x48440000+0x10)))&0x40)==0x0))
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "XOFF1,XOFF1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)"
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "XOFF2,XOFF2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
endif
|
|
if (((d.w((ad:0x48440000+0x20)))&0x7)==(0x4||0x5))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x48440000+0x20)))&0x7)==0x1)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x48440000+0x20)))&0x7)==0x6)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles"
|
|
elif (((d.w((ad:0x48440000+0x20)))&0x7)==(0x0||0x2||0x3))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
hgroup.word 0x24++0x01
|
|
hide.word 0x00 "MDR2,Mode Definition Register 2"
|
|
endif
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "SFLSR,Status FIFO Line Status Register"
|
|
bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error"
|
|
bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected"
|
|
bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error"
|
|
wgroup.word 0x28++0x01
|
|
line.word 0x00 "TXFLL,Transmit Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs"
|
|
rgroup.word 0x2c++0x01
|
|
line.word 0x00 "RESUME,Resume register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX"
|
|
wgroup.word 0x2c++0x01
|
|
line.word 0x00 "TXFLH,Transmit Frame Length High Register"
|
|
hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SFREGL,Status FIFO Register Low"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "RXFLL,Received Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "SFREGH,Status FIFO Register High"
|
|
bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.word 0x34++0x01
|
|
line.word 0x00 "RXFLH,Received Frame Length High Register"
|
|
bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.w((ad:0x48440000+0x0c)))&0x80)==0x00)
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "BLR,BOF Control Register"
|
|
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
else
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "UASR,UART Autobauding Status Register"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..."
|
|
endif
|
|
if (((d.w((ad:0x48440000+0x0c)))&0x80)==0x00)
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred"
|
|
else
|
|
hgroup.word 0x3c++0x01
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
endif
|
|
width 15.
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
|
|
width 15.
|
|
if ((((d.w((ad:0x48440000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48440000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags"
|
|
elif ((((d.w((ad:0x48440000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48440000+0x20)))&0x7)==0x6))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt"
|
|
else
|
|
hgroup.word 0x48++0x01
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "MVR,Module Version Register"
|
|
hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
|
|
hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "SYSC,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup"
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
rgroup.word 0x58++0x01
|
|
line.word 0x00 "SYSS,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x01
|
|
line.word 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed"
|
|
bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
if (((d.w((ad:0x48440000+0x20)))&0x7)==0x6)
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler"
|
|
else
|
|
hgroup.word 0x60++0x01
|
|
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
endif
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "MDR3,Mode Definition Register 3"
|
|
bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different"
|
|
bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault"
|
|
bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable"
|
|
endif
|
|
sif (cpuis("AM335*"))
|
|
width 18.
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh."
|
|
hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "UART 7"
|
|
base ad:0x48442000
|
|
width 15.
|
|
if (((d.w((ad:0x48442000+0x0c)))&0x80)==0x00)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x48442000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48442000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48442000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48442000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48442000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48442000+0x20)))&0x7)==0x6))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48442000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48442000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "IER,Interrupt Enable Register"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
endif
|
|
if ((((d.w((ad:0x48442000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48442000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48442000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48442000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48442000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48442000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
|
|
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
|
|
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x48442000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48442000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "LCR,Line Control Register"
|
|
bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced"
|
|
bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits"
|
|
if (((d.w((ad:0x48442000+0x0c)))&0xff)!=0xbf)
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low"
|
|
bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x48442000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48442000+0x20)))&0x7)==(0x0||0x2||0x3)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48442000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48442000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48442000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48442000+0x20)))&0x7)==0x6))
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
|
|
elif ((((d.w((ad:0x48442000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48442000+0x20)))&0x7)==0x7))
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "LSR,Line Status Register"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)"
|
|
endif
|
|
if ((((d.w((ad:0x48442000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48442000+0x10)))&0x40)==0x0))
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "MSR,Modem Status Register"
|
|
in
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x48442000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x48442000+0x10)))&0x40)==0x0))
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "XOFF1,XOFF1 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)"
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "XOFF2,XOFF2 Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
endif
|
|
if (((d.w((ad:0x48442000+0x20)))&0x7)==(0x4||0x5))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x48442000+0x20)))&0x7)==0x1)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
elif (((d.w((ad:0x48442000+0x20)))&0x7)==0x6)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles"
|
|
elif (((d.w((ad:0x48442000+0x20)))&0x7)==(0x0||0x2||0x3))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
hgroup.word 0x24++0x01
|
|
hide.word 0x00 "MDR2,Mode Definition Register 2"
|
|
endif
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "SFLSR,Status FIFO Line Status Register"
|
|
bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error"
|
|
bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected"
|
|
bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error"
|
|
wgroup.word 0x28++0x01
|
|
line.word 0x00 "TXFLL,Transmit Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs"
|
|
rgroup.word 0x2c++0x01
|
|
line.word 0x00 "RESUME,Resume register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX"
|
|
wgroup.word 0x2c++0x01
|
|
line.word 0x00 "TXFLH,Transmit Frame Length High Register"
|
|
hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SFREGL,Status FIFO Register Low"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "RXFLL,Received Frame Length Low Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "SFREGH,Status FIFO Register High"
|
|
bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.word 0x34++0x01
|
|
line.word 0x00 "RXFLH,Received Frame Length High Register"
|
|
bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.w((ad:0x48442000+0x0c)))&0x80)==0x00)
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "BLR,BOF Control Register"
|
|
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
else
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "UASR,UART Autobauding Status Register"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..."
|
|
endif
|
|
if (((d.w((ad:0x48442000+0x0c)))&0x80)==0x00)
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred"
|
|
else
|
|
hgroup.word 0x3c++0x01
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
endif
|
|
width 15.
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
|
|
width 15.
|
|
if ((((d.w((ad:0x48442000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48442000+0x20)))&0x7)==(0x1||0x4||0x5)))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags"
|
|
elif ((((d.w((ad:0x48442000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48442000+0x20)))&0x7)==0x6))
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt"
|
|
else
|
|
hgroup.word 0x48++0x01
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "MVR,Module Version Register"
|
|
hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
|
|
hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "SYSC,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup"
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
rgroup.word 0x58++0x01
|
|
line.word 0x00 "SYSS,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x01
|
|
line.word 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed"
|
|
bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed"
|
|
bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
if (((d.w((ad:0x48442000+0x20)))&0x7)==0x6)
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler"
|
|
else
|
|
hgroup.word 0x60++0x01
|
|
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
endif
|
|
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "MDR3,Mode Definition Register 3"
|
|
bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different"
|
|
bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault"
|
|
bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable"
|
|
endif
|
|
sif (cpuis("AM335*"))
|
|
width 18.
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh."
|
|
hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "USB (Universal Serial Bus)"
|
|
tree "USBSS"
|
|
base ad:0x47400000
|
|
width 12.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REVREG,Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "Legacy ASP or WTBU,Highlander 0.8,?..."
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SYSCONFIG,SYSCONFIG Register"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 17. " USB1_D2_OCP_EN_N ,Active low clock enable for USB1_D2_OCP_CLK" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " USB0_D2_OCP_EN_N ,Active low clock enable for USB1_D2_OCP_CLK" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " USB0_OCP_CLK_EN ,Active low clock enable for usb0_ocp_clk" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " PHY0_UTMI_CLK_EN ,Active low clock enable for phy0_utmi_clk" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " USB1_OCP_CLK_EN ,Active low clock enable for usb1_ocp_clk" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " PHY1_UTMI_CLK_EN ,Active low clock enable for phy1_utmi_clk" "Enabled,Disabled"
|
|
textline " "
|
|
sif (cpuis("DM814?DSP")||cpuis("AM335*")||cpuis("AM387*")||cpuis("DRA62*"))
|
|
bitfld.long 0x00 4.--5. " STANDBY_MODE ,Standby mode select" "Force-standby,No-standby,Smart-standby,Smart-standby wakeup capable"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Idlemode select" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup capable"
|
|
else
|
|
bitfld.long 0x00 4.--5. " STANDBY_MODE ,Standby mode select" "Force-standby,Reserved,Smart-standby,Smart-standby wakeup capable"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Idlemode select" "Reserved,Reserved,Smart-standby,Smart-standby wakeup capable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal" "Sensitive,Not sensitive"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Software reset of USBSS USB0 and USB1 modules" "No reset,Reset"
|
|
sif (!cpuis("AM335*"))
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "EOI,End of Interrupt Register"
|
|
bitfld.long 0x00 0. " EOI_VECTOR ,End of interrupt for USBSS Interrupt" "Completed,Not completed"
|
|
endif
|
|
group.long 0x24++0xf
|
|
line.long 0x00 "IRQSTATRAW,IRQ Status Raw Register"
|
|
bitfld.long 0x00 11. " RX_PKT_CMP_1 ,USB1 Rx CPPI DMA packet completion interrupt raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " TX_PKT_CMP_1 ,USB1 Tx CPPI DMA packet completion interrupt raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_PKT_CMP_0 ,USB0 Rx CPPI DMA packet completion interrupt raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " TX_PKT_CMP_0 ,USB0 Tx CPPI DMA packet completion interrupt raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PD_CMP_FLAG ,Packet completed interrupt raw status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RX_MOP_STARVATION ,Rx buffer cannot be allocated in the middle of packet interrupt raw status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RX_SOP_STARVATION ,Rx buffer cannot be allocated in the start of packet interrupt raw status" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQSTAT,IRQ Status Register"
|
|
eventfld.long 0x04 11. " RX_PKT_CMP_1 ,USB1 Rx CPPI DMA packet completion interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 10. " TX_PKT_CMP_1 ,USB1 Tx CPPI DMA packet completion interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 9. " RX_PKT_CMP_0 ,USB0 Rx CPPI DMA packet completion interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " TX_PKT_CMP_0 ,IUSB0 Tx CPPI DMA packet completion interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 2. " PD_CMP_FLAG ,Packet completed interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " RX_MOP_STARVATION ,Rx buffer cannot be allocated in the middle of packet interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 0. " RX_SOP_STARVATION ,Rx buffer cannot be allocated in the start of packet interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQENABLER,IRQ Enable Set Register"
|
|
bitfld.long 0x08 11. " RX_PKT_CMP_1 ,USB1 Rx CPPI DMA packet completion interrupt enable status" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " TX_PKT_CMP_1 ,USB1 Tx CPPI DMA packet completion interrupt enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " RX_PKT_CMP_0 ,USB0 Rx CPPI DMA packet completion interrupt enable status" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " TX_PKT_CMP_0 ,IUSB0 Tx CPPI DMA packet completion interrupt enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PD_CMP_FLAG ,Packet completed interrupt enable status" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RX_MOP_STARVATION ,Rx buffer cannot be allocated in the middle of packet interrupt enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " RX_SOP_STARVATION ,Rx buffer cannot be allocated in the start of packet interrupt enable status" "Disabled,Enabled"
|
|
line.long 0x0c "IRQCLEARR,IRQ Enable Clear Register"
|
|
eventfld.long 0x0c 11. " RX_PKT_CMP_1 ,USB1 Rx CPPI DMA packet completion interrupt disable status" "Disabled,Enabled"
|
|
eventfld.long 0x0c 10. " TX_PKT_CMP_1 ,USB1 Tx CPPI DMA packet completion interrupt disable status" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0c 9. " RX_PKT_CMP_0 ,USB0 Rx CPPI DMA packet completion interrupt disable status" "Disabled,Enabled"
|
|
eventfld.long 0x0c 8. " TX_PKT_CMP_0 ,IUSB0 Tx CPPI DMA packet completion interrupt disable status" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0c 2. " PD_CMP_FLAG ,Packet completed interrupt disable status" "Disabled,Enabled"
|
|
eventfld.long 0x0c 1. " RX_MOP_STARVATION ,Rx buffer cannot be allocated in the middle of packet interrupt disable status" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0c 0. " RX_SOP_STARVATION ,Rx buffer cannot be allocated in the start of packet interrupt disable status" "Disabled,Enabled"
|
|
width 17.
|
|
tree "DMA Thresholds"
|
|
group.long 0x100++0x47
|
|
line.long (0x0+0x00) "IRQDMATHOLDTX00,IRQ DMA Threshold TX0 0 Register"
|
|
hexmask.long.byte (0x0+0x00) 24.--31. 1. " DMA_THRES_TX0_3 ,Threshold value for USB0 endpoint 3"
|
|
hexmask.long.byte (0x0+0x00) 16.--23. 1. " DMA_THRES_TX0_2 ,Threshold value for USB0 endpoint 2"
|
|
textline " "
|
|
hexmask.long.byte (0x0+0x00) 8.--15. 1. " DMA_THRES_TX0_1 ,Threshold value for USB0 endpoint 1"
|
|
line.long (0x0+0x04) "IRQDMATHOLDTX01,IRQ DMA Threshold TX0 1 Register"
|
|
hexmask.long.byte (0x0+0x04) 24.--31. 1. " DMA_THRES_TX0_7 ,Threshold value for USB0 endpoint 7"
|
|
hexmask.long.byte (0x0+0x04) 16.--23. 1. " DMA_THRES_TX0_6 ,Threshold value for USB0 endpoint 6"
|
|
textline " "
|
|
hexmask.long.byte (0x0+0x04) 8.--15. 1. " DMA_THRES_TX0_5 ,Threshold value for USB0 endpoint 5"
|
|
hexmask.long.byte (0x0+0x04) 0.--7. 1. " DMA_THRES_TX0_4 ,Threshold value for USB0 endpoint 4"
|
|
line.long (0x0+0x08) "IRQDMATHOLDTX02,IRQ DMA Threshold TX0 2 Register"
|
|
hexmask.long.byte (0x0+0x08) 24.--31. 1. " DMA_THRES_TX0_11 ,Threshold value for USB0 endpoint 11"
|
|
hexmask.long.byte (0x0+0x08) 16.--23. 1. " DMA_THRES_TX0_10 ,Threshold value for USB0 endpoint 10"
|
|
textline " "
|
|
hexmask.long.byte (0x0+0x08) 8.--15. 1. " DMA_THRES_TX0_9 ,Threshold value for USB0 endpoint 9"
|
|
hexmask.long.byte (0x0+0x08) 0.--7. 1. " DMA_THRES_TX0_8 ,Threshold value for USB0 endpoint 8"
|
|
line.long (0x0+0x0C) "IRQDMATHOLDTX03,IRQ DMA Threshold TX0 3 Register"
|
|
hexmask.long.byte (0x0+0x0C) 24.--31. 1. " DMA_THRES_TX0_15 ,Threshold value for USB0 endpoint 15"
|
|
hexmask.long.byte (0x0+0x0C) 16.--23. 1. " DMA_THRES_TX0_14 ,Threshold value for USB0 endpoint 14"
|
|
textline " "
|
|
hexmask.long.byte (0x0+0x0C) 8.--15. 1. " DMA_THRES_TX0_13 ,Threshold value for USB0 endpoint 13"
|
|
hexmask.long.byte (0x0+0x0C) 0.--7. 1. " DMA_THRES_TX0_12 ,Threshold value for USB0 endpoint 12"
|
|
line.long (0x10+0x00) "IRQDMATHOLDRX00,IRQ DMA Threshold RX0 0 Register"
|
|
hexmask.long.byte (0x10+0x00) 24.--31. 1. " DMA_THRES_RX0_3 ,Threshold value for USB0 endpoint 3"
|
|
hexmask.long.byte (0x10+0x00) 16.--23. 1. " DMA_THRES_RX0_2 ,Threshold value for USB0 endpoint 2"
|
|
textline " "
|
|
hexmask.long.byte (0x10+0x00) 8.--15. 1. " DMA_THRES_RX0_1 ,Threshold value for USB0 endpoint 1"
|
|
line.long (0x10+0x04) "IRQDMATHOLDRX01,IRQ DMA Threshold RX0 1 Register"
|
|
hexmask.long.byte (0x10+0x04) 24.--31. 1. " DMA_THRES_RX0_7 ,Threshold value for USB0 endpoint 7"
|
|
hexmask.long.byte (0x10+0x04) 16.--23. 1. " DMA_THRES_RX0_6 ,Threshold value for USB0 endpoint 6"
|
|
textline " "
|
|
hexmask.long.byte (0x10+0x04) 8.--15. 1. " DMA_THRES_RX0_5 ,Threshold value for USB0 endpoint 5"
|
|
hexmask.long.byte (0x10+0x04) 0.--7. 1. " DMA_THRES_RX0_4 ,Threshold value for USB0 endpoint 4"
|
|
line.long (0x10+0x08) "IRQDMATHOLDRX02,IRQ DMA Threshold RX0 2 Register"
|
|
hexmask.long.byte (0x10+0x08) 24.--31. 1. " DMA_THRES_RX0_11 ,Threshold value for USB0 endpoint 11"
|
|
hexmask.long.byte (0x10+0x08) 16.--23. 1. " DMA_THRES_RX0_10 ,Threshold value for USB0 endpoint 10"
|
|
textline " "
|
|
hexmask.long.byte (0x10+0x08) 8.--15. 1. " DMA_THRES_RX0_9 ,Threshold value for USB0 endpoint 9"
|
|
hexmask.long.byte (0x10+0x08) 0.--7. 1. " DMA_THRES_RX0_8 ,Threshold value for USB0 endpoint 8"
|
|
line.long (0x10+0x0C) "IRQDMATHOLDRX03,IRQ DMA Threshold RX0 3 Register"
|
|
hexmask.long.byte (0x10+0x0C) 24.--31. 1. " DMA_THRES_RX0_15 ,Threshold value for USB0 endpoint 15"
|
|
hexmask.long.byte (0x10+0x0C) 16.--23. 1. " DMA_THRES_RX0_14 ,Threshold value for USB0 endpoint 14"
|
|
textline " "
|
|
hexmask.long.byte (0x10+0x0C) 8.--15. 1. " DMA_THRES_RX0_13 ,Threshold value for USB0 endpoint 13"
|
|
hexmask.long.byte (0x10+0x0C) 0.--7. 1. " DMA_THRES_RX0_12 ,Threshold value for USB0 endpoint 12"
|
|
line.long (0x20+0x00) "IRQDMATHOLDTX10,IRQ DMA Threshold TX1 0 Register"
|
|
hexmask.long.byte (0x20+0x00) 24.--31. 1. " DMA_THRES_TX1_3 ,Threshold value for USB1 endpoint 3"
|
|
hexmask.long.byte (0x20+0x00) 16.--23. 1. " DMA_THRES_TX1_2 ,Threshold value for USB1 endpoint 2"
|
|
textline " "
|
|
hexmask.long.byte (0x20+0x00) 8.--15. 1. " DMA_THRES_TX1_1 ,Threshold value for USB1 endpoint 1"
|
|
line.long (0x20+0x04) "IRQDMATHOLDTX11,IRQ DMA Threshold TX1 1 Register"
|
|
hexmask.long.byte (0x20+0x04) 24.--31. 1. " DMA_THRES_TX1_7 ,Threshold value for USB1 endpoint 7"
|
|
hexmask.long.byte (0x20+0x04) 16.--23. 1. " DMA_THRES_TX1_6 ,Threshold value for USB1 endpoint 6"
|
|
textline " "
|
|
hexmask.long.byte (0x20+0x04) 8.--15. 1. " DMA_THRES_TX1_5 ,Threshold value for USB1 endpoint 5"
|
|
hexmask.long.byte (0x20+0x04) 0.--7. 1. " DMA_THRES_TX1_4 ,Threshold value for USB1 endpoint 4"
|
|
line.long (0x20+0x08) "IRQDMATHOLDTX12,IRQ DMA Threshold TX1 2 Register"
|
|
hexmask.long.byte (0x20+0x08) 24.--31. 1. " DMA_THRES_TX1_11 ,Threshold value for USB1 endpoint 11"
|
|
hexmask.long.byte (0x20+0x08) 16.--23. 1. " DMA_THRES_TX1_10 ,Threshold value for USB1 endpoint 10"
|
|
textline " "
|
|
hexmask.long.byte (0x20+0x08) 8.--15. 1. " DMA_THRES_TX1_9 ,Threshold value for USB1 endpoint 9"
|
|
hexmask.long.byte (0x20+0x08) 0.--7. 1. " DMA_THRES_TX1_8 ,Threshold value for USB1 endpoint 8"
|
|
line.long (0x20+0x0C) "IRQDMATHOLDTX13,IRQ DMA Threshold TX1 3 Register"
|
|
hexmask.long.byte (0x20+0x0C) 24.--31. 1. " DMA_THRES_TX1_15 ,Threshold value for USB1 endpoint 15"
|
|
hexmask.long.byte (0x20+0x0C) 16.--23. 1. " DMA_THRES_TX1_14 ,Threshold value for USB1 endpoint 14"
|
|
textline " "
|
|
hexmask.long.byte (0x20+0x0C) 8.--15. 1. " DMA_THRES_TX1_13 ,Threshold value for USB1 endpoint 13"
|
|
hexmask.long.byte (0x20+0x0C) 0.--7. 1. " DMA_THRES_TX1_12 ,Threshold value for USB1 endpoint 12"
|
|
line.long (0x30+0x00) "IRQDMATHOLDRX10,IRQ DMA Threshold RX1 0 Register"
|
|
hexmask.long.byte (0x30+0x00) 24.--31. 1. " DMA_THRES_RX1_3 ,Threshold value for USB1 endpoint 3"
|
|
hexmask.long.byte (0x30+0x00) 16.--23. 1. " DMA_THRES_RX1_2 ,Threshold value for USB1 endpoint 2"
|
|
textline " "
|
|
hexmask.long.byte (0x30+0x00) 8.--15. 1. " DMA_THRES_RX1_1 ,Threshold value for USB1 endpoint 1"
|
|
line.long (0x30+0x04) "IRQDMATHOLDRX11,IRQ DMA Threshold RX1 1 Register"
|
|
hexmask.long.byte (0x30+0x04) 24.--31. 1. " DMA_THRES_RX1_7 ,Threshold value for USB1 endpoint 7"
|
|
hexmask.long.byte (0x30+0x04) 16.--23. 1. " DMA_THRES_RX1_6 ,Threshold value for USB1 endpoint 6"
|
|
textline " "
|
|
hexmask.long.byte (0x30+0x04) 8.--15. 1. " DMA_THRES_RX1_5 ,Threshold value for USB1 endpoint 5"
|
|
hexmask.long.byte (0x30+0x04) 0.--7. 1. " DMA_THRES_RX1_4 ,Threshold value for USB1 endpoint 4"
|
|
line.long (0x30+0x08) "IRQDMATHOLDRX12,IRQ DMA Threshold RX1 2 Register"
|
|
hexmask.long.byte (0x30+0x08) 24.--31. 1. " DMA_THRES_RX1_11 ,Threshold value for USB1 endpoint 11"
|
|
hexmask.long.byte (0x30+0x08) 16.--23. 1. " DMA_THRES_RX1_10 ,Threshold value for USB1 endpoint 10"
|
|
textline " "
|
|
hexmask.long.byte (0x30+0x08) 8.--15. 1. " DMA_THRES_RX1_9 ,Threshold value for USB1 endpoint 9"
|
|
hexmask.long.byte (0x30+0x08) 0.--7. 1. " DMA_THRES_RX1_8 ,Threshold value for USB1 endpoint 8"
|
|
line.long (0x30+0x0C) "IRQDMATHOLDRX13,IRQ DMA Threshold RX1 3 Register"
|
|
hexmask.long.byte (0x30+0x0C) 24.--31. 1. " DMA_THRES_RX1_15 ,Threshold value for USB1 endpoint 15"
|
|
hexmask.long.byte (0x30+0x0C) 16.--23. 1. " DMA_THRES_RX1_14 ,Threshold value for USB1 endpoint 14"
|
|
textline " "
|
|
hexmask.long.byte (0x30+0x0C) 8.--15. 1. " DMA_THRES_RX1_13 ,Threshold value for USB1 endpoint 13"
|
|
hexmask.long.byte (0x30+0x0C) 0.--7. 1. " DMA_THRES_RX1_12 ,Threshold value for USB1 endpoint 12"
|
|
line.long 0x40 "IRQDMAENABLE0,IRQ DMA Enable 0 Register"
|
|
bitfld.long 0x40 31. " DMA_EN_RX0_15 ,Threshold enable value for USB0 endpoint 15" "Disabled,Enabled"
|
|
sif (!cpuis("AM335*"))
|
|
bitfld.long 0x40 30. " DMA_EN_RX0_14 ,Threshold enable value for USB0 endpoint 14" "Disabled,Enabled"
|
|
bitfld.long 0x40 29. " DMA_EN_RX0_13 ,Threshold enable value for USB0 endpoint 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 28. " DMA_EN_RX0_12 ,Threshold enable value for USB0 endpoint 12" "Disabled,Enabled"
|
|
bitfld.long 0x40 27. " DMA_EN_RX0_11 ,Threshold enable value for USB0 endpoint 11" "Disabled,Enabled"
|
|
bitfld.long 0x40 26. " DMA_EN_RX0_10 ,Threshold enable value for USB0 endpoint 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 25. " DMA_EN_RX0_9 ,Threshold enable value for USB0 endpoint 9" "Disabled,Enabled"
|
|
bitfld.long 0x40 24. " DMA_EN_RX0_8 ,Threshold enable value for USB0 endpoint 8" "Disabled,Enabled"
|
|
bitfld.long 0x40 23. " DMA_EN_RX0_7 ,Threshold enable value for USB0 endpoint 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 22. " DMA_EN_RX0_6 ,Threshold enable value for USB0 endpoint 6" "Disabled,Enabled"
|
|
bitfld.long 0x40 21. " DMA_EN_RX0_5 ,Threshold enable value for USB0 endpoint 5" "Disabled,Enabled"
|
|
bitfld.long 0x40 20. " DMA_EN_RX0_4 ,Threshold enable value for USB0 endpoint 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 19. " DMA_EN_RX0_3 ,Threshold enable value for USB0 endpoint 3" "Disabled,Enabled"
|
|
bitfld.long 0x40 18. " DMA_EN_RX0_2 ,Threshold enable value for USB0 endpoint 2" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x40 17. " DMA_EN_RX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 15. " DMA_EN_TX0_15 ,Threshold enable value for USB0 endpoint 15" "Disabled,Enabled"
|
|
sif (!cpuis("AM335*"))
|
|
bitfld.long 0x40 14. " DMA_EN_TX0_14 ,Threshold enable value for USB0 endpoint 14" "Disabled,Enabled"
|
|
bitfld.long 0x40 13. " DMA_EN_TX0_13 ,Threshold enable value for USB0 endpoint 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 12. " DMA_EN_TX0_12 ,Threshold enable value for USB0 endpoint 12" "Disabled,Enabled"
|
|
bitfld.long 0x40 11. " DMA_EN_TX0_11 ,Threshold enable value for USB0 endpoint 11" "Disabled,Enabled"
|
|
bitfld.long 0x40 10. " DMA_EN_TX0_10 ,Threshold enable value for USB0 endpoint 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 9. " DMA_EN_TX0_9 ,Threshold enable value for USB0 endpoint 9" "Disabled,Enabled"
|
|
bitfld.long 0x40 8. " DMA_EN_TX0_8 ,Threshold enable value for USB0 endpoint 8" "Disabled,Enabled"
|
|
bitfld.long 0x40 7. " DMA_EN_TX0_7 ,Threshold enable value for USB0 endpoint 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 6. " DMA_EN_TX0_6 ,Threshold enable value for USB0 endpoint 6" "Disabled,Enabled"
|
|
bitfld.long 0x40 5. " DMA_EN_TX0_5 ,Threshold enable value for USB0 endpoint 5" "Disabled,Enabled"
|
|
bitfld.long 0x40 4. " DMA_EN_TX0_4 ,Threshold enable value for USB0 endpoint 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 3. " DMA_EN_TX0_3 ,Threshold enable value for USB0 endpoint 3" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x40 2. " DMA_EN_TX0_2 ,Threshold enable value for USB0 endpoint 2" "Disabled,Enabled"
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x40 0. " DMA_EN_TX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x40 1. " DMA_EN_TX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x44 "IRQDMAENABLE1,IRQ DMA Enable 1 Register"
|
|
bitfld.long 0x44 31. " DMA_EN_RX1_15 ,Threshold enable value for USB1 endpoint 15" "Disabled,Enabled"
|
|
sif (!cpuis("AM335*"))
|
|
bitfld.long 0x44 30. " DMA_EN_RX1_14 ,Threshold enable value for USB1 endpoint 14" "Disabled,Enabled"
|
|
bitfld.long 0x44 29. " DMA_EN_RX1_13 ,Threshold enable value for USB1 endpoint 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 28. " DMA_EN_RX1_12 ,Threshold enable value for USB1 endpoint 12" "Disabled,Enabled"
|
|
bitfld.long 0x44 27. " DMA_EN_RX1_11 ,Threshold enable value for USB1 endpoint 11" "Disabled,Enabled"
|
|
bitfld.long 0x44 26. " DMA_EN_RX1_10 ,Threshold enable value for USB1 endpoint 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 25. " DMA_EN_RX1_9 ,Threshold enable value for USB1 endpoint 9" "Disabled,Enabled"
|
|
bitfld.long 0x44 24. " DMA_EN_RX1_8 ,Threshold enable value for USB1 endpoint 8" "Disabled,Enabled"
|
|
bitfld.long 0x44 23. " DMA_EN_RX1_7 ,Threshold enable value for USB1 endpoint 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 22. " DMA_EN_RX1_6 ,Threshold enable value for USB1 endpoint 6" "Disabled,Enabled"
|
|
bitfld.long 0x44 21. " DMA_EN_RX1_5 ,Threshold enable value for USB1 endpoint 5" "Disabled,Enabled"
|
|
bitfld.long 0x44 20. " DMA_EN_RX1_4 ,Threshold enable value for USB1 endpoint 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 19. " DMA_EN_RX1_3 ,Threshold enable value for USB1 endpoint 3" "Disabled,Enabled"
|
|
bitfld.long 0x44 18. " DMA_EN_RX1_2 ,Threshold enable value for USB1 endpoint 2" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x44 17. " DMA_EN_RX1_1 ,Threshold enable value for USB1 endpoint 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 15. " DMA_EN_TX1_15 ,Threshold enable value for USB1 endpoint 15" "Disabled,Enabled"
|
|
sif (!cpuis("AM335*"))
|
|
bitfld.long 0x44 14. " DMA_EN_TX1_14 ,Threshold enable value for USB1 endpoint 14" "Disabled,Enabled"
|
|
bitfld.long 0x44 13. " DMA_EN_TX1_13 ,Threshold enable value for USB1 endpoint 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 12. " DMA_EN_TX1_12 ,Threshold enable value for USB1 endpoint 12" "Disabled,Enabled"
|
|
bitfld.long 0x44 11. " DMA_EN_TX1_11 ,Threshold enable value for USB1 endpoint 11" "Disabled,Enabled"
|
|
bitfld.long 0x44 10. " DMA_EN_TX1_10 ,Threshold enable value for USB1 endpoint 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 9. " DMA_EN_TX1_9 ,Threshold enable value for USB1 endpoint 9" "Disabled,Enabled"
|
|
bitfld.long 0x44 8. " DMA_EN_TX1_8 ,Threshold enable value for USB1 endpoint 8" "Disabled,Enabled"
|
|
bitfld.long 0x44 7. " DMA_EN_TX1_7 ,Threshold enable value for USB1 endpoint 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 6. " DMA_EN_TX1_6 ,Threshold enable value for USB1 endpoint 6" "Disabled,Enabled"
|
|
bitfld.long 0x44 5. " DMA_EN_TX1_5 ,Threshold enable value for USB1 endpoint 5" "Disabled,Enabled"
|
|
bitfld.long 0x44 4. " DMA_EN_TX1_4 ,Threshold enable value for USB1 endpoint 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 3. " DMA_EN_TX1_3 ,Threshold enable value for USB1 endpoint 3" "Disabled,Enabled"
|
|
bitfld.long 0x44 2. " DMA_EN_TX1_2 ,Threshold enable value for USB1 endpoint 2" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x44 1. " DMA_EN_TX1_1 ,Threshold enable value for USB1 endpoint 1" "Disabled,Enabled"
|
|
tree.end
|
|
tree "FRAME Thresholds"
|
|
group.long 0x200++0x47
|
|
line.long (0x0+0x00) "IRQFRAMETHOLDTX00,IRQ FRAME Threshold TX0 0 Register"
|
|
hexmask.long.byte (0x0+0x00) 24.--31. 1. " FRAME_THRES_TX0_3 ,Threshold value for USB0 endpoint 3"
|
|
hexmask.long.byte (0x0+0x00) 16.--23. 1. " FRAME_THRES_TX0_2 ,Threshold value for USB0 endpoint 2"
|
|
textline " "
|
|
hexmask.long.byte (0x0+0x00) 8.--15. 1. " FRAME_THRES_TX0_1 ,Threshold value for USB0 endpoint 1"
|
|
line.long (0x0+0x04) "IRQFRAMETHOLDTX01,IRQ FRAME Threshold TX0 1 Register"
|
|
hexmask.long.byte (0x0+0x04) 24.--31. 1. " FRAME_THRES_TX0_7 ,Threshold value for USB0 endpoint 7"
|
|
hexmask.long.byte (0x0+0x04) 16.--23. 1. " FRAME_THRES_TX0_6 ,Threshold value for USB0 endpoint 6"
|
|
textline " "
|
|
hexmask.long.byte (0x0+0x04) 8.--15. 1. " FRAME_THRES_TX0_5 ,Threshold value for USB0 endpoint 5"
|
|
hexmask.long.byte (0x0+0x04) 0.--7. 1. " FRAME_THRES_TX0_4 ,Threshold value for USB0 endpoint 4"
|
|
line.long (0x0+0x08) "IRQFRAMETHOLDTX02,IRQ FRAME Threshold TX0 2 Register"
|
|
hexmask.long.byte (0x0+0x08) 24.--31. 1. " FRAME_THRES_TX0_11 ,Threshold value for USB0 endpoint 11"
|
|
hexmask.long.byte (0x0+0x08) 16.--23. 1. " FRAME_THRES_TX0_10 ,Threshold value for USB0 endpoint 10"
|
|
textline " "
|
|
hexmask.long.byte (0x0+0x08) 8.--15. 1. " FRAME_THRES_TX0_9 ,Threshold value for USB0 endpoint 9"
|
|
hexmask.long.byte (0x0+0x08) 0.--7. 1. " FRAME_THRES_TX0_8 ,Threshold value for USB0 endpoint 8"
|
|
line.long (0x0+0x0C) "IRQFRAMETHOLDTX03,IRQ FRAME Threshold TX0 3 Register"
|
|
hexmask.long.byte (0x0+0x0C) 24.--31. 1. " FRAME_THRES_TX0_15 ,Threshold value for USB0 endpoint 15"
|
|
hexmask.long.byte (0x0+0x0C) 16.--23. 1. " FRAME_THRES_TX0_14 ,Threshold value for USB0 endpoint 14"
|
|
textline " "
|
|
hexmask.long.byte (0x0+0x0C) 8.--15. 1. " FRAME_THRES_TX0_13 ,Threshold value for USB0 endpoint 13"
|
|
hexmask.long.byte (0x0+0x0C) 0.--7. 1. " FRAME_THRES_TX0_12 ,Threshold value for USB0 endpoint 12"
|
|
line.long (0x10+0x00) "IRQFRAMETHOLDRX00,IRQ FRAME Threshold RX0 0 Register"
|
|
hexmask.long.byte (0x10+0x00) 24.--31. 1. " FRAME_THRES_RX0_3 ,Threshold value for USB0 endpoint 3"
|
|
hexmask.long.byte (0x10+0x00) 16.--23. 1. " FRAME_THRES_RX0_2 ,Threshold value for USB0 endpoint 2"
|
|
textline " "
|
|
hexmask.long.byte (0x10+0x00) 8.--15. 1. " FRAME_THRES_RX0_1 ,Threshold value for USB0 endpoint 1"
|
|
line.long (0x10+0x04) "IRQFRAMETHOLDRX01,IRQ FRAME Threshold RX0 1 Register"
|
|
hexmask.long.byte (0x10+0x04) 24.--31. 1. " FRAME_THRES_RX0_7 ,Threshold value for USB0 endpoint 7"
|
|
hexmask.long.byte (0x10+0x04) 16.--23. 1. " FRAME_THRES_RX0_6 ,Threshold value for USB0 endpoint 6"
|
|
textline " "
|
|
hexmask.long.byte (0x10+0x04) 8.--15. 1. " FRAME_THRES_RX0_5 ,Threshold value for USB0 endpoint 5"
|
|
hexmask.long.byte (0x10+0x04) 0.--7. 1. " FRAME_THRES_RX0_4 ,Threshold value for USB0 endpoint 4"
|
|
line.long (0x10+0x08) "IRQFRAMETHOLDRX02,IRQ FRAME Threshold RX0 2 Register"
|
|
hexmask.long.byte (0x10+0x08) 24.--31. 1. " FRAME_THRES_RX0_11 ,Threshold value for USB0 endpoint 11"
|
|
hexmask.long.byte (0x10+0x08) 16.--23. 1. " FRAME_THRES_RX0_10 ,Threshold value for USB0 endpoint 10"
|
|
textline " "
|
|
hexmask.long.byte (0x10+0x08) 8.--15. 1. " FRAME_THRES_RX0_9 ,Threshold value for USB0 endpoint 9"
|
|
hexmask.long.byte (0x10+0x08) 0.--7. 1. " FRAME_THRES_RX0_8 ,Threshold value for USB0 endpoint 8"
|
|
line.long (0x10+0x0C) "IRQFRAMETHOLDRX03,IRQ FRAME Threshold RX0 3 Register"
|
|
hexmask.long.byte (0x10+0x0C) 24.--31. 1. " FRAME_THRES_RX0_15 ,Threshold value for USB0 endpoint 15"
|
|
hexmask.long.byte (0x10+0x0C) 16.--23. 1. " FRAME_THRES_RX0_14 ,Threshold value for USB0 endpoint 14"
|
|
textline " "
|
|
hexmask.long.byte (0x10+0x0C) 8.--15. 1. " FRAME_THRES_RX0_13 ,Threshold value for USB0 endpoint 13"
|
|
hexmask.long.byte (0x10+0x0C) 0.--7. 1. " FRAME_THRES_RX0_12 ,Threshold value for USB0 endpoint 12"
|
|
line.long (0x20+0x00) "IRQFRAMETHOLDTX10,IRQ FRAME Threshold TX1 0 Register"
|
|
hexmask.long.byte (0x20+0x00) 24.--31. 1. " FRAME_THRES_TX1_3 ,Threshold value for USB1 endpoint 3"
|
|
hexmask.long.byte (0x20+0x00) 16.--23. 1. " FRAME_THRES_TX1_2 ,Threshold value for USB1 endpoint 2"
|
|
textline " "
|
|
hexmask.long.byte (0x20+0x00) 8.--15. 1. " FRAME_THRES_TX1_1 ,Threshold value for USB1 endpoint 1"
|
|
line.long (0x20+0x04) "IRQFRAMETHOLDTX11,IRQ FRAME Threshold TX1 1 Register"
|
|
hexmask.long.byte (0x20+0x04) 24.--31. 1. " FRAME_THRES_TX1_7 ,Threshold value for USB1 endpoint 7"
|
|
hexmask.long.byte (0x20+0x04) 16.--23. 1. " FRAME_THRES_TX1_6 ,Threshold value for USB1 endpoint 6"
|
|
textline " "
|
|
hexmask.long.byte (0x20+0x04) 8.--15. 1. " FRAME_THRES_TX1_5 ,Threshold value for USB1 endpoint 5"
|
|
hexmask.long.byte (0x20+0x04) 0.--7. 1. " FRAME_THRES_TX1_4 ,Threshold value for USB1 endpoint 4"
|
|
line.long (0x20+0x08) "IRQFRAMETHOLDTX12,IRQ FRAME Threshold TX1 2 Register"
|
|
hexmask.long.byte (0x20+0x08) 24.--31. 1. " FRAME_THRES_TX1_11 ,Threshold value for USB1 endpoint 11"
|
|
hexmask.long.byte (0x20+0x08) 16.--23. 1. " FRAME_THRES_TX1_10 ,Threshold value for USB1 endpoint 10"
|
|
textline " "
|
|
hexmask.long.byte (0x20+0x08) 8.--15. 1. " FRAME_THRES_TX1_9 ,Threshold value for USB1 endpoint 9"
|
|
hexmask.long.byte (0x20+0x08) 0.--7. 1. " FRAME_THRES_TX1_8 ,Threshold value for USB1 endpoint 8"
|
|
line.long (0x20+0x0C) "IRQFRAMETHOLDTX13,IRQ FRAME Threshold TX1 3 Register"
|
|
hexmask.long.byte (0x20+0x0C) 24.--31. 1. " FRAME_THRES_TX1_15 ,Threshold value for USB1 endpoint 15"
|
|
hexmask.long.byte (0x20+0x0C) 16.--23. 1. " FRAME_THRES_TX1_14 ,Threshold value for USB1 endpoint 14"
|
|
textline " "
|
|
hexmask.long.byte (0x20+0x0C) 8.--15. 1. " FRAME_THRES_TX1_13 ,Threshold value for USB1 endpoint 13"
|
|
hexmask.long.byte (0x20+0x0C) 0.--7. 1. " FRAME_THRES_TX1_12 ,Threshold value for USB1 endpoint 12"
|
|
line.long (0x30+0x00) "IRQFRAMETHOLDRX10,IRQ FRAME Threshold RX1 0 Register"
|
|
hexmask.long.byte (0x30+0x00) 24.--31. 1. " FRAME_THRES_RX1_3 ,Threshold value for USB1 endpoint 3"
|
|
hexmask.long.byte (0x30+0x00) 16.--23. 1. " FRAME_THRES_RX1_2 ,Threshold value for USB1 endpoint 2"
|
|
textline " "
|
|
hexmask.long.byte (0x30+0x00) 8.--15. 1. " FRAME_THRES_RX1_1 ,Threshold value for USB1 endpoint 1"
|
|
line.long (0x30+0x04) "IRQFRAMETHOLDRX11,IRQ FRAME Threshold RX1 1 Register"
|
|
hexmask.long.byte (0x30+0x04) 24.--31. 1. " FRAME_THRES_RX1_7 ,Threshold value for USB1 endpoint 7"
|
|
hexmask.long.byte (0x30+0x04) 16.--23. 1. " FRAME_THRES_RX1_6 ,Threshold value for USB1 endpoint 6"
|
|
textline " "
|
|
hexmask.long.byte (0x30+0x04) 8.--15. 1. " FRAME_THRES_RX1_5 ,Threshold value for USB1 endpoint 5"
|
|
hexmask.long.byte (0x30+0x04) 0.--7. 1. " FRAME_THRES_RX1_4 ,Threshold value for USB1 endpoint 4"
|
|
line.long (0x30+0x08) "IRQFRAMETHOLDRX12,IRQ FRAME Threshold RX1 2 Register"
|
|
hexmask.long.byte (0x30+0x08) 24.--31. 1. " FRAME_THRES_RX1_11 ,Threshold value for USB1 endpoint 11"
|
|
hexmask.long.byte (0x30+0x08) 16.--23. 1. " FRAME_THRES_RX1_10 ,Threshold value for USB1 endpoint 10"
|
|
textline " "
|
|
hexmask.long.byte (0x30+0x08) 8.--15. 1. " FRAME_THRES_RX1_9 ,Threshold value for USB1 endpoint 9"
|
|
hexmask.long.byte (0x30+0x08) 0.--7. 1. " FRAME_THRES_RX1_8 ,Threshold value for USB1 endpoint 8"
|
|
line.long (0x30+0x0C) "IRQFRAMETHOLDRX13,IRQ FRAME Threshold RX1 3 Register"
|
|
hexmask.long.byte (0x30+0x0C) 24.--31. 1. " FRAME_THRES_RX1_15 ,Threshold value for USB1 endpoint 15"
|
|
hexmask.long.byte (0x30+0x0C) 16.--23. 1. " FRAME_THRES_RX1_14 ,Threshold value for USB1 endpoint 14"
|
|
textline " "
|
|
hexmask.long.byte (0x30+0x0C) 8.--15. 1. " FRAME_THRES_RX1_13 ,Threshold value for USB1 endpoint 13"
|
|
hexmask.long.byte (0x30+0x0C) 0.--7. 1. " FRAME_THRES_RX1_12 ,Threshold value for USB1 endpoint 12"
|
|
line.long 0x40 "IRQFRAMEENABLE0,IRQ FRAME Enable 0 Register"
|
|
bitfld.long 0x40 31. " FRAME_EN_RX0_15 ,Threshold enable value for USB0 endpoint 15" "Disabled,Enabled"
|
|
sif (!cpuis("AM335*"))
|
|
bitfld.long 0x40 30. " FRAME_EN_RX0_14 ,Threshold enable value for USB0 endpoint 14" "Disabled,Enabled"
|
|
bitfld.long 0x40 29. " FRAME_EN_RX0_13 ,Threshold enable value for USB0 endpoint 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 28. " FRAME_EN_RX0_12 ,Threshold enable value for USB0 endpoint 12" "Disabled,Enabled"
|
|
bitfld.long 0x40 27. " FRAME_EN_RX0_11 ,Threshold enable value for USB0 endpoint 11" "Disabled,Enabled"
|
|
bitfld.long 0x40 26. " FRAME_EN_RX0_10 ,Threshold enable value for USB0 endpoint 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 25. " FRAME_EN_RX0_9 ,Threshold enable value for USB0 endpoint 9" "Disabled,Enabled"
|
|
bitfld.long 0x40 24. " FRAME_EN_RX0_8 ,Threshold enable value for USB0 endpoint 8" "Disabled,Enabled"
|
|
bitfld.long 0x40 23. " FRAME_EN_RX0_7 ,Threshold enable value for USB0 endpoint 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 22. " FRAME_EN_RX0_6 ,Threshold enable value for USB0 endpoint 6" "Disabled,Enabled"
|
|
bitfld.long 0x40 21. " FRAME_EN_RX0_5 ,Threshold enable value for USB0 endpoint 5" "Disabled,Enabled"
|
|
bitfld.long 0x40 20. " FRAME_EN_RX0_4 ,Threshold enable value for USB0 endpoint 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 19. " FRAME_EN_RX0_3 ,Threshold enable value for USB0 endpoint 3" "Disabled,Enabled"
|
|
bitfld.long 0x40 18. " FRAME_EN_RX0_2 ,Threshold enable value for USB0 endpoint 2" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x40 17. " FRAME_EN_RX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 15. " FRAME_EN_TX0_15 ,Threshold enable value for USB0 endpoint 15" "Disabled,Enabled"
|
|
sif (!cpuis("AM335*"))
|
|
bitfld.long 0x40 14. " FRAME_EN_TX0_14 ,Threshold enable value for USB0 endpoint 14" "Disabled,Enabled"
|
|
bitfld.long 0x40 13. " FRAME_EN_TX0_13 ,Threshold enable value for USB0 endpoint 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 12. " FRAME_EN_TX0_12 ,Threshold enable value for USB0 endpoint 12" "Disabled,Enabled"
|
|
bitfld.long 0x40 11. " FRAME_EN_TX0_11 ,Threshold enable value for USB0 endpoint 11" "Disabled,Enabled"
|
|
bitfld.long 0x40 10. " FRAME_EN_TX0_10 ,Threshold enable value for USB0 endpoint 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 9. " FRAME_EN_TX0_9 ,Threshold enable value for USB0 endpoint 9" "Disabled,Enabled"
|
|
bitfld.long 0x40 8. " FRAME_EN_TX0_8 ,Threshold enable value for USB0 endpoint 8" "Disabled,Enabled"
|
|
bitfld.long 0x40 7. " FRAME_EN_TX0_7 ,Threshold enable value for USB0 endpoint 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 6. " FRAME_EN_TX0_6 ,Threshold enable value for USB0 endpoint 6" "Disabled,Enabled"
|
|
bitfld.long 0x40 5. " FRAME_EN_TX0_5 ,Threshold enable value for USB0 endpoint 5" "Disabled,Enabled"
|
|
bitfld.long 0x40 4. " FRAME_EN_TX0_4 ,Threshold enable value for USB0 endpoint 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 3. " FRAME_EN_TX0_3 ,Threshold enable value for USB0 endpoint 3" "Disabled,Enabled"
|
|
bitfld.long 0x40 2. " FRAME_EN_TX0_2 ,Threshold enable value for USB0 endpoint 2" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x40 1. " FRAME_EN_TX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled"
|
|
line.long 0x44 "IRQFRAMEENABLE1,IRQ FRAME Enable 1 Register"
|
|
bitfld.long 0x44 31. " FRAME_EN_RX1_15 ,Threshold enable value for USB1 endpoint 15" "Disabled,Enabled"
|
|
sif (!cpuis("AM335*"))
|
|
bitfld.long 0x44 30. " FRAME_EN_RX1_14 ,Threshold enable value for USB1 endpoint 14" "Disabled,Enabled"
|
|
bitfld.long 0x44 29. " FRAME_EN_RX1_13 ,Threshold enable value for USB1 endpoint 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 28. " FRAME_EN_RX1_12 ,Threshold enable value for USB1 endpoint 12" "Disabled,Enabled"
|
|
bitfld.long 0x44 27. " FRAME_EN_RX1_11 ,Threshold enable value for USB1 endpoint 11" "Disabled,Enabled"
|
|
bitfld.long 0x44 26. " FRAME_EN_RX1_10 ,Threshold enable value for USB1 endpoint 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 25. " FRAME_EN_RX1_9 ,Threshold enable value for USB1 endpoint 9" "Disabled,Enabled"
|
|
bitfld.long 0x44 24. " FRAME_EN_RX1_8 ,Threshold enable value for USB1 endpoint 8" "Disabled,Enabled"
|
|
bitfld.long 0x44 23. " FRAME_EN_RX1_7 ,Threshold enable value for USB1 endpoint 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 22. " FRAME_EN_RX1_6 ,Threshold enable value for USB1 endpoint 6" "Disabled,Enabled"
|
|
bitfld.long 0x44 21. " FRAME_EN_RX1_5 ,Threshold enable value for USB1 endpoint 5" "Disabled,Enabled"
|
|
bitfld.long 0x44 20. " FRAME_EN_RX1_4 ,Threshold enable value for USB1 endpoint 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 19. " FRAME_EN_RX1_3 ,Threshold enable value for USB1 endpoint 3" "Disabled,Enabled"
|
|
bitfld.long 0x44 18. " FRAME_EN_RX1_2 ,Threshold enable value for USB1 endpoint 2" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x44 17. " FRAME_EN_RX1_1 ,Threshold enable value for USB1 endpoint 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 15. " FRAME_EN_TX1_15 ,Threshold enable value for USB1 endpoint 15" "Disabled,Enabled"
|
|
sif (!cpuis("AM335*"))
|
|
bitfld.long 0x44 14. " FRAME_EN_TX1_14 ,Threshold enable value for USB1 endpoint 14" "Disabled,Enabled"
|
|
bitfld.long 0x44 13. " FRAME_EN_TX1_13 ,Threshold enable value for USB1 endpoint 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 12. " FRAME_EN_TX1_12 ,Threshold enable value for USB1 endpoint 12" "Disabled,Enabled"
|
|
bitfld.long 0x44 11. " FRAME_EN_TX1_11 ,Threshold enable value for USB1 endpoint 11" "Disabled,Enabled"
|
|
bitfld.long 0x44 10. " FRAME_EN_TX1_10 ,Threshold enable value for USB1 endpoint 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 9. " FRAME_EN_TX1_9 ,Threshold enable value for USB1 endpoint 9" "Disabled,Enabled"
|
|
bitfld.long 0x44 8. " FRAME_EN_TX1_8 ,Threshold enable value for USB1 endpoint 8" "Disabled,Enabled"
|
|
bitfld.long 0x44 7. " FRAME_EN_TX1_7 ,Threshold enable value for USB1 endpoint 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 6. " FRAME_EN_TX1_6 ,Threshold enable value for USB1 endpoint 6" "Disabled,Enabled"
|
|
bitfld.long 0x44 5. " FRAME_EN_TX1_5 ,Threshold enable value for USB1 endpoint 5" "Disabled,Enabled"
|
|
bitfld.long 0x44 4. " FRAME_EN_TX1_4 ,Threshold enable value for USB1 endpoint 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 3. " FRAME_EN_TX1_3 ,Threshold enable value for USB1 endpoint 3" "Disabled,Enabled"
|
|
bitfld.long 0x44 2. " FRAME_EN_TX1_2 ,Threshold enable value for USB1 endpoint 2" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x44 1. " FRAME_EN_TX1_1 ,Threshold enable value for USB1 endpoint 1" "Disabled,Enabled"
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
tree "USB Controller"
|
|
tree "USB0 Controller Registers"
|
|
base ad:0x47401000
|
|
width 18.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "USB0REV,USB0 Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "Legacy ASP or WTBU,Highlander 0.8,?..."
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USB0CONTROL,USB0 Control Register"
|
|
bitfld.long 0x00 31. " DIS_DEB ,Disable the VBUS debouncer circuit fix" "No,Yes"
|
|
bitfld.long 0x00 30. " DIS_SRP ,Disable the SRP a_valid circuit fix" "No,Yes"
|
|
textline " "
|
|
sif ((cpuis("DM814?DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="AM3874")||(cpu()=="AM3872")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 5. " SRI ,Soft reset isolation" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RNDIS ,Global RNDIS mode enable for all endpoints" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 4. " RNDIS ,Global RNDIS mode enable for all endpoints" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " UINT ,USB non-Highlander interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CLKFACK ,Clock stop fast ack enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Software reset of USB0" "No reset,Reset"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "USB0STATUS,USB0 Status Register"
|
|
bitfld.long 0x00 0. " DRVVBUS ,Current DRVVBUS value" "Low,High"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "USB0IRQMSTAT,USB0 IRQ Merged Status Register"
|
|
bitfld.long 0x00 1. " BANK1 ,Events from IRQ_STATUS_1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BANK0 ,Events from IRQ_STATUS_0" "Not pending,Pending"
|
|
sif (!cpuis("AM335*"))
|
|
group.long 0x24++03
|
|
line.long 0x00 "USB0IRQEOI,USB0 IRQ End of Interrupt Register"
|
|
bitfld.long 0x00 0. " EOI ,End of interrupt" "Low,High"
|
|
endif
|
|
group.long 0x28++0x1F
|
|
line.long 0x00 "USB0IRQSTATRAW0,USB0 IRQ Status Raw 0 Register"
|
|
bitfld.long 0x00 31. " RX_EP15 ,RX EP15 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " RX_EP14 ,RX EP14 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RX_EP13 ,RX EP13 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " RX_EP12 ,RX EP12 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " RX_EP11 ,RX EP11 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " RX_EP10 ,RX EP10 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RX_EP9 ,RX EP9 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " RX_EP8 ,RX EP8 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " RX_EP7 ,RX EP7 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " RX_EP6 ,RX EP6 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RX_EP5 ,RX EP5 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " RX_EP4 ,RX EP4 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RX_EP3 ,RX EP3 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " RX_EP2 ,RX EP2 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RX_EP1 ,RX EP1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " TX_EP15 ,TX EP15 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_EP14 ,TX EP14 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " TX_EP13 ,TX EP13 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_EP12 ,TX EP12 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " TX_EP11 ,TX EP11 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TX_EP10 ,TX EP10 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " TX_EP9 ,TX EP9 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TX_EP8 ,TX EP8 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " TX_EP7 ,TX EP7 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TX_EP6 ,TX EP6 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " TX_EP5 ,TX EP5 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TX_EP4 ,TX EP4 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " TX_EP3 ,TX EP3 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX_EP2 ,TX EP2 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " TX_EP1 ,TX EP1 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TX_EP0 ,TX EP0 interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "USB0IRQSTATRAW1,USB0 IRQ Status Raw 1 Register"
|
|
bitfld.long 0x04 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 9. " USB[9] , Mentor controller USB_INT generic interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 8. " USB[8] ,DRVVBUS level change interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 7. " USB[7] ,VBUS < VBUS valid threshold interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " USB[6] ,SRP detected interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 5. " USB[5] ,Device disconnected interrupt raw status (host mode)" "Not pending,Pending"
|
|
bitfld.long 0x04 4. " USB[4] ,Device connected interrupt raw status (host mode)" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 3. " USB[3] ,SOF started interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " USB[2] ,Reset signaling/Babble detected interrupt raw status (peripheral/host mode)" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 1. " USB[1] ,Resume signaling interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " USB[0] ,Suspend signaling interrupt raw status" "Not pending,Pending"
|
|
line.long 0x08 "USB0IRQSTAT0,USB0 IRQ Status 0 Register"
|
|
eventfld.long 0x08 31. " RX_EP15 ,RX EP15 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " RX_EP14 ,RX EP14 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 29. " RX_EP13 ,RX EP13 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 28. " RX_EP12 ,RX EP12 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 27. " RX_EP11 ,RX EP11 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 26. " RX_EP10 ,RX EP10 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 25. " RX_EP9 ,RX EP9 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 24. " RX_EP8 ,RX EP8 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 23. " RX_EP7 ,RX EP7 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 22. " RX_EP6 ,RX EP6 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 21. " RX_EP5 ,RX EP5 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 20. " RX_EP4 ,RX EP4 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 19. " RX_EP3 ,RX EP3 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 18. " RX_EP2 ,RX EP2 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 17. " RX_EP1 ,RX EP1 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 15. " TX_EP15 ,TX EP15 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 14. " TX_EP14 ,TX EP14 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 13. " TX_EP13 ,TX EP13 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 12. " TX_EP12 ,TX EP12 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " TX_EP11 ,TX EP11 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " TX_EP10 ,TX EP10 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " TX_EP9 ,TX EP9 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " TX_EP8 ,TX EP8 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " TX_EP7 ,TX EP7 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 6. " TX_EP6 ,TX EP6 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " TX_EP5 ,TX EP5 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " TX_EP4 ,TX EP4 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " TX_EP3 ,TX EP3 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " TX_EP2 ,TX EP2 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " TX_EP1 ,TX EP1 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 0. " TX_EP0 ,TX EP0 interrupt status" "Not pending,Pending"
|
|
line.long 0x0C "USB0IRQSTAT1,USB0 IRQ Status 1 Register"
|
|
eventfld.long 0x0C 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 9. " USB[9] , Mentor controller USB_INT generic interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 8. " USB[8] ,DRVVBUS level change interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " USB[7] ,VBUS < VBUS valid threshold interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 6. " USB[6] ,SRP detected interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 5. " USB[5] ,Device disconnected interrupt status (host mode)" "Not pending,Pending"
|
|
eventfld.long 0x0C 4. " USB[4] ,Device connected interrupt status (host mode)" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 3. " USB[3] ,SOF started interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 2. " USB[2] ,Reset signaling/Babble detected interrupt status (peripheral/host mode)" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " USB[1] ,Resume signaling interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 0. " USB[0] ,Suspend signaling interrupt status" "Not pending,Pending"
|
|
line.long 0x10 "USB0IRQENABLESET0,USB0 IRQ Enable Set 0 Register"
|
|
bitfld.long 0x10 31. " RX_EP15 ,RX EP15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " RX_EP14 ,RX EP14 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " RX_EP13 ,RX EP13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " RX_EP12 ,RX EP12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " RX_EP11 ,RX EP11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " RX_EP10 ,RX EP10 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " RX_EP9 ,RX EP9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " RX_EP8 ,RX EP8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " RX_EP7 ,RX EP7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " RX_EP6 ,RX EP6 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " RX_EP5 ,RX EP5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " RX_EP4 ,RX EP4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " RX_EP3 ,RX EP3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " RX_EP2 ,RX EP2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " RX_EP1 ,RX EP1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " TX_EP15 ,TX EP15 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 14. " TX_EP14 ,TX EP14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " TX_EP13 ,TX EP13 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 12. " TX_EP12 ,TX EP12 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " TX_EP11 ,TX EP11 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 10. " TX_EP10 ,TX EP10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " TX_EP9 ,TX EP9 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " TX_EP8 ,TX EP8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 7. " TX_EP7 ,TX EP7 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 6. " TX_EP6 ,TX EP6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " TX_EP5 ,TX EP5 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " TX_EP4 ,TX EP4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " TX_EP3 ,TX EP3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " TX_EP2 ,TX EP2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " TX_EP1 ,TX EP1 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " TX_EP0 ,TX EP0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x14 "USB0IRQENABLESET1,USB0 IRQ Enable Set 1 Register"
|
|
bitfld.long 0x14 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " USB[9] , Mentor controller USB_INT generic interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " USB[8] ,DRVVBUS level change interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " USB[7] ,VBUS < VBUS valid threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " USB[6] ,SRP detected interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " USB[5] ,Device disconnected interrupt enable status (host mode)" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " USB[4] ,Device connected interrupt enable status (host mode)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " USB[3] ,SOF started interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " USB[2] ,Reset signaling/Babble detected interrupt enable status (peripheral/host mode)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " USB[1] ,Resume signaling interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " USB[0] ,Suspend signaling interrupt enable" "Disabled,Enabled"
|
|
line.long 0x18 "USB0IRQENABLECLR0,USB0 IRQ Enable Clear 0 Register"
|
|
eventfld.long 0x18 31. " RX_EP15 ,RX EP15 iinterrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 30. " RX_EP14 ,RX EP14 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 29. " RX_EP13 ,RX EP13 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 28. " RX_EP12 ,RX EP12 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 27. " RX_EP11 ,RX EP11 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 26. " RX_EP10 ,RX EP10 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 25. " RX_EP9 ,RX EP9 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 24. " RX_EP8 ,RX EP8 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 23. " RX_EP7 ,RX EP7 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 22. " RX_EP6 ,RX EP6 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 21. " RX_EP5 ,RX EP5 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 20. " RX_EP4 ,RX EP4 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 19. " RX_EP3 ,RX EP3 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 18. " RX_EP2 ,RX EP2 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 17. " RX_EP1 ,RX EP1 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 15. " TX_EP15 ,TX EP15 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 14. " TX_EP14 ,TX EP14 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 13. " TX_EP13 ,TX EP13 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 12. " TX_EP12 ,TX EP12 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 11. " TX_EP11 ,TX EP11 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 10. " TX_EP10 ,TX EP10 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 9. " TX_EP9 ,TX EP9 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 8. " TX_EP8 ,TX EP8 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 7. " TX_EP7 ,TX EP7 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 6. " TX_EP6 ,TX EP6 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 5. " TX_EP5 ,TX EP5 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 4. " TX_EP4 ,TX EP4 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 3. " TX_EP3 ,TX EP3 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 2. " TX_EP2 ,TX EP2 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 1. " TX_EP1 ,TX EP1 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 0. " TX_EP0 ,TX EP0 interrupt disable" "Disabled,Enabled"
|
|
line.long 0x1C "USB0IRQENABLECLR1,USB0 IRQ Enable Clear 1 Register"
|
|
eventfld.long 0x1C 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 9. " USB[9] , Mentor controller USB_INT generic interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 8. " USB[8] ,DRVVBUS level change interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 7. " USB[7] ,VBUS < VBUS valid threshold interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 6. " USB[6] ,SRP detected interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 5. " USB[5] ,Device disconnected interrupt disable (host mode)" "Disabled,Enabled"
|
|
eventfld.long 0x1C 4. " USB[4] ,Device connected interrupt disable (host mode)" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 3. " USB[3] ,SOF started interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 2. " USB[2] ,Reset signaling/Babble detected interrupt disable (peripheral/host mode)" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 1. " USB[1] ,Resume signaling interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 0. " USB[0] ,Suspend signaling interrupt disable" "Disabled,Enabled"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "USB0TXMODE,USB0 Tx Mode Register"
|
|
bitfld.long 0x00 28.--29. " TX15_MODE ,Endpoint 15 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 26.--27. " TX14_MODE ,Endpoint 14 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " TX13_MODE ,Endpoint 13 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 22.--23. " TX12_MODE ,Endpoint 12 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " TX11_MODE ,Endpoint 11 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 18.--19. " TX10_MODE ,Endpoint 10 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " TX9_MODE ,Endpoint 9 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 14.--15. " TX8_MODE ,Endpoint 8 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX7_MODE ,Endpoint 7 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 10.--11. " TX6_MODE ,Endpoint 6 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX5_MODE ,Endpoint 5 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 6.--7. " TX4_MODE ,Endpoint 4 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TX3_MODE ,Endpoint 3 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 2.--3. " TX2_MODE ,Endpoint 2 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TX1_MODE ,Endpoint 1 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
line.long 0x04 "USB0RXMODE,USB0 Rx Mode Register"
|
|
bitfld.long 0x04 28.--29. " RX15_MODE ,Endpoint 15 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 26.--27. " RX14_MODE ,Endpoint 14 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 24.--25. " RX13_MODE ,Endpoint 13 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 22.--23. " RX12_MODE ,Endpoint 12 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 20.--21. " RX11_MODE ,Endpoint 11 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 18.--19. " RX10_MODE ,Endpoint 10 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " RX9_MODE ,Endpoint 9 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 14.--15. " RX8_MODE ,Endpoint 8 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX7_MODE ,Endpoint 7 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 10.--11. " RX6_MODE ,Endpoint 6 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " RX5_MODE ,Endpoint 5 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 6.--7. " RX4_MODE ,Endpoint 4 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RX3_MODE ,Endpoint 3 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 2.--3. " RX2_MODE ,Endpoint 2 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " RX1_MODE ,Endpoint 1 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
group.long 0x80++0x3B
|
|
line.long 0x0 "USB0GENRNDISEP1,USB0 Generic RNDIS EP1 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP1_SIZE ,Generic RNDIS packeet size 1"
|
|
line.long 0x4 "USB0GENRNDISEP2,USB0 Generic RNDIS EP2 Size Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. " EP2_SIZE ,Generic RNDIS packeet size 2"
|
|
line.long 0x8 "USB0GENRNDISEP3,USB0 Generic RNDIS EP3 Size Register"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. " EP3_SIZE ,Generic RNDIS packeet size 3"
|
|
line.long 0xC "USB0GENRNDISEP4,USB0 Generic RNDIS EP4 Size Register"
|
|
hexmask.long.tbyte 0xC 0.--16. 1. " EP4_SIZE ,Generic RNDIS packeet size 4"
|
|
line.long 0x10 "USB0GENRNDISEP5,USB0 Generic RNDIS EP5 Size Register"
|
|
hexmask.long.tbyte 0x10 0.--16. 1. " EP5_SIZE ,Generic RNDIS packeet size 5"
|
|
line.long 0x14 "USB0GENRNDISEP6,USB0 Generic RNDIS EP6 Size Register"
|
|
hexmask.long.tbyte 0x14 0.--16. 1. " EP6_SIZE ,Generic RNDIS packeet size 6"
|
|
line.long 0x18 "USB0GENRNDISEP7,USB0 Generic RNDIS EP7 Size Register"
|
|
hexmask.long.tbyte 0x18 0.--16. 1. " EP7_SIZE ,Generic RNDIS packeet size 7"
|
|
line.long 0x1C "USB0GENRNDISEP8,USB0 Generic RNDIS EP8 Size Register"
|
|
hexmask.long.tbyte 0x1C 0.--16. 1. " EP8_SIZE ,Generic RNDIS packeet size 8"
|
|
line.long 0x20 "USB0GENRNDISEP9,USB0 Generic RNDIS EP9 Size Register"
|
|
hexmask.long.tbyte 0x20 0.--16. 1. " EP9_SIZE ,Generic RNDIS packeet size 9"
|
|
line.long 0x24 "USB0GENRNDISEP10,USB0 Generic RNDIS EP10 Size Register"
|
|
hexmask.long.tbyte 0x24 0.--16. 1. " EP10_SIZE ,Generic RNDIS packeet size 10"
|
|
line.long 0x28 "USB0GENRNDISEP11,USB0 Generic RNDIS EP11 Size Register"
|
|
hexmask.long.tbyte 0x28 0.--16. 1. " EP11_SIZE ,Generic RNDIS packeet size 11"
|
|
line.long 0x2C "USB0GENRNDISEP12,USB0 Generic RNDIS EP12 Size Register"
|
|
hexmask.long.tbyte 0x2C 0.--16. 1. " EP12_SIZE ,Generic RNDIS packeet size 12"
|
|
line.long 0x30 "USB0GENRNDISEP13,USB0 Generic RNDIS EP13 Size Register"
|
|
hexmask.long.tbyte 0x30 0.--16. 1. " EP13_SIZE ,Generic RNDIS packeet size 13"
|
|
line.long 0x34 "USB0GENRNDISEP14,USB0 Generic RNDIS EP14 Size Register"
|
|
hexmask.long.tbyte 0x34 0.--16. 1. " EP14_SIZE ,Generic RNDIS packeet size 14"
|
|
line.long 0x38 "USB0GENRNDISEP15,USB0 Generic RNDIS EP15 Size Register"
|
|
hexmask.long.tbyte 0x38 0.--16. 1. " EP15_SIZE ,Generic RNDIS packeet size 15"
|
|
group.long 0xD0++0xB
|
|
line.long 0x00 "USB0AUTOREQ,USB0 Auto Req Register"
|
|
bitfld.long 0x00 28.--29. " RX15_AUTOREQ ,RX endpoint 15 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 26.--27. " RX14_AUTOREQ ,RX endpoint 14 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX13_AUTOREQ ,RX endpoint 13 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 22.--23. " RX12_AUTOREQ ,RX endpoint 12 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " RX11_AUTOREQ ,RX endpoint 11 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 18.--19. " RX10_AUTOREQ ,RX endpoint 10 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " RX9_AUTOREQ ,RX endpoint 9 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 14.--15. " RX8_AUTOREQ ,RX endpoint 8 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX7_AUTOREQ ,RX endpoint 7 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 10.--11. " RX6_AUTOREQ ,RX endpoint 6 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RX5_AUTOREQ ,RX endpoint 5 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 6.--7. " RX4_AUTOREQ ,RX endpoint 4 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " RX3_AUTOREQ ,RX endpoint 3 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 2.--3. " RX2_AUTOREQ ,RX endpoint 2 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " RX1_AUTOREQ ,RX endpoint 1 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
line.long 0x04 "USB0SRPFIXTIME,USB0 SRP Fix Time Register"
|
|
line.long 0x08 "USB0TDOWN,USB0 Teardown Register"
|
|
bitfld.long 0x08 31. " TX_TDOWN15 ,Transmit endpoint 15 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " TX_TDOWN14 ,Transmit endpoint 14 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " TX_TDOWN13 ,Transmit endpoint 13 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 28. " TX_TDOWN12 ,Transmit endpoint 12 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " TX_TDOWN11 ,Transmit endpoint 11 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " TX_TDOWN10 ,Transmit endpoint 10 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " TX_TDOWN9 ,Transmit endpoint 9 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " TX_TDOWN8 ,Transmit endpoint 8 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " TX_TDOWN7 ,Transmit endpoint 7 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " TX_TDOWN6 ,Transmit endpoint 6 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " TX_TDOWN5 ,Transmit endpoint 5 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " TX_TDOWN4 ,Transmit endpoint 4 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " TX_TDOWN3 ,Transmit endpoint 3 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " TX_TDOWN2 ,Transmit endpoint 2 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " TX_TDOWN1 ,Transmit endpoint 1 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " RX_TDOWN15 ,Receive endpoint 15 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " RX_TDOWN14 ,Receive endpoint 14 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " RX_TDOWN13 ,Receive endpoint 13 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " RX_TDOWN12 ,Receive endpoint 12 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " RX_TDOWN11 ,Receive endpoint 11 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " RX_TDOWN10 ,Receive endpoint 10 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " RX_TDOWN9 ,Receive endpoint 9 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RX_TDOWN8 ,Receive endpoint 8 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " RX_TDOWN7 ,Receive endpoint 7 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " RX_TDOWN6 ,Receive endpoint 6 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " RX_TDOWN5 ,Receive endpoint 5 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RX_TDOWN4 ,Receive endpoint 4 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RX_TDOWN3 ,Receive endpoint 3 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RX_TDOWN2 ,Receive endpoint 2 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RX_TDOWN1 ,Receive endpoint 1 teardown" "Disabled,Enabled"
|
|
sif cpuis("DM814?DSP")
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "USB0THRESXDMA,USB0 Threshold XDMA Idle Register"
|
|
hexmask.long.byte 0x00 0.--7. 0x1 " THRES_XDMA_IDLE ,Threshold XDMA Idle cycle parameter"
|
|
endif
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "USB0UTMI,USB0 PHY UTMI Register"
|
|
bitfld.long 0x00 23. " TXBITSTUFFEN ,Input for signal txbitstuffen" "Low,High"
|
|
sif !cpuis("DM814?DSP")
|
|
bitfld.long 0x00 22. " TXBITSTUFFENH ,Input for signal txbitstuffenh" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " OTGDISABLE ,Input for signal otgdisable" "Low,High"
|
|
bitfld.long 0x00 20. " VBUSVLDEXTSEL ,Input for signal vbusvldextsel" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " VBUSVLDEXT ,Input for signal vbusvldext" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 18. " TXENABLEN ,Input for signal txenablen" "Low,High"
|
|
sif !cpuis("DM814?DSP")
|
|
textline " "
|
|
bitfld.long 0x00 17. " FSXCVROWNER ,Input for signal fsxcvrowner" "Low,High"
|
|
bitfld.long 0x00 16. " TXVALIDH ,Input for signal txvalidh" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAINH ,Input for signal datainh"
|
|
bitfld.long 0x00 2. " WORDINTERFACE ,Input for signal wordinterface" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSDATAEXT ,Input for signal fsdataext" "Low,High"
|
|
bitfld.long 0x00 0. " FSSE0EXT ,Input for signal fsse0ext" "Low,High"
|
|
endif
|
|
line.long 0x04 "USB0UTMILB,USB0 MGC UTMI Loopback Register"
|
|
sif (cpuis("DM814?DSP")||cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x04 28. " SUSPENDM ,LB test value for suspendm" "Low,High"
|
|
rbitfld.long 0x04 26.--27. " OPMODE ,LB test value for opmode" "0,1,2,3"
|
|
textline " "
|
|
rbitfld.long 0x04 25. " TXVALID ,LB test value for txvalid" "Low,High"
|
|
rbitfld.long 0x04 23.--24. " XCVRSEL ,LB test value for xcvrsel" "0,1,2,3"
|
|
textline " "
|
|
rbitfld.long 0x04 22. " TERMSEL ,LB test value for termsel" "Low,High"
|
|
rbitfld.long 0x04 21. " DRVVBUS ,LB test value for drvvbus" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 20. " CHRGVBUS ,LB test value for chrgvbus" "Low,High"
|
|
rbitfld.long 0x04 19. " DISCHRGVBUS ,LB test value for dischrgvbus" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 18. " DPPULLDOWN ,LB test value for dppulldown" "Low,High"
|
|
rbitfld.long 0x04 17. " DMPULLDOWN ,LB test value for dmpulldown" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 16. " IDPULLUP ,LB test value for idpullup" "Low,High"
|
|
else
|
|
bitfld.long 0x04 28. " SUSPENDM ,LB test value for suspendm" "Low,High"
|
|
bitfld.long 0x04 26.--27. " OPMODE ,LB test value for opmode" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 25. " TXVALID ,LB test value for txvalid" "Low,High"
|
|
bitfld.long 0x04 23.--24. " XCVRSEL ,LB test value for xcvrsel" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 22. " TERMSEL ,LB test value for termsel" "Low,High"
|
|
bitfld.long 0x04 21. " DRVVBUS ,LB test value for drvvbus" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CHRGVBUS ,LB test value for chrgvbus" "Low,High"
|
|
bitfld.long 0x04 19. " DISCHRGVBUS ,LB test value for dischrgvbus" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 18. " DPPULLDOWN ,LB test value for dppulldown" "Low,High"
|
|
bitfld.long 0x04 17. " DMPULLDOWN ,LB test value for dmpulldown" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 16. " IDPULLUP ,LB test value for idpullup" "Low,High"
|
|
endif
|
|
bitfld.long 0x04 11. " IDDIG ,LB test value for iddig" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HOSTDISCON ,LB test value for hostdiscon" "Low,High"
|
|
bitfld.long 0x04 9. " SESSEND ,LB test value for sessend" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 8. " AVALID ,LB test value for avalid" "Low,High"
|
|
bitfld.long 0x04 7. " VBUSVALID ,LB test value for vbusvalid" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 6. " RXERROR ,LB test value for rxerror" "Low,High"
|
|
bitfld.long 0x04 2.--3. " LINESTATE ,LB test value for linestate" "0,1,2,3"
|
|
line.long 0x08 "USB0MODE,USB0 Mode Register"
|
|
bitfld.long 0x08 8. " IDDIG ,MGC input value for IDDIG" "A-type,B-type"
|
|
textline " "
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x08 7. " IDDIG_MUX ,Multiplexer control for IDDIG signal going to the controller" "From PHY,From bit 8 (IDDIG)"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 1. " PHY_TEST ,PHY test" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " LOOPBACK ,Loopback test mode" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "USB1 Controller Registers"
|
|
base ad:0x47401800
|
|
width 18.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "USB1REV,USB1 Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "Legacy ASP or WTBU,Highlander 0.8,?..."
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USB1CONTROL,USB1 Control Register"
|
|
bitfld.long 0x00 31. " DIS_DEB ,Disable the VBUS debouncer circuit fix" "No,Yes"
|
|
bitfld.long 0x00 30. " DIS_SRP ,Disable the SRP a_valid circuit fix" "No,Yes"
|
|
textline " "
|
|
sif ((cpuis("DM814?DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="AM3874")||(cpu()=="AM3872")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 5. " SRI ,Soft reset isolation" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RNDIS ,Global RNDIS mode enable for all endpoints" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 4. " RNDIS ,Global RNDIS mode enable for all endpoints" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " UINT ,USB non-Highlander interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CLKFACK ,Clock stop fast ack enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Software reset of USB1" "No reset,Reset"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "USB1STATUS,USB1 Status Register"
|
|
bitfld.long 0x00 0. " DRVVBUS ,Current DRVVBUS value" "Low,High"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "USB1IRQMSTAT,USB1 IRQ Merged Status Register"
|
|
bitfld.long 0x00 1. " BANK1 ,Events from IRQ_STATUS_1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BANK0 ,Events from IRQ_STATUS_0" "Not pending,Pending"
|
|
sif (!cpuis("AM335*"))
|
|
group.long 0x24++03
|
|
line.long 0x00 "USB1IRQEOI,USB1 IRQ End of Interrupt Register"
|
|
bitfld.long 0x00 0. " EOI ,End of interrupt" "Low,High"
|
|
endif
|
|
group.long 0x28++0x1F
|
|
line.long 0x00 "USB1IRQSTATRAW0,USB1 IRQ Status Raw 0 Register"
|
|
bitfld.long 0x00 31. " RX_EP15 ,RX EP15 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " RX_EP14 ,RX EP14 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RX_EP13 ,RX EP13 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " RX_EP12 ,RX EP12 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " RX_EP11 ,RX EP11 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " RX_EP10 ,RX EP10 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RX_EP9 ,RX EP9 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " RX_EP8 ,RX EP8 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " RX_EP7 ,RX EP7 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " RX_EP6 ,RX EP6 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RX_EP5 ,RX EP5 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " RX_EP4 ,RX EP4 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RX_EP3 ,RX EP3 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " RX_EP2 ,RX EP2 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RX_EP1 ,RX EP1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " TX_EP15 ,TX EP15 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_EP14 ,TX EP14 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " TX_EP13 ,TX EP13 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_EP12 ,TX EP12 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " TX_EP11 ,TX EP11 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TX_EP10 ,TX EP10 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " TX_EP9 ,TX EP9 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TX_EP8 ,TX EP8 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " TX_EP7 ,TX EP7 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TX_EP6 ,TX EP6 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " TX_EP5 ,TX EP5 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TX_EP4 ,TX EP4 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " TX_EP3 ,TX EP3 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX_EP2 ,TX EP2 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " TX_EP1 ,TX EP1 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TX_EP0 ,TX EP0 interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "USB1IRQSTATRAW1,USB1 IRQ Status Raw 1 Register"
|
|
bitfld.long 0x04 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 9. " USB[9] , Mentor controller USB_INT generic interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 8. " USB[8] ,DRVVBUS level change interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 7. " USB[7] ,VBUS < VBUS valid threshold interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " USB[6] ,SRP detected interrupt raw status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 5. " USB[5] ,Device disconnected interrupt raw status (host mode)" "Not pending,Pending"
|
|
bitfld.long 0x04 4. " USB[4] ,Device connected interrupt raw status (host mode)" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 3. " USB[3] ,SOF started interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " USB[2] ,Reset signaling/Babble detected interrupt raw status (peripheral/host mode)" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 1. " USB[1] ,Resume signaling interrupt raw status" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " USB[0] ,Suspend signaling interrupt raw status" "Not pending,Pending"
|
|
line.long 0x08 "USB1IRQSTAT0,USB1 IRQ Status 0 Register"
|
|
eventfld.long 0x08 31. " RX_EP15 ,RX EP15 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " RX_EP14 ,RX EP14 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 29. " RX_EP13 ,RX EP13 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 28. " RX_EP12 ,RX EP12 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 27. " RX_EP11 ,RX EP11 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 26. " RX_EP10 ,RX EP10 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 25. " RX_EP9 ,RX EP9 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 24. " RX_EP8 ,RX EP8 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 23. " RX_EP7 ,RX EP7 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 22. " RX_EP6 ,RX EP6 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 21. " RX_EP5 ,RX EP5 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 20. " RX_EP4 ,RX EP4 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 19. " RX_EP3 ,RX EP3 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 18. " RX_EP2 ,RX EP2 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 17. " RX_EP1 ,RX EP1 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 15. " TX_EP15 ,TX EP15 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 14. " TX_EP14 ,TX EP14 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 13. " TX_EP13 ,TX EP13 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 12. " TX_EP12 ,TX EP12 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " TX_EP11 ,TX EP11 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " TX_EP10 ,TX EP10 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " TX_EP9 ,TX EP9 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " TX_EP8 ,TX EP8 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " TX_EP7 ,TX EP7 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 6. " TX_EP6 ,TX EP6 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " TX_EP5 ,TX EP5 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " TX_EP4 ,TX EP4 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " TX_EP3 ,TX EP3 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " TX_EP2 ,TX EP2 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " TX_EP1 ,TX EP1 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 0. " TX_EP0 ,TX EP0 interrupt status" "Not pending,Pending"
|
|
line.long 0x0C "USB1IRQSTAT1,USB1 IRQ Status 1 Register"
|
|
eventfld.long 0x0C 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 9. " USB[9] , Mentor controller USB_INT generic interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 8. " USB[8] ,DRVVBUS level change interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " USB[7] ,VBUS < VBUS valid threshold interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 6. " USB[6] ,SRP detected interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 5. " USB[5] ,Device disconnected interrupt status (host mode)" "Not pending,Pending"
|
|
eventfld.long 0x0C 4. " USB[4] ,Device connected interrupt status (host mode)" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 3. " USB[3] ,SOF started interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 2. " USB[2] ,Reset signaling/Babble detected interrupt status (peripheral/host mode)" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " USB[1] ,Resume signaling interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x0C 0. " USB[0] ,Suspend signaling interrupt status" "Not pending,Pending"
|
|
line.long 0x10 "USB1IRQENABLESET0,USB1 IRQ Enable Set 0 Register"
|
|
bitfld.long 0x10 31. " RX_EP15 ,RX EP15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " RX_EP14 ,RX EP14 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " RX_EP13 ,RX EP13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " RX_EP12 ,RX EP12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " RX_EP11 ,RX EP11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " RX_EP10 ,RX EP10 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " RX_EP9 ,RX EP9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " RX_EP8 ,RX EP8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " RX_EP7 ,RX EP7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " RX_EP6 ,RX EP6 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " RX_EP5 ,RX EP5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " RX_EP4 ,RX EP4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " RX_EP3 ,RX EP3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " RX_EP2 ,RX EP2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " RX_EP1 ,RX EP1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " TX_EP15 ,TX EP15 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 14. " TX_EP14 ,TX EP14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " TX_EP13 ,TX EP13 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 12. " TX_EP12 ,TX EP12 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " TX_EP11 ,TX EP11 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 10. " TX_EP10 ,TX EP10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " TX_EP9 ,TX EP9 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " TX_EP8 ,TX EP8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 7. " TX_EP7 ,TX EP7 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 6. " TX_EP6 ,TX EP6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " TX_EP5 ,TX EP5 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " TX_EP4 ,TX EP4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " TX_EP3 ,TX EP3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " TX_EP2 ,TX EP2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " TX_EP1 ,TX EP1 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " TX_EP0 ,TX EP0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x14 "USB1IRQENABLESET1,USB1 IRQ Enable Set 1 Register"
|
|
bitfld.long 0x14 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " USB[9] , Mentor controller USB_INT generic interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " USB[8] ,DRVVBUS level change interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " USB[7] ,VBUS < VBUS valid threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " USB[6] ,SRP detected interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " USB[5] ,Device disconnected interrupt enable status (host mode)" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " USB[4] ,Device connected interrupt enable status (host mode)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " USB[3] ,SOF started interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " USB[2] ,Reset signaling/Babble detected interrupt enable status (peripheral/host mode)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " USB[1] ,Resume signaling interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " USB[0] ,Suspend signaling interrupt enable" "Disabled,Enabled"
|
|
line.long 0x18 "USB1IRQENABLECLR0,USB1 IRQ Enable Clear 0 Register"
|
|
eventfld.long 0x18 31. " RX_EP15 ,RX EP15 iinterrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 30. " RX_EP14 ,RX EP14 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 29. " RX_EP13 ,RX EP13 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 28. " RX_EP12 ,RX EP12 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 27. " RX_EP11 ,RX EP11 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 26. " RX_EP10 ,RX EP10 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 25. " RX_EP9 ,RX EP9 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 24. " RX_EP8 ,RX EP8 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 23. " RX_EP7 ,RX EP7 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 22. " RX_EP6 ,RX EP6 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 21. " RX_EP5 ,RX EP5 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 20. " RX_EP4 ,RX EP4 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 19. " RX_EP3 ,RX EP3 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 18. " RX_EP2 ,RX EP2 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 17. " RX_EP1 ,RX EP1 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 15. " TX_EP15 ,TX EP15 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 14. " TX_EP14 ,TX EP14 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 13. " TX_EP13 ,TX EP13 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 12. " TX_EP12 ,TX EP12 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 11. " TX_EP11 ,TX EP11 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 10. " TX_EP10 ,TX EP10 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 9. " TX_EP9 ,TX EP9 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 8. " TX_EP8 ,TX EP8 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 7. " TX_EP7 ,TX EP7 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 6. " TX_EP6 ,TX EP6 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 5. " TX_EP5 ,TX EP5 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 4. " TX_EP4 ,TX EP4 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 3. " TX_EP3 ,TX EP3 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 2. " TX_EP2 ,TX EP2 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x18 1. " TX_EP1 ,TX EP1 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 0. " TX_EP0 ,TX EP0 interrupt disable" "Disabled,Enabled"
|
|
line.long 0x1C "USB1IRQENABLECLR1,USB1 IRQ Enable Clear 1 Register"
|
|
eventfld.long 0x1C 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 9. " USB[9] , Mentor controller USB_INT generic interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 8. " USB[8] ,DRVVBUS level change interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 7. " USB[7] ,VBUS < VBUS valid threshold interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 6. " USB[6] ,SRP detected interrupt disable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 5. " USB[5] ,Device disconnected interrupt disable (host mode)" "Disabled,Enabled"
|
|
eventfld.long 0x1C 4. " USB[4] ,Device connected interrupt disable (host mode)" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 3. " USB[3] ,SOF started interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 2. " USB[2] ,Reset signaling/Babble detected interrupt disable (peripheral/host mode)" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 1. " USB[1] ,Resume signaling interrupt disable" "Disabled,Enabled"
|
|
eventfld.long 0x1C 0. " USB[0] ,Suspend signaling interrupt disable" "Disabled,Enabled"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "USB1TXMODE,USB1 Tx Mode Register"
|
|
bitfld.long 0x00 28.--29. " TX15_MODE ,Endpoint 15 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 26.--27. " TX14_MODE ,Endpoint 14 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " TX13_MODE ,Endpoint 13 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 22.--23. " TX12_MODE ,Endpoint 12 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " TX11_MODE ,Endpoint 11 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 18.--19. " TX10_MODE ,Endpoint 10 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " TX9_MODE ,Endpoint 9 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 14.--15. " TX8_MODE ,Endpoint 8 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX7_MODE ,Endpoint 7 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 10.--11. " TX6_MODE ,Endpoint 6 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX5_MODE ,Endpoint 5 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 6.--7. " TX4_MODE ,Endpoint 4 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TX3_MODE ,Endpoint 3 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 2.--3. " TX2_MODE ,Endpoint 2 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TX1_MODE ,Endpoint 1 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
line.long 0x04 "USB1RXMODE,USB1 Rx Mode Register"
|
|
bitfld.long 0x04 28.--29. " RX15_MODE ,Endpoint 15 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 26.--27. " RX14_MODE ,Endpoint 14 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 24.--25. " RX13_MODE ,Endpoint 13 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 22.--23. " RX12_MODE ,Endpoint 12 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 20.--21. " RX11_MODE ,Endpoint 11 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 18.--19. " RX10_MODE ,Endpoint 10 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " RX9_MODE ,Endpoint 9 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 14.--15. " RX8_MODE ,Endpoint 8 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX7_MODE ,Endpoint 7 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 10.--11. " RX6_MODE ,Endpoint 6 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " RX5_MODE ,Endpoint 5 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 6.--7. " RX4_MODE ,Endpoint 4 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RX3_MODE ,Endpoint 3 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 2.--3. " RX2_MODE ,Endpoint 2 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " RX1_MODE ,Endpoint 1 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
group.long 0x80++0x3B
|
|
line.long 0x0 "USB1GENRNDISEP1,USB1 Generic RNDIS EP1 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP1_SIZE ,Generic RNDIS packeet size 1"
|
|
line.long 0x4 "USB1GENRNDISEP2,USB1 Generic RNDIS EP2 Size Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. " EP2_SIZE ,Generic RNDIS packeet size 2"
|
|
line.long 0x8 "USB1GENRNDISEP3,USB1 Generic RNDIS EP3 Size Register"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. " EP3_SIZE ,Generic RNDIS packeet size 3"
|
|
line.long 0xC "USB1GENRNDISEP4,USB1 Generic RNDIS EP4 Size Register"
|
|
hexmask.long.tbyte 0xC 0.--16. 1. " EP4_SIZE ,Generic RNDIS packeet size 4"
|
|
line.long 0x10 "USB1GENRNDISEP5,USB1 Generic RNDIS EP5 Size Register"
|
|
hexmask.long.tbyte 0x10 0.--16. 1. " EP5_SIZE ,Generic RNDIS packeet size 5"
|
|
line.long 0x14 "USB1GENRNDISEP6,USB1 Generic RNDIS EP6 Size Register"
|
|
hexmask.long.tbyte 0x14 0.--16. 1. " EP6_SIZE ,Generic RNDIS packeet size 6"
|
|
line.long 0x18 "USB1GENRNDISEP7,USB1 Generic RNDIS EP7 Size Register"
|
|
hexmask.long.tbyte 0x18 0.--16. 1. " EP7_SIZE ,Generic RNDIS packeet size 7"
|
|
line.long 0x1C "USB1GENRNDISEP8,USB1 Generic RNDIS EP8 Size Register"
|
|
hexmask.long.tbyte 0x1C 0.--16. 1. " EP8_SIZE ,Generic RNDIS packeet size 8"
|
|
line.long 0x20 "USB1GENRNDISEP9,USB1 Generic RNDIS EP9 Size Register"
|
|
hexmask.long.tbyte 0x20 0.--16. 1. " EP9_SIZE ,Generic RNDIS packeet size 9"
|
|
line.long 0x24 "USB1GENRNDISEP10,USB1 Generic RNDIS EP10 Size Register"
|
|
hexmask.long.tbyte 0x24 0.--16. 1. " EP10_SIZE ,Generic RNDIS packeet size 10"
|
|
line.long 0x28 "USB1GENRNDISEP11,USB1 Generic RNDIS EP11 Size Register"
|
|
hexmask.long.tbyte 0x28 0.--16. 1. " EP11_SIZE ,Generic RNDIS packeet size 11"
|
|
line.long 0x2C "USB1GENRNDISEP12,USB1 Generic RNDIS EP12 Size Register"
|
|
hexmask.long.tbyte 0x2C 0.--16. 1. " EP12_SIZE ,Generic RNDIS packeet size 12"
|
|
line.long 0x30 "USB1GENRNDISEP13,USB1 Generic RNDIS EP13 Size Register"
|
|
hexmask.long.tbyte 0x30 0.--16. 1. " EP13_SIZE ,Generic RNDIS packeet size 13"
|
|
line.long 0x34 "USB1GENRNDISEP14,USB1 Generic RNDIS EP14 Size Register"
|
|
hexmask.long.tbyte 0x34 0.--16. 1. " EP14_SIZE ,Generic RNDIS packeet size 14"
|
|
line.long 0x38 "USB1GENRNDISEP15,USB1 Generic RNDIS EP15 Size Register"
|
|
hexmask.long.tbyte 0x38 0.--16. 1. " EP15_SIZE ,Generic RNDIS packeet size 15"
|
|
group.long 0xD0++0xB
|
|
line.long 0x00 "USB1AUTOREQ,USB1 Auto Req Register"
|
|
bitfld.long 0x00 28.--29. " RX15_AUTOREQ ,RX endpoint 15 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 26.--27. " RX14_AUTOREQ ,RX endpoint 14 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX13_AUTOREQ ,RX endpoint 13 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 22.--23. " RX12_AUTOREQ ,RX endpoint 12 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " RX11_AUTOREQ ,RX endpoint 11 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 18.--19. " RX10_AUTOREQ ,RX endpoint 10 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " RX9_AUTOREQ ,RX endpoint 9 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 14.--15. " RX8_AUTOREQ ,RX endpoint 8 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX7_AUTOREQ ,RX endpoint 7 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 10.--11. " RX6_AUTOREQ ,RX endpoint 6 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RX5_AUTOREQ ,RX endpoint 5 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 6.--7. " RX4_AUTOREQ ,RX endpoint 4 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " RX3_AUTOREQ ,RX endpoint 3 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
bitfld.long 0x00 2.--3. " RX2_AUTOREQ ,RX endpoint 2 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " RX1_AUTOREQ ,RX endpoint 1 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
|
|
line.long 0x04 "USB1SRPFIXTIME,USB1 SRP Fix Time Register"
|
|
line.long 0x08 "USB1TDOWN,USB1 Teardown Register"
|
|
bitfld.long 0x08 31. " TX_TDOWN15 ,Transmit endpoint 15 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " TX_TDOWN14 ,Transmit endpoint 14 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " TX_TDOWN13 ,Transmit endpoint 13 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 28. " TX_TDOWN12 ,Transmit endpoint 12 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " TX_TDOWN11 ,Transmit endpoint 11 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " TX_TDOWN10 ,Transmit endpoint 10 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " TX_TDOWN9 ,Transmit endpoint 9 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " TX_TDOWN8 ,Transmit endpoint 8 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " TX_TDOWN7 ,Transmit endpoint 7 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " TX_TDOWN6 ,Transmit endpoint 6 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " TX_TDOWN5 ,Transmit endpoint 5 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " TX_TDOWN4 ,Transmit endpoint 4 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " TX_TDOWN3 ,Transmit endpoint 3 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " TX_TDOWN2 ,Transmit endpoint 2 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " TX_TDOWN1 ,Transmit endpoint 1 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " RX_TDOWN15 ,Receive endpoint 15 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " RX_TDOWN14 ,Receive endpoint 14 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " RX_TDOWN13 ,Receive endpoint 13 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " RX_TDOWN12 ,Receive endpoint 12 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " RX_TDOWN11 ,Receive endpoint 11 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " RX_TDOWN10 ,Receive endpoint 10 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " RX_TDOWN9 ,Receive endpoint 9 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RX_TDOWN8 ,Receive endpoint 8 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " RX_TDOWN7 ,Receive endpoint 7 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " RX_TDOWN6 ,Receive endpoint 6 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " RX_TDOWN5 ,Receive endpoint 5 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RX_TDOWN4 ,Receive endpoint 4 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RX_TDOWN3 ,Receive endpoint 3 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RX_TDOWN2 ,Receive endpoint 2 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RX_TDOWN1 ,Receive endpoint 1 teardown" "Disabled,Enabled"
|
|
sif cpuis("DM814?DSP")
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "USB1THRESXDMA,USB1 Threshold XDMA Idle Register"
|
|
hexmask.long.byte 0x00 0.--7. 0x1 " THRES_XDMA_IDLE ,Threshold XDMA Idle cycle parameter"
|
|
endif
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "USB1UTMI,USB1 PHY UTMI Register"
|
|
bitfld.long 0x00 23. " TXBITSTUFFEN ,Input for signal txbitstuffen" "Low,High"
|
|
sif !cpuis("DM814?DSP")
|
|
bitfld.long 0x00 22. " TXBITSTUFFENH ,Input for signal txbitstuffenh" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " OTGDISABLE ,Input for signal otgdisable" "Low,High"
|
|
bitfld.long 0x00 20. " VBUSVLDEXTSEL ,Input for signal vbusvldextsel" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " VBUSVLDEXT ,Input for signal vbusvldext" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 18. " TXENABLEN ,Input for signal txenablen" "Low,High"
|
|
sif !cpuis("DM814?DSP")
|
|
textline " "
|
|
bitfld.long 0x00 17. " FSXCVROWNER ,Input for signal fsxcvrowner" "Low,High"
|
|
bitfld.long 0x00 16. " TXVALIDH ,Input for signal txvalidh" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAINH ,Input for signal datainh"
|
|
bitfld.long 0x00 2. " WORDINTERFACE ,Input for signal wordinterface" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSDATAEXT ,Input for signal fsdataext" "Low,High"
|
|
bitfld.long 0x00 0. " FSSE0EXT ,Input for signal fsse0ext" "Low,High"
|
|
endif
|
|
line.long 0x04 "USB1UTMILB,USB1 MGC UTMI Loopback Register"
|
|
sif (cpuis("DM814?DSP")||cpuis("DRA62*")||cpuis("AM335*"))
|
|
rbitfld.long 0x04 28. " SUSPENDM ,LB test value for suspendm" "Low,High"
|
|
rbitfld.long 0x04 26.--27. " OPMODE ,LB test value for opmode" "0,1,2,3"
|
|
textline " "
|
|
rbitfld.long 0x04 25. " TXVALID ,LB test value for txvalid" "Low,High"
|
|
rbitfld.long 0x04 23.--24. " XCVRSEL ,LB test value for xcvrsel" "0,1,2,3"
|
|
textline " "
|
|
rbitfld.long 0x04 22. " TERMSEL ,LB test value for termsel" "Low,High"
|
|
rbitfld.long 0x04 21. " DRVVBUS ,LB test value for drvvbus" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 20. " CHRGVBUS ,LB test value for chrgvbus" "Low,High"
|
|
rbitfld.long 0x04 19. " DISCHRGVBUS ,LB test value for dischrgvbus" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 18. " DPPULLDOWN ,LB test value for dppulldown" "Low,High"
|
|
rbitfld.long 0x04 17. " DMPULLDOWN ,LB test value for dmpulldown" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 16. " IDPULLUP ,LB test value for idpullup" "Low,High"
|
|
else
|
|
bitfld.long 0x04 28. " SUSPENDM ,LB test value for suspendm" "Low,High"
|
|
bitfld.long 0x04 26.--27. " OPMODE ,LB test value for opmode" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 25. " TXVALID ,LB test value for txvalid" "Low,High"
|
|
bitfld.long 0x04 23.--24. " XCVRSEL ,LB test value for xcvrsel" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 22. " TERMSEL ,LB test value for termsel" "Low,High"
|
|
bitfld.long 0x04 21. " DRVVBUS ,LB test value for drvvbus" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CHRGVBUS ,LB test value for chrgvbus" "Low,High"
|
|
bitfld.long 0x04 19. " DISCHRGVBUS ,LB test value for dischrgvbus" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 18. " DPPULLDOWN ,LB test value for dppulldown" "Low,High"
|
|
bitfld.long 0x04 17. " DMPULLDOWN ,LB test value for dmpulldown" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 16. " IDPULLUP ,LB test value for idpullup" "Low,High"
|
|
endif
|
|
bitfld.long 0x04 11. " IDDIG ,LB test value for iddig" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HOSTDISCON ,LB test value for hostdiscon" "Low,High"
|
|
bitfld.long 0x04 9. " SESSEND ,LB test value for sessend" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 8. " AVALID ,LB test value for avalid" "Low,High"
|
|
bitfld.long 0x04 7. " VBUSVALID ,LB test value for vbusvalid" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 6. " RXERROR ,LB test value for rxerror" "Low,High"
|
|
bitfld.long 0x04 2.--3. " LINESTATE ,LB test value for linestate" "0,1,2,3"
|
|
line.long 0x08 "USB1MODE,USB1 Mode Register"
|
|
bitfld.long 0x08 8. " IDDIG ,MGC input value for IDDIG" "A-type,B-type"
|
|
textline " "
|
|
sif (cpuis("AM335*"))
|
|
bitfld.long 0x08 7. " IDDIG_MUX ,Multiplexer control for IDDIG signal going to the controller" "From PHY,From bit 8 (IDDIG)"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 1. " PHY_TEST ,PHY test" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " LOOPBACK ,Loopback test mode" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "CPPI DMA"
|
|
base ad:0x47402000
|
|
width 18.
|
|
tree "CPPI DMA Registers"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x0 "DMAREVID,CPPI DMA Revision Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " MODID ,Module ID field"
|
|
bitfld.long 0x00 11.--15. " REVRTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " REVMAJ ,Major revision" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVMIN ,Minor revision"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "TDFDQ,CPPI DMA Teardown Free Descriptor Queue Control Register"
|
|
bitfld.long 0x00 12.--13. " TD_DESC_QMGR ,Teardown descriptor queue menager select" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TD_DESC_QNUM ,Teardown descriptor queue number select"
|
|
line.long 0x04 "DMAEMU,CPPI DMA Emulation Control Register"
|
|
bitfld.long 0x04 1. " SOFT ,Force emulation pause request low" "Forced,Not forced"
|
|
bitfld.long 0x04 0. " FREE ,Emulation suspend enable" "Disabled,Enabled"
|
|
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="AM3874")||(cpu()=="AM3872"))
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMAMEM1BA,CPPI Mem1 Base Address Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MEM1_BASE ,CPPI mem1 base address"
|
|
line.long 0x04 "DMAMEM1MASK,CPPI Mem1 Mask Address Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " MEM1_MASK ,CPPI mem1 mask address"
|
|
endif
|
|
group.long 0x800++0x3
|
|
line.long 0x00 "TXGCR[0],CPPI DMA Transmit Channel 0 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x800+0x08)++0x3
|
|
line.long 0x00 "RXGCR[0],CPPI DMA Receive Channel 0 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x800+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[0],CPPI DMA Receive Channel 0 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x800+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[0],CPPI DMA Receive Channel 0 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x820++0x3
|
|
line.long 0x00 "TXGCR[1],CPPI DMA Transmit Channel 1 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x820+0x08)++0x3
|
|
line.long 0x00 "RXGCR[1],CPPI DMA Receive Channel 1 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x820+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[1],CPPI DMA Receive Channel 1 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x820+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[1],CPPI DMA Receive Channel 1 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x840++0x3
|
|
line.long 0x00 "TXGCR[2],CPPI DMA Transmit Channel 2 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x840+0x08)++0x3
|
|
line.long 0x00 "RXGCR[2],CPPI DMA Receive Channel 2 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x840+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[2],CPPI DMA Receive Channel 2 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x840+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[2],CPPI DMA Receive Channel 2 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x860++0x3
|
|
line.long 0x00 "TXGCR[3],CPPI DMA Transmit Channel 3 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x860+0x08)++0x3
|
|
line.long 0x00 "RXGCR[3],CPPI DMA Receive Channel 3 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x860+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[3],CPPI DMA Receive Channel 3 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x860+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[3],CPPI DMA Receive Channel 3 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x880++0x3
|
|
line.long 0x00 "TXGCR[4],CPPI DMA Transmit Channel 4 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x880+0x08)++0x3
|
|
line.long 0x00 "RXGCR[4],CPPI DMA Receive Channel 4 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x880+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[4],CPPI DMA Receive Channel 4 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x880+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[4],CPPI DMA Receive Channel 4 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x8A0++0x3
|
|
line.long 0x00 "TXGCR[5],CPPI DMA Transmit Channel 5 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x8A0+0x08)++0x3
|
|
line.long 0x00 "RXGCR[5],CPPI DMA Receive Channel 5 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x8A0+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[5],CPPI DMA Receive Channel 5 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x8A0+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[5],CPPI DMA Receive Channel 5 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x8C0++0x3
|
|
line.long 0x00 "TXGCR[6],CPPI DMA Transmit Channel 6 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x8C0+0x08)++0x3
|
|
line.long 0x00 "RXGCR[6],CPPI DMA Receive Channel 6 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x8C0+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[6],CPPI DMA Receive Channel 6 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x8C0+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[6],CPPI DMA Receive Channel 6 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x8E0++0x3
|
|
line.long 0x00 "TXGCR[7],CPPI DMA Transmit Channel 7 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x8E0+0x08)++0x3
|
|
line.long 0x00 "RXGCR[7],CPPI DMA Receive Channel 7 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x8E0+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[7],CPPI DMA Receive Channel 7 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x8E0+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[7],CPPI DMA Receive Channel 7 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x900++0x3
|
|
line.long 0x00 "TXGCR[8],CPPI DMA Transmit Channel 8 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x900+0x08)++0x3
|
|
line.long 0x00 "RXGCR[8],CPPI DMA Receive Channel 8 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x900+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[8],CPPI DMA Receive Channel 8 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x900+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[8],CPPI DMA Receive Channel 8 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x920++0x3
|
|
line.long 0x00 "TXGCR[9],CPPI DMA Transmit Channel 9 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x920+0x08)++0x3
|
|
line.long 0x00 "RXGCR[9],CPPI DMA Receive Channel 9 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x920+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[9],CPPI DMA Receive Channel 9 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x920+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[9],CPPI DMA Receive Channel 9 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x940++0x3
|
|
line.long 0x00 "TXGCR[10],CPPI DMA Transmit Channel 10 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x940+0x08)++0x3
|
|
line.long 0x00 "RXGCR[10],CPPI DMA Receive Channel 10 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x940+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[10],CPPI DMA Receive Channel 10 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x940+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[10],CPPI DMA Receive Channel 10 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x960++0x3
|
|
line.long 0x00 "TXGCR[11],CPPI DMA Transmit Channel 11 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x960+0x08)++0x3
|
|
line.long 0x00 "RXGCR[11],CPPI DMA Receive Channel 11 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x960+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[11],CPPI DMA Receive Channel 11 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x960+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[11],CPPI DMA Receive Channel 11 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x980++0x3
|
|
line.long 0x00 "TXGCR[12],CPPI DMA Transmit Channel 12 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x980+0x08)++0x3
|
|
line.long 0x00 "RXGCR[12],CPPI DMA Receive Channel 12 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x980+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[12],CPPI DMA Receive Channel 12 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x980+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[12],CPPI DMA Receive Channel 12 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x9A0++0x3
|
|
line.long 0x00 "TXGCR[13],CPPI DMA Transmit Channel 13 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x9A0+0x08)++0x3
|
|
line.long 0x00 "RXGCR[13],CPPI DMA Receive Channel 13 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x9A0+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[13],CPPI DMA Receive Channel 13 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x9A0+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[13],CPPI DMA Receive Channel 13 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x9C0++0x3
|
|
line.long 0x00 "TXGCR[14],CPPI DMA Transmit Channel 14 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x9C0+0x08)++0x3
|
|
line.long 0x00 "RXGCR[14],CPPI DMA Receive Channel 14 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
wgroup.long (0x9C0+0x0C)++0x3
|
|
line.long 0x00 "RXHPCRA[14],CPPI DMA Receive Channel 14 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
wgroup.long (0x9C0+0x10)++0x3
|
|
line.long 0x00 "RXHPCRB[14],CPPI DMA Receive Channel 14 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
tree.end
|
|
tree "CPPI DMA Scheduler Registers"
|
|
width 16.
|
|
group.long 0x1000++0x3
|
|
line.long 0x00 "DMA_SCHED_CTRL,CPPI DMA Scheduler Control Register"
|
|
bitfld.long 0x00 31. " ENABLE ,Scheduler enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " LAST_ENTRY ,Last valid entry in the scheduler table"
|
|
width 11.
|
|
wgroup.long 0x1800++0xff
|
|
line.long 0x0 "WORD[0],CPPI DMA Scheduler Table Word 0 Register"
|
|
bitfld.long 0x0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x4 "WORD[1],CPPI DMA Scheduler Table Word 1 Register"
|
|
bitfld.long 0x4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x8 "WORD[2],CPPI DMA Scheduler Table Word 2 Register"
|
|
bitfld.long 0x8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xC "WORD[3],CPPI DMA Scheduler Table Word 3 Register"
|
|
bitfld.long 0xC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "WORD[4],CPPI DMA Scheduler Table Word 4 Register"
|
|
bitfld.long 0x10 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x10 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x10 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x10 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x10 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x10 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x10 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "WORD[5],CPPI DMA Scheduler Table Word 5 Register"
|
|
bitfld.long 0x14 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x14 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x14 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x14 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x14 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x14 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x14 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "WORD[6],CPPI DMA Scheduler Table Word 6 Register"
|
|
bitfld.long 0x18 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x18 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x18 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x18 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x18 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x18 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x18 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "WORD[7],CPPI DMA Scheduler Table Word 7 Register"
|
|
bitfld.long 0x1C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x1C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x1C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x1C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x1C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "WORD[8],CPPI DMA Scheduler Table Word 8 Register"
|
|
bitfld.long 0x20 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x20 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x20 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x20 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x20 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x20 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x20 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x20 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "WORD[9],CPPI DMA Scheduler Table Word 9 Register"
|
|
bitfld.long 0x24 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x24 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x24 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x24 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x24 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x24 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x24 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x24 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "WORD[10],CPPI DMA Scheduler Table Word 10 Register"
|
|
bitfld.long 0x28 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x28 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x28 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x28 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x28 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x28 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x28 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x28 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "WORD[11],CPPI DMA Scheduler Table Word 11 Register"
|
|
bitfld.long 0x2C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x2C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x2C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x2C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x2C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x2C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x2C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x2C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "WORD[12],CPPI DMA Scheduler Table Word 12 Register"
|
|
bitfld.long 0x30 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x30 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x30 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x30 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x30 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x30 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x30 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x30 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "WORD[13],CPPI DMA Scheduler Table Word 13 Register"
|
|
bitfld.long 0x34 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x34 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x34 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x34 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x34 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x34 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x34 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x34 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x38 "WORD[14],CPPI DMA Scheduler Table Word 14 Register"
|
|
bitfld.long 0x38 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x38 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x38 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x38 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x38 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x38 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x38 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x38 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x3C "WORD[15],CPPI DMA Scheduler Table Word 15 Register"
|
|
bitfld.long 0x3C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x3C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x3C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x3C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x3C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x3C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x3C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x3C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x40 "WORD[16],CPPI DMA Scheduler Table Word 16 Register"
|
|
bitfld.long 0x40 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x40 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x40 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x40 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x40 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x40 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x40 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x40 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x44 "WORD[17],CPPI DMA Scheduler Table Word 17 Register"
|
|
bitfld.long 0x44 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x44 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x44 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x44 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x44 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x44 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x44 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x44 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x48 "WORD[18],CPPI DMA Scheduler Table Word 18 Register"
|
|
bitfld.long 0x48 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x48 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x48 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x48 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x48 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x48 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x48 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x48 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x4C "WORD[19],CPPI DMA Scheduler Table Word 19 Register"
|
|
bitfld.long 0x4C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x4C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x4C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x4C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x50 "WORD[20],CPPI DMA Scheduler Table Word 20 Register"
|
|
bitfld.long 0x50 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x50 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x50 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x50 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x50 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x50 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x50 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x50 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x54 "WORD[21],CPPI DMA Scheduler Table Word 21 Register"
|
|
bitfld.long 0x54 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x54 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x54 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x54 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x54 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x54 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x54 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x54 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x58 "WORD[22],CPPI DMA Scheduler Table Word 22 Register"
|
|
bitfld.long 0x58 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x58 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x58 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x58 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x58 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x58 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x58 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x58 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x5C "WORD[23],CPPI DMA Scheduler Table Word 23 Register"
|
|
bitfld.long 0x5C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x5C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x5C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x5C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x5C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x5C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x5C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x5C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x60 "WORD[24],CPPI DMA Scheduler Table Word 24 Register"
|
|
bitfld.long 0x60 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x60 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x60 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x60 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x60 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x60 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x60 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x60 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x64 "WORD[25],CPPI DMA Scheduler Table Word 25 Register"
|
|
bitfld.long 0x64 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x64 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x64 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x64 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x64 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x64 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x64 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x64 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x68 "WORD[26],CPPI DMA Scheduler Table Word 26 Register"
|
|
bitfld.long 0x68 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x68 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x68 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x68 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x68 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x68 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x68 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x68 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x6C "WORD[27],CPPI DMA Scheduler Table Word 27 Register"
|
|
bitfld.long 0x6C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x6C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x6C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x6C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x6C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x6C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x6C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x6C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x70 "WORD[28],CPPI DMA Scheduler Table Word 28 Register"
|
|
bitfld.long 0x70 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x70 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x70 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x70 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x70 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x70 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x70 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x70 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x74 "WORD[29],CPPI DMA Scheduler Table Word 29 Register"
|
|
bitfld.long 0x74 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x74 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x74 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x74 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x74 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x74 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x74 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x74 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x78 "WORD[30],CPPI DMA Scheduler Table Word 30 Register"
|
|
bitfld.long 0x78 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x78 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x78 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x78 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x78 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x78 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x78 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x78 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
line.long 0x7C "WORD[31],CPPI DMA Scheduler Table Word 31 Register"
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|
bitfld.long 0x7C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x7C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x7C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x7C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x7C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x7C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x7C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x7C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
line.long 0x80 "WORD[32],CPPI DMA Scheduler Table Word 32 Register"
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|
bitfld.long 0x80 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x80 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
|
|
bitfld.long 0x80 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x80 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x80 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x80 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
|
|
bitfld.long 0x80 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x80 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
line.long 0x84 "WORD[33],CPPI DMA Scheduler Table Word 33 Register"
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|
bitfld.long 0x84 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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|
bitfld.long 0x84 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x84 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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|
bitfld.long 0x84 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x84 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x84 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x84 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x84 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
line.long 0x88 "WORD[34],CPPI DMA Scheduler Table Word 34 Register"
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|
bitfld.long 0x88 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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|
bitfld.long 0x88 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x88 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x88 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x88 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x88 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x88 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x88 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
line.long 0x8C "WORD[35],CPPI DMA Scheduler Table Word 35 Register"
|
|
bitfld.long 0x8C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x8C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x8C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x8C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x90 "WORD[36],CPPI DMA Scheduler Table Word 36 Register"
|
|
bitfld.long 0x90 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x90 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x90 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x90 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x90 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x90 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x90 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x90 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x94 "WORD[37],CPPI DMA Scheduler Table Word 37 Register"
|
|
bitfld.long 0x94 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x94 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x94 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x94 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x94 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x94 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x94 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x94 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x98 "WORD[38],CPPI DMA Scheduler Table Word 38 Register"
|
|
bitfld.long 0x98 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x98 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x98 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x98 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x98 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x98 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x98 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x98 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x9C "WORD[39],CPPI DMA Scheduler Table Word 39 Register"
|
|
bitfld.long 0x9C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x9C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x9C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x9C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x9C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x9C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x9C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x9C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xA0 "WORD[40],CPPI DMA Scheduler Table Word 40 Register"
|
|
bitfld.long 0xA0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xA0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xA0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xA0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xA4 "WORD[41],CPPI DMA Scheduler Table Word 41 Register"
|
|
bitfld.long 0xA4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xA4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xA4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xA4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xA8 "WORD[42],CPPI DMA Scheduler Table Word 42 Register"
|
|
bitfld.long 0xA8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xA8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xA8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xA8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xAC "WORD[43],CPPI DMA Scheduler Table Word 43 Register"
|
|
bitfld.long 0xAC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xAC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xAC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xAC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xAC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xAC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xAC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xAC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xB0 "WORD[44],CPPI DMA Scheduler Table Word 44 Register"
|
|
bitfld.long 0xB0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xB0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xB0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xB0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xB4 "WORD[45],CPPI DMA Scheduler Table Word 45 Register"
|
|
bitfld.long 0xB4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xB4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xB4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xB4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xB8 "WORD[46],CPPI DMA Scheduler Table Word 46 Register"
|
|
bitfld.long 0xB8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xB8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xB8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xB8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xBC "WORD[47],CPPI DMA Scheduler Table Word 47 Register"
|
|
bitfld.long 0xBC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xBC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xBC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xBC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xBC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xBC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xBC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xBC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xC0 "WORD[48],CPPI DMA Scheduler Table Word 48 Register"
|
|
bitfld.long 0xC0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xC0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xC0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xC0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xC4 "WORD[49],CPPI DMA Scheduler Table Word 49 Register"
|
|
bitfld.long 0xC4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xC4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xC4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xC4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xC8 "WORD[50],CPPI DMA Scheduler Table Word 50 Register"
|
|
bitfld.long 0xC8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xC8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xC8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xC8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xCC "WORD[51],CPPI DMA Scheduler Table Word 51 Register"
|
|
bitfld.long 0xCC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xCC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xCC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xCC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xCC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xCC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xCC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xCC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xD0 "WORD[52],CPPI DMA Scheduler Table Word 52 Register"
|
|
bitfld.long 0xD0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xD0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xD0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xD0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xD4 "WORD[53],CPPI DMA Scheduler Table Word 53 Register"
|
|
bitfld.long 0xD4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xD4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xD4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xD4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xD8 "WORD[54],CPPI DMA Scheduler Table Word 54 Register"
|
|
bitfld.long 0xD8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xD8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xD8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xD8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xDC "WORD[55],CPPI DMA Scheduler Table Word 55 Register"
|
|
bitfld.long 0xDC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xDC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xDC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xDC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xDC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xDC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xDC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xDC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xE0 "WORD[56],CPPI DMA Scheduler Table Word 56 Register"
|
|
bitfld.long 0xE0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xE0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xE0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xE0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xE4 "WORD[57],CPPI DMA Scheduler Table Word 57 Register"
|
|
bitfld.long 0xE4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xE4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xE4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xE4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xE8 "WORD[58],CPPI DMA Scheduler Table Word 58 Register"
|
|
bitfld.long 0xE8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xE8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xE8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xE8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xEC "WORD[59],CPPI DMA Scheduler Table Word 59 Register"
|
|
bitfld.long 0xEC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xEC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xEC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xEC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xEC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xEC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xEC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xEC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xF0 "WORD[60],CPPI DMA Scheduler Table Word 60 Register"
|
|
bitfld.long 0xF0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xF0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xF0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xF0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xF4 "WORD[61],CPPI DMA Scheduler Table Word 61 Register"
|
|
bitfld.long 0xF4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xF4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xF4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xF4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xF8 "WORD[62],CPPI DMA Scheduler Table Word 62 Register"
|
|
bitfld.long 0xF8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xF8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xF8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xF8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0xFC "WORD[63],CPPI DMA Scheduler Table Word 63 Register"
|
|
bitfld.long 0xFC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xFC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xFC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xFC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xFC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xFC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0xFC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xFC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
width 14.
|
|
tree "CPPI DMA Queue Manager Registers"
|
|
rgroup.long 0x2000++0x03
|
|
line.long 0x00 "QMGRREVID,Queue Manager Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme that this register is compliant with" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " REVRTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " REVMAJ ,Major revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " REVCUSTOM ,Custom revision" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " RVMIN ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif ((!cpuis("DM814?DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
group.long 0x2004++0x03
|
|
line.long 0x00 "QMGRRST,Queue Manager Reset Register"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--29. 1. " DEST_QNUM ,Destination Queue Number"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--13. 1. " SOURCE_QNUM ,Source Queue Number"
|
|
endif
|
|
wgroup.long 0x2008++0x03
|
|
line.long 0x00 "DIVERSION,Queue Manager Queue Diversion Register"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--29. 1. " DEST_QNUM ,Destination Queue Number"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--13. 1. " SOURCE_QNUM ,Source Queue Number"
|
|
hgroup.long 0x2020++0x03
|
|
hide.long 0x00 "FDBSC0,Queue Manager Free Descriptor/Buffer Starvation Count Register 0"
|
|
in
|
|
hgroup.long 0x2024++0x03
|
|
hide.long 0x00 "FDBSC1,Queue Manager Free Descriptor/Buffer Starvation Count Register 1"
|
|
in
|
|
hgroup.long 0x2028++0x03
|
|
hide.long 0x00 "FDBSC2,Queue Manager Free Descriptor/Buffer Starvation Count Register 2"
|
|
in
|
|
hgroup.long 0x202c++0x03
|
|
hide.long 0x00 "FDBSC3,Queue Manager Free Descriptor/Buffer Starvation Count Register 3"
|
|
in
|
|
hgroup.long 0x2030++0x03
|
|
hide.long 0x00 "FDBSC4,Queue Manager Free Descriptor/Buffer Starvation Count Register 4"
|
|
in
|
|
hgroup.long 0x2034++0x03
|
|
hide.long 0x00 "FDBSC5,Queue Manager Free Descriptor/Buffer Starvation Count Register 5"
|
|
in
|
|
hgroup.long 0x2038++0x03
|
|
hide.long 0x00 "FDBSC6,Queue Manager Free Descriptor/Buffer Starvation Count Register 6"
|
|
in
|
|
hgroup.long 0x203c++0x03
|
|
hide.long 0x00 "FDBSC7,Queue Manager Free Descriptor/Buffer Starvation Count Register 7"
|
|
in
|
|
group.long 0x2080++0xb
|
|
line.long 0x00 "LRAM0BASE,Queue Manager Linking RAM Region 0 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 2.--31. 0x4 " REGION0_BASE ,Linking RAM first region base address"
|
|
endif
|
|
line.long 0x04 "LRAM0SIZE,Queue Manager Linking RAM Region 0 Size Register"
|
|
sif (cpuis("DRA62*")||cpuis("DM814?DSP"))
|
|
hexmask.long.word 0x04 0.--13. 1. " REGION0_SIZE , Number of entries that are contained in the linking RAM region 0"
|
|
endif
|
|
line.long 0x08 "LRAM1BASE,Queue Manager Linking RAM Region 1 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x08 2.--31. 0x4 " REGION1_BASE ,Linking RAM second region base address"
|
|
endif
|
|
rgroup.long 0x2090++0xb
|
|
line.long 0x00 "PEND0,Queue Manager Queue Pending Register 0"
|
|
bitfld.long 0x00 31. " QPEND31 ,Queue 31 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " QPEND30 ,Queue 30 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " QPEND29 ,Queue 29 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " QPEND28 ,Queue 28 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " QPEND27 ,Queue 27 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " QPEND26 ,Queue 26 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " QPEND25 ,Queue 25 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " QPEND24 ,Queue 24 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " QPEND23 ,Queue 23 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " QPEND22 ,Queue 22 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " QPEND21 ,Queue 21 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " QPEND20 ,Queue 20 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " QPEND19 ,Queue 19 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " QPEND18 ,Queue 18 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " QPEND17 ,Queue 17 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " QPEND16 ,Queue 16 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " QPEND15 ,Queue 15 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " QPEND14 ,Queue 14 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " QPEND13 ,Queue 13 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " QPEND12 ,Queue 12 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " QPEND11 ,Queue 11 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " QPEND10 ,Queue 10 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " QPEND9 ,Queue 9 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " QPEND8 ,Queue 8 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " QPEND7 ,Queue 7 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " QPEND6 ,Queue 6 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " QPEND5 ,Queue 5 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " QPEND4 ,Queue 4 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " QPEND3 ,Queue 3 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " QPEND2 ,Queue 2 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " QPEND1 ,Queue 1 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " QPEND0 ,Queue 0 pending status" "Not pending,Pending"
|
|
line.long 0x04 "PEND1,Queue Manager Queue Pending Register 1"
|
|
bitfld.long 0x04 31. " QPEND63 ,Queue 63 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 30. " QPEND62 ,Queue 62 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 29. " QPEND61 ,Queue 61 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 28. " QPEND60 ,Queue 60 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 27. " QPEND59 ,Queue 59 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 26. " QPEND58 ,Queue 58 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 25. " QPEND57 ,Queue 57 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " QPEND56 ,Queue 56 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 23. " QPEND55 ,Queue 55 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 22. " QPEND54 ,Queue 54 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 21. " QPEND53 ,Queue 53 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 20. " QPEND52 ,Queue 52 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 19. " QPEND51 ,Queue 51 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 18. " QPEND50 ,Queue 50 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 17. " QPEND49 ,Queue 49 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 16. " QPEND48 ,Queue 48 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 15. " QPEND47 ,Queue 47 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 14. " QPEND46 ,Queue 46 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 13. " QPEND45 ,Queue 45 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 12. " QPEND44 ,Queue 44 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 11. " QPEND43 ,Queue 43 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 10. " QPEND42 ,Queue 42 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 9. " QPEND41 ,Queue 41 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 8. " QPEND40 ,Queue 40 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 7. " QPEND39 ,Queue 39 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " QPEND38 ,Queue 38 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 5. " QPEND37 ,Queue 37 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 4. " QPEND36 ,Queue 36 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 3. " QPEND35 ,Queue 35 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " QPEND34 ,Queue 34 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 1. " QPEND33 ,Queue 33 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " QPEND32 ,Queue 32 pending status" "Not pending,Pending"
|
|
line.long 0x08 "PEND2,Queue Manager Queue Pending Register 2"
|
|
bitfld.long 0x08 31. " QPEND95 ,Queue 95 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 30. " QPEND94 ,Queue 94 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 29. " QPEND93 ,Queue 93 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 28. " QPEND92 ,Queue 92 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 27. " QPEND91 ,Queue 91 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 26. " QPEND90 ,Queue 90 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 25. " QPEND89 ,Queue 89 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 24. " QPEND88 ,Queue 88 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 23. " QPEND87 ,Queue 87 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 22. " QPEND86 ,Queue 86 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 21. " QPEND85 ,Queue 85 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 20. " QPEND84 ,Queue 84 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 19. " QPEND83 ,Queue 83 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 18. " QPEND82 ,Queue 82 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 17. " QPEND81 ,Queue 81 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 16. " QPEND80 ,Queue 80 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 15. " QPEND79 ,Queue 79 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 14. " QPEND78 ,Queue 78 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 13. " QPEND77 ,Queue 77 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 12. " QPEND76 ,Queue 76 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 11. " QPEND75 ,Queue 75 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 10. " QPEND74 ,Queue 74 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 9. " QPEND73 ,Queue 73 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 8. " QPEND72 ,Queue 72 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 7. " QPEND71 ,Queue 71 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 6. " QPEND70 ,Queue 70 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 5. " QPEND69 ,Queue 69 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 4. " QPEND68 ,Queue 68 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 3. " QPEND67 ,Queue 67 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 2. " QPEND66 ,Queue 66 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 1. " QPEND65 ,Queue 65 pending status" "Not pending,Pending"
|
|
bitfld.long 0x08 0. " QPEND64 ,Queue 64 pending status" "Not pending,Pending"
|
|
sif ((!cpuis("DRA6*")||cpuis("DRA62*"))&&(!cpuis("C674*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="AM3874")&&(cpu()!="AM3872"))
|
|
rgroup.long 0x209c++0x7
|
|
line.long 0x00 "PEND3,Queue Manager Queue Pending Register 3"
|
|
bitfld.long 0x00 31. " QPEND127 ,Queue 127 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " QPEND126 ,Queue 126 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " QPEND125 ,Queue 125 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " QPEND124 ,Queue 124 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " QPEND123 ,Queue 123 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " QPEND122 ,Queue 122 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " QPEND121 ,Queue 121 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " QPEND120 ,Queue 120 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " QPEND119 ,Queue 119 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " QPEND118 ,Queue 118 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " QPEND117 ,Queue 117 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " QPEND116 ,Queue 116 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " QPEND115 ,Queue 115 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " QPEND114 ,Queue 114 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " QPEND113 ,Queue 113 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " QPEND112 ,Queue 112 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " QPEND111 ,Queue 111 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " QPEND110 ,Queue 110 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " QPEND109 ,Queue 109 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " QPEND108 ,Queue 108 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " QPEND107 ,Queue 107 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " QPEND106 ,Queue 106 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " QPEND105 ,Queue 105 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " QPEND104 ,Queue 104 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " QPEND103 ,Queue 103 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " QPEND102 ,Queue 102 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " QPEND101 ,Queue 101 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " QPEND100 ,Queue 100 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " QPEND99 ,Queue 99 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " QPEND98 ,Queue 98 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " QPEND97 ,Queue 97 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " QPEND96 ,Queue 96 pending status" "Not pending,Pending"
|
|
line.long 0x04 "PEND4,Queue Manager Queue Pending Register 4"
|
|
sif cpu()=="DM8147DSP"||cpu()=="DM8148DSP"
|
|
bitfld.long 0x04 27. " QPEND155 ,Queue 155 pending status" "Not pending,Pending"
|
|
else
|
|
bitfld.long 0x04 31. " QPEND159 ,Queue 159 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 30. " QPEND158 ,Queue 158 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 29. " QPEND157 ,Queue 157 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 28. " QPEND156 ,Queue 156 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 27. " QPEND155 ,Queue 155 pending status" "Not pending,Pending"
|
|
endif
|
|
bitfld.long 0x04 26. " QPEND154 ,Queue 154 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 25. " QPEND153 ,Queue 153 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " QPEND152 ,Queue 152 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 23. " QPEND151 ,Queue 151 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 22. " QPEND150 ,Queue 150 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 21. " QPEND149 ,Queue 149 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 20. " QPEND148 ,Queue 148 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 19. " QPEND147 ,Queue 147 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 18. " QPEND146 ,Queue 146 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 17. " QPEND145 ,Queue 145 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 16. " QPEND144 ,Queue 144 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 15. " QPEND143 ,Queue 143 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 14. " QPEND142 ,Queue 142 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 13. " QPEND141 ,Queue 141 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 12. " QPEND140 ,Queue 140 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 11. " QPEND139 ,Queue 139 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 10. " QPEND138 ,Queue 138 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 9. " QPEND137 ,Queue 137 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 8. " QPEND136 ,Queue 136 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 7. " QPEND135 ,Queue 135 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " QPEND134 ,Queue 134 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 5. " QPEND133 ,Queue 133 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 4. " QPEND132 ,Queue 132 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 3. " QPEND131 ,Queue 131 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " QPEND130 ,Queue 130 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 1. " QPEND129 ,Queue 129 pending status" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " QPEND128 ,Queue 128 pending status" "Not pending,Pending"
|
|
endif
|
|
group.long 0x3000++0x7
|
|
line.long 0x00 "QMEMRBASE[0],Queue Manager Memory Region 0 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 0 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[0],Queue Manager Memory Region 0 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 0 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x3010++0x7
|
|
line.long 0x00 "QMEMRBASE[1],Queue Manager Memory Region 1 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 1 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[1],Queue Manager Memory Region 1 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 1 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x3020++0x7
|
|
line.long 0x00 "QMEMRBASE[2],Queue Manager Memory Region 2 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 2 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[2],Queue Manager Memory Region 2 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 2 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x3030++0x7
|
|
line.long 0x00 "QMEMRBASE[3],Queue Manager Memory Region 3 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 3 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[3],Queue Manager Memory Region 3 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 3 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x3040++0x7
|
|
line.long 0x00 "QMEMRBASE[4],Queue Manager Memory Region 4 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 4 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[4],Queue Manager Memory Region 4 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 4 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x3050++0x7
|
|
line.long 0x00 "QMEMRBASE[5],Queue Manager Memory Region 5 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 5 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[5],Queue Manager Memory Region 5 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 5 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x3060++0x7
|
|
line.long 0x00 "QMEMRBASE[6],Queue Manager Memory Region 6 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 6 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[6],Queue Manager Memory Region 6 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 6 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x3070++0x7
|
|
line.long 0x00 "QMEMRBASE[7],Queue Manager Memory Region 7 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 7 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[7],Queue Manager Memory Region 7 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 7 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x3080++0x7
|
|
line.long 0x00 "QMEMRBASE[8],Queue Manager Memory Region 8 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 8 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[8],Queue Manager Memory Region 8 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 8 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x3090++0x7
|
|
line.long 0x00 "QMEMRBASE[9],Queue Manager Memory Region 9 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 9 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[9],Queue Manager Memory Region 9 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 9 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x30A0++0x7
|
|
line.long 0x00 "QMEMRBASE[10],Queue Manager Memory Region 10 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 10 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[10],Queue Manager Memory Region 10 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 10 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x30B0++0x7
|
|
line.long 0x00 "QMEMRBASE[11],Queue Manager Memory Region 11 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 11 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[11],Queue Manager Memory Region 11 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 11 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x30C0++0x7
|
|
line.long 0x00 "QMEMRBASE[12],Queue Manager Memory Region 12 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 12 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[12],Queue Manager Memory Region 12 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 12 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x30D0++0x7
|
|
line.long 0x00 "QMEMRBASE[13],Queue Manager Memory Region 13 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 13 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[13],Queue Manager Memory Region 13 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 13 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x30E0++0x7
|
|
line.long 0x00 "QMEMRBASE[14],Queue Manager Memory Region 14 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 14 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[14],Queue Manager Memory Region 14 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 14 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x30F0++0x7
|
|
line.long 0x00 "QMEMRBASE[15],Queue Manager Memory Region 15 Base Address Register"
|
|
sif cpuis("DM814?DSP")
|
|
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 15 base address"
|
|
endif
|
|
line.long 0x04 "QMEMRCTRL[15],Queue Manager Memory Region 15 Control Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 15 start index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
tree "Queues"
|
|
tree "Queue 0 Registers"
|
|
rgroup.long 0x4000++0xB
|
|
line.long 0x00 "CTRLA[0],Queue Manager Queue 0 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[0],Queue Manager Queue 0 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[0],Queue Manager Queue 0 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4000+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[0],Queue Manager Queue 0 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5000++0xB
|
|
line.long 0x00 "QSTATA[0],Queue Manager Queue 0 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[0],Queue Manager Queue 0 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[0],Queue Manager Queue 0 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 1 Registers"
|
|
rgroup.long 0x4010++0xB
|
|
line.long 0x00 "CTRLA[1],Queue Manager Queue 1 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[1],Queue Manager Queue 1 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[1],Queue Manager Queue 1 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4010+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[1],Queue Manager Queue 1 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5010++0xB
|
|
line.long 0x00 "QSTATA[1],Queue Manager Queue 1 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[1],Queue Manager Queue 1 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[1],Queue Manager Queue 1 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 2 Registers"
|
|
rgroup.long 0x4020++0xB
|
|
line.long 0x00 "CTRLA[2],Queue Manager Queue 2 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[2],Queue Manager Queue 2 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[2],Queue Manager Queue 2 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4020+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[2],Queue Manager Queue 2 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5020++0xB
|
|
line.long 0x00 "QSTATA[2],Queue Manager Queue 2 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[2],Queue Manager Queue 2 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[2],Queue Manager Queue 2 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 3 Registers"
|
|
rgroup.long 0x4030++0xB
|
|
line.long 0x00 "CTRLA[3],Queue Manager Queue 3 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[3],Queue Manager Queue 3 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[3],Queue Manager Queue 3 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4030+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[3],Queue Manager Queue 3 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5030++0xB
|
|
line.long 0x00 "QSTATA[3],Queue Manager Queue 3 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[3],Queue Manager Queue 3 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[3],Queue Manager Queue 3 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 4 Registers"
|
|
rgroup.long 0x4040++0xB
|
|
line.long 0x00 "CTRLA[4],Queue Manager Queue 4 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[4],Queue Manager Queue 4 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[4],Queue Manager Queue 4 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4040+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[4],Queue Manager Queue 4 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5040++0xB
|
|
line.long 0x00 "QSTATA[4],Queue Manager Queue 4 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[4],Queue Manager Queue 4 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[4],Queue Manager Queue 4 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 5 Registers"
|
|
rgroup.long 0x4050++0xB
|
|
line.long 0x00 "CTRLA[5],Queue Manager Queue 5 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[5],Queue Manager Queue 5 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[5],Queue Manager Queue 5 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4050+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[5],Queue Manager Queue 5 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5050++0xB
|
|
line.long 0x00 "QSTATA[5],Queue Manager Queue 5 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[5],Queue Manager Queue 5 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[5],Queue Manager Queue 5 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 6 Registers"
|
|
rgroup.long 0x4060++0xB
|
|
line.long 0x00 "CTRLA[6],Queue Manager Queue 6 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[6],Queue Manager Queue 6 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[6],Queue Manager Queue 6 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4060+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[6],Queue Manager Queue 6 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5060++0xB
|
|
line.long 0x00 "QSTATA[6],Queue Manager Queue 6 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[6],Queue Manager Queue 6 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[6],Queue Manager Queue 6 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 7 Registers"
|
|
rgroup.long 0x4070++0xB
|
|
line.long 0x00 "CTRLA[7],Queue Manager Queue 7 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[7],Queue Manager Queue 7 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[7],Queue Manager Queue 7 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4070+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[7],Queue Manager Queue 7 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5070++0xB
|
|
line.long 0x00 "QSTATA[7],Queue Manager Queue 7 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[7],Queue Manager Queue 7 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[7],Queue Manager Queue 7 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 8 Registers"
|
|
rgroup.long 0x4080++0xB
|
|
line.long 0x00 "CTRLA[8],Queue Manager Queue 8 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[8],Queue Manager Queue 8 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[8],Queue Manager Queue 8 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4080+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[8],Queue Manager Queue 8 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5080++0xB
|
|
line.long 0x00 "QSTATA[8],Queue Manager Queue 8 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[8],Queue Manager Queue 8 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[8],Queue Manager Queue 8 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 9 Registers"
|
|
rgroup.long 0x4090++0xB
|
|
line.long 0x00 "CTRLA[9],Queue Manager Queue 9 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[9],Queue Manager Queue 9 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[9],Queue Manager Queue 9 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4090+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[9],Queue Manager Queue 9 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5090++0xB
|
|
line.long 0x00 "QSTATA[9],Queue Manager Queue 9 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[9],Queue Manager Queue 9 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[9],Queue Manager Queue 9 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 10 Registers"
|
|
rgroup.long 0x40A0++0xB
|
|
line.long 0x00 "CTRLA[10],Queue Manager Queue 10 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[10],Queue Manager Queue 10 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[10],Queue Manager Queue 10 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x40A0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[10],Queue Manager Queue 10 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x50A0++0xB
|
|
line.long 0x00 "QSTATA[10],Queue Manager Queue 10 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[10],Queue Manager Queue 10 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[10],Queue Manager Queue 10 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 11 Registers"
|
|
rgroup.long 0x40B0++0xB
|
|
line.long 0x00 "CTRLA[11],Queue Manager Queue 11 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[11],Queue Manager Queue 11 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[11],Queue Manager Queue 11 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x40B0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[11],Queue Manager Queue 11 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x50B0++0xB
|
|
line.long 0x00 "QSTATA[11],Queue Manager Queue 11 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[11],Queue Manager Queue 11 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[11],Queue Manager Queue 11 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 12 Registers"
|
|
rgroup.long 0x40C0++0xB
|
|
line.long 0x00 "CTRLA[12],Queue Manager Queue 12 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[12],Queue Manager Queue 12 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[12],Queue Manager Queue 12 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x40C0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[12],Queue Manager Queue 12 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x50C0++0xB
|
|
line.long 0x00 "QSTATA[12],Queue Manager Queue 12 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[12],Queue Manager Queue 12 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[12],Queue Manager Queue 12 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 13 Registers"
|
|
rgroup.long 0x40D0++0xB
|
|
line.long 0x00 "CTRLA[13],Queue Manager Queue 13 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[13],Queue Manager Queue 13 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[13],Queue Manager Queue 13 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x40D0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[13],Queue Manager Queue 13 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x50D0++0xB
|
|
line.long 0x00 "QSTATA[13],Queue Manager Queue 13 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[13],Queue Manager Queue 13 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[13],Queue Manager Queue 13 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 14 Registers"
|
|
rgroup.long 0x40E0++0xB
|
|
line.long 0x00 "CTRLA[14],Queue Manager Queue 14 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[14],Queue Manager Queue 14 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[14],Queue Manager Queue 14 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x40E0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[14],Queue Manager Queue 14 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x50E0++0xB
|
|
line.long 0x00 "QSTATA[14],Queue Manager Queue 14 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[14],Queue Manager Queue 14 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[14],Queue Manager Queue 14 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 15 Registers"
|
|
rgroup.long 0x40F0++0xB
|
|
line.long 0x00 "CTRLA[15],Queue Manager Queue 15 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[15],Queue Manager Queue 15 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[15],Queue Manager Queue 15 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x40F0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[15],Queue Manager Queue 15 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x50F0++0xB
|
|
line.long 0x00 "QSTATA[15],Queue Manager Queue 15 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[15],Queue Manager Queue 15 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[15],Queue Manager Queue 15 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 16 Registers"
|
|
rgroup.long 0x4100++0xB
|
|
line.long 0x00 "CTRLA[16],Queue Manager Queue 16 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[16],Queue Manager Queue 16 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[16],Queue Manager Queue 16 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4100+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[16],Queue Manager Queue 16 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5100++0xB
|
|
line.long 0x00 "QSTATA[16],Queue Manager Queue 16 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[16],Queue Manager Queue 16 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[16],Queue Manager Queue 16 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 17 Registers"
|
|
rgroup.long 0x4110++0xB
|
|
line.long 0x00 "CTRLA[17],Queue Manager Queue 17 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[17],Queue Manager Queue 17 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[17],Queue Manager Queue 17 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4110+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[17],Queue Manager Queue 17 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5110++0xB
|
|
line.long 0x00 "QSTATA[17],Queue Manager Queue 17 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[17],Queue Manager Queue 17 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[17],Queue Manager Queue 17 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 18 Registers"
|
|
rgroup.long 0x4120++0xB
|
|
line.long 0x00 "CTRLA[18],Queue Manager Queue 18 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[18],Queue Manager Queue 18 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[18],Queue Manager Queue 18 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4120+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[18],Queue Manager Queue 18 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5120++0xB
|
|
line.long 0x00 "QSTATA[18],Queue Manager Queue 18 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[18],Queue Manager Queue 18 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[18],Queue Manager Queue 18 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 19 Registers"
|
|
rgroup.long 0x4130++0xB
|
|
line.long 0x00 "CTRLA[19],Queue Manager Queue 19 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[19],Queue Manager Queue 19 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[19],Queue Manager Queue 19 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4130+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[19],Queue Manager Queue 19 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5130++0xB
|
|
line.long 0x00 "QSTATA[19],Queue Manager Queue 19 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[19],Queue Manager Queue 19 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[19],Queue Manager Queue 19 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 20 Registers"
|
|
rgroup.long 0x4140++0xB
|
|
line.long 0x00 "CTRLA[20],Queue Manager Queue 20 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[20],Queue Manager Queue 20 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[20],Queue Manager Queue 20 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4140+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[20],Queue Manager Queue 20 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5140++0xB
|
|
line.long 0x00 "QSTATA[20],Queue Manager Queue 20 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[20],Queue Manager Queue 20 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[20],Queue Manager Queue 20 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 21 Registers"
|
|
rgroup.long 0x4150++0xB
|
|
line.long 0x00 "CTRLA[21],Queue Manager Queue 21 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[21],Queue Manager Queue 21 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[21],Queue Manager Queue 21 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4150+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[21],Queue Manager Queue 21 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5150++0xB
|
|
line.long 0x00 "QSTATA[21],Queue Manager Queue 21 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[21],Queue Manager Queue 21 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[21],Queue Manager Queue 21 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 22 Registers"
|
|
rgroup.long 0x4160++0xB
|
|
line.long 0x00 "CTRLA[22],Queue Manager Queue 22 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[22],Queue Manager Queue 22 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[22],Queue Manager Queue 22 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4160+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[22],Queue Manager Queue 22 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5160++0xB
|
|
line.long 0x00 "QSTATA[22],Queue Manager Queue 22 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[22],Queue Manager Queue 22 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[22],Queue Manager Queue 22 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 23 Registers"
|
|
rgroup.long 0x4170++0xB
|
|
line.long 0x00 "CTRLA[23],Queue Manager Queue 23 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[23],Queue Manager Queue 23 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[23],Queue Manager Queue 23 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4170+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[23],Queue Manager Queue 23 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5170++0xB
|
|
line.long 0x00 "QSTATA[23],Queue Manager Queue 23 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[23],Queue Manager Queue 23 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[23],Queue Manager Queue 23 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 24 Registers"
|
|
rgroup.long 0x4180++0xB
|
|
line.long 0x00 "CTRLA[24],Queue Manager Queue 24 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[24],Queue Manager Queue 24 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[24],Queue Manager Queue 24 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4180+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[24],Queue Manager Queue 24 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5180++0xB
|
|
line.long 0x00 "QSTATA[24],Queue Manager Queue 24 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[24],Queue Manager Queue 24 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[24],Queue Manager Queue 24 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 25 Registers"
|
|
rgroup.long 0x4190++0xB
|
|
line.long 0x00 "CTRLA[25],Queue Manager Queue 25 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[25],Queue Manager Queue 25 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[25],Queue Manager Queue 25 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4190+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[25],Queue Manager Queue 25 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5190++0xB
|
|
line.long 0x00 "QSTATA[25],Queue Manager Queue 25 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[25],Queue Manager Queue 25 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[25],Queue Manager Queue 25 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 26 Registers"
|
|
rgroup.long 0x41A0++0xB
|
|
line.long 0x00 "CTRLA[26],Queue Manager Queue 26 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[26],Queue Manager Queue 26 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[26],Queue Manager Queue 26 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x41A0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[26],Queue Manager Queue 26 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x51A0++0xB
|
|
line.long 0x00 "QSTATA[26],Queue Manager Queue 26 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[26],Queue Manager Queue 26 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[26],Queue Manager Queue 26 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 27 Registers"
|
|
rgroup.long 0x41B0++0xB
|
|
line.long 0x00 "CTRLA[27],Queue Manager Queue 27 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[27],Queue Manager Queue 27 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[27],Queue Manager Queue 27 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x41B0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[27],Queue Manager Queue 27 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x51B0++0xB
|
|
line.long 0x00 "QSTATA[27],Queue Manager Queue 27 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[27],Queue Manager Queue 27 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[27],Queue Manager Queue 27 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 28 Registers"
|
|
rgroup.long 0x41C0++0xB
|
|
line.long 0x00 "CTRLA[28],Queue Manager Queue 28 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[28],Queue Manager Queue 28 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[28],Queue Manager Queue 28 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x41C0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[28],Queue Manager Queue 28 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x51C0++0xB
|
|
line.long 0x00 "QSTATA[28],Queue Manager Queue 28 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[28],Queue Manager Queue 28 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[28],Queue Manager Queue 28 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 29 Registers"
|
|
rgroup.long 0x41D0++0xB
|
|
line.long 0x00 "CTRLA[29],Queue Manager Queue 29 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[29],Queue Manager Queue 29 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[29],Queue Manager Queue 29 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x41D0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[29],Queue Manager Queue 29 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x51D0++0xB
|
|
line.long 0x00 "QSTATA[29],Queue Manager Queue 29 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[29],Queue Manager Queue 29 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[29],Queue Manager Queue 29 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 30 Registers"
|
|
rgroup.long 0x41E0++0xB
|
|
line.long 0x00 "CTRLA[30],Queue Manager Queue 30 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[30],Queue Manager Queue 30 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[30],Queue Manager Queue 30 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x41E0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[30],Queue Manager Queue 30 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x51E0++0xB
|
|
line.long 0x00 "QSTATA[30],Queue Manager Queue 30 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[30],Queue Manager Queue 30 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[30],Queue Manager Queue 30 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 31 Registers"
|
|
rgroup.long 0x41F0++0xB
|
|
line.long 0x00 "CTRLA[31],Queue Manager Queue 31 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[31],Queue Manager Queue 31 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[31],Queue Manager Queue 31 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x41F0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[31],Queue Manager Queue 31 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x51F0++0xB
|
|
line.long 0x00 "QSTATA[31],Queue Manager Queue 31 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[31],Queue Manager Queue 31 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[31],Queue Manager Queue 31 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 32 Registers"
|
|
rgroup.long 0x4200++0xB
|
|
line.long 0x00 "CTRLA[32],Queue Manager Queue 32 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[32],Queue Manager Queue 32 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[32],Queue Manager Queue 32 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4200+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[32],Queue Manager Queue 32 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5200++0xB
|
|
line.long 0x00 "QSTATA[32],Queue Manager Queue 32 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[32],Queue Manager Queue 32 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[32],Queue Manager Queue 32 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 33 Registers"
|
|
rgroup.long 0x4210++0xB
|
|
line.long 0x00 "CTRLA[33],Queue Manager Queue 33 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[33],Queue Manager Queue 33 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[33],Queue Manager Queue 33 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4210+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[33],Queue Manager Queue 33 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5210++0xB
|
|
line.long 0x00 "QSTATA[33],Queue Manager Queue 33 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[33],Queue Manager Queue 33 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[33],Queue Manager Queue 33 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 34 Registers"
|
|
rgroup.long 0x4220++0xB
|
|
line.long 0x00 "CTRLA[34],Queue Manager Queue 34 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[34],Queue Manager Queue 34 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[34],Queue Manager Queue 34 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4220+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[34],Queue Manager Queue 34 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5220++0xB
|
|
line.long 0x00 "QSTATA[34],Queue Manager Queue 34 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[34],Queue Manager Queue 34 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[34],Queue Manager Queue 34 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 35 Registers"
|
|
rgroup.long 0x4230++0xB
|
|
line.long 0x00 "CTRLA[35],Queue Manager Queue 35 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[35],Queue Manager Queue 35 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[35],Queue Manager Queue 35 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4230+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[35],Queue Manager Queue 35 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5230++0xB
|
|
line.long 0x00 "QSTATA[35],Queue Manager Queue 35 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[35],Queue Manager Queue 35 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[35],Queue Manager Queue 35 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 36 Registers"
|
|
rgroup.long 0x4240++0xB
|
|
line.long 0x00 "CTRLA[36],Queue Manager Queue 36 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[36],Queue Manager Queue 36 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[36],Queue Manager Queue 36 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4240+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[36],Queue Manager Queue 36 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5240++0xB
|
|
line.long 0x00 "QSTATA[36],Queue Manager Queue 36 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[36],Queue Manager Queue 36 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[36],Queue Manager Queue 36 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 37 Registers"
|
|
rgroup.long 0x4250++0xB
|
|
line.long 0x00 "CTRLA[37],Queue Manager Queue 37 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[37],Queue Manager Queue 37 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[37],Queue Manager Queue 37 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4250+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[37],Queue Manager Queue 37 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5250++0xB
|
|
line.long 0x00 "QSTATA[37],Queue Manager Queue 37 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[37],Queue Manager Queue 37 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[37],Queue Manager Queue 37 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 38 Registers"
|
|
rgroup.long 0x4260++0xB
|
|
line.long 0x00 "CTRLA[38],Queue Manager Queue 38 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[38],Queue Manager Queue 38 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[38],Queue Manager Queue 38 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4260+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[38],Queue Manager Queue 38 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5260++0xB
|
|
line.long 0x00 "QSTATA[38],Queue Manager Queue 38 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[38],Queue Manager Queue 38 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[38],Queue Manager Queue 38 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 39 Registers"
|
|
rgroup.long 0x4270++0xB
|
|
line.long 0x00 "CTRLA[39],Queue Manager Queue 39 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[39],Queue Manager Queue 39 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[39],Queue Manager Queue 39 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4270+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[39],Queue Manager Queue 39 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5270++0xB
|
|
line.long 0x00 "QSTATA[39],Queue Manager Queue 39 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[39],Queue Manager Queue 39 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[39],Queue Manager Queue 39 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 40 Registers"
|
|
rgroup.long 0x4280++0xB
|
|
line.long 0x00 "CTRLA[40],Queue Manager Queue 40 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[40],Queue Manager Queue 40 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[40],Queue Manager Queue 40 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4280+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[40],Queue Manager Queue 40 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5280++0xB
|
|
line.long 0x00 "QSTATA[40],Queue Manager Queue 40 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[40],Queue Manager Queue 40 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[40],Queue Manager Queue 40 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 41 Registers"
|
|
rgroup.long 0x4290++0xB
|
|
line.long 0x00 "CTRLA[41],Queue Manager Queue 41 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[41],Queue Manager Queue 41 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[41],Queue Manager Queue 41 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4290+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[41],Queue Manager Queue 41 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5290++0xB
|
|
line.long 0x00 "QSTATA[41],Queue Manager Queue 41 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[41],Queue Manager Queue 41 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[41],Queue Manager Queue 41 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 42 Registers"
|
|
rgroup.long 0x42A0++0xB
|
|
line.long 0x00 "CTRLA[42],Queue Manager Queue 42 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[42],Queue Manager Queue 42 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[42],Queue Manager Queue 42 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x42A0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[42],Queue Manager Queue 42 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x52A0++0xB
|
|
line.long 0x00 "QSTATA[42],Queue Manager Queue 42 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[42],Queue Manager Queue 42 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[42],Queue Manager Queue 42 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 43 Registers"
|
|
rgroup.long 0x42B0++0xB
|
|
line.long 0x00 "CTRLA[43],Queue Manager Queue 43 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[43],Queue Manager Queue 43 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[43],Queue Manager Queue 43 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x42B0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[43],Queue Manager Queue 43 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x52B0++0xB
|
|
line.long 0x00 "QSTATA[43],Queue Manager Queue 43 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[43],Queue Manager Queue 43 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[43],Queue Manager Queue 43 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 44 Registers"
|
|
rgroup.long 0x42C0++0xB
|
|
line.long 0x00 "CTRLA[44],Queue Manager Queue 44 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[44],Queue Manager Queue 44 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[44],Queue Manager Queue 44 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x42C0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[44],Queue Manager Queue 44 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x52C0++0xB
|
|
line.long 0x00 "QSTATA[44],Queue Manager Queue 44 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[44],Queue Manager Queue 44 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[44],Queue Manager Queue 44 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 45 Registers"
|
|
rgroup.long 0x42D0++0xB
|
|
line.long 0x00 "CTRLA[45],Queue Manager Queue 45 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[45],Queue Manager Queue 45 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[45],Queue Manager Queue 45 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x42D0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[45],Queue Manager Queue 45 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x52D0++0xB
|
|
line.long 0x00 "QSTATA[45],Queue Manager Queue 45 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[45],Queue Manager Queue 45 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[45],Queue Manager Queue 45 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 46 Registers"
|
|
rgroup.long 0x42E0++0xB
|
|
line.long 0x00 "CTRLA[46],Queue Manager Queue 46 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[46],Queue Manager Queue 46 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[46],Queue Manager Queue 46 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x42E0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[46],Queue Manager Queue 46 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x52E0++0xB
|
|
line.long 0x00 "QSTATA[46],Queue Manager Queue 46 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[46],Queue Manager Queue 46 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[46],Queue Manager Queue 46 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 47 Registers"
|
|
rgroup.long 0x42F0++0xB
|
|
line.long 0x00 "CTRLA[47],Queue Manager Queue 47 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[47],Queue Manager Queue 47 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[47],Queue Manager Queue 47 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x42F0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[47],Queue Manager Queue 47 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x52F0++0xB
|
|
line.long 0x00 "QSTATA[47],Queue Manager Queue 47 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[47],Queue Manager Queue 47 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[47],Queue Manager Queue 47 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 48 Registers"
|
|
rgroup.long 0x4300++0xB
|
|
line.long 0x00 "CTRLA[48],Queue Manager Queue 48 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[48],Queue Manager Queue 48 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[48],Queue Manager Queue 48 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4300+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[48],Queue Manager Queue 48 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5300++0xB
|
|
line.long 0x00 "QSTATA[48],Queue Manager Queue 48 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[48],Queue Manager Queue 48 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[48],Queue Manager Queue 48 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 49 Registers"
|
|
rgroup.long 0x4310++0xB
|
|
line.long 0x00 "CTRLA[49],Queue Manager Queue 49 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[49],Queue Manager Queue 49 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[49],Queue Manager Queue 49 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4310+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[49],Queue Manager Queue 49 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5310++0xB
|
|
line.long 0x00 "QSTATA[49],Queue Manager Queue 49 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[49],Queue Manager Queue 49 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[49],Queue Manager Queue 49 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 50 Registers"
|
|
rgroup.long 0x4320++0xB
|
|
line.long 0x00 "CTRLA[50],Queue Manager Queue 50 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[50],Queue Manager Queue 50 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[50],Queue Manager Queue 50 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4320+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[50],Queue Manager Queue 50 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5320++0xB
|
|
line.long 0x00 "QSTATA[50],Queue Manager Queue 50 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[50],Queue Manager Queue 50 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[50],Queue Manager Queue 50 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 51 Registers"
|
|
rgroup.long 0x4330++0xB
|
|
line.long 0x00 "CTRLA[51],Queue Manager Queue 51 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[51],Queue Manager Queue 51 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[51],Queue Manager Queue 51 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4330+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[51],Queue Manager Queue 51 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5330++0xB
|
|
line.long 0x00 "QSTATA[51],Queue Manager Queue 51 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[51],Queue Manager Queue 51 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[51],Queue Manager Queue 51 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 52 Registers"
|
|
rgroup.long 0x4340++0xB
|
|
line.long 0x00 "CTRLA[52],Queue Manager Queue 52 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[52],Queue Manager Queue 52 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[52],Queue Manager Queue 52 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4340+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[52],Queue Manager Queue 52 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5340++0xB
|
|
line.long 0x00 "QSTATA[52],Queue Manager Queue 52 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[52],Queue Manager Queue 52 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[52],Queue Manager Queue 52 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 53 Registers"
|
|
rgroup.long 0x4350++0xB
|
|
line.long 0x00 "CTRLA[53],Queue Manager Queue 53 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[53],Queue Manager Queue 53 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[53],Queue Manager Queue 53 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4350+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[53],Queue Manager Queue 53 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5350++0xB
|
|
line.long 0x00 "QSTATA[53],Queue Manager Queue 53 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[53],Queue Manager Queue 53 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[53],Queue Manager Queue 53 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 54 Registers"
|
|
rgroup.long 0x4360++0xB
|
|
line.long 0x00 "CTRLA[54],Queue Manager Queue 54 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[54],Queue Manager Queue 54 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[54],Queue Manager Queue 54 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4360+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[54],Queue Manager Queue 54 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5360++0xB
|
|
line.long 0x00 "QSTATA[54],Queue Manager Queue 54 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[54],Queue Manager Queue 54 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[54],Queue Manager Queue 54 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 55 Registers"
|
|
rgroup.long 0x4370++0xB
|
|
line.long 0x00 "CTRLA[55],Queue Manager Queue 55 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[55],Queue Manager Queue 55 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[55],Queue Manager Queue 55 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4370+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[55],Queue Manager Queue 55 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5370++0xB
|
|
line.long 0x00 "QSTATA[55],Queue Manager Queue 55 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[55],Queue Manager Queue 55 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[55],Queue Manager Queue 55 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 56 Registers"
|
|
rgroup.long 0x4380++0xB
|
|
line.long 0x00 "CTRLA[56],Queue Manager Queue 56 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[56],Queue Manager Queue 56 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[56],Queue Manager Queue 56 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4380+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[56],Queue Manager Queue 56 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5380++0xB
|
|
line.long 0x00 "QSTATA[56],Queue Manager Queue 56 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[56],Queue Manager Queue 56 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[56],Queue Manager Queue 56 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 57 Registers"
|
|
rgroup.long 0x4390++0xB
|
|
line.long 0x00 "CTRLA[57],Queue Manager Queue 57 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[57],Queue Manager Queue 57 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[57],Queue Manager Queue 57 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4390+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[57],Queue Manager Queue 57 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5390++0xB
|
|
line.long 0x00 "QSTATA[57],Queue Manager Queue 57 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[57],Queue Manager Queue 57 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[57],Queue Manager Queue 57 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 58 Registers"
|
|
rgroup.long 0x43A0++0xB
|
|
line.long 0x00 "CTRLA[58],Queue Manager Queue 58 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[58],Queue Manager Queue 58 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[58],Queue Manager Queue 58 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x43A0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[58],Queue Manager Queue 58 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x53A0++0xB
|
|
line.long 0x00 "QSTATA[58],Queue Manager Queue 58 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[58],Queue Manager Queue 58 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[58],Queue Manager Queue 58 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 59 Registers"
|
|
rgroup.long 0x43B0++0xB
|
|
line.long 0x00 "CTRLA[59],Queue Manager Queue 59 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[59],Queue Manager Queue 59 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[59],Queue Manager Queue 59 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x43B0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[59],Queue Manager Queue 59 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x53B0++0xB
|
|
line.long 0x00 "QSTATA[59],Queue Manager Queue 59 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[59],Queue Manager Queue 59 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[59],Queue Manager Queue 59 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 60 Registers"
|
|
rgroup.long 0x43C0++0xB
|
|
line.long 0x00 "CTRLA[60],Queue Manager Queue 60 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[60],Queue Manager Queue 60 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[60],Queue Manager Queue 60 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x43C0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[60],Queue Manager Queue 60 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x53C0++0xB
|
|
line.long 0x00 "QSTATA[60],Queue Manager Queue 60 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[60],Queue Manager Queue 60 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[60],Queue Manager Queue 60 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 61 Registers"
|
|
rgroup.long 0x43D0++0xB
|
|
line.long 0x00 "CTRLA[61],Queue Manager Queue 61 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[61],Queue Manager Queue 61 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[61],Queue Manager Queue 61 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x43D0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[61],Queue Manager Queue 61 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x53D0++0xB
|
|
line.long 0x00 "QSTATA[61],Queue Manager Queue 61 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[61],Queue Manager Queue 61 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[61],Queue Manager Queue 61 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 62 Registers"
|
|
rgroup.long 0x43E0++0xB
|
|
line.long 0x00 "CTRLA[62],Queue Manager Queue 62 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[62],Queue Manager Queue 62 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[62],Queue Manager Queue 62 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x43E0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[62],Queue Manager Queue 62 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x53E0++0xB
|
|
line.long 0x00 "QSTATA[62],Queue Manager Queue 62 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[62],Queue Manager Queue 62 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[62],Queue Manager Queue 62 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 63 Registers"
|
|
rgroup.long 0x43F0++0xB
|
|
line.long 0x00 "CTRLA[63],Queue Manager Queue 63 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[63],Queue Manager Queue 63 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[63],Queue Manager Queue 63 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x43F0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[63],Queue Manager Queue 63 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x53F0++0xB
|
|
line.long 0x00 "QSTATA[63],Queue Manager Queue 63 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[63],Queue Manager Queue 63 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[63],Queue Manager Queue 63 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 64 Registers"
|
|
rgroup.long 0x4400++0xB
|
|
line.long 0x00 "CTRLA[64],Queue Manager Queue 64 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[64],Queue Manager Queue 64 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[64],Queue Manager Queue 64 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4400+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[64],Queue Manager Queue 64 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5400++0xB
|
|
line.long 0x00 "QSTATA[64],Queue Manager Queue 64 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[64],Queue Manager Queue 64 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[64],Queue Manager Queue 64 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 65 Registers"
|
|
rgroup.long 0x4410++0xB
|
|
line.long 0x00 "CTRLA[65],Queue Manager Queue 65 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[65],Queue Manager Queue 65 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[65],Queue Manager Queue 65 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4410+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[65],Queue Manager Queue 65 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5410++0xB
|
|
line.long 0x00 "QSTATA[65],Queue Manager Queue 65 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[65],Queue Manager Queue 65 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[65],Queue Manager Queue 65 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 66 Registers"
|
|
rgroup.long 0x4420++0xB
|
|
line.long 0x00 "CTRLA[66],Queue Manager Queue 66 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[66],Queue Manager Queue 66 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[66],Queue Manager Queue 66 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4420+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[66],Queue Manager Queue 66 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5420++0xB
|
|
line.long 0x00 "QSTATA[66],Queue Manager Queue 66 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[66],Queue Manager Queue 66 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[66],Queue Manager Queue 66 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 67 Registers"
|
|
rgroup.long 0x4430++0xB
|
|
line.long 0x00 "CTRLA[67],Queue Manager Queue 67 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[67],Queue Manager Queue 67 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[67],Queue Manager Queue 67 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4430+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[67],Queue Manager Queue 67 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5430++0xB
|
|
line.long 0x00 "QSTATA[67],Queue Manager Queue 67 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[67],Queue Manager Queue 67 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[67],Queue Manager Queue 67 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 68 Registers"
|
|
rgroup.long 0x4440++0xB
|
|
line.long 0x00 "CTRLA[68],Queue Manager Queue 68 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[68],Queue Manager Queue 68 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[68],Queue Manager Queue 68 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4440+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[68],Queue Manager Queue 68 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5440++0xB
|
|
line.long 0x00 "QSTATA[68],Queue Manager Queue 68 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[68],Queue Manager Queue 68 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[68],Queue Manager Queue 68 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 69 Registers"
|
|
rgroup.long 0x4450++0xB
|
|
line.long 0x00 "CTRLA[69],Queue Manager Queue 69 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[69],Queue Manager Queue 69 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[69],Queue Manager Queue 69 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4450+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[69],Queue Manager Queue 69 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5450++0xB
|
|
line.long 0x00 "QSTATA[69],Queue Manager Queue 69 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[69],Queue Manager Queue 69 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[69],Queue Manager Queue 69 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 70 Registers"
|
|
rgroup.long 0x4460++0xB
|
|
line.long 0x00 "CTRLA[70],Queue Manager Queue 70 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[70],Queue Manager Queue 70 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[70],Queue Manager Queue 70 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4460+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[70],Queue Manager Queue 70 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5460++0xB
|
|
line.long 0x00 "QSTATA[70],Queue Manager Queue 70 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[70],Queue Manager Queue 70 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[70],Queue Manager Queue 70 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 71 Registers"
|
|
rgroup.long 0x4470++0xB
|
|
line.long 0x00 "CTRLA[71],Queue Manager Queue 71 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[71],Queue Manager Queue 71 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[71],Queue Manager Queue 71 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4470+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[71],Queue Manager Queue 71 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5470++0xB
|
|
line.long 0x00 "QSTATA[71],Queue Manager Queue 71 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[71],Queue Manager Queue 71 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[71],Queue Manager Queue 71 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 72 Registers"
|
|
rgroup.long 0x4480++0xB
|
|
line.long 0x00 "CTRLA[72],Queue Manager Queue 72 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[72],Queue Manager Queue 72 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[72],Queue Manager Queue 72 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4480+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[72],Queue Manager Queue 72 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5480++0xB
|
|
line.long 0x00 "QSTATA[72],Queue Manager Queue 72 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[72],Queue Manager Queue 72 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[72],Queue Manager Queue 72 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 73 Registers"
|
|
rgroup.long 0x4490++0xB
|
|
line.long 0x00 "CTRLA[73],Queue Manager Queue 73 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[73],Queue Manager Queue 73 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[73],Queue Manager Queue 73 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4490+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[73],Queue Manager Queue 73 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5490++0xB
|
|
line.long 0x00 "QSTATA[73],Queue Manager Queue 73 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[73],Queue Manager Queue 73 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[73],Queue Manager Queue 73 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 74 Registers"
|
|
rgroup.long 0x44A0++0xB
|
|
line.long 0x00 "CTRLA[74],Queue Manager Queue 74 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[74],Queue Manager Queue 74 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[74],Queue Manager Queue 74 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x44A0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[74],Queue Manager Queue 74 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x54A0++0xB
|
|
line.long 0x00 "QSTATA[74],Queue Manager Queue 74 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[74],Queue Manager Queue 74 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[74],Queue Manager Queue 74 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 75 Registers"
|
|
rgroup.long 0x44B0++0xB
|
|
line.long 0x00 "CTRLA[75],Queue Manager Queue 75 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[75],Queue Manager Queue 75 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[75],Queue Manager Queue 75 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x44B0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[75],Queue Manager Queue 75 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x54B0++0xB
|
|
line.long 0x00 "QSTATA[75],Queue Manager Queue 75 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[75],Queue Manager Queue 75 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[75],Queue Manager Queue 75 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 76 Registers"
|
|
rgroup.long 0x44C0++0xB
|
|
line.long 0x00 "CTRLA[76],Queue Manager Queue 76 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[76],Queue Manager Queue 76 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[76],Queue Manager Queue 76 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x44C0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[76],Queue Manager Queue 76 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x54C0++0xB
|
|
line.long 0x00 "QSTATA[76],Queue Manager Queue 76 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[76],Queue Manager Queue 76 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[76],Queue Manager Queue 76 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 77 Registers"
|
|
rgroup.long 0x44D0++0xB
|
|
line.long 0x00 "CTRLA[77],Queue Manager Queue 77 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[77],Queue Manager Queue 77 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[77],Queue Manager Queue 77 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x44D0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[77],Queue Manager Queue 77 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x54D0++0xB
|
|
line.long 0x00 "QSTATA[77],Queue Manager Queue 77 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[77],Queue Manager Queue 77 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[77],Queue Manager Queue 77 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 78 Registers"
|
|
rgroup.long 0x44E0++0xB
|
|
line.long 0x00 "CTRLA[78],Queue Manager Queue 78 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[78],Queue Manager Queue 78 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[78],Queue Manager Queue 78 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x44E0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[78],Queue Manager Queue 78 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x54E0++0xB
|
|
line.long 0x00 "QSTATA[78],Queue Manager Queue 78 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[78],Queue Manager Queue 78 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[78],Queue Manager Queue 78 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 79 Registers"
|
|
rgroup.long 0x44F0++0xB
|
|
line.long 0x00 "CTRLA[79],Queue Manager Queue 79 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[79],Queue Manager Queue 79 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[79],Queue Manager Queue 79 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x44F0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[79],Queue Manager Queue 79 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x54F0++0xB
|
|
line.long 0x00 "QSTATA[79],Queue Manager Queue 79 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[79],Queue Manager Queue 79 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[79],Queue Manager Queue 79 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 80 Registers"
|
|
rgroup.long 0x4500++0xB
|
|
line.long 0x00 "CTRLA[80],Queue Manager Queue 80 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[80],Queue Manager Queue 80 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[80],Queue Manager Queue 80 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4500+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[80],Queue Manager Queue 80 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5500++0xB
|
|
line.long 0x00 "QSTATA[80],Queue Manager Queue 80 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[80],Queue Manager Queue 80 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[80],Queue Manager Queue 80 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 81 Registers"
|
|
rgroup.long 0x4510++0xB
|
|
line.long 0x00 "CTRLA[81],Queue Manager Queue 81 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[81],Queue Manager Queue 81 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[81],Queue Manager Queue 81 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4510+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[81],Queue Manager Queue 81 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5510++0xB
|
|
line.long 0x00 "QSTATA[81],Queue Manager Queue 81 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[81],Queue Manager Queue 81 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[81],Queue Manager Queue 81 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 82 Registers"
|
|
rgroup.long 0x4520++0xB
|
|
line.long 0x00 "CTRLA[82],Queue Manager Queue 82 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[82],Queue Manager Queue 82 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[82],Queue Manager Queue 82 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4520+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[82],Queue Manager Queue 82 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5520++0xB
|
|
line.long 0x00 "QSTATA[82],Queue Manager Queue 82 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[82],Queue Manager Queue 82 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[82],Queue Manager Queue 82 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 83 Registers"
|
|
rgroup.long 0x4530++0xB
|
|
line.long 0x00 "CTRLA[83],Queue Manager Queue 83 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[83],Queue Manager Queue 83 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[83],Queue Manager Queue 83 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4530+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[83],Queue Manager Queue 83 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5530++0xB
|
|
line.long 0x00 "QSTATA[83],Queue Manager Queue 83 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[83],Queue Manager Queue 83 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[83],Queue Manager Queue 83 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 84 Registers"
|
|
rgroup.long 0x4540++0xB
|
|
line.long 0x00 "CTRLA[84],Queue Manager Queue 84 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[84],Queue Manager Queue 84 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[84],Queue Manager Queue 84 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4540+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[84],Queue Manager Queue 84 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5540++0xB
|
|
line.long 0x00 "QSTATA[84],Queue Manager Queue 84 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[84],Queue Manager Queue 84 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[84],Queue Manager Queue 84 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 85 Registers"
|
|
rgroup.long 0x4550++0xB
|
|
line.long 0x00 "CTRLA[85],Queue Manager Queue 85 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[85],Queue Manager Queue 85 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[85],Queue Manager Queue 85 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4550+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[85],Queue Manager Queue 85 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5550++0xB
|
|
line.long 0x00 "QSTATA[85],Queue Manager Queue 85 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[85],Queue Manager Queue 85 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[85],Queue Manager Queue 85 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 86 Registers"
|
|
rgroup.long 0x4560++0xB
|
|
line.long 0x00 "CTRLA[86],Queue Manager Queue 86 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[86],Queue Manager Queue 86 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[86],Queue Manager Queue 86 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4560+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[86],Queue Manager Queue 86 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5560++0xB
|
|
line.long 0x00 "QSTATA[86],Queue Manager Queue 86 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[86],Queue Manager Queue 86 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[86],Queue Manager Queue 86 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 87 Registers"
|
|
rgroup.long 0x4570++0xB
|
|
line.long 0x00 "CTRLA[87],Queue Manager Queue 87 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[87],Queue Manager Queue 87 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[87],Queue Manager Queue 87 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4570+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[87],Queue Manager Queue 87 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5570++0xB
|
|
line.long 0x00 "QSTATA[87],Queue Manager Queue 87 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[87],Queue Manager Queue 87 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[87],Queue Manager Queue 87 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 88 Registers"
|
|
rgroup.long 0x4580++0xB
|
|
line.long 0x00 "CTRLA[88],Queue Manager Queue 88 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[88],Queue Manager Queue 88 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[88],Queue Manager Queue 88 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4580+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[88],Queue Manager Queue 88 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5580++0xB
|
|
line.long 0x00 "QSTATA[88],Queue Manager Queue 88 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[88],Queue Manager Queue 88 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[88],Queue Manager Queue 88 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 89 Registers"
|
|
rgroup.long 0x4590++0xB
|
|
line.long 0x00 "CTRLA[89],Queue Manager Queue 89 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[89],Queue Manager Queue 89 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[89],Queue Manager Queue 89 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4590+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[89],Queue Manager Queue 89 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5590++0xB
|
|
line.long 0x00 "QSTATA[89],Queue Manager Queue 89 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[89],Queue Manager Queue 89 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[89],Queue Manager Queue 89 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 90 Registers"
|
|
rgroup.long 0x45A0++0xB
|
|
line.long 0x00 "CTRLA[90],Queue Manager Queue 90 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[90],Queue Manager Queue 90 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[90],Queue Manager Queue 90 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x45A0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[90],Queue Manager Queue 90 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x55A0++0xB
|
|
line.long 0x00 "QSTATA[90],Queue Manager Queue 90 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[90],Queue Manager Queue 90 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[90],Queue Manager Queue 90 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 91 Registers"
|
|
rgroup.long 0x45B0++0xB
|
|
line.long 0x00 "CTRLA[91],Queue Manager Queue 91 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[91],Queue Manager Queue 91 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[91],Queue Manager Queue 91 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x45B0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[91],Queue Manager Queue 91 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x55B0++0xB
|
|
line.long 0x00 "QSTATA[91],Queue Manager Queue 91 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[91],Queue Manager Queue 91 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[91],Queue Manager Queue 91 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 92 Registers"
|
|
rgroup.long 0x45C0++0xB
|
|
line.long 0x00 "CTRLA[92],Queue Manager Queue 92 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[92],Queue Manager Queue 92 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[92],Queue Manager Queue 92 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x45C0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[92],Queue Manager Queue 92 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x55C0++0xB
|
|
line.long 0x00 "QSTATA[92],Queue Manager Queue 92 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[92],Queue Manager Queue 92 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[92],Queue Manager Queue 92 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 93 Registers"
|
|
rgroup.long 0x45D0++0xB
|
|
line.long 0x00 "CTRLA[93],Queue Manager Queue 93 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[93],Queue Manager Queue 93 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[93],Queue Manager Queue 93 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x45D0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[93],Queue Manager Queue 93 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x55D0++0xB
|
|
line.long 0x00 "QSTATA[93],Queue Manager Queue 93 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[93],Queue Manager Queue 93 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[93],Queue Manager Queue 93 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 94 Registers"
|
|
rgroup.long 0x45E0++0xB
|
|
line.long 0x00 "CTRLA[94],Queue Manager Queue 94 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[94],Queue Manager Queue 94 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[94],Queue Manager Queue 94 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x45E0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[94],Queue Manager Queue 94 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x55E0++0xB
|
|
line.long 0x00 "QSTATA[94],Queue Manager Queue 94 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[94],Queue Manager Queue 94 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[94],Queue Manager Queue 94 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 95 Registers"
|
|
rgroup.long 0x45F0++0xB
|
|
line.long 0x00 "CTRLA[95],Queue Manager Queue 95 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[95],Queue Manager Queue 95 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[95],Queue Manager Queue 95 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x45F0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[95],Queue Manager Queue 95 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x55F0++0xB
|
|
line.long 0x00 "QSTATA[95],Queue Manager Queue 95 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[95],Queue Manager Queue 95 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[95],Queue Manager Queue 95 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 96 Registers"
|
|
rgroup.long 0x4600++0xB
|
|
line.long 0x00 "CTRLA[96],Queue Manager Queue 96 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[96],Queue Manager Queue 96 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[96],Queue Manager Queue 96 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4600+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[96],Queue Manager Queue 96 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5600++0xB
|
|
line.long 0x00 "QSTATA[96],Queue Manager Queue 96 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[96],Queue Manager Queue 96 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[96],Queue Manager Queue 96 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 97 Registers"
|
|
rgroup.long 0x4610++0xB
|
|
line.long 0x00 "CTRLA[97],Queue Manager Queue 97 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[97],Queue Manager Queue 97 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[97],Queue Manager Queue 97 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4610+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[97],Queue Manager Queue 97 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5610++0xB
|
|
line.long 0x00 "QSTATA[97],Queue Manager Queue 97 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[97],Queue Manager Queue 97 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[97],Queue Manager Queue 97 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 98 Registers"
|
|
rgroup.long 0x4620++0xB
|
|
line.long 0x00 "CTRLA[98],Queue Manager Queue 98 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[98],Queue Manager Queue 98 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[98],Queue Manager Queue 98 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4620+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[98],Queue Manager Queue 98 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5620++0xB
|
|
line.long 0x00 "QSTATA[98],Queue Manager Queue 98 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[98],Queue Manager Queue 98 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[98],Queue Manager Queue 98 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 99 Registers"
|
|
rgroup.long 0x4630++0xB
|
|
line.long 0x00 "CTRLA[99],Queue Manager Queue 99 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[99],Queue Manager Queue 99 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[99],Queue Manager Queue 99 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4630+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[99],Queue Manager Queue 99 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5630++0xB
|
|
line.long 0x00 "QSTATA[99],Queue Manager Queue 99 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[99],Queue Manager Queue 99 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[99],Queue Manager Queue 99 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 100 Registers"
|
|
rgroup.long 0x4640++0xB
|
|
line.long 0x00 "CTRLA[100],Queue Manager Queue 100 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[100],Queue Manager Queue 100 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[100],Queue Manager Queue 100 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4640+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[100],Queue Manager Queue 100 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5640++0xB
|
|
line.long 0x00 "QSTATA[100],Queue Manager Queue 100 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[100],Queue Manager Queue 100 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[100],Queue Manager Queue 100 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 101 Registers"
|
|
rgroup.long 0x4650++0xB
|
|
line.long 0x00 "CTRLA[101],Queue Manager Queue 101 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[101],Queue Manager Queue 101 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[101],Queue Manager Queue 101 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4650+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[101],Queue Manager Queue 101 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5650++0xB
|
|
line.long 0x00 "QSTATA[101],Queue Manager Queue 101 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[101],Queue Manager Queue 101 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[101],Queue Manager Queue 101 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 102 Registers"
|
|
rgroup.long 0x4660++0xB
|
|
line.long 0x00 "CTRLA[102],Queue Manager Queue 102 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[102],Queue Manager Queue 102 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[102],Queue Manager Queue 102 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4660+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[102],Queue Manager Queue 102 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5660++0xB
|
|
line.long 0x00 "QSTATA[102],Queue Manager Queue 102 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[102],Queue Manager Queue 102 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[102],Queue Manager Queue 102 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 103 Registers"
|
|
rgroup.long 0x4670++0xB
|
|
line.long 0x00 "CTRLA[103],Queue Manager Queue 103 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[103],Queue Manager Queue 103 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[103],Queue Manager Queue 103 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4670+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[103],Queue Manager Queue 103 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5670++0xB
|
|
line.long 0x00 "QSTATA[103],Queue Manager Queue 103 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[103],Queue Manager Queue 103 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[103],Queue Manager Queue 103 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 104 Registers"
|
|
rgroup.long 0x4680++0xB
|
|
line.long 0x00 "CTRLA[104],Queue Manager Queue 104 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[104],Queue Manager Queue 104 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[104],Queue Manager Queue 104 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4680+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[104],Queue Manager Queue 104 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5680++0xB
|
|
line.long 0x00 "QSTATA[104],Queue Manager Queue 104 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[104],Queue Manager Queue 104 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[104],Queue Manager Queue 104 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 105 Registers"
|
|
rgroup.long 0x4690++0xB
|
|
line.long 0x00 "CTRLA[105],Queue Manager Queue 105 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[105],Queue Manager Queue 105 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[105],Queue Manager Queue 105 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4690+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[105],Queue Manager Queue 105 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5690++0xB
|
|
line.long 0x00 "QSTATA[105],Queue Manager Queue 105 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[105],Queue Manager Queue 105 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[105],Queue Manager Queue 105 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 106 Registers"
|
|
rgroup.long 0x46A0++0xB
|
|
line.long 0x00 "CTRLA[106],Queue Manager Queue 106 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[106],Queue Manager Queue 106 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[106],Queue Manager Queue 106 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x46A0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[106],Queue Manager Queue 106 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x56A0++0xB
|
|
line.long 0x00 "QSTATA[106],Queue Manager Queue 106 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[106],Queue Manager Queue 106 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[106],Queue Manager Queue 106 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 107 Registers"
|
|
rgroup.long 0x46B0++0xB
|
|
line.long 0x00 "CTRLA[107],Queue Manager Queue 107 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[107],Queue Manager Queue 107 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[107],Queue Manager Queue 107 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x46B0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[107],Queue Manager Queue 107 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x56B0++0xB
|
|
line.long 0x00 "QSTATA[107],Queue Manager Queue 107 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[107],Queue Manager Queue 107 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[107],Queue Manager Queue 107 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 108 Registers"
|
|
rgroup.long 0x46C0++0xB
|
|
line.long 0x00 "CTRLA[108],Queue Manager Queue 108 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[108],Queue Manager Queue 108 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[108],Queue Manager Queue 108 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x46C0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[108],Queue Manager Queue 108 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x56C0++0xB
|
|
line.long 0x00 "QSTATA[108],Queue Manager Queue 108 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[108],Queue Manager Queue 108 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[108],Queue Manager Queue 108 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 109 Registers"
|
|
rgroup.long 0x46D0++0xB
|
|
line.long 0x00 "CTRLA[109],Queue Manager Queue 109 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[109],Queue Manager Queue 109 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[109],Queue Manager Queue 109 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x46D0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[109],Queue Manager Queue 109 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x56D0++0xB
|
|
line.long 0x00 "QSTATA[109],Queue Manager Queue 109 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[109],Queue Manager Queue 109 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[109],Queue Manager Queue 109 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 110 Registers"
|
|
rgroup.long 0x46E0++0xB
|
|
line.long 0x00 "CTRLA[110],Queue Manager Queue 110 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[110],Queue Manager Queue 110 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[110],Queue Manager Queue 110 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x46E0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[110],Queue Manager Queue 110 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x56E0++0xB
|
|
line.long 0x00 "QSTATA[110],Queue Manager Queue 110 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[110],Queue Manager Queue 110 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[110],Queue Manager Queue 110 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 111 Registers"
|
|
rgroup.long 0x46F0++0xB
|
|
line.long 0x00 "CTRLA[111],Queue Manager Queue 111 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[111],Queue Manager Queue 111 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[111],Queue Manager Queue 111 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x46F0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[111],Queue Manager Queue 111 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x56F0++0xB
|
|
line.long 0x00 "QSTATA[111],Queue Manager Queue 111 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[111],Queue Manager Queue 111 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[111],Queue Manager Queue 111 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 112 Registers"
|
|
rgroup.long 0x4700++0xB
|
|
line.long 0x00 "CTRLA[112],Queue Manager Queue 112 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[112],Queue Manager Queue 112 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[112],Queue Manager Queue 112 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4700+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[112],Queue Manager Queue 112 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5700++0xB
|
|
line.long 0x00 "QSTATA[112],Queue Manager Queue 112 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[112],Queue Manager Queue 112 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[112],Queue Manager Queue 112 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 113 Registers"
|
|
rgroup.long 0x4710++0xB
|
|
line.long 0x00 "CTRLA[113],Queue Manager Queue 113 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[113],Queue Manager Queue 113 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[113],Queue Manager Queue 113 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4710+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[113],Queue Manager Queue 113 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5710++0xB
|
|
line.long 0x00 "QSTATA[113],Queue Manager Queue 113 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[113],Queue Manager Queue 113 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[113],Queue Manager Queue 113 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 114 Registers"
|
|
rgroup.long 0x4720++0xB
|
|
line.long 0x00 "CTRLA[114],Queue Manager Queue 114 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[114],Queue Manager Queue 114 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[114],Queue Manager Queue 114 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4720+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[114],Queue Manager Queue 114 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5720++0xB
|
|
line.long 0x00 "QSTATA[114],Queue Manager Queue 114 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[114],Queue Manager Queue 114 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[114],Queue Manager Queue 114 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 115 Registers"
|
|
rgroup.long 0x4730++0xB
|
|
line.long 0x00 "CTRLA[115],Queue Manager Queue 115 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[115],Queue Manager Queue 115 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[115],Queue Manager Queue 115 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4730+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[115],Queue Manager Queue 115 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5730++0xB
|
|
line.long 0x00 "QSTATA[115],Queue Manager Queue 115 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[115],Queue Manager Queue 115 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[115],Queue Manager Queue 115 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 116 Registers"
|
|
rgroup.long 0x4740++0xB
|
|
line.long 0x00 "CTRLA[116],Queue Manager Queue 116 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[116],Queue Manager Queue 116 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[116],Queue Manager Queue 116 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4740+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[116],Queue Manager Queue 116 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5740++0xB
|
|
line.long 0x00 "QSTATA[116],Queue Manager Queue 116 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[116],Queue Manager Queue 116 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[116],Queue Manager Queue 116 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 117 Registers"
|
|
rgroup.long 0x4750++0xB
|
|
line.long 0x00 "CTRLA[117],Queue Manager Queue 117 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[117],Queue Manager Queue 117 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[117],Queue Manager Queue 117 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4750+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[117],Queue Manager Queue 117 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5750++0xB
|
|
line.long 0x00 "QSTATA[117],Queue Manager Queue 117 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[117],Queue Manager Queue 117 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[117],Queue Manager Queue 117 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 118 Registers"
|
|
rgroup.long 0x4760++0xB
|
|
line.long 0x00 "CTRLA[118],Queue Manager Queue 118 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[118],Queue Manager Queue 118 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[118],Queue Manager Queue 118 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4760+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[118],Queue Manager Queue 118 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5760++0xB
|
|
line.long 0x00 "QSTATA[118],Queue Manager Queue 118 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[118],Queue Manager Queue 118 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[118],Queue Manager Queue 118 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 119 Registers"
|
|
rgroup.long 0x4770++0xB
|
|
line.long 0x00 "CTRLA[119],Queue Manager Queue 119 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[119],Queue Manager Queue 119 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[119],Queue Manager Queue 119 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4770+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[119],Queue Manager Queue 119 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5770++0xB
|
|
line.long 0x00 "QSTATA[119],Queue Manager Queue 119 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[119],Queue Manager Queue 119 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[119],Queue Manager Queue 119 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 120 Registers"
|
|
rgroup.long 0x4780++0xB
|
|
line.long 0x00 "CTRLA[120],Queue Manager Queue 120 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[120],Queue Manager Queue 120 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[120],Queue Manager Queue 120 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4780+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[120],Queue Manager Queue 120 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5780++0xB
|
|
line.long 0x00 "QSTATA[120],Queue Manager Queue 120 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[120],Queue Manager Queue 120 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[120],Queue Manager Queue 120 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 121 Registers"
|
|
rgroup.long 0x4790++0xB
|
|
line.long 0x00 "CTRLA[121],Queue Manager Queue 121 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[121],Queue Manager Queue 121 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[121],Queue Manager Queue 121 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4790+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[121],Queue Manager Queue 121 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5790++0xB
|
|
line.long 0x00 "QSTATA[121],Queue Manager Queue 121 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[121],Queue Manager Queue 121 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[121],Queue Manager Queue 121 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 122 Registers"
|
|
rgroup.long 0x47A0++0xB
|
|
line.long 0x00 "CTRLA[122],Queue Manager Queue 122 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[122],Queue Manager Queue 122 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[122],Queue Manager Queue 122 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x47A0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[122],Queue Manager Queue 122 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x57A0++0xB
|
|
line.long 0x00 "QSTATA[122],Queue Manager Queue 122 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[122],Queue Manager Queue 122 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[122],Queue Manager Queue 122 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 123 Registers"
|
|
rgroup.long 0x47B0++0xB
|
|
line.long 0x00 "CTRLA[123],Queue Manager Queue 123 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[123],Queue Manager Queue 123 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[123],Queue Manager Queue 123 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x47B0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[123],Queue Manager Queue 123 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x57B0++0xB
|
|
line.long 0x00 "QSTATA[123],Queue Manager Queue 123 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[123],Queue Manager Queue 123 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[123],Queue Manager Queue 123 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 124 Registers"
|
|
rgroup.long 0x47C0++0xB
|
|
line.long 0x00 "CTRLA[124],Queue Manager Queue 124 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[124],Queue Manager Queue 124 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[124],Queue Manager Queue 124 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x47C0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[124],Queue Manager Queue 124 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x57C0++0xB
|
|
line.long 0x00 "QSTATA[124],Queue Manager Queue 124 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[124],Queue Manager Queue 124 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[124],Queue Manager Queue 124 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 125 Registers"
|
|
rgroup.long 0x47D0++0xB
|
|
line.long 0x00 "CTRLA[125],Queue Manager Queue 125 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[125],Queue Manager Queue 125 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[125],Queue Manager Queue 125 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x47D0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[125],Queue Manager Queue 125 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x57D0++0xB
|
|
line.long 0x00 "QSTATA[125],Queue Manager Queue 125 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[125],Queue Manager Queue 125 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[125],Queue Manager Queue 125 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 126 Registers"
|
|
rgroup.long 0x47E0++0xB
|
|
line.long 0x00 "CTRLA[126],Queue Manager Queue 126 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[126],Queue Manager Queue 126 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[126],Queue Manager Queue 126 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x47E0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[126],Queue Manager Queue 126 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x57E0++0xB
|
|
line.long 0x00 "QSTATA[126],Queue Manager Queue 126 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[126],Queue Manager Queue 126 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[126],Queue Manager Queue 126 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 127 Registers"
|
|
rgroup.long 0x47F0++0xB
|
|
line.long 0x00 "CTRLA[127],Queue Manager Queue 127 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[127],Queue Manager Queue 127 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[127],Queue Manager Queue 127 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x47F0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[127],Queue Manager Queue 127 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x57F0++0xB
|
|
line.long 0x00 "QSTATA[127],Queue Manager Queue 127 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[127],Queue Manager Queue 127 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[127],Queue Manager Queue 127 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 128 Registers"
|
|
rgroup.long 0x4800++0xB
|
|
line.long 0x00 "CTRLA[128],Queue Manager Queue 128 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[128],Queue Manager Queue 128 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[128],Queue Manager Queue 128 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4800+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[128],Queue Manager Queue 128 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5800++0xB
|
|
line.long 0x00 "QSTATA[128],Queue Manager Queue 128 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[128],Queue Manager Queue 128 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[128],Queue Manager Queue 128 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 129 Registers"
|
|
rgroup.long 0x4810++0xB
|
|
line.long 0x00 "CTRLA[129],Queue Manager Queue 129 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[129],Queue Manager Queue 129 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[129],Queue Manager Queue 129 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4810+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[129],Queue Manager Queue 129 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5810++0xB
|
|
line.long 0x00 "QSTATA[129],Queue Manager Queue 129 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[129],Queue Manager Queue 129 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[129],Queue Manager Queue 129 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 130 Registers"
|
|
rgroup.long 0x4820++0xB
|
|
line.long 0x00 "CTRLA[130],Queue Manager Queue 130 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[130],Queue Manager Queue 130 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[130],Queue Manager Queue 130 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4820+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[130],Queue Manager Queue 130 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5820++0xB
|
|
line.long 0x00 "QSTATA[130],Queue Manager Queue 130 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[130],Queue Manager Queue 130 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[130],Queue Manager Queue 130 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 131 Registers"
|
|
rgroup.long 0x4830++0xB
|
|
line.long 0x00 "CTRLA[131],Queue Manager Queue 131 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[131],Queue Manager Queue 131 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[131],Queue Manager Queue 131 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4830+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[131],Queue Manager Queue 131 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5830++0xB
|
|
line.long 0x00 "QSTATA[131],Queue Manager Queue 131 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[131],Queue Manager Queue 131 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[131],Queue Manager Queue 131 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 132 Registers"
|
|
rgroup.long 0x4840++0xB
|
|
line.long 0x00 "CTRLA[132],Queue Manager Queue 132 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[132],Queue Manager Queue 132 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[132],Queue Manager Queue 132 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4840+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[132],Queue Manager Queue 132 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5840++0xB
|
|
line.long 0x00 "QSTATA[132],Queue Manager Queue 132 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[132],Queue Manager Queue 132 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[132],Queue Manager Queue 132 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 133 Registers"
|
|
rgroup.long 0x4850++0xB
|
|
line.long 0x00 "CTRLA[133],Queue Manager Queue 133 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[133],Queue Manager Queue 133 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[133],Queue Manager Queue 133 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4850+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[133],Queue Manager Queue 133 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5850++0xB
|
|
line.long 0x00 "QSTATA[133],Queue Manager Queue 133 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[133],Queue Manager Queue 133 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[133],Queue Manager Queue 133 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 134 Registers"
|
|
rgroup.long 0x4860++0xB
|
|
line.long 0x00 "CTRLA[134],Queue Manager Queue 134 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[134],Queue Manager Queue 134 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[134],Queue Manager Queue 134 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4860+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[134],Queue Manager Queue 134 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5860++0xB
|
|
line.long 0x00 "QSTATA[134],Queue Manager Queue 134 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[134],Queue Manager Queue 134 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[134],Queue Manager Queue 134 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 135 Registers"
|
|
rgroup.long 0x4870++0xB
|
|
line.long 0x00 "CTRLA[135],Queue Manager Queue 135 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[135],Queue Manager Queue 135 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[135],Queue Manager Queue 135 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4870+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[135],Queue Manager Queue 135 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5870++0xB
|
|
line.long 0x00 "QSTATA[135],Queue Manager Queue 135 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[135],Queue Manager Queue 135 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[135],Queue Manager Queue 135 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 136 Registers"
|
|
rgroup.long 0x4880++0xB
|
|
line.long 0x00 "CTRLA[136],Queue Manager Queue 136 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[136],Queue Manager Queue 136 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[136],Queue Manager Queue 136 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4880+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[136],Queue Manager Queue 136 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5880++0xB
|
|
line.long 0x00 "QSTATA[136],Queue Manager Queue 136 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[136],Queue Manager Queue 136 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[136],Queue Manager Queue 136 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 137 Registers"
|
|
rgroup.long 0x4890++0xB
|
|
line.long 0x00 "CTRLA[137],Queue Manager Queue 137 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[137],Queue Manager Queue 137 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[137],Queue Manager Queue 137 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4890+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[137],Queue Manager Queue 137 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5890++0xB
|
|
line.long 0x00 "QSTATA[137],Queue Manager Queue 137 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[137],Queue Manager Queue 137 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[137],Queue Manager Queue 137 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 138 Registers"
|
|
rgroup.long 0x48A0++0xB
|
|
line.long 0x00 "CTRLA[138],Queue Manager Queue 138 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[138],Queue Manager Queue 138 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[138],Queue Manager Queue 138 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x48A0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[138],Queue Manager Queue 138 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x58A0++0xB
|
|
line.long 0x00 "QSTATA[138],Queue Manager Queue 138 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[138],Queue Manager Queue 138 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[138],Queue Manager Queue 138 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 139 Registers"
|
|
rgroup.long 0x48B0++0xB
|
|
line.long 0x00 "CTRLA[139],Queue Manager Queue 139 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[139],Queue Manager Queue 139 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[139],Queue Manager Queue 139 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x48B0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[139],Queue Manager Queue 139 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x58B0++0xB
|
|
line.long 0x00 "QSTATA[139],Queue Manager Queue 139 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[139],Queue Manager Queue 139 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[139],Queue Manager Queue 139 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 140 Registers"
|
|
rgroup.long 0x48C0++0xB
|
|
line.long 0x00 "CTRLA[140],Queue Manager Queue 140 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[140],Queue Manager Queue 140 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[140],Queue Manager Queue 140 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x48C0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[140],Queue Manager Queue 140 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x58C0++0xB
|
|
line.long 0x00 "QSTATA[140],Queue Manager Queue 140 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[140],Queue Manager Queue 140 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[140],Queue Manager Queue 140 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 141 Registers"
|
|
rgroup.long 0x48D0++0xB
|
|
line.long 0x00 "CTRLA[141],Queue Manager Queue 141 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[141],Queue Manager Queue 141 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[141],Queue Manager Queue 141 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x48D0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[141],Queue Manager Queue 141 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x58D0++0xB
|
|
line.long 0x00 "QSTATA[141],Queue Manager Queue 141 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[141],Queue Manager Queue 141 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[141],Queue Manager Queue 141 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 142 Registers"
|
|
rgroup.long 0x48E0++0xB
|
|
line.long 0x00 "CTRLA[142],Queue Manager Queue 142 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[142],Queue Manager Queue 142 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[142],Queue Manager Queue 142 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x48E0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[142],Queue Manager Queue 142 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x58E0++0xB
|
|
line.long 0x00 "QSTATA[142],Queue Manager Queue 142 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[142],Queue Manager Queue 142 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[142],Queue Manager Queue 142 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 143 Registers"
|
|
rgroup.long 0x48F0++0xB
|
|
line.long 0x00 "CTRLA[143],Queue Manager Queue 143 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[143],Queue Manager Queue 143 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[143],Queue Manager Queue 143 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x48F0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[143],Queue Manager Queue 143 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x58F0++0xB
|
|
line.long 0x00 "QSTATA[143],Queue Manager Queue 143 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[143],Queue Manager Queue 143 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[143],Queue Manager Queue 143 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 144 Registers"
|
|
rgroup.long 0x4900++0xB
|
|
line.long 0x00 "CTRLA[144],Queue Manager Queue 144 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[144],Queue Manager Queue 144 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[144],Queue Manager Queue 144 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4900+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[144],Queue Manager Queue 144 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5900++0xB
|
|
line.long 0x00 "QSTATA[144],Queue Manager Queue 144 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[144],Queue Manager Queue 144 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[144],Queue Manager Queue 144 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 145 Registers"
|
|
rgroup.long 0x4910++0xB
|
|
line.long 0x00 "CTRLA[145],Queue Manager Queue 145 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[145],Queue Manager Queue 145 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[145],Queue Manager Queue 145 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4910+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[145],Queue Manager Queue 145 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5910++0xB
|
|
line.long 0x00 "QSTATA[145],Queue Manager Queue 145 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[145],Queue Manager Queue 145 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[145],Queue Manager Queue 145 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 146 Registers"
|
|
rgroup.long 0x4920++0xB
|
|
line.long 0x00 "CTRLA[146],Queue Manager Queue 146 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[146],Queue Manager Queue 146 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[146],Queue Manager Queue 146 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4920+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[146],Queue Manager Queue 146 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5920++0xB
|
|
line.long 0x00 "QSTATA[146],Queue Manager Queue 146 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[146],Queue Manager Queue 146 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[146],Queue Manager Queue 146 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 147 Registers"
|
|
rgroup.long 0x4930++0xB
|
|
line.long 0x00 "CTRLA[147],Queue Manager Queue 147 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[147],Queue Manager Queue 147 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[147],Queue Manager Queue 147 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4930+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[147],Queue Manager Queue 147 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5930++0xB
|
|
line.long 0x00 "QSTATA[147],Queue Manager Queue 147 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[147],Queue Manager Queue 147 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[147],Queue Manager Queue 147 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 148 Registers"
|
|
rgroup.long 0x4940++0xB
|
|
line.long 0x00 "CTRLA[148],Queue Manager Queue 148 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[148],Queue Manager Queue 148 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[148],Queue Manager Queue 148 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4940+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[148],Queue Manager Queue 148 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5940++0xB
|
|
line.long 0x00 "QSTATA[148],Queue Manager Queue 148 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[148],Queue Manager Queue 148 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[148],Queue Manager Queue 148 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 149 Registers"
|
|
rgroup.long 0x4950++0xB
|
|
line.long 0x00 "CTRLA[149],Queue Manager Queue 149 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[149],Queue Manager Queue 149 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[149],Queue Manager Queue 149 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4950+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[149],Queue Manager Queue 149 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5950++0xB
|
|
line.long 0x00 "QSTATA[149],Queue Manager Queue 149 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[149],Queue Manager Queue 149 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[149],Queue Manager Queue 149 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 150 Registers"
|
|
rgroup.long 0x4960++0xB
|
|
line.long 0x00 "CTRLA[150],Queue Manager Queue 150 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[150],Queue Manager Queue 150 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[150],Queue Manager Queue 150 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4960+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[150],Queue Manager Queue 150 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5960++0xB
|
|
line.long 0x00 "QSTATA[150],Queue Manager Queue 150 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[150],Queue Manager Queue 150 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[150],Queue Manager Queue 150 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 151 Registers"
|
|
rgroup.long 0x4970++0xB
|
|
line.long 0x00 "CTRLA[151],Queue Manager Queue 151 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[151],Queue Manager Queue 151 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[151],Queue Manager Queue 151 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4970+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[151],Queue Manager Queue 151 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5970++0xB
|
|
line.long 0x00 "QSTATA[151],Queue Manager Queue 151 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[151],Queue Manager Queue 151 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[151],Queue Manager Queue 151 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 152 Registers"
|
|
rgroup.long 0x4980++0xB
|
|
line.long 0x00 "CTRLA[152],Queue Manager Queue 152 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[152],Queue Manager Queue 152 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[152],Queue Manager Queue 152 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4980+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[152],Queue Manager Queue 152 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5980++0xB
|
|
line.long 0x00 "QSTATA[152],Queue Manager Queue 152 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[152],Queue Manager Queue 152 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[152],Queue Manager Queue 152 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 153 Registers"
|
|
rgroup.long 0x4990++0xB
|
|
line.long 0x00 "CTRLA[153],Queue Manager Queue 153 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[153],Queue Manager Queue 153 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[153],Queue Manager Queue 153 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x4990+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[153],Queue Manager Queue 153 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x5990++0xB
|
|
line.long 0x00 "QSTATA[153],Queue Manager Queue 153 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[153],Queue Manager Queue 153 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[153],Queue Manager Queue 153 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 154 Registers"
|
|
rgroup.long 0x49A0++0xB
|
|
line.long 0x00 "CTRLA[154],Queue Manager Queue 154 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[154],Queue Manager Queue 154 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[154],Queue Manager Queue 154 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x49A0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[154],Queue Manager Queue 154 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x59A0++0xB
|
|
line.long 0x00 "QSTATA[154],Queue Manager Queue 154 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[154],Queue Manager Queue 154 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[154],Queue Manager Queue 154 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree "Queue 155 Registers"
|
|
rgroup.long 0x49B0++0xB
|
|
line.long 0x00 "CTRLA[155],Queue Manager Queue 155 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "CTRLB[155],Queue Manager Queue 155 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "CTRLC[155],Queue Manager Queue 155 Status Register C"
|
|
sif cpuis("DM814?DSP")
|
|
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
|
|
group.long (0x49B0+0x0C)++0x3
|
|
line.long 0x00 "CTRLD[155],Queue Manager Queue 155 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x59B0++0xB
|
|
line.long 0x00 "QSTATA[155],Queue Manager Queue 155 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[155],Queue Manager Queue 155 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
|
|
line.long 0x08 "QSTATC[155],Queue Manager Queue 155 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
tree "USB Mentor Core"
|
|
tree "USB 0 Mentor Core and FIFO Registers"
|
|
base ad:0x47401400
|
|
width 0xa
|
|
tree "Common USB Registers"
|
|
wgroup.byte 0x00++0x0
|
|
line.byte 0x0 "FADDR,Function Address Register"
|
|
hexmask.byte 0x0 0.--6. 1. " FUNCADDR ,7_bit address of the peripheral part of the transaction"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x0 "POWER,Power Management Register"
|
|
bitfld.byte 0x0 7. " ISOUPDATE ,Waiting for SOF token" "No wait,Wait"
|
|
bitfld.byte 0x0 6. " SOFTCONN ,Soft Connect/Disconnect feature" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 5. " HSEN ,High-speed mode negotiation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4. " HSMODE ,High-speed mode" "Full speed,High speed"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " RESET ,Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 2. " RESUME ,Resume in suspend mode" "No resume,Resume"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " SUSPENDM ,Suspend mode" "No effect,Suspend mode"
|
|
bitfld.byte 0x0 0. " ENSUSPM ,SUSPENDM output enable" "Disabled,Enabled"
|
|
rgroup.word 0x02++0x7
|
|
line.word 0x0 "INTRTX,Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 15"
|
|
bitfld.word 0x0 15. " EP15TX ,Tx Endpoint 15 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 14. " EP14TX ,Tx Endpoint 14 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 13. " EP13TX ,Tx Endpoint 13 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 2. " EP12TX ,Tx Endpoint 12 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 11. " EP11TX ,Tx Endpoint 11 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 10. " EP10TX ,Tx Endpoint 10 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 9. " EP9TX ,Tx Endpoint 9 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 8. " EP8TX ,Tx Endpoint 8 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 7. " EP7TX ,Tx Endpoint 7 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 6. " EP6TX ,Tx Endpoint 6 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 5. " EP5TX ,Tx Endpoint 5 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 4. " EP4TX ,Tx Endpoint 4 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 3. " EP3TX ,Tx Endpoint 3 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 2. " EP2TX ,Tx Endpoint 2 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 1. " EP1TX ,Tx Endpoint 1 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 0. " EP0 ,Endpoint 0 interrupt active" "Not active,Active"
|
|
line.word 0x2 "INTRRX,Interrupt Register for Receive Endpoints 1 to 15"
|
|
bitfld.word 0x02 15. " EP15RX ,Rx Endpoint 15 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 14. " EP14RX ,Rx Endpoint 14 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 13. " EP13RX ,Rx Endpoint 13 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 2. " EP12RX ,Rx Endpoint 12 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 11. " EP11RX ,Rx Endpoint 11 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 10. " EP10RX ,Rx Endpoint 10 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 9. " EP9RX ,Rx Endpoint 9 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 8. " EP8RX ,Rx Endpoint 8 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 7. " EP7RX ,Rx Endpoint 7 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 6. " EP6RX ,Rx Endpoint 6 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 5. " EP5RX ,Rx Endpoint 5 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 4. " EP4RX ,Receive Endpoint 4 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 3. " EP3RX ,Receive Endpoint 3 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 2. " EP2RX ,Receive Endpoint 2 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 1. " EP1RX ,Receive Endpoint 1 interrupt active" "Not active,Active"
|
|
line.word 0x04 "INTRTXE,Interrupt Enable Register for INTRTX"
|
|
bitfld.word 0x04 15. " EP15TX ,Tx Endpoint 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 14. " EP14TX ,Tx Endpoint 14 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 13. " EP13TX ,Tx Endpoint 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 2. " EP12TX ,Tx Endpoint 12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 11. " EP11TX ,Tx Endpoint 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 10. " EP10TX ,Tx Endpoint 10 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 9. " EP9TX ,Tx Endpoint 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 8. " EP8TX ,Tx Endpoint 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 7. " EP7TX ,Tx Endpoint 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 6. " EP6TX ,Tx Endpoint 6 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 5. " EP5TX ,Tx Endpoint 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 4. " EP4TX ,Tx Endpoint 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 3. " EP3TX ,Tx Endpoint 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 2. " EP2TX ,Tx Endpoint 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 1. " EP1TX ,Tx Endpoint 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 0. " EP0 ,Endpoint 0 interrupt enable" "Disabled,Enabled"
|
|
line.word 0x06 "INTRRXE,Interrupt Enable Register for INTRRX"
|
|
bitfld.word 0x06 15. " EP15RX ,Rx Endpoint 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 14. " EP14RX ,Rx Endpoint 14 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 13. " EP13RX ,Rx Endpoint 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 2. " EP12RX ,Rx Endpoint 12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 11. " EP11RX ,Rx Endpoint 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 10. " EP10RX ,Rx Endpoint 10 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 9. " EP9RX ,Rx Endpoint 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 8. " EP8RX ,Rx Endpoint 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 7. " EP7RX ,Rx Endpoint 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 6. " EP6RX ,Rx Endpoint 6 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 5. " EP5RX ,Rx Endpoint 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 4. " EP4RX ,Receive Endpoint 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 3. " EP3RX ,Receive Endpoint 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 2. " EP2RX ,Receive Endpoint 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 1. " EP1RX ,Receive Endpoint 1 interrupt enable" "Disabled,Enabled"
|
|
hgroup.byte 0x0a++0x0
|
|
hide.byte 0x0 "INTRUSB,Interrupt Register for Common USB Interrupts"
|
|
in
|
|
group.byte 0x0b++0x0
|
|
line.byte 0x0 "INTRUSBE,Interrupt Enable Register for INTRUSB"
|
|
bitfld.byte 0x0 7. " VBUSERR ,Vbus error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " SESSREQ ,Session request interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 5. " DISCON ,Disconnect interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4. " CONN ,Connect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " SOF ,Start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " RESET_BABBLE ,Reset interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " RESUME ,Resume interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " SUSPEND ,Suspend interrupt enable" "Disabled,Enabled"
|
|
rgroup.word 0x0c++0x1
|
|
line.word 0x0 "FRAME,Frame Number Register"
|
|
hexmask.word 0x0 0.--10. 1. " FRAMENUMBER ,Last received frame number"
|
|
group.byte 0x0e++0x1
|
|
line.byte 0x0 "INDEX,Index Register for Selecting the Endpoint Status and Control Registers"
|
|
bitfld.byte 0x0 0.--3. " EPSEL ,Endpoint control/status register select" "EP 0,EP 1,EP 2,EP 3,EP 4,EP 5,EP 6,EP 7,EP 8,EP 9,EP 10,EP 11,EP 12,EP 13,EP 14,EP 15"
|
|
line.byte 0x1 "TESTMODE,Register to Enable the USB 2.0 Test Modes"
|
|
bitfld.byte 0x1 7. " FORCE_HOST ,Force Host mode" "Normal,Host"
|
|
bitfld.byte 0x1 6. " FIFO_ACCESS ,Transfer packet EP0 Tx FIFO to EP0 Receive FIFO" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.byte 0x1 5. " FORCE_FS ,Force full-speed mode" "Normal,Full speed"
|
|
bitfld.byte 0x1 4. " FORCE_HS ,Force high-speed mode" "Normal,High speed"
|
|
textline " "
|
|
bitfld.byte 0x1 3. " TEST_PACKET ,Test_Packet test mode" "Normal,Test_Packet"
|
|
bitfld.byte 0x1 2. " TEST_K ,Test_K test mode" "Normal,Test_K"
|
|
textline " "
|
|
bitfld.byte 0x1 1. " TEST_J ,Test_J test mode" "Normal,Test_J"
|
|
bitfld.byte 0x1 0. " TEST_SE0_NAK ,Test_SE0_NAK test mode" "Normal,Test_SE0_NAK"
|
|
tree.end
|
|
width 17.
|
|
tree "Indexed Region Registers"
|
|
if ((((d.b(ad:0x47401400+0x60))&0x4)==0x4)&&(((d.b(ad:0x47401400+0x0e))&0xf)==0x0))
|
|
group.word 0x12++0x1
|
|
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
|
|
bitfld.word 0x00 11. " DISPING ,PING tokens in data and status phases" "Enabled,Disabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
|
|
textline " "
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
|
|
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
group.byte 0x1a++0x0
|
|
line.byte 0x00 "HOST_TYPE0,Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
group.byte 0x1b++0x0
|
|
line.byte 0x00 "HOST_NAKLIMIT0,NAKLIMIT0 Register"
|
|
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
rgroup.byte 0x1f++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b(ad:0x47401400+0x60))&0x4)==0x0)&&(((d.b(ad:0x47401400+0x0e))&0xf)==0x0))
|
|
group.word 0x12++0x1
|
|
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
rgroup.byte 0x1f++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b(ad:0x47401400+0x60))&0x4)==0x4)&&((((d.b(ad:0x47401400+0x0e))&0xf)!=0x0)))
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word 0x12++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word 0x16++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte 0x1a++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1b++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte 0x1c++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1d++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Recieve Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word 0x12++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word 0x16++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "FIFOs"
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x00 "FIFO0,Transmit and Receive FIFO Register for Endpoint 0"
|
|
in
|
|
hgroup.long 0x24++0x3
|
|
hide.long 0x00 "FIFO1,Transmit and Receive FIFO Register for Endpoint 1"
|
|
in
|
|
hgroup.long 0x28++0x3
|
|
hide.long 0x00 "FIFO2,Transmit and Receive FIFO Register for Endpoint 2"
|
|
in
|
|
hgroup.long 0x2C++0x3
|
|
hide.long 0x00 "FIFO3,Transmit and Receive FIFO Register for Endpoint 3"
|
|
in
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "FIFO4,Transmit and Receive FIFO Register for Endpoint 4"
|
|
in
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x00 "FIFO5,Transmit and Receive FIFO Register for Endpoint 5"
|
|
in
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x00 "FIFO6,Transmit and Receive FIFO Register for Endpoint 6"
|
|
in
|
|
hgroup.long 0x3C++0x3
|
|
hide.long 0x00 "FIFO7,Transmit and Receive FIFO Register for Endpoint 7"
|
|
in
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "FIFO8,Transmit and Receive FIFO Register for Endpoint 8"
|
|
in
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x00 "FIFO9,Transmit and Receive FIFO Register for Endpoint 9"
|
|
in
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x00 "FIFO10,Transmit and Receive FIFO Register for Endpoint 10"
|
|
in
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x00 "FIFO11,Transmit and Receive FIFO Register for Endpoint 11"
|
|
in
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x00 "FIFO12,Transmit and Receive FIFO Register for Endpoint 12"
|
|
in
|
|
hgroup.long 0x54++0x3
|
|
hide.long 0x00 "FIFO13,Transmit and Receive FIFO Register for Endpoint 13"
|
|
in
|
|
hgroup.long 0x58++0x3
|
|
hide.long 0x00 "FIFO14,Transmit and Receive FIFO Register for Endpoint 14"
|
|
in
|
|
hgroup.long 0x5C++0x3
|
|
hide.long 0x00 "FIFO15,Transmit and Receive FIFO Register for Endpoint 15"
|
|
in
|
|
tree.end
|
|
tree "Additional Control and Configuration Registers"
|
|
if ((((data.byte(ad:0x47401400+0x60))&0x04)==0x04)&&(((data.byte(ad:0x47401400+0x60))&0x80)==0x80))
|
|
group.byte 0x60++0x0
|
|
line.byte 0x00 "DEVCTL,OTG Device Control Register"
|
|
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
|
|
bitfld.byte 0x00 6. " FSDEV ,Full speed or high speed detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " LSDEV ,Low speed detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
|
|
bitfld.byte 0x00 1. " HOSTREQ ,Host Negotiation initiated" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
|
|
elif ((((data.byte(ad:0x47401400+0x60))&0x04)==0x04)&&(((data.byte(ad:0x47401400+0x60))&0x80)==0x00))
|
|
group.byte 0x60++0x0
|
|
line.byte 0x00 "DEVCTL,OTG Device Control Register"
|
|
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
|
|
bitfld.byte 0x00 6. " FSDEV ,Full speed or high speed detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " LSDEV ,Low speed detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
|
|
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
|
|
elif ((((data.byte(ad:0x47401400+0x60))&0x04)==0x00)&&(((data.byte(ad:0x47401400+0x60))&0x80)==0x80))
|
|
group.byte 0x60++0x0
|
|
line.byte 0x00 "DEVCTL,OTG Device Control Register"
|
|
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
|
|
bitfld.byte 0x00 1. " HOSTREQ ,Host Negotiation initiated" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
|
|
else
|
|
group.byte 0x60++0x0
|
|
line.byte 0x00 "DEVCTL,OTG Device Control Register"
|
|
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
|
|
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
|
|
endif
|
|
sif (cpuis("DM814?DSP")||cpuis("DRA62*"))
|
|
if (((data.byte(ad:0x47401400+0x62))&(0x10))==0x0)
|
|
rgroup.byte 0x62++0x0 "Dynamic FIFO Control"
|
|
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36"
|
|
else
|
|
rgroup.byte 0x62++0x0 "Dynamic FIFO Control"
|
|
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38"
|
|
endif
|
|
else
|
|
if (((data.byte(ad:0x47401400+0x62))&(0x10))==0x0)
|
|
group.byte 0x62++0x0 "Dynamic FIFO Control"
|
|
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38"
|
|
else
|
|
group.byte 0x62++0x0 "Dynamic FIFO Control"
|
|
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36"
|
|
endif
|
|
endif
|
|
if (((data.byte(ad:0x47401400+0x63))&0x10)==0x0)
|
|
group.byte 0x63++0x0
|
|
line.byte 0x00 "RXFIFOSZ ,Receive Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38"
|
|
else
|
|
group.byte 0x63++0x0
|
|
line.byte 0x00 "RXFIFOSZ ,Receive Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36"
|
|
endif
|
|
group.word 0x64++0x1
|
|
line.word 0x00 "TXFIFOADDR,Transmit Endpoint FIFO Address"
|
|
hexmask.word 0x00 0.--12. 1. " ADDR ,Start address of endpoint FIFO"
|
|
group.word 0x66++0x1
|
|
line.word 0x00 "RXFIFOADDR,Receive Endpoint FIFO Address"
|
|
hexmask.word 0x00 0.--12. 1. " ADDR ,Start address of endpoint FIFO"
|
|
group.word 0x6C++0x1
|
|
line.word 0x00 "HWVERS,Hardware Version Register"
|
|
bitfld.word 0x00 15. " RC ,RTL version from which the core hardware was generated" "Release candidate,Full release"
|
|
bitfld.word 0x00 10.--14. " REVMAJ ,Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--9. 1. " REVMIN ,Minor revision"
|
|
tree.end
|
|
width 12.
|
|
tree "Target Endpoint Control"
|
|
tree "EPTRG0"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0x80)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x80+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x80+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0x80)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0x80+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0x80+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG1"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0x88)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x88+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x88+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0x88)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0x88+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0x88+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG2"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0x90)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x90+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x90+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0x90)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0x90+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0x90+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG3"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0x98)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x98+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x98+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0x98)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0x98+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0x98+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG4"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0xA0)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xA0+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xA0+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xA0)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xA0+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xA0+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG5"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0xA8)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xA8+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xA8+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xA8)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xA8+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xA8+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG6"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0xB0)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xB0+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xB0+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xB0)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xB0+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xB0+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG7"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0xB8)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xB8+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xB8+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xB8)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xB8+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xB8+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG8"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0xC0)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xC0+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xC0+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xC0)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xC0+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xC0+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG9"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0xC8)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xC8+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xC8+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xC8)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xC8+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xC8+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG10"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0xD0)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xD0+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xD0+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xD0)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xD0+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xD0+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG11"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0xD8)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xD8+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xD8+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xD8)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xD8+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xD8+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG12"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0xE0)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xE0+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xE0+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xE0)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xE0+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xE0+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG13"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0xE8)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xE8+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xE8+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xE8)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xE8+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xE8+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG14"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0xF0)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xF0+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xF0+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xF0)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xF0+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xF0+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG15"
|
|
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.byte (0xF8)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xF8+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xF8+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xF8)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xF8+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xF8+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
width 17.
|
|
tree "Control and Status Registers for Endpoints"
|
|
tree "EOCSR0"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word 0x102++0x1
|
|
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
|
|
bitfld.word 0x00 11. " DISPING ,PING tokens in data and status phases" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
|
|
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word 0x108++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
group.byte 0x10a++0x0
|
|
line.byte 0x00 "HOST_TYPE0,Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
group.byte 0x10b++0x0
|
|
line.byte 0x00 "HOST_NAKLIMIT0,NAKLimit0 Register"
|
|
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
rgroup.byte 0x10f++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
else
|
|
group.word 0x102++0x1
|
|
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
|
|
rgroup.word 0x108++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
rgroup.byte 0x10f++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR1"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x110)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x110+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x110+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x110+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x110+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x110+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x110+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x110+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x110+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x110)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x110+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x110+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x110+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR2"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x120)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x120+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x120+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x120+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x120+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x120+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x120+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x120+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x120+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x120)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x120+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x120+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x120+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR3"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x130)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x130+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x130+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x130+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x130+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x130+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x130+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x130+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x130+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x130)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x130+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x130+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x130+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR4"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x140)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x140+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x140+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x140+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x140+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x140+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x140+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x140+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x140+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x140)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x140+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x140+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x140+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR5"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x150)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x150+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x150+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x150+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x150+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x150+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x150+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x150+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x150+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x150)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x150+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x150+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x150+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR6"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x160)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x160+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x160+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x160+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x160+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x160+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x160+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x160+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x160+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x160)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x160+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x160+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x160+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR7"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x170)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x170+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x170+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x170+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x170+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x170+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x170+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x170+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x170+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x170)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x170+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x170+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x170+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR8"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x180)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x180+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x180+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x180+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x180+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x180+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x180+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x180+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x180+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x180)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x180+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x180+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x180+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR9"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x190)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x190+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x190+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x190+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x190+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x190+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x190+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x190+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x190+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x190)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x190+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x190+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x190+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR10"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x1A0)++0x1
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|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
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|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
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|
group.word (0x1A0+0x2)++0x1
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|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
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|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
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|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
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|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
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|
textline " "
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|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
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|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
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|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
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|
textline " "
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|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
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|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
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|
textline " "
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bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
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|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
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|
textline " "
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|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
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|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
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|
textline " "
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|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
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|
group.word (0x1A0+0x4)++0x1
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|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
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|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
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|
group.word (0x1A0+0x6)++0x1
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|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
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|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
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|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
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|
textline " "
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|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
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|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
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|
textline " "
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bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
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|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
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|
textline " "
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bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
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bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
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|
textline " "
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bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
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|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
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|
textline " "
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bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
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bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
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bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
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textline " "
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bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
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rgroup.word (0x1A0+0x8)++0x1
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line.word 0x00 "RXCOUNT,Receive Count Register"
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hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
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group.byte (0x1A0+0xa)++0x0
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line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
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bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
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bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
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|
textline " "
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bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.byte (0x1A0+0xb)++0x0
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line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
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hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x1A0+0xc)++0x0
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line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
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|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
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|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1A0+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
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|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
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|
group.word (0x1A0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1A0+0x2)++0x1
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|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
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|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
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|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
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|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1A0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1A0+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
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|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
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|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
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tree.end
|
|
tree "EOCSR11"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
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group.word (0x1B0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1B0+0x2)++0x1
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|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
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|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
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|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
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|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
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|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
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|
textline " "
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|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
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|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
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|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1B0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1B0+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x1B0+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x1B0+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1B0+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x1B0+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1B0+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x1B0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1B0+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1B0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1B0+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR12"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x1C0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1C0+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1C0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1C0+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x1C0+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x1C0+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1C0+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x1C0+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1C0+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x1C0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1C0+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1C0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1C0+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR13"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x1D0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1D0+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1D0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1D0+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x1D0+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x1D0+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1D0+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x1D0+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1D0+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x1D0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1D0+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1D0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1D0+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR14"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x1E0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1E0+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1E0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1E0+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x1E0+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x1E0+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1E0+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x1E0+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1E0+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x1E0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1E0+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1E0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1E0+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR15"
|
|
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
|
|
group.word (0x1F0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1F0+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1F0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1F0+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x1F0+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x1F0+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1F0+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x1F0+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1F0+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x1F0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1F0+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1F0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1F0+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "USB 1 Mentor Core and FIFO Registers"
|
|
base ad:0x47401C00
|
|
width 0xa
|
|
tree "Common USB Registers"
|
|
wgroup.byte 0x00++0x0
|
|
line.byte 0x0 "FADDR,Function Address Register"
|
|
hexmask.byte 0x0 0.--6. 1. " FUNCADDR ,7_bit address of the peripheral part of the transaction"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x0 "POWER,Power Management Register"
|
|
bitfld.byte 0x0 7. " ISOUPDATE ,Waiting for SOF token" "No wait,Wait"
|
|
bitfld.byte 0x0 6. " SOFTCONN ,Soft Connect/Disconnect feature" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 5. " HSEN ,High-speed mode negotiation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4. " HSMODE ,High-speed mode" "Full speed,High speed"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " RESET ,Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 2. " RESUME ,Resume in suspend mode" "No resume,Resume"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " SUSPENDM ,Suspend mode" "No effect,Suspend mode"
|
|
bitfld.byte 0x0 0. " ENSUSPM ,SUSPENDM output enable" "Disabled,Enabled"
|
|
rgroup.word 0x02++0x7
|
|
line.word 0x0 "INTRTX,Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 15"
|
|
bitfld.word 0x0 15. " EP15TX ,Tx Endpoint 15 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 14. " EP14TX ,Tx Endpoint 14 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 13. " EP13TX ,Tx Endpoint 13 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 2. " EP12TX ,Tx Endpoint 12 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 11. " EP11TX ,Tx Endpoint 11 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 10. " EP10TX ,Tx Endpoint 10 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 9. " EP9TX ,Tx Endpoint 9 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 8. " EP8TX ,Tx Endpoint 8 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 7. " EP7TX ,Tx Endpoint 7 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 6. " EP6TX ,Tx Endpoint 6 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 5. " EP5TX ,Tx Endpoint 5 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 4. " EP4TX ,Tx Endpoint 4 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 3. " EP3TX ,Tx Endpoint 3 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 2. " EP2TX ,Tx Endpoint 2 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 1. " EP1TX ,Tx Endpoint 1 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 0. " EP0 ,Endpoint 0 interrupt active" "Not active,Active"
|
|
line.word 0x2 "INTRRX,Interrupt Register for Receive Endpoints 1 to 15"
|
|
bitfld.word 0x02 15. " EP15RX ,Rx Endpoint 15 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 14. " EP14RX ,Rx Endpoint 14 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 13. " EP13RX ,Rx Endpoint 13 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 2. " EP12RX ,Rx Endpoint 12 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 11. " EP11RX ,Rx Endpoint 11 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 10. " EP10RX ,Rx Endpoint 10 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 9. " EP9RX ,Rx Endpoint 9 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 8. " EP8RX ,Rx Endpoint 8 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 7. " EP7RX ,Rx Endpoint 7 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 6. " EP6RX ,Rx Endpoint 6 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 5. " EP5RX ,Rx Endpoint 5 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 4. " EP4RX ,Receive Endpoint 4 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 3. " EP3RX ,Receive Endpoint 3 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 2. " EP2RX ,Receive Endpoint 2 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 1. " EP1RX ,Receive Endpoint 1 interrupt active" "Not active,Active"
|
|
line.word 0x04 "INTRTXE,Interrupt Enable Register for INTRTX"
|
|
bitfld.word 0x04 15. " EP15TX ,Tx Endpoint 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 14. " EP14TX ,Tx Endpoint 14 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 13. " EP13TX ,Tx Endpoint 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 2. " EP12TX ,Tx Endpoint 12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 11. " EP11TX ,Tx Endpoint 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 10. " EP10TX ,Tx Endpoint 10 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 9. " EP9TX ,Tx Endpoint 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 8. " EP8TX ,Tx Endpoint 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 7. " EP7TX ,Tx Endpoint 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 6. " EP6TX ,Tx Endpoint 6 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 5. " EP5TX ,Tx Endpoint 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 4. " EP4TX ,Tx Endpoint 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 3. " EP3TX ,Tx Endpoint 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 2. " EP2TX ,Tx Endpoint 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 1. " EP1TX ,Tx Endpoint 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 0. " EP0 ,Endpoint 0 interrupt enable" "Disabled,Enabled"
|
|
line.word 0x06 "INTRRXE,Interrupt Enable Register for INTRRX"
|
|
bitfld.word 0x06 15. " EP15RX ,Rx Endpoint 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 14. " EP14RX ,Rx Endpoint 14 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 13. " EP13RX ,Rx Endpoint 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 2. " EP12RX ,Rx Endpoint 12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 11. " EP11RX ,Rx Endpoint 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 10. " EP10RX ,Rx Endpoint 10 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 9. " EP9RX ,Rx Endpoint 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 8. " EP8RX ,Rx Endpoint 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 7. " EP7RX ,Rx Endpoint 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 6. " EP6RX ,Rx Endpoint 6 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 5. " EP5RX ,Rx Endpoint 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 4. " EP4RX ,Receive Endpoint 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 3. " EP3RX ,Receive Endpoint 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 2. " EP2RX ,Receive Endpoint 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 1. " EP1RX ,Receive Endpoint 1 interrupt enable" "Disabled,Enabled"
|
|
hgroup.byte 0x0a++0x0
|
|
hide.byte 0x0 "INTRUSB,Interrupt Register for Common USB Interrupts"
|
|
in
|
|
group.byte 0x0b++0x0
|
|
line.byte 0x0 "INTRUSBE,Interrupt Enable Register for INTRUSB"
|
|
bitfld.byte 0x0 7. " VBUSERR ,Vbus error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " SESSREQ ,Session request interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 5. " DISCON ,Disconnect interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4. " CONN ,Connect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " SOF ,Start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " RESET_BABBLE ,Reset interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " RESUME ,Resume interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " SUSPEND ,Suspend interrupt enable" "Disabled,Enabled"
|
|
rgroup.word 0x0c++0x1
|
|
line.word 0x0 "FRAME,Frame Number Register"
|
|
hexmask.word 0x0 0.--10. 1. " FRAMENUMBER ,Last received frame number"
|
|
group.byte 0x0e++0x1
|
|
line.byte 0x0 "INDEX,Index Register for Selecting the Endpoint Status and Control Registers"
|
|
bitfld.byte 0x0 0.--3. " EPSEL ,Endpoint control/status register select" "EP 0,EP 1,EP 2,EP 3,EP 4,EP 5,EP 6,EP 7,EP 8,EP 9,EP 10,EP 11,EP 12,EP 13,EP 14,EP 15"
|
|
line.byte 0x1 "TESTMODE,Register to Enable the USB 2.0 Test Modes"
|
|
bitfld.byte 0x1 7. " FORCE_HOST ,Force Host mode" "Normal,Host"
|
|
bitfld.byte 0x1 6. " FIFO_ACCESS ,Transfer packet EP0 Tx FIFO to EP0 Receive FIFO" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.byte 0x1 5. " FORCE_FS ,Force full-speed mode" "Normal,Full speed"
|
|
bitfld.byte 0x1 4. " FORCE_HS ,Force high-speed mode" "Normal,High speed"
|
|
textline " "
|
|
bitfld.byte 0x1 3. " TEST_PACKET ,Test_Packet test mode" "Normal,Test_Packet"
|
|
bitfld.byte 0x1 2. " TEST_K ,Test_K test mode" "Normal,Test_K"
|
|
textline " "
|
|
bitfld.byte 0x1 1. " TEST_J ,Test_J test mode" "Normal,Test_J"
|
|
bitfld.byte 0x1 0. " TEST_SE0_NAK ,Test_SE0_NAK test mode" "Normal,Test_SE0_NAK"
|
|
tree.end
|
|
width 17.
|
|
tree "Indexed Region Registers"
|
|
if ((((d.b(ad:0x47401C00+0x60))&0x4)==0x4)&&(((d.b(ad:0x47401C00+0x0e))&0xf)==0x0))
|
|
group.word 0x12++0x1
|
|
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
|
|
bitfld.word 0x00 11. " DISPING ,PING tokens in data and status phases" "Enabled,Disabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
|
|
textline " "
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
|
|
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
group.byte 0x1a++0x0
|
|
line.byte 0x00 "HOST_TYPE0,Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
group.byte 0x1b++0x0
|
|
line.byte 0x00 "HOST_NAKLIMIT0,NAKLIMIT0 Register"
|
|
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
rgroup.byte 0x1f++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b(ad:0x47401C00+0x60))&0x4)==0x0)&&(((d.b(ad:0x47401C00+0x0e))&0xf)==0x0))
|
|
group.word 0x12++0x1
|
|
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
rgroup.byte 0x1f++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b(ad:0x47401C00+0x60))&0x4)==0x4)&&((((d.b(ad:0x47401C00+0x0e))&0xf)!=0x0)))
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word 0x12++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word 0x16++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte 0x1a++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1b++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte 0x1c++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1d++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Recieve Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word 0x12++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word 0x16++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "FIFOs"
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x00 "FIFO0,Transmit and Receive FIFO Register for Endpoint 0"
|
|
in
|
|
hgroup.long 0x24++0x3
|
|
hide.long 0x00 "FIFO1,Transmit and Receive FIFO Register for Endpoint 1"
|
|
in
|
|
hgroup.long 0x28++0x3
|
|
hide.long 0x00 "FIFO2,Transmit and Receive FIFO Register for Endpoint 2"
|
|
in
|
|
hgroup.long 0x2C++0x3
|
|
hide.long 0x00 "FIFO3,Transmit and Receive FIFO Register for Endpoint 3"
|
|
in
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "FIFO4,Transmit and Receive FIFO Register for Endpoint 4"
|
|
in
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x00 "FIFO5,Transmit and Receive FIFO Register for Endpoint 5"
|
|
in
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x00 "FIFO6,Transmit and Receive FIFO Register for Endpoint 6"
|
|
in
|
|
hgroup.long 0x3C++0x3
|
|
hide.long 0x00 "FIFO7,Transmit and Receive FIFO Register for Endpoint 7"
|
|
in
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "FIFO8,Transmit and Receive FIFO Register for Endpoint 8"
|
|
in
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x00 "FIFO9,Transmit and Receive FIFO Register for Endpoint 9"
|
|
in
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x00 "FIFO10,Transmit and Receive FIFO Register for Endpoint 10"
|
|
in
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x00 "FIFO11,Transmit and Receive FIFO Register for Endpoint 11"
|
|
in
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x00 "FIFO12,Transmit and Receive FIFO Register for Endpoint 12"
|
|
in
|
|
hgroup.long 0x54++0x3
|
|
hide.long 0x00 "FIFO13,Transmit and Receive FIFO Register for Endpoint 13"
|
|
in
|
|
hgroup.long 0x58++0x3
|
|
hide.long 0x00 "FIFO14,Transmit and Receive FIFO Register for Endpoint 14"
|
|
in
|
|
hgroup.long 0x5C++0x3
|
|
hide.long 0x00 "FIFO15,Transmit and Receive FIFO Register for Endpoint 15"
|
|
in
|
|
tree.end
|
|
tree "Additional Control and Configuration Registers"
|
|
if ((((data.byte(ad:0x47401C00+0x60))&0x04)==0x04)&&(((data.byte(ad:0x47401C00+0x60))&0x80)==0x80))
|
|
group.byte 0x60++0x0
|
|
line.byte 0x00 "DEVCTL,OTG Device Control Register"
|
|
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
|
|
bitfld.byte 0x00 6. " FSDEV ,Full speed or high speed detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " LSDEV ,Low speed detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
|
|
bitfld.byte 0x00 1. " HOSTREQ ,Host Negotiation initiated" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
|
|
elif ((((data.byte(ad:0x47401C00+0x60))&0x04)==0x04)&&(((data.byte(ad:0x47401C00+0x60))&0x80)==0x00))
|
|
group.byte 0x60++0x0
|
|
line.byte 0x00 "DEVCTL,OTG Device Control Register"
|
|
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
|
|
bitfld.byte 0x00 6. " FSDEV ,Full speed or high speed detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " LSDEV ,Low speed detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
|
|
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
|
|
elif ((((data.byte(ad:0x47401C00+0x60))&0x04)==0x00)&&(((data.byte(ad:0x47401C00+0x60))&0x80)==0x80))
|
|
group.byte 0x60++0x0
|
|
line.byte 0x00 "DEVCTL,OTG Device Control Register"
|
|
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
|
|
bitfld.byte 0x00 1. " HOSTREQ ,Host Negotiation initiated" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
|
|
else
|
|
group.byte 0x60++0x0
|
|
line.byte 0x00 "DEVCTL,OTG Device Control Register"
|
|
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
|
|
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
|
|
endif
|
|
sif (cpuis("DM814?DSP")||cpuis("DRA62*"))
|
|
if (((data.byte(ad:0x47401C00+0x62))&(0x10))==0x0)
|
|
rgroup.byte 0x62++0x0 "Dynamic FIFO Control"
|
|
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36"
|
|
else
|
|
rgroup.byte 0x62++0x0 "Dynamic FIFO Control"
|
|
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38"
|
|
endif
|
|
else
|
|
if (((data.byte(ad:0x47401C00+0x62))&(0x10))==0x0)
|
|
group.byte 0x62++0x0 "Dynamic FIFO Control"
|
|
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38"
|
|
else
|
|
group.byte 0x62++0x0 "Dynamic FIFO Control"
|
|
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36"
|
|
endif
|
|
endif
|
|
if (((data.byte(ad:0x47401C00+0x63))&0x10)==0x0)
|
|
group.byte 0x63++0x0
|
|
line.byte 0x00 "RXFIFOSZ ,Receive Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38"
|
|
else
|
|
group.byte 0x63++0x0
|
|
line.byte 0x00 "RXFIFOSZ ,Receive Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36"
|
|
endif
|
|
group.word 0x64++0x1
|
|
line.word 0x00 "TXFIFOADDR,Transmit Endpoint FIFO Address"
|
|
hexmask.word 0x00 0.--12. 1. " ADDR ,Start address of endpoint FIFO"
|
|
group.word 0x66++0x1
|
|
line.word 0x00 "RXFIFOADDR,Receive Endpoint FIFO Address"
|
|
hexmask.word 0x00 0.--12. 1. " ADDR ,Start address of endpoint FIFO"
|
|
group.word 0x6C++0x1
|
|
line.word 0x00 "HWVERS,Hardware Version Register"
|
|
bitfld.word 0x00 15. " RC ,RTL version from which the core hardware was generated" "Release candidate,Full release"
|
|
bitfld.word 0x00 10.--14. " REVMAJ ,Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--9. 1. " REVMIN ,Minor revision"
|
|
tree.end
|
|
width 12.
|
|
tree "Target Endpoint Control"
|
|
tree "EPTRG0"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0x80)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x80+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x80+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0x80)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0x80+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0x80+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG1"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0x88)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x88+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x88+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0x88)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0x88+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0x88+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG2"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0x90)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x90+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x90+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0x90)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0x90+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0x90+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG3"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0x98)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x98+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x98+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0x98)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0x98+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0x98+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG4"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0xA0)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xA0+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xA0+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xA0)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xA0+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xA0+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG5"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0xA8)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xA8+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xA8+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xA8)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xA8+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xA8+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG6"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0xB0)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xB0+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xB0+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xB0)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xB0+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xB0+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG7"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0xB8)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xB8+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xB8+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xB8)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xB8+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xB8+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG8"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0xC0)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xC0+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xC0+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xC0)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xC0+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xC0+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG9"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0xC8)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xC8+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xC8+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xC8)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xC8+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xC8+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG10"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0xD0)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xD0+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xD0+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xD0)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xD0+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xD0+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG11"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0xD8)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xD8+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xD8+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xD8)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xD8+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xD8+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG12"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0xE0)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xE0+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xE0+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xE0)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xE0+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xE0+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG13"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0xE8)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xE8+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xE8+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xE8)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xE8+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xE8+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG14"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0xF0)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xF0+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xF0+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xF0)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xF0+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xF0+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG15"
|
|
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.byte (0xF8)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xF8+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0xF8+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0xF8)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0xF8+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0xF8+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
width 17.
|
|
tree "Control and Status Registers for Endpoints"
|
|
tree "EOCSR0"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word 0x102++0x1
|
|
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
|
|
bitfld.word 0x00 11. " DISPING ,PING tokens in data and status phases" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
|
|
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word 0x108++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
group.byte 0x10a++0x0
|
|
line.byte 0x00 "HOST_TYPE0,Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
group.byte 0x10b++0x0
|
|
line.byte 0x00 "HOST_NAKLIMIT0,NAKLimit0 Register"
|
|
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
rgroup.byte 0x10f++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
else
|
|
group.word 0x102++0x1
|
|
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
|
|
rgroup.word 0x108++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
rgroup.byte 0x10f++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR1"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x110)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x110+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x110+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x110+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x110+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x110+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x110+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x110+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x110+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x110)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x110+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x110+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x110+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR2"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x120)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x120+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x120+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x120+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x120+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x120+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x120+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x120+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x120+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x120)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x120+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x120+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x120+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR3"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x130)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x130+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x130+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x130+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x130+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x130+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x130+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x130+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x130+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x130)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x130+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x130+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x130+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR4"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x140)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x140+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x140+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x140+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x140+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x140+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x140+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x140+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x140+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x140)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x140+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x140+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x140+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR5"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x150)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x150+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x150+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x150+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x150+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x150+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x150+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x150+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x150+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x150)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x150+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x150+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x150+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR6"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x160)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x160+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x160+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x160+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x160+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x160+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x160+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x160+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x160+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x160)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x160+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x160+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x160+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR7"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x170)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x170+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x170+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x170+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x170+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x170+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x170+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x170+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x170+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x170)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x170+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x170+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x170+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR8"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x180)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x180+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x180+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x180+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x180+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x180+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x180+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x180+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x180+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x180)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x180+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x180+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x180+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR9"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x190)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x190+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x190+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x190+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x190+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x190+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x190+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x190+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x190+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x190)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x190+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x190+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x190+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR10"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x1A0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1A0+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1A0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1A0+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x1A0+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x1A0+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1A0+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x1A0+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1A0+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x1A0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1A0+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1A0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1A0+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR11"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x1B0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1B0+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1B0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1B0+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x1B0+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x1B0+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1B0+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x1B0+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1B0+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x1B0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1B0+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1B0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1B0+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR12"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x1C0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1C0+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1C0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1C0+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x1C0+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x1C0+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1C0+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x1C0+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1C0+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x1C0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1C0+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1C0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1C0+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR13"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x1D0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1D0+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1D0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1D0+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x1D0+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x1D0+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1D0+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x1D0+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1D0+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x1D0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1D0+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1D0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1D0+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR14"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x1E0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1E0+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1E0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1E0+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x1E0+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x1E0+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1E0+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x1E0+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1E0+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x1E0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1E0+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1E0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1E0+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR15"
|
|
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
|
|
group.word (0x1F0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1F0+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1F0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1F0+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x1F0+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x1F0+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1F0+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x1F0+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (0x1F0+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
else
|
|
group.word (0x1F0)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x1F0+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x1F0+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x1F0+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("DRA62*"))
|
|
tree "ATL (Audio Tracking Logic)"
|
|
base ad:0x481D4000
|
|
width 22.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REVID,ATL REVID Register"
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "PPMR0,Parts-Per-Million Register 0"
|
|
bitfld.long 0x00 15. " PPMSLOWDOWN ,Part-Per-Million Slowdown" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--8. 1. " PPMSETTING ,Parts-Per-Million Setting"
|
|
rgroup.long (0x200+0x04)++0x3
|
|
line.long 0x00 "BBSR0,Baseband Sample Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLECOUNT ,Sample count"
|
|
group.long (0x200+0x08)++0x3
|
|
line.long 0x00 "ATLCR0,ATL Configuration Register 0"
|
|
bitfld.long 0x00 5. " MODEMCLOCKDIVIDESELECT ,Modem Clock Divide Select" "AWS/2^16,AWS/2^12"
|
|
bitfld.long 0x00 0.--4. " ATLINTERNALDIVIDER ,ATL Internal Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x200+0x10)++0xf
|
|
line.long 0x00 "SWEN0,Software Enable Register 0"
|
|
bitfld.long 0x00 0. " SWEN ,Software enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BWSMUX0,Baseband Word Select Mux Register 0"
|
|
bitfld.long 0x04 0.--3. " BWSMUX ,Baseband Word Select Mux" "McASP0_FSR,McASP0_FSX,McASP1_FSR,McASP1_FSX,McASP2_FSX,McASP3_FSX,McASP4_FSX,McASP5_FSX,McASP3_AHCLKX,McASP4_AHCLKX,McASP5_AHCLKX,Reserved,XREF_CLK0 input pad,XREF_CLK1 input pad,XREF_CLK2 input pad,OSC1_X1 input pad"
|
|
line.long 0x08 "AWSMUX0,Audio Word Select Mux Register 0"
|
|
bitfld.long 0x08 0.--3. " AWSMUX ,Audio Word Select Mux" "McASP0_FSR,McASP0_FSX,McASP1_FSR,McASP1_FSX,McASP2_FSX,McASP3_FSX,McASP4_FSX,McASP5_FSX,McASP3_AHCLKX,McASP4_AHCLKX,McASP5_AHCLKX,Reserved,XREF_CLK0 input pad,XREF_CLK1 input pad,XREF_CLK2 input pad,OSC1_X1 input pad"
|
|
line.long 0x0C "PCLKMUX0,ATLPCLK Selection Register 0"
|
|
bitfld.long 0x0C 0. " PCLKMUX ,ATLPCLK Selection Register Mux" "OCP_CLK,ATLPCLK"
|
|
group.long 0x280++0x3
|
|
line.long 0x00 "PPMR1,Parts-Per-Million Register 1"
|
|
bitfld.long 0x00 15. " PPMSLOWDOWN ,Part-Per-Million Slowdown" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--8. 1. " PPMSETTING ,Parts-Per-Million Setting"
|
|
rgroup.long (0x280+0x04)++0x3
|
|
line.long 0x00 "BBSR1,Baseband Sample Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLECOUNT ,Sample count"
|
|
group.long (0x280+0x08)++0x3
|
|
line.long 0x00 "ATLCR1,ATL Configuration Register 1"
|
|
bitfld.long 0x00 5. " MODEMCLOCKDIVIDESELECT ,Modem Clock Divide Select" "AWS/2^16,AWS/2^12"
|
|
bitfld.long 0x00 0.--4. " ATLINTERNALDIVIDER ,ATL Internal Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x280+0x10)++0xf
|
|
line.long 0x00 "SWEN1,Software Enable Register 1"
|
|
bitfld.long 0x00 0. " SWEN ,Software enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BWSMUX1,Baseband Word Select Mux Register 1"
|
|
bitfld.long 0x04 0.--3. " BWSMUX ,Baseband Word Select Mux" "McASP0_FSR,McASP0_FSX,McASP1_FSR,McASP1_FSX,McASP2_FSX,McASP3_FSX,McASP4_FSX,McASP5_FSX,McASP3_AHCLKX,McASP4_AHCLKX,McASP5_AHCLKX,Reserved,XREF_CLK0 input pad,XREF_CLK1 input pad,XREF_CLK2 input pad,OSC1_X1 input pad"
|
|
line.long 0x08 "AWSMUX1,Audio Word Select Mux Register 1"
|
|
bitfld.long 0x08 0.--3. " AWSMUX ,Audio Word Select Mux" "McASP0_FSR,McASP0_FSX,McASP1_FSR,McASP1_FSX,McASP2_FSX,McASP3_FSX,McASP4_FSX,McASP5_FSX,McASP3_AHCLKX,McASP4_AHCLKX,McASP5_AHCLKX,Reserved,XREF_CLK0 input pad,XREF_CLK1 input pad,XREF_CLK2 input pad,OSC1_X1 input pad"
|
|
line.long 0x0C "PCLKMUX1,ATLPCLK Selection Register 1"
|
|
bitfld.long 0x0C 0. " PCLKMUX ,ATLPCLK Selection Register Mux" "OCP_CLK,ATLPCLK"
|
|
group.long 0x300++0x3
|
|
line.long 0x00 "PPMR2,Parts-Per-Million Register 2"
|
|
bitfld.long 0x00 15. " PPMSLOWDOWN ,Part-Per-Million Slowdown" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--8. 1. " PPMSETTING ,Parts-Per-Million Setting"
|
|
rgroup.long (0x300+0x04)++0x3
|
|
line.long 0x00 "BBSR2,Baseband Sample Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLECOUNT ,Sample count"
|
|
group.long (0x300+0x08)++0x3
|
|
line.long 0x00 "ATLCR2,ATL Configuration Register 2"
|
|
bitfld.long 0x00 5. " MODEMCLOCKDIVIDESELECT ,Modem Clock Divide Select" "AWS/2^16,AWS/2^12"
|
|
bitfld.long 0x00 0.--4. " ATLINTERNALDIVIDER ,ATL Internal Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x300+0x10)++0xf
|
|
line.long 0x00 "SWEN2,Software Enable Register 2"
|
|
bitfld.long 0x00 0. " SWEN ,Software enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BWSMUX2,Baseband Word Select Mux Register 2"
|
|
bitfld.long 0x04 0.--3. " BWSMUX ,Baseband Word Select Mux" "McASP0_FSR,McASP0_FSX,McASP1_FSR,McASP1_FSX,McASP2_FSX,McASP3_FSX,McASP4_FSX,McASP5_FSX,McASP3_AHCLKX,McASP4_AHCLKX,McASP5_AHCLKX,Reserved,XREF_CLK0 input pad,XREF_CLK1 input pad,XREF_CLK2 input pad,OSC1_X1 input pad"
|
|
line.long 0x08 "AWSMUX2,Audio Word Select Mux Register 2"
|
|
bitfld.long 0x08 0.--3. " AWSMUX ,Audio Word Select Mux" "McASP0_FSR,McASP0_FSX,McASP1_FSR,McASP1_FSX,McASP2_FSX,McASP3_FSX,McASP4_FSX,McASP5_FSX,McASP3_AHCLKX,McASP4_AHCLKX,McASP5_AHCLKX,Reserved,XREF_CLK0 input pad,XREF_CLK1 input pad,XREF_CLK2 input pad,OSC1_X1 input pad"
|
|
line.long 0x0C "PCLKMUX2,ATLPCLK Selection Register 2"
|
|
bitfld.long 0x0C 0. " PCLKMUX ,ATLPCLK Selection Register Mux" "OCP_CLK,ATLPCLK"
|
|
group.long 0x380++0x3
|
|
line.long 0x00 "PPMR3,Parts-Per-Million Register 3"
|
|
bitfld.long 0x00 15. " PPMSLOWDOWN ,Part-Per-Million Slowdown" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--8. 1. " PPMSETTING ,Parts-Per-Million Setting"
|
|
rgroup.long (0x380+0x04)++0x3
|
|
line.long 0x00 "BBSR3,Baseband Sample Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLECOUNT ,Sample count"
|
|
group.long (0x380+0x08)++0x3
|
|
line.long 0x00 "ATLCR3,ATL Configuration Register 3"
|
|
bitfld.long 0x00 5. " MODEMCLOCKDIVIDESELECT ,Modem Clock Divide Select" "AWS/2^16,AWS/2^12"
|
|
bitfld.long 0x00 0.--4. " ATLINTERNALDIVIDER ,ATL Internal Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x380+0x10)++0xf
|
|
line.long 0x00 "SWEN3,Software Enable Register 3"
|
|
bitfld.long 0x00 0. " SWEN ,Software enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BWSMUX3,Baseband Word Select Mux Register 3"
|
|
bitfld.long 0x04 0.--3. " BWSMUX ,Baseband Word Select Mux" "McASP0_FSR,McASP0_FSX,McASP1_FSR,McASP1_FSX,McASP2_FSX,McASP3_FSX,McASP4_FSX,McASP5_FSX,McASP3_AHCLKX,McASP4_AHCLKX,McASP5_AHCLKX,Reserved,XREF_CLK0 input pad,XREF_CLK1 input pad,XREF_CLK2 input pad,OSC1_X1 input pad"
|
|
line.long 0x08 "AWSMUX3,Audio Word Select Mux Register 3"
|
|
bitfld.long 0x08 0.--3. " AWSMUX ,Audio Word Select Mux" "McASP0_FSR,McASP0_FSX,McASP1_FSR,McASP1_FSX,McASP2_FSX,McASP3_FSX,McASP4_FSX,McASP5_FSX,McASP3_AHCLKX,McASP4_AHCLKX,McASP5_AHCLKX,Reserved,XREF_CLK0 input pad,XREF_CLK1 input pad,XREF_CLK2 input pad,OSC1_X1 input pad"
|
|
line.long 0x0C "PCLKMUX3,ATLPCLK Selection Register 3"
|
|
bitfld.long 0x0C 0. " PCLKMUX ,ATLPCLK Selection Register Mux" "OCP_CLK,ATLPCLK"
|
|
width 11.
|
|
tree.end
|
|
tree "Touchscreen Controller"
|
|
base ad:0x48450000
|
|
width 22.
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "REVISION,Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,R_RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SYSCONFIG,SYSCONFIG Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Idle mode" "Force Idle,No Idle Mode,Smart-Idle Mode,Smart-Idle-Wakeup"
|
|
group.long 0x20++0x23
|
|
sif (!cpuis("AM335*"))
|
|
line.long 0x00 "IRQ_EOI,IRQ_EOI Register"
|
|
bitfld.long 0x00 0. " LINE_NUMBER ,LINE_NUMBER" "0,1"
|
|
endif
|
|
line.long 0x04 "IRQSTATUS_RAW,IRQSTATUS_RAW Register"
|
|
bitfld.long 0x04 10. " PEN_IRQ_SYNCHRONIZED ,PEN IRQ synchronized" "No event pending,Event pending"
|
|
bitfld.long 0x04 9. " PEN_UP_EVENT ,Pen Up Event" "No event pending,Event pending"
|
|
textline " "
|
|
bitfld.long 0x04 8. " OUT_OF_RANGE ,Out of Range" "No event pending,Event pending"
|
|
bitfld.long 0x04 7. " FIFO1_UNDERFLOW ,FIFO1 Underflow" "No event pending,Event pending"
|
|
textline " "
|
|
bitfld.long 0x04 6. " FIFO1_OVERRUN ,FIFO1 Overrun" "No event pending,Event pending"
|
|
bitfld.long 0x04 5. " FIFO1_THRESHOLD ,FIFO1 Threshold" "No event pending,Event pending"
|
|
textline " "
|
|
bitfld.long 0x04 4. " FIFO0_UNDERFLOW ,FIFO0 Underflow" "No event pending,Event pending"
|
|
bitfld.long 0x04 3. " FIFO0_OVERRUN ,FIFO0 Overrun" "No event pending,Event pending"
|
|
textline " "
|
|
bitfld.long 0x04 2. " FIFO0_THRESHOLD ,FIFO0 Threshold" "No event pending,Event pending"
|
|
bitfld.long 0x04 1. " END_OF_SEQUENCE ,End of Sequence" "No event pending,Event pending"
|
|
textline " "
|
|
bitfld.long 0x04 0. " HW_PEN_EVENT_ASYNCHRONOUS ,HW Pen Event asynchronous" "No event pending,Event pending"
|
|
line.long 0x08 "IRQSTATUS,IRQSTATUS Register"
|
|
setclrfld.long 0x08 10. 0x04 10. 0x08 10. " HW_PEN_IRQ_SYNCHRONIZED_set/clr ,PEN IRQ synchronized" "No event pending,Event pending"
|
|
setclrfld.long 0x08 9. 0x04 9. 0x08 9. " PEN_UP_EVENT_set/clr ,Pen Up Event" "No event pending,Event pending"
|
|
textline " "
|
|
setclrfld.long 0x08 8. 0x04 8. 0x08 8. " OUT_OF_RANGE_set/clr ,Out of Range" "No event pending,Event pending"
|
|
setclrfld.long 0x08 7. 0x04 7. 0x08 7. " FIFO1_UNDERFLOW_set/clr ,FIFO1 Underflow" "No event pending,Event pending"
|
|
textline " "
|
|
setclrfld.long 0x08 6. 0x04 6. 0x08 6. " FIFO1_OVERRUN_set/clr ,FIFO1 Overrun" "No event pending,Event pending"
|
|
setclrfld.long 0x08 5. 0x04 5. 0x08 5. " FIFO1_THRESHOLD_set/clr ,FIFO1 Threshold" "No event pending,Event pending"
|
|
textline " "
|
|
setclrfld.long 0x08 4. 0x04 4. 0x08 4. " FIFO0_UNDERFLOW_set/clr ,FIFO0 Underflow" "No event pending,Event pending"
|
|
setclrfld.long 0x08 3. 0x04 3. 0x08 3. " FIFO0_OVERRUN_set/clr ,FIFO0 Overrun" "No event pending,Event pending"
|
|
textline " "
|
|
setclrfld.long 0x08 2. 0x04 2. 0x08 2. " FIFO0_THRESHOLD_set/clr ,FIFO0 Threshold" "No event pending,Event pending"
|
|
setclrfld.long 0x08 1. 0x04 1. 0x08 1. " END_OF_SEQUENCE_set/clr ,End of Sequence" "No event pending,Event pending"
|
|
textline " "
|
|
setclrfld.long 0x08 0. 0x04 0. 0x08 0. " HW_PEN_EVENT_ASYNCHRONOUS_set/clr ,HW Pen Event asynchronous" "No event pending,Event pending"
|
|
line.long 0x0C "IRQENABLE,IRQENABLE Register"
|
|
setclrfld.long 0x0C 10. 0x0C 10. 0x10 10. " HW_PEN_IRQ_SYNCHRONIZED_set/clr ,PEN IRQ synchronized" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 9. 0x0C 9. 0x10 9. " PEN_UP_EVENT_set/clr ,Pen Up Event" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0C 8. 0x0C 8. 0x10 8. " OUT_OF_RANGE_set/clr ,Out of Range" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 7. 0x0C 7. 0x10 7. " FIFO1_UNDERFLOW_set/clr ,FIFO1 Underflow" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0C 6. 0x0C 6. 0x10 6. " FIFO1_OVERRUN_set/clr ,FIFO1 Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 5. 0x0C 5. 0x10 5. " FIFO1_THRESHOLD_set/clr ,FIFO1 Threshold" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0C 4. 0x0C 4. 0x10 4. " FIFO0_UNDERFLOW_set/clr ,FIFO0 Underflow" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 3. 0x0C 3. 0x10 3. " FIFO0_OVERRUN_set/clr ,FIFO0 Overrun" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0C 2. 0x0C 2. 0x10 2. " FIFO0_THRESHOLD_set/clr ,FIFO0 Threshold" "Disabled,Enabled"
|
|
setclrfld.long 0x0C 1. 0x0C 1. 0x10 1. " END_OF_SEQUENCE_set/clr ,End of Sequence" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0C 0. 0x0C 0. 0x10 0. " HW_PEN_EVENT_ASYNCHRONOUS_set/clr ,HW Pen Event asynchronous" "Disabled,Enabled"
|
|
line.long 0x14 "IRQWAKEUP,IRQWAKEUP Register"
|
|
bitfld.long 0x14 0. " WAKEEN0 ,Wakeup generation for HW Pen event" "Disabled,Enabled"
|
|
line.long 0x18 "DMAENABLE_SET,Per-Line DMA Set Register"
|
|
bitfld.long 0x18 1. " ENABLE_1 ,Enable DMA request FIFO 1" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " ENABLE_0 ,Enable DMA request FIFO 0" "Disabled,Enabled"
|
|
line.long 0x1c "DMAENABLE_CLR,Per-Line DMA Clr Register"
|
|
bitfld.long 0x1c 1. " ENABLE_1 ,Enable DMA request FIFO 1 read/write" "Disabled/No action,Enabled/Disable"
|
|
bitfld.long 0x1c 0. " ENABLE_0 ,Enable DMA request FIFO 0 read/write" "Disabled/No action,Enabled/Disable"
|
|
line.long 0x20 "CTRL,@TSC_ADC_SS Control Register"
|
|
bitfld.long 0x20 9. " HW_PREEMPT ,SW steps are preempted by HW events" "Disabled,Enabled"
|
|
bitfld.long 0x20 8. " HW_EVENT_MAPPING ,Map HW event" "Pen touch irq,HW event input"
|
|
textline " "
|
|
bitfld.long 0x20 7. " TOUCH_SCREEN_ENABLE ,Touchscreen transistors" "Disabled,Enabled"
|
|
bitfld.long 0x20 6. " AFE_PEN_CTRL[1] ,AFE Pen Ctrl (Wiper touch)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x20 5. " AFE_PEN_CTRL[0] ,AFE Pen Ctrl(X+touch)" "Low,High"
|
|
bitfld.long 0x20 4. " POWER_DOWN ,ADC Power Down control" "AFE is Up,AFE is Down"
|
|
textline " "
|
|
bitfld.long 0x20 3. " ADC_BIAS_SELECT ,Select Internal or External Bias to AFE" "Internal,External"
|
|
bitfld.long 0x20 2. " STEPCONFIG_WRITEPROTECT_N_ACTIVE_LOW ,Step configuration registers are protected" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x20 1. " STEP_ID_TAG ,Step ID number with the captured ADC data in the FIFO" "0,ID tag"
|
|
bitfld.long 0x20 0. " ENABLE ,TSC_ADC_SS module enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "ADCSTAT,General Status bits @TSC_ADC_SS_Sequencer_Status Register"
|
|
bitfld.long 0x00 7. " PEN_IRQ1 ,PEN_IRQ[1] status" "Not occured,Occured"
|
|
bitfld.long 0x00 6. " PEN_IRQ0 ,PEN_IRQ[0] status" "Not occured,Occured"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FSM_BUSY ,Status of OCP FSM and ADC FSM" "Idle,Busy"
|
|
bitfld.long 0x00 0.--4. " STEP_ID ,Encoded values" "Step 1,Step 2,Step 3,Step 4,Step 5,Step 6,Step 7,Step 8,Step 9,Step 10,Step 11,Step 12,Step 13,Step 14,Step 15,Step 16,Idle,Charge,?..."
|
|
group.long 0x48++0x1f
|
|
line.long 0x00 "ADCRANGE,High and Low Range Threshold@TSC_ADC_SS_Range_Check Register"
|
|
hexmask.long.word 0x00 12.--27. 1. " HIGH_RANGE_DATA ,Sampled ADC data is compared to this value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOW_RANGE_DATA ,Sampled ADC data is compared to this value"
|
|
line.long 0x04 "ADC_CLKDIV,ADC clock divider register@TSC_ADC_SS_Clock_Divider Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " ADC_CLKDIV ,The input ADC clock will be divided by this value and sent to the AFE"
|
|
line.long 0x08 "ADC_MISC,AFE misc debug@TSC_ADC_SS_MISC Register"
|
|
bitfld.long 0x08 4.--7. " AFE_SPARE_OUTPUT ,Connected to AFE Spare Output pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " AFE_SPARE_INPUT ,Connected to AFE Spare Input pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0c "STEPENABLE,Step Enable Registe"
|
|
bitfld.long 0x0c 16. " STEP16 ,Enable step 16" "Disabled,Enabled"
|
|
bitfld.long 0x0c 15. " STEP15 ,Enable step 115" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 14. " STEP14 ,Enable step 14" "Disabled,Enabled"
|
|
bitfld.long 0x0c 13. " STEP13 ,Enable step 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " STEP12 ,Enable step 112" "Disabled,Enabled"
|
|
bitfld.long 0x0c 11. " STEP11 ,Enable step 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " STEP10 ,Enable step 10" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " STEP9 ,Enable step 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 8. " STEP8 ,Enable step 8" "Disabled,Enabled"
|
|
bitfld.long 0x0c 7. " STEP7 ,Enable step 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " STEP6 ,Enable step 6" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " STEP5 ,Enable step 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " STEP4 ,Enable step 4" "Disabled,Enabled"
|
|
bitfld.long 0x0c 3. " STEP3 ,Enable step 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " STEP2 ,Enable step 2" "Disabled,Enabled"
|
|
bitfld.long 0x0c 1. " STEP1 ,Enable step 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " TS_CHARGE ,Enable TS Charge step" "Disabled,Enabled"
|
|
line.long 0x10 "IDLECONFIG,Idle Step configuration@TSC_ADC_SS_IDLE_StepConfig Registerr"
|
|
bitfld.long 0x10 25. " DIFF_CNTRL ,Differential Control Pin" "Single Ended,Differential Pair"
|
|
bitfld.long 0x10 23.--24. " SEL_RF_MUNDER_SCORE_UNDER_SCORE_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x10 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x10 15.--18. " SEL_INM_SWM3_0 ,SEL_INM pins for neg differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x10 12.--14. " SEL_RFP_UNDER_SCORE_UNDER_SCORE_SWC_2_0 ,SEL_RFP pins SW configuration" "VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x10 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x10 7. " YPPSWUNDERSCOREUNDERSCORESWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 6. " XNNSWUNDERSCOREUNDERSCORESWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
line.long 0x14 "TS_CHARGE_STEPCONFIG,TS Charge StepConfiguration@TSC_ADC_SS_TS_Charge_StepConfig Register"
|
|
bitfld.long 0x14 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x14 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN"
|
|
textline " "
|
|
bitfld.long 0x14 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN"
|
|
else
|
|
bitfld.long 0x14 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x14 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
endif
|
|
bitfld.long 0x14 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF,INTREF"
|
|
textline " "
|
|
bitfld.long 0x14 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
line.long 0x18 "TS_CHARGE_DELAY,TS Charge Delay Register"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. " OPENDELAY ,Program the # of ADC clock cycles to wait between applying the step configuration registers and going back to the IDLE state"
|
|
tree "Step Configuration & Step Delay Registers"
|
|
group.long 0x64++0x7f
|
|
line.long 0x0 "STEPCONFIG1,Step configuration 1"
|
|
bitfld.long 0x0 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x0 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x0 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x0 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x0 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x0 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x0 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x0 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x0 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x0 "STEPDELAY1,Step Delay Register 1"
|
|
hexmask.long.byte 0x04+0x0 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x0 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x8 "STEPCONFIG2,Step configuration 2"
|
|
bitfld.long 0x8 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x8 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x8 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x8 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x8 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x8 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x8 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x8 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x8 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x8 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x8 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x8 "STEPDELAY2,Step Delay Register 2"
|
|
hexmask.long.byte 0x04+0x8 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x8 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x10 "STEPCONFIG3,Step configuration 3"
|
|
bitfld.long 0x10 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x10 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x10 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x10 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x10 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x10 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x10 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x10 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x10 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x10 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x10 "STEPDELAY3,Step Delay Register 3"
|
|
hexmask.long.byte 0x04+0x10 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x10 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x18 "STEPCONFIG4,Step configuration 4"
|
|
bitfld.long 0x18 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x18 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x18 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x18 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x18 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x18 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x18 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x18 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x18 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x18 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x18 "STEPDELAY4,Step Delay Register 4"
|
|
hexmask.long.byte 0x04+0x18 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x18 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x20 "STEPCONFIG5,Step configuration 5"
|
|
bitfld.long 0x20 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x20 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x20 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x20 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x20 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x20 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x20 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x20 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x20 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x20 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x20 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x20 "STEPDELAY5,Step Delay Register 5"
|
|
hexmask.long.byte 0x04+0x20 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x20 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x28 "STEPCONFIG6,Step configuration 6"
|
|
bitfld.long 0x28 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x28 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x28 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x28 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x28 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x28 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x28 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x28 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x28 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x28 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x28 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x28 "STEPDELAY6,Step Delay Register 6"
|
|
hexmask.long.byte 0x04+0x28 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x28 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x30 "STEPCONFIG7,Step configuration 7"
|
|
bitfld.long 0x30 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x30 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x30 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x30 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x30 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x30 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x30 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x30 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x30 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x30 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x30 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x30 "STEPDELAY7,Step Delay Register 7"
|
|
hexmask.long.byte 0x04+0x30 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x30 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x38 "STEPCONFIG8,Step configuration 8"
|
|
bitfld.long 0x38 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x38 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x38 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x38 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x38 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x38 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x38 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x38 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x38 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x38 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x38 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x38 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x38 "STEPDELAY8,Step Delay Register 8"
|
|
hexmask.long.byte 0x04+0x38 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x38 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x40 "STEPCONFIG9,Step configuration 9"
|
|
bitfld.long 0x40 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x40 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x40 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x40 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x40 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x40 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x40 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x40 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x40 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x40 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x40 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x40 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x40 "STEPDELAY9,Step Delay Register 9"
|
|
hexmask.long.byte 0x04+0x40 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x40 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x48 "STEPCONFIG10,Step configuration 10"
|
|
bitfld.long 0x48 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x48 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x48 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x48 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x48 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x48 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x48 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x48 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x48 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x48 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x48 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x48 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x48 "STEPDELAY10,Step Delay Register 10"
|
|
hexmask.long.byte 0x04+0x48 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x48 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x50 "STEPCONFIG11,Step configuration 11"
|
|
bitfld.long 0x50 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x50 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x50 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x50 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x50 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x50 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x50 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x50 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x50 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x50 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x50 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x50 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x50 "STEPDELAY11,Step Delay Register 11"
|
|
hexmask.long.byte 0x04+0x50 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x50 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x58 "STEPCONFIG12,Step configuration 12"
|
|
bitfld.long 0x58 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x58 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x58 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x58 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x58 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x58 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x58 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x58 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x58 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x58 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x58 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x58 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x58 "STEPDELAY12,Step Delay Register 12"
|
|
hexmask.long.byte 0x04+0x58 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x58 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x60 "STEPCONFIG13,Step configuration 13"
|
|
bitfld.long 0x60 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x60 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x60 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x60 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x60 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x60 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x60 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x60 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x60 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x60 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x60 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x60 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x60 "STEPDELAY13,Step Delay Register 13"
|
|
hexmask.long.byte 0x04+0x60 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x60 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x68 "STEPCONFIG14,Step configuration 14"
|
|
bitfld.long 0x68 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x68 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x68 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x68 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x68 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x68 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x68 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
|
bitfld.long 0x68 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x68 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x68 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
|
|
bitfld.long 0x68 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
|
|
bitfld.long 0x68 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
|
|
line.long 0x04+0x68 "STEPDELAY14,Step Delay Register 14"
|
|
hexmask.long.byte 0x04+0x68 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
|
|
hexmask.long.tbyte 0x04+0x68 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
|
|
line.long 0x70 "STEPCONFIG15,Step configuration 15"
|
|
bitfld.long 0x70 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
|
|
bitfld.long 0x70 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
|
|
textline " "
|
|
bitfld.long 0x70 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
|
|
bitfld.long 0x70 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x70 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
bitfld.long 0x70 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
|
|
textline " "
|
|
bitfld.long 0x70 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
|
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bitfld.long 0x70 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
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textline " "
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bitfld.long 0x70 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
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bitfld.long 0x70 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
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textline " "
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bitfld.long 0x70 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
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bitfld.long 0x70 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
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textline " "
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bitfld.long 0x70 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
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bitfld.long 0x70 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
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textline " "
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bitfld.long 0x70 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
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bitfld.long 0x70 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
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line.long 0x04+0x70 "STEPDELAY15,Step Delay Register 15"
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hexmask.long.byte 0x04+0x70 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
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hexmask.long.tbyte 0x04+0x70 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
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line.long 0x78 "STEPCONFIG16,Step configuration 16"
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bitfld.long 0x78 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC"
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bitfld.long 0x78 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1"
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textline " "
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bitfld.long 0x78 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled"
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bitfld.long 0x78 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM"
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textline " "
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bitfld.long 0x78 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
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bitfld.long 0x78 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM"
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textline " "
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bitfld.long 0x78 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF"
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bitfld.long 0x78 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled"
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textline " "
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bitfld.long 0x78 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled"
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bitfld.long 0x78 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled"
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textline " "
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bitfld.long 0x78 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled"
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bitfld.long 0x78 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled"
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textline " "
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bitfld.long 0x78 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled"
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bitfld.long 0x78 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled"
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textline " "
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bitfld.long 0x78 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..."
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bitfld.long 0x78 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous"
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line.long 0x04+0x78 "STEPDELAY16,Step Delay Register 16"
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hexmask.long.byte 0x04+0x78 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample"
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hexmask.long.tbyte 0x04+0x78 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait"
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tree.end
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rgroup.long 0xE4++0x3
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line.long 0x00 "FIFO0COUNT,FIFO0COUNT Register"
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hexmask.long.byte 0x00 0.--6. 1. " WORDS_IN_FIFO ,Number of words currently in the FIFO"
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group.long 0xE8++0x7
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line.long 0x00 "FIFO0THRESHOLD,FIFO0 Threshold trigger@TSC_ADC_SS_FIFO0 Threshold Level Register"
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hexmask.long.byte 0x00 0.--5. 1. " FIFO0_THRESHOLD_LEVEL ,Program the desired FIFO0 data sample level to reach before generating interrupt to CPU"
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line.long 0x04 "DMA0REQ,FIFO0 DMA req0 trigger@TSC_ADC_SS_FIFO0 DMA REQUEST Register"
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hexmask.long.byte 0x04 0.--5. 1. " DMA_REQUEST_LEVEL ,Number of words in FIFO0 before generating a DMA request"
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sif (cpuis("DRA62*")||cpuis("AM335*"))
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rgroup.long 0xf0++0x3
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line.long 0x00 "FIFO1COUNT,FIFO1COUNT Register"
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hexmask.long.byte 0x00 0.--6. 1. " WORDS_IN_FIFO ,FIFO1 Word Count Register"
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else
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rgroup.long 0xf0++0x3
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line.long 0x00 "FIFO1COUNT,FIFO1COUNT Register"
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hexmask.long.byte 0x00 0.--5. 1. " WORDS_IN_FIFO ,FIFO1 Word Count Register"
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endif
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group.long 0xF4++0x7
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line.long 0x00 "FIFO1THRESHOLD,FIFO1 Threshold Level Register"
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hexmask.long.byte 0x00 0.--5. 1. " FIFO1_THRESHOLD_LEVEL ,Program the desired FIFO1 data sample level to reach before generating interrupt to CPU"
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line.long 0x04 "DMA1REQ,FIFO1 DMA Request Register"
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hexmask.long.byte 0x04 0.--5. 1. " DMA_REQUEST_LEVEL ,Number of words in FIFO1 before generating a DMA request"
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rgroup.long 0x100++0x3
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line.long 0x00 "FIFO0DATA,ADC_ FIFO0 _READ Data @TSC_ADC_SS_FIFO0 READ Register"
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hexmask.long.byte 0x00 16.--19. 1. " ADCCHNLID ,Optional ID tag of channel that captured the data"
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hexmask.long.word 0x00 0.--11. 1. " ADCDATA ,12 bit sampled ADC converted data value stored in FIFO 0"
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rgroup.long 0x200++0x3
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line.long 0x00 "FIFO1DATA,ADC_ FIFO1 _READ Data @TSC_ADC_SS_FIFO1 READ Register"
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hexmask.long.byte 0x00 16.--19. 1. " ADCCHNLID ,Optional ID tag of channel that captured the data"
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hexmask.long.word 0x00 0.--11. 1. " ADCDATA ,12 bit sampled ADC converted data value stored in FIFO 1"
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tree.end
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endif
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textline ""
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