12127 lines
860 KiB
Plaintext
12127 lines
860 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: 88MW32X On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2022-10-19 NEJ
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: SVD generated (SVD2PER 1.8.6), based on: 88MW320.svd (Ver. 1.0)
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; @Core: Cortex-M4F
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; @Chip: 88MW320, 88MW322
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: per88mw32x.per 15328 2022-10-20 10:09:15Z kwisniewski $
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
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bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
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line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
autoindent.on center tree
|
|
tree "ACOMP"
|
|
base ad:0x460B0400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ctrl0,ACOMP0 Control Register"
|
|
bitfld.long 0x00 31. "edge_levl_sel,ACOMP0 interrupt type select" "0: level triggered interrupt,1: edge triggered interrupt"
|
|
bitfld.long 0x00 30. "int_act_hi,ACOMP0 interrupt active mode select" "0: Low level or falling edge triggered interrupt,1: High level or rising edge triggered interrupt"
|
|
newline
|
|
bitfld.long 0x00 29. "fie,ACOMP0 enable/disable falling edge triggered edge pulse" "0: no description available,1: no description available"
|
|
bitfld.long 0x00 28. "rie,ACOMP0 enable/disable rising edge triggered edge pulse" "0: no description available,1: no description available"
|
|
newline
|
|
bitfld.long 0x00 27. "inact_val,Set output value when ACOMP0 is inactive" "0: output 0 when ACOMP0 is inactive,1: output 1 when ACOMP0 is inactive"
|
|
bitfld.long 0x00 26. "muxen,ACOMP0 input MUX enable bit" "0: disable input mux,1: enable input mux"
|
|
newline
|
|
bitfld.long 0x00 22.--25. "pos_sel,ACOMP0 positive input select bits" "0: acomp_ch<0>,1: acomp_ch<1>,2: acomp_ch<2>,3: acomp_ch<3>,4: acomp_ch<4>,5: acomp_ch<5>,6: acomp_ch<6>,7: acomp_ch<7>,8: no description available,9: no description available,?..."
|
|
bitfld.long 0x00 18.--21. "neg_sel,ACOMP0 negative input select bits" "0: acomp_ch<0>,1: acomp_ch<1>,2: acomp_ch<2>,3: acomp_ch<3>,4: acomp_ch<4>,5: acomp_ch<5>,6: acomp_ch<6>,7: acomp_ch<7>,8: no description available,9: no description available,10: no description available,11: no description available,12: vio*scaling factor,13: vio*scaling factor,14: vio*scaling factor,15: vio*scaling factor"
|
|
newline
|
|
bitfld.long 0x00 12.--17. "level_sel,Scaling factor select bits for VIO reference level" "0: Scaling factor=0.25,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: Scaling factor= 0.5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Scaling factor= 0.75,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,48: Scaling factor= 1,?..."
|
|
bitfld.long 0x00 10.--11. "bias_prog,ACOMP0 bias current control bits or response time control bits" "0: power mode1 (slow response mode),1: power mode2 (medium response mode),2: power mode3 (fast response mode),?..."
|
|
newline
|
|
bitfld.long 0x00 7.--9. "hyst_selp,Select ACOMP0 positive hysteresis voltage level" "0: No hysteresis,1: +10 mV hysteresis,2: +20 mV hysteresis,3: +30 mV hysteresis,4: +40 mV hysteresis,5: +50 mV hysteresis,6: +60 mV hysteresis,7: +70 mV hysteresis"
|
|
bitfld.long 0x00 4.--6. "hyst_seln,Select ACOMP0 negative hysteresis voltage level" "0: no hysteresis,1: -10 mV hysteresis,2: -20 mV hysteresis,3: -30 mV hysteresis,4: -40 mV hysteresis,5: -50 mV hysteresis,6: -60 mV hysteresis,7: -70 mV hysteresis"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "warmtime,Set ACOMP0 Warm-Up time" "0: 1 us,1: 2 us,2: 4 us,3: 8 us"
|
|
bitfld.long 0x00 1. "gpioinv,Enable/Disable inversion of ACOMP0 output to GPIO" "0: do not invert ACOMP0 output,1: invert ACOMP0 output"
|
|
newline
|
|
bitfld.long 0x00 0. "en,ACOMP0 enable" "0: no description available,1: no description available"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ctrl1,ACOMP1 Control Register"
|
|
bitfld.long 0x00 31. "edge_levl_sel,ACOMP1 interrupt type select" "0: level triggered interrupt,1: edge triggered interrupt"
|
|
bitfld.long 0x00 30. "int_act_hi,ACOMP1 interrupt active mode select" "0: Low level or falling edge triggered interrupt,1: High level or rising edge triggered interrupt"
|
|
newline
|
|
bitfld.long 0x00 29. "fie,ACOMP1 enable/disable falling edge triggered edge pulse" "0: no description available,1: no description available"
|
|
bitfld.long 0x00 28. "rie,ACOMP1 enable/disable rising edge triggered edge pulse" "0: no description available,1: no description available"
|
|
newline
|
|
bitfld.long 0x00 27. "inact_val,Set output value when ACOMP1 is inactive" "0: output 0 when ACOMP1 is inactive,1: output 1 when ACOMP1 is inactive"
|
|
bitfld.long 0x00 26. "muxen,ACOMP1 input MUX enable" "0: disable input mux,1: enable input mux"
|
|
newline
|
|
bitfld.long 0x00 22.--25. "pos_sel,ACOMP1 positive input select" "0: acomp_ch<0>,1: acomp_ch<1>,2: acomp_ch<2>,3: acomp_ch<3>,4: acomp_ch<4>,5: acomp_ch<5>,6: acomp_ch<6>,7: acomp_ch<7>,8: no description available,9: no description available,?..."
|
|
bitfld.long 0x00 18.--21. "neg_sel,ACOMP1 negative input select" "0: acomp_ch<0>,1: acomp_ch<1>,2: acomp_ch<2>,3: acomp_ch<3>,4: acomp_ch<4>,5: acomp_ch<5>,6: acomp_ch<6>,7: acomp_ch<7>,8: no description available,9: no description available,10: no description available,11: no description available,12: vio*scaling factor,13: vio*scaling factor,14: vio*scaling factor,15: vio*scaling factor"
|
|
newline
|
|
bitfld.long 0x00 12.--17. "level_sel,Scaling factor select bits for vio reference level" "0: Scaling factor=0.25,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: Scaling factor= 0.5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Scaling factor= 0.75,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,48: Scaling factor= 1,?..."
|
|
bitfld.long 0x00 10.--11. "bias_prog,ACOMP1 bias current control bits Or response time control bits" "0: power mode1 (Slow response mode),1: power mode2 (Medium response mode),2: power mode3 (Fast response mode),?..."
|
|
newline
|
|
bitfld.long 0x00 7.--9. "hyst_selp,Select ACOMP1 positive hysteresis voltage level" "0: No hysteresis,1: +10 mV hysteresis,2: +20 mV hysteresis,3: +30 mV hysteresis,4: +40 mV hysteresis,5: +50 mV hysteresis,6: +60 mV hysteresis,7: +70 mV hysteresis"
|
|
bitfld.long 0x00 4.--6. "hyst_seln,Select ACOMP1 negative hysteresis voltage level" "0: No hysteresis,1: -10 mV hysteresis,2: -20 mV hysteresis,3: -30 mV hysteresis,4: -40 mV hysteresis,5: -50 mV hysteresis,6: -60 mV hysteresis,7: -70 mV hysteresis"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "warmtime,Set ACOMP1 warm-up time" "0: 1 us,1: 2 us,2: 4 us,3: 8 us"
|
|
bitfld.long 0x00 1. "gpioinv,Enable/disable inversion of ACOMP1 output to GPIO" "0: do not invert ACOMP1 output,1: invert ACOMP1 output"
|
|
newline
|
|
bitfld.long 0x00 0. "en,ACOMP1 enable bit" "0: no description available,1: no description available"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "status0,ACOMP0 Status Register"
|
|
bitfld.long 0x00 1. "out,ACOMP0 comparison output value" "0,1"
|
|
bitfld.long 0x00 0. "act,ACOMP0 active status" "0: ACOMP0 is inactive,1: ACOMP0 is active"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "status1,ACOMP1 Status Register"
|
|
bitfld.long 0x00 1. "out,ACOMP1 comparison output value" "0,1"
|
|
bitfld.long 0x00 0. "act,ACOMP1 active status" "0: ACOMP1 is inactive,1: ACOMP1 is active"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "route0,ACOMP0 Route Register"
|
|
bitfld.long 0x00 1. "pe,Enable/disable ACOMP0 output to pin" "0: no description available,1: no description available"
|
|
bitfld.long 0x00 0. "outsel,Select ACOMP0 synchronous or asynchronous output to pin" "0: Synchronous output,1: Asynchronous output"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "route1,ACOMP1 Route Register"
|
|
bitfld.long 0x00 1. "pe,Enable/disable ACOMP1 output to pin" "0: no description available,1: no description available"
|
|
bitfld.long 0x00 0. "outsel,Select ACOMP1 synchronous or asynchronous output to pin" "0: Synchronous output,1: Asynchronous output"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "isr0,ACOMP0 Interrupt Status Register"
|
|
bitfld.long 0x00 1. "outa_int,ACOMP0 Asynchronized Output Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "out_int,ACOMP0 Synchronized Output Interrupt" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "isr1,ACOMP1 Interrupt Status Register"
|
|
bitfld.long 0x00 1. "outa_int,ACOMP1 Asynchronized Output Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "out_int,ACOMP1 Synchronized Output Interrupt" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "imr0,ACOMP0 Interrupt Mask Register"
|
|
bitfld.long 0x00 1. "outa_int_mask,Mask Asynchronized Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "out_int_mask,Mask Synchronized Interrupt" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "imr1,ACOMP1 Interrupt Mask Register"
|
|
bitfld.long 0x00 1. "outa_int_mask,Mask Asynchronized Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "out_int_mask,Mask Synchronized Interrupt" "0,1"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "irsr0,ACOMP0 Interrupt Raw Status Register"
|
|
bitfld.long 0x00 1. "outa_int_raw,Raw Mask Asynchronized Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "out_int_raw,Raw Mask Synchronized Interrupt" "0,1"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "irsr1,ACOMP1 Interrupt Raw Status Register"
|
|
bitfld.long 0x00 1. "outa_int_raw,Raw Mask Asynchronized Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "out_int_raw,Raw Mask Synchronized Interrupt" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "icr0,ACOMP0 Interrupt Clear Register"
|
|
bitfld.long 0x00 1. "outa_int_clr,ACOMP0 asyncrhonized output interrupt flag clear signal" "0,1"
|
|
bitfld.long 0x00 0. "out_int_clr,ACOMP0 syncrhonized output interrupt flag clear signal" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "icr1,ACOMP1 Interrupt Clear Register"
|
|
bitfld.long 0x00 1. "outa_int_clr,ACOMP1 asyncrhonized output interrupt flag clear signal" "0,1"
|
|
bitfld.long 0x00 0. "out_int_clr,ACOMP1 syncrhonized output interrupt flag clear signal" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "rst0,ACOMP0 Soft Reset Register"
|
|
bitfld.long 0x00 0. "soft_rst,Soft Reset for ACOMP0 (active high)" "0: no action,1: no description available"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "rst1,ACOMP1 Soft Reset Register"
|
|
bitfld.long 0x00 0. "soft_rst,Soft Reset for ACOMP1 (active high)" "0: no action,1: no description available"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "clk,Clock Register"
|
|
bitfld.long 0x00 1. "soft_clk_rst,soft reset for clock divider" "0: no action,1: no description available"
|
|
tree.end
|
|
tree "ADC"
|
|
base ad:0x460B0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "adc_reg_cmd,no description available"
|
|
bitfld.long 0x00 2. "soft_clk_rst,user reset clock" "0,1"
|
|
bitfld.long 0x00 1. "soft_rst,user reset the whole block" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "conv_start,converaion control bit" "0: stop converation,1: start converation"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "adc_reg_general,no description available"
|
|
bitfld.long 0x00 8.--13. "clk_div_ratio,analog 64M clock division ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 5. "adc_cal_en,calibration enable auto cleared after calibration done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "clk_ana2M_inv,analog clock 2M inverted" "0,1"
|
|
bitfld.long 0x00 3. "clk_ana64M_inv,analog clock 64M inverted" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "global_en,ADC enable/disable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "adc_reg_config,no description available"
|
|
bitfld.long 0x00 20. "pwr_mode,ADC power mode select" "0: Power mode 0,1: Power mode 1"
|
|
bitfld.long 0x00 16.--19. "scan_length,scan converation length actual length is scan_length+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "avg_sel,moving average length" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "cal_data_sel,select calibration data source" "0: use self calibration data,1: user user defined calibration data"
|
|
newline
|
|
bitfld.long 0x00 11. "cal_data_rst,reset the self calibration data" "0: no reset,1: no description available"
|
|
bitfld.long 0x00 10. "cal_vref_sel,select input reference channel for gain calibration" "0: select internal vref as input for calibration,1: select external vref as input for calibration"
|
|
newline
|
|
bitfld.long 0x00 9. "data_format_sel,set data format for the final data" "0: signed differential code in two's complement,1: unsigned single-end code"
|
|
bitfld.long 0x00 8. "cont_conv_en,To enable continuous conversion" "0: one shot conversion,1: continuous conversion"
|
|
newline
|
|
bitfld.long 0x00 4. "trigger_en,External elevel trigger enable bit support gpadc_trigger/gpadc_data_valid handshake" "0: no description available,1: conversion start further controlled by.."
|
|
bitfld.long 0x00 0.--3. "trigger_sel,External trigger source select bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "adc_reg_interval,no description available"
|
|
bitfld.long 0x00 5. "bypass_warmup,Bypass warmup state inside adc" "0: adc warmup state enabled (warmup period is..,1: adc warmup state bypassed"
|
|
bitfld.long 0x00 0.--4. "Warmup_time,warmup time should be set equal to or higher than 1uS" "0: ADC warm-up is 1us,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: ADC warm-up is 32us"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "adc_reg_ana,no description available"
|
|
bitfld.long 0x00 17.--18. "res_sel,adc resolution/data rate select" "0,1,2,3"
|
|
bitfld.long 0x00 16. "bias_sel,adc analog portion low power mode select" "0: Full biasing current,1: Half biasing current"
|
|
newline
|
|
bitfld.long 0x00 15. "chop_en,adc chopper/auto-zero(only in 12bit mode) enable" "0: disable chopper,1: enable chopper"
|
|
bitfld.long 0x00 14. "inbuf_en,gpadc input gain buffer enable bit" "0: input gain buffer disabled,1: input gain buffer enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "inbuf_chop_en,Input buffer chopper enable" "0: disable chopper,1: enable chopper"
|
|
bitfld.long 0x00 11.--12. "inbuf_gain,adc gain control" "0: PGA gain is 0.5,1: PGA gain is 1,2: PGA gain is 2,?..."
|
|
newline
|
|
bitfld.long 0x00 10. "Singlediff,Select single ended or differential input" "0: Single-ended input,1: Differential input"
|
|
bitfld.long 0x00 4.--5. "vref_sel,adc reference voltage select" "0: Internal 1.8V vaa,1: Internal 1.2V bandgap,2: External single-ended reference (gpadc_ch[3]),3: Internal 1.2V bandgap with external bypass.."
|
|
newline
|
|
bitfld.long 0x00 3. "vref_chop_en,adc voltage reference buffer chopper enable" "0: disable chopper,1: enable chopper"
|
|
bitfld.long 0x00 2. "vref_scf_bypass,adc voltage reference buffer sc-filter bypass" "0: not bypass sc-filter,1: bypass sc-filter"
|
|
newline
|
|
bitfld.long 0x00 1. "ts_en,temperature sensor enable only enable when channel source is temperature sensor" "0: no description available,1: no description available"
|
|
bitfld.long 0x00 0. "tsext_sel,temperature sensor diode select" "0: internal diode mode,1: external diode mode"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "adc_reg_scn1,adc converation sequence 1"
|
|
bitfld.long 0x00 28.--31. "scan_ch_7,amux source 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "scan_ch_6,amux source 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "scan_ch_5,amux source 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "scan_ch_4,amux source 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "scan_ch_3,amux source 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "scan_ch_2,amux source 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "scan_ch_1,amux source 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "scan_ch_0,amux source 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "adc_reg_scn2,adc converation sequence 2"
|
|
bitfld.long 0x00 28.--31. "scan_ch_15,amux source 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "scan_ch_14,amux source 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "scan_ch_13,amux source 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "scan_ch_12,amux source 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "scan_ch_11,amux source 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "scan_ch_10,amux source 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "scan_ch_9,amux source 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "scan_ch_8,amux source 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "adc_reg_result_buf,no description available"
|
|
bitfld.long 0x00 0. "width_sel,adc finial result fifo data packed format select must set scan_length as even when choose 32-bits" "0: 16-bits and adc_reg_result fifo is lower..,1: 32-bits and adc_reg_result fifo is 32-bits.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "adc_reg_dmar,no description available"
|
|
bitfld.long 0x00 1.--2. "fifo_thl,fifo threshold" "0: 1 data,1: 4 data,2: 8 data,3: 16 data"
|
|
bitfld.long 0x00 0. "dma_en,dma enbale" "0: disable dma handshake,1: enable dma handshake"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "adc_reg_status,no description available"
|
|
bitfld.long 0x00 3.--8. "fifo_data_count,fifo data number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 2. "fifo_full,fifo full status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "fifo_ne,fifo not empty status" "0,1"
|
|
bitfld.long 0x00 0. "act,adc status" "0: ADC converstion inactive status,1: ADC conversion active status"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "adc_reg_isr,no description available"
|
|
bitfld.long 0x00 6. "fifo_underrun,FIFO underrun interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "fifo_overrun,FIFO overrun interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "datasat_pos,ADC data positive side saturation interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "datasat_neg,ADC data negative side saturation interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "offsat,Offset correction saturation interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "gainsat,Gain correction saturation interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "rdy,Conversion data ready interrupt flag" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "adc_reg_imr,no description available"
|
|
bitfld.long 0x00 6. "fifo_underrun_mask,write 1 mask" "0,1"
|
|
bitfld.long 0x00 5. "fifo_overrun_mask,write 1 mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "datasat_pos_mask,write 1 mask" "0,1"
|
|
bitfld.long 0x00 3. "datasat_neg_mask,write 1 mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "offsat_mask,write 1 mask" "0,1"
|
|
bitfld.long 0x00 1. "gainsat_mask,write 1 mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "rdy_mask,write 1 mask" "0,1"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "adc_reg_irsr,no description available"
|
|
bitfld.long 0x00 6. "fifo_underrun_raw,The corresponding flag will be captured into this register regardless the interrupt mask" "0,1"
|
|
bitfld.long 0x00 5. "fifo_overrun_raw,The corresponding flag will be captured into this register regardless the interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "datasat_pos_raw,The corresponding flag will be captured into this register regardless the interrupt mask" "0,1"
|
|
bitfld.long 0x00 3. "datasat_neg_raw,The corresponding flag will be captured into this register regardless the interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "offsat_raw,The corresponding flag will be captured into this register regardless the interrupt mask" "0,1"
|
|
bitfld.long 0x00 1. "gainsat_raw,The corresponding flag will be captured into this register regardless the interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "rdy_raw,The corresponding flag will be captured into this register regardless the interrupt mask" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "adc_reg_icr,no description available"
|
|
bitfld.long 0x00 6. "fifo_underrun_clr,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
|
|
bitfld.long 0x00 5. "fifo_overrun_clr,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "datasat_pos_clr,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
|
|
bitfld.long 0x00 3. "datasat_neg_clr,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "offsat_clr,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
|
|
bitfld.long 0x00 1. "gainsat_clr,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "rdy_clr,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "adc_reg_result,no description available"
|
|
hexmask.long 0x00 0.--31. 1. "data,ADC finial conversion result data after calibratiob and signed/unsigned process"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "adc_reg_raw_result,no description available"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "raw_data,ADC Raw data in signed 22bit format"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "adc_reg_offset_cal,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "offset_cal_usr,User offset calibration data"
|
|
hexmask.long.word 0x00 0.--15. 1. "offset_cal,ADC self offset calibration value"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "adc_reg_gain_cal,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "gain_cal_usr,ADC user gain calibration value"
|
|
hexmask.long.word 0x00 0.--15. 1. "gain_cal,ADC self gain calibration value"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "adc_reg_test,no description available"
|
|
bitfld.long 0x00 1.--3. "test_sel,no description available" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "test_en,Analog test enable" "0: disable analog test,1: enable analog test"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "adc_reg_audio,no description available"
|
|
bitfld.long 0x00 9. "pga_chop_en,Audio PGA chopper enable" "0: disable audio pga chopper,1: enable audio pga chopper"
|
|
bitfld.long 0x00 6.--8. "pga_cm,Audio PGA output common mode control" "0: common mode is 0.82V,1: common mode is 0.84V,2: common mode is 0.86V,3: common mode is 0.88V,4: common mode is 0.90V,5: common mode is 0.92V,6: common mode is 0.94V,7: common mode is 0.96V"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "pga_gain,Audio PGA voltage gain select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "en,Audio enable" "0: disable audio pga and decimation rate select,1: enable audio pga and decimation rate select"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "adc_reg_voice_det,no description available"
|
|
bitfld.long 0x00 1.--3. "level_sel,Voice level selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "det_en,Voice level detection enable select" "0: Disable level detection,1: Ensable level detection"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "adc_reg_rsvd,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "unused_ADC,no description available"
|
|
tree.end
|
|
tree "AES"
|
|
base ad:0x44004000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ctrl1,AES Control Register 1"
|
|
bitfld.long 0x00 26. "cts_mode,Cipher stealing mode of CBC" "0: Marvell mode,1: NIST-CS2 mode"
|
|
hexmask.long.byte 0x00 19.--25. 1. "ctr_mod,CTR mode's counter modular"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "mode,AES running mode" "0: no description available,1: no description available,2: no description available,?,?,5: CCM*,6: no description available,7: no description available"
|
|
bitfld.long 0x00 15. "decrypt,Decrypt operation (ignored in MMO and BYPASS mode)" "0: no description available,1: no description available"
|
|
newline
|
|
bitfld.long 0x00 14. "out_mic,Append MIC/HASH at the end of output stream in CCM* mode" "0: Not append MIC/HASH at the end of output..,1: Append MIC/HASH at the end of output stream.."
|
|
bitfld.long 0x00 12.--13. "mic_len,Length of MIC field" "0: 0 bytes,1: 4 bytes,2: 8 bytes,3: 16 bytes"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "key_size,Key size parameter" "0: 16 bytes,1: 32 bytes,2: 24 bytes,?..."
|
|
bitfld.long 0x00 9. "dma_en,Enable DMA" "0: Disable DMA,1: Enable DMA"
|
|
newline
|
|
bitfld.long 0x00 8. "io_src,AES data input source" "0: I/O through register,1: I/O through DMA"
|
|
bitfld.long 0x00 7. "pri1,AES priority on hardware (BH-MAC) side" "0: Low priority,1: High priority"
|
|
newline
|
|
bitfld.long 0x00 6. "pri0,AES priority on MCU (software) side" "0: Low priority,1: High priority"
|
|
bitfld.long 0x00 5. "out_hdr,Output B0 and l(a) in CCM* mode" "0: do not output B0 and l(a) at the beginning of..,1: output B0 and l(a) at the beginning of output.."
|
|
newline
|
|
bitfld.long 0x00 4. "out_msg,Output stream to output FIFO" "0: block output stream from output FIFO,1: forward output stream to output FIFO"
|
|
bitfld.long 0x00 3. "of_clr,Clear output FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "if_clr,Clear input FIFO" "0,1"
|
|
bitfld.long 0x00 1. "lock0,Lock AES on MCU side" "0: Write 0 to release AES,1: Write 1 to lock AES on behalf of MCU"
|
|
newline
|
|
bitfld.long 0x00 0. "start,Start AES" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ctrl2,AES Control Register 2"
|
|
bitfld.long 0x00 1. "auto_reset_en,Enable atutomatic reset after lock successfully" "0: No automatic reset,1: Automatic reset after lock successfully"
|
|
bitfld.long 0x00 0. "aes_reset,Reset AES" "0: un-reset AES,1: Reset AES"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "status,AES Status Register"
|
|
bitfld.long 0x00 20. "rsvd_vld,RSVD Valid" "0: rsvd0 and rsvd1 not valid,1: rsvd0 and rsvd1 are valid"
|
|
bitfld.long 0x00 17.--19. "of_depth,output FIFO depth" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 14.--16. "if_depth,input FIFO depth" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11.--13. "status,AES operation error status" "0: No operation error,1: Input stream size less than 16 byte in ECB..,2: Data is not multiple of 16 bytes in ECB mode..,3: Data is not multiple of 16 bytes and less..,4: MIC Mismatch during CCM* Decryption,?..."
|
|
newline
|
|
bitfld.long 0x00 7. "of_empty,Output FIFO empty" "0: Output FIFO is not empty,1: Output FIFO is empty"
|
|
bitfld.long 0x00 6. "of_rdy,Output FIFO is ready to" "0: Output FIFO is not ready to,1: Output FIFO is ready to"
|
|
newline
|
|
bitfld.long 0x00 4. "if_full,Input FIFO full" "0: Input FIFO is not full,1: Input FIFO is full"
|
|
bitfld.long 0x00 3. "lock1,Lock AES on hardware (BH-MAC) side" "0: hardware unlocks AES,1: hardware requests to lock AES"
|
|
newline
|
|
bitfld.long 0x00 2. "rsvd1,AES is locked by hardware (BH-MAC)" "0: AES is not locked by hardware,1: AES is locked by hardware"
|
|
bitfld.long 0x00 1. "rsvd0,AES is locked by MCU" "0: AES is not locked by MCU,1: AES is locked by MCU"
|
|
newline
|
|
bitfld.long 0x00 0. "done,AES operation done" "0: AES operation has not done yet,1: AES operation done"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "astr_len,AES Astr Length Register"
|
|
hexmask.long 0x00 0.--31. 1. "astr_len,Size of associate string"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "mstr_len,AES Mstr Length Register"
|
|
hexmask.long 0x00 0.--31. 1. "mstr_len,Size of message string"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "str_in,AES Stream Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "str_in,Input message word"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "iv0,AES Input Vector Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "iv0,Byte 0-3 of initial vector"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "iv1,AES Input Vector Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "iv1,Byte 4-7 of initial vector"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "iv2,AES Input Vector Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "iv2,Byte 8-11 of initial vector"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "iv3,AES Input Vector Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "iv3,Byte 12-15 of initial vector"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "key0,AES Key 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "key0,Byte 0-3 of key"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "key1,AES Key 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. "key1,Byte 4-7 of key"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "key2,AES Key 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. "key2,Byte 8-11 of key"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "key3,AES Key 3 Register"
|
|
hexmask.long 0x00 0.--31. 1. "key3,Byte 12-15 of key"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "key4,AES Key 4 Register"
|
|
hexmask.long 0x00 0.--31. 1. "key4,Byte 16-19 of key"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "key5,AES Key 5 Register"
|
|
hexmask.long 0x00 0.--31. 1. "key5,Byte 20-23 of key"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "key6,AES Key 6 Register"
|
|
hexmask.long 0x00 0.--31. 1. "key6,Byte 24-27 of key"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "key7,AES Key 7 Register"
|
|
hexmask.long 0x00 0.--31. 1. "key7,Byte 28-31 of key"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "str_out,AES Stream Output Port Register"
|
|
hexmask.long 0x00 0.--31. 1. "str_out,Output message word"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "ov0,AES Output Vector 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ov0,Byte 0-3 of output vector"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "ov1,AES Output Vector 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ov1,Byte 4-7 of output vector"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ov2,AES Output Vector 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ov2,Byte 8-11 of output vector"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "ov3,AES Output Vector 3 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ov3,Byte 12-15 of output vector"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "isr,AES Interrupt Status Register"
|
|
bitfld.long 0x00 2. "status_2,Status of AES output FIFO empty interrupt" "0: AES output FIFO empty interrupt not occurred,1: AES output FIFO empty interrupt occurred"
|
|
bitfld.long 0x00 1. "status_1,Status of AES input FIFO full interrupt" "0: AES input FIFO full interrupt not occurred,1: AES input FIFO full interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 0. "status_0,Status of AES output FIFO empty interrupt" "0: AES operation done interrupt not occurred,1: AES operation done interrupt occurred"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "imr,AES Interrupt Mask Register"
|
|
bitfld.long 0x00 2. "mask_2,Mask of AES output FIFO empty interrupt" "0: Enable AES output FIFO empty interrupt,1: Disable AES output FIFO empty interrupt"
|
|
bitfld.long 0x00 1. "mask_1,Mask of AES input FIFO full interrupt" "0: Enable AES input FIFO full interrupt,1: Disable AES input FIFO full interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. "mask_0,mask[0]: Mask of AES operation done interrupt" "0: Enable AES operation done interrupt,1: Disable AES operation done interrupt"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "irsr,AES Interrupt Raw Status Register"
|
|
bitfld.long 0x00 2. "status_raw_2,AES output FIFO empty interrupt raw status regardless of mask" "0: AES output FIFO empty interrupt not occurred,1: AES output FIFO empty interrupt"
|
|
bitfld.long 0x00 1. "status_raw_1,AES input FIFO full interrupt raw status regardless of mask" "0: AES no input FIFO full interrupt not occurred,1: AES no input FIFO full interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 0. "status_raw_0,AES operation done interrupt raw status regardless of mask" "0: AES operation done interrupt not occurred,1: AES operation done interrupt occurred"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "icr,AES Interrupt Clear Register"
|
|
bitfld.long 0x00 2. "clear_2,Clearance of AES output FIFO empty interrupt status and raw status" "0,1"
|
|
bitfld.long 0x00 1. "clear_1,Clearance of AES input FIFO full interrupt status and raw status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "clear_0,Clearance of AES operation done interrupt status and raw status" "0,1"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "rev_id,AES Revision Register"
|
|
bitfld.long 0x00 4.--7. "major_rev_id,Major revision ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "minor_rev_id,Minor revision ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "BG"
|
|
base ad:0x460B0700
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ctrl,Control Register"
|
|
bitfld.long 0x00 4.--7. "res_trim,1.2V voltage reference resistor trim" "0: 1.159V,1: 1.163V,2: 1.168V,3: 1.172V,4: 1.177V,5: 1.181V,6: 1.186V,7: 1.190V,8: 1.194V,9: 1.199V,10: 1.204V,11: 1.208V,12: 1.213V,13: 1.217V,14: 1.222V,15: 1.226V"
|
|
bitfld.long 0x00 3. "chop_en,Enable Chopping" "0: disable,1: enable"
|
|
bitfld.long 0x00 1.--2. "sel_clk_chop,Select Chopping Clock" "0: 250 kHz,1: 500 kHz,2: 1 MHz,3: 2 MHz"
|
|
bitfld.long 0x00 0. "pd,Bandgap power down" "0: Power up,1: Power down"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "status,Status Register"
|
|
bitfld.long 0x00 0. "rdy,1'b1 indicates BG ready flag" "0,1"
|
|
tree.end
|
|
tree "CRC"
|
|
base ad:0x44005000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "isr,Interrupt Status Register"
|
|
bitfld.long 0x00 0. "status,CRC calculation interrupt status after mask" "0: interrupt is not occurred,1: interrupt is occurred"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "irsr,Interrupt Raw Status Register"
|
|
bitfld.long 0x00 0. "status_raw_0,Raw status of IRQ regardless of mask" "0,1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "icr,Interrupt Clear Register"
|
|
bitfld.long 0x00 0. "clear,Clearance of status[0] and status_raw[0]" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "imr,Interrupt Mask Register"
|
|
bitfld.long 0x00 0. "mask,Mask of interrupt" "0: enable generation of IRQ and corresponding..,1: disable generation of IRQ and corresponding.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ctrl,CRC Module Control Register"
|
|
bitfld.long 0x00 1.--3. "mode,CRC mode select" "0: x**16+x**12+x**5+1 (CRC-16-CCITT CRC-CCITT),1: x**16+x**15+x**2+1 (CRC-16 CRC-16-IBM..,2:..,3:..,4:..,?..."
|
|
bitfld.long 0x00 0. "enable,CRC calcuate enable" "0: diable CRC calculation,1: enable CRC calculation (automatically cleared.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "stream_len_m1,Stream Length Minus 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. "length_m1,Input stream length minus 1 (units of bytes)"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "stream_in,Stream Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "data,Stream input data"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "result,CRC Calculation Result Register"
|
|
hexmask.long 0x00 0.--31. 1. "data,CRC calculation result"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "rev_id,CRC Revision ID register"
|
|
bitfld.long 0x00 4.--7. "major_rev_id,Major revision ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "minor_rev_id,Minor revision ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "DAC"
|
|
base ad:0x460B0200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ctrl,DAC Control Register"
|
|
bitfld.long 0x00 0. "ref_sel,Reference selector" "0: internal reference,1: external reference"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "status,DAC Status Register"
|
|
bitfld.long 0x00 1. "b_dv,DACB conversion status" "0: channel B conversion is not done,1: channel B conversion complete"
|
|
bitfld.long 0x00 0. "a_dv,DACA conversion status" "0: channel A conversion is not done,1: channel A conversion complete"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "actrl,Channel A Control Register"
|
|
bitfld.long 0x00 18.--19. "a_range,Output voltage range control with Internal/External reference" "0: 0.16+(0.64*input code/1023) with..,1: 0.19+(1.01*input code /1023) with..,2: 0.19+(1.01*input code /1023) with..,3: 0.18+(1.42*input code /1023) with.."
|
|
bitfld.long 0x00 16.--17. "a_wave,Channel A wave type select" "0: no description available,1: triangle wave,2: sine wave,3: no description available"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "a_tria_step_sel,Channel A triangle wave step selector" "0: V1,1: V3,2: V15,3: V511"
|
|
bitfld.long 0x00 10.--13. "a_tria_mamp_sel,Channel A triangle wave max amplitude selector" "0: V63,1: V127,2: V191,3: V255,4: V319,5: V383,6: V447,7: V511,8: V575,9: V639,10: V703,11: V767,12: V831,13: V895,14: V959,15: V1023"
|
|
newline
|
|
bitfld.long 0x00 9. "a_tria_half,Channel A triangle wave type selector" "0: full triangle,1: half triangle"
|
|
bitfld.long 0x00 8. "a_time_mode,Channel A Mode" "0: non-timing related,1: timing related"
|
|
newline
|
|
bitfld.long 0x00 7. "a_den,Channel A DMA enable" "0: DMA data transfer disabled,1: DMA data transfer enabled"
|
|
bitfld.long 0x00 5.--6. "a_trig_typ,Channel A trigger type" "?,1: rising edge trigger,2: falling edge trigger,3: both rising and falling edge trigger"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "a_trig_sel,Channel A trigger selector" "0,1,2,3"
|
|
bitfld.long 0x00 2. "a_trig_en,Channel A trigger enable" "0: Channel A conversion triggered by external..,1: Channel A conversion triggered by external.."
|
|
newline
|
|
bitfld.long 0x00 1. "a_io_en,Channel A conversion output to pad enable" "0: disable channel A conversion result to GPIO,1: enable channel A conversion result to GPIO"
|
|
bitfld.long 0x00 0. "a_en,Channel A Enable/Disable signal" "0: disable channel A conversion,1: enable channel A conversion"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "bctrl,Channel B Control Register"
|
|
bitfld.long 0x00 9.--10. "b_wave,Channel B wave type select" "0: no description available,?,?,3: differential mode with channel A"
|
|
bitfld.long 0x00 8. "b_time_mode,Channel B Mode" "0: non-timing related,1: timing related"
|
|
newline
|
|
bitfld.long 0x00 7. "b_den,Channel B DMA enable" "0: DMA data transfer disabled,1: DMA data transfer enabled"
|
|
bitfld.long 0x00 5.--6. "b_trig_typ,Channel B trigger type" "?,1: rising edge trigger,2: falling edge trigger,3: both rising and falling edge trigger"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "b_trig_sel,Channel B trigger selector" "0,1,2,3"
|
|
bitfld.long 0x00 2. "b_trig_en,Channel B trigger enable" "0: Channel B conversion triggered by external..,1: Channel B conversion triggered by external.."
|
|
newline
|
|
bitfld.long 0x00 1. "b_io_en,Channel B conversion output to pad enable" "0: disable channel B conversion result to GPIO,1: enable channel B conversion result to GPIO"
|
|
bitfld.long 0x00 0. "b_en,Channel B Enable/Disable signal" "0: disable channel B conversion,1: enable channel B conversion"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "adata,Channel A Data Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "a_data,Channel A Data input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "bdata,Channel B Data Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "b_data,Channel B Data input"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "isr,Interrupt Status Register"
|
|
bitfld.long 0x00 4. "tria_ovfl_int,Triangle Overflow" "0,1"
|
|
bitfld.long 0x00 3. "b_to_int,Channel B Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "a_to_int,Channel A Timeout" "0,1"
|
|
bitfld.long 0x00 1. "b_rdy_int,Channel B Data Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "a_rdy_int,Channel A Data Ready" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "imr,Interrupt Mask Register"
|
|
bitfld.long 0x00 4. "tria_ovfl_int_msk,Triangle Overflow Mask" "0,1"
|
|
bitfld.long 0x00 3. "b_to_int_msk,Channel B Timeout Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "a_to_int_msk,Channel A Timeout Mask" "0,1"
|
|
bitfld.long 0x00 1. "b_rdy_int_msk,Channel B Data Ready Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "a_rdy_int_msk,Channel A Data Ready Mask" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "irsr,Interrupt Raw Status Register"
|
|
bitfld.long 0x00 4. "tria_ovfl_int_raw,Triangle Overflow Raw" "0,1"
|
|
bitfld.long 0x00 3. "b_to_int_raw,Channel B Timeout Raw" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "a_to_int_raw,Channel A Timeout Raw" "0,1"
|
|
bitfld.long 0x00 1. "b_rdy_int_raw,Channel B Data Ready Raw" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "a_rdy_int_raw,Channel A Data Ready Raw" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "icr,Interrupt Clear Register"
|
|
bitfld.long 0x00 4. "tria_ovfl_int_clr,Triangle Overflow Clear" "0,1"
|
|
bitfld.long 0x00 3. "b_to_int_clr,Channel B Timeout Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "a_to_int_clr,Channel A Timeout Clear" "0,1"
|
|
bitfld.long 0x00 1. "b_rdy_int_clr,Channel B Data Ready Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "a_rdy_int_clr,Channel A Data Ready Clear" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "clk,Clock Register"
|
|
bitfld.long 0x00 4. "soft_clk_rst,Soft reset for clock divider" "0: no description available,1: no description available"
|
|
bitfld.long 0x00 1.--2. "clk_ctrl,DAC conversion rate selector" "0: 62.5K,1: V125K,2: V250K,3: V500K"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "rst,Soft Reset Register"
|
|
bitfld.long 0x00 1. "b_soft_rst,Soft reset for DAC channel B active high" "0: no action,1: no description available"
|
|
bitfld.long 0x00 0. "a_soft_rst,Soft reset for DAC channel A active high" "0: no action,1: no description available"
|
|
tree.end
|
|
tree "DMAC"
|
|
base ad:0x44000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MASK_BLOCKINT,DMA channel BLOCK TRANSFER INTERRUPT MASK registers"
|
|
bitfld.long 0x00 31. "MASK_BLOCKINT31,DMA channel 31 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 30. "MASK_BLOCKINT30,DMA channel 30 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 29. "MASK_BLOCKINT29,DMA channel 29 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 28. "MASK_BLOCKINT28,DMA channel 28 block transfer interrupt mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "MASK_BLOCKINT27,DMA channel 27 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 26. "MASK_BLOCKINT26,DMA channel 26 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 25. "MASK_BLOCKINT25,DMA channel 25 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 24. "MASK_BLOCKINT24,DMA channel 24 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 23. "MASK_BLOCKINT23,DMA channel 23 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 22. "MASK_BLOCKINT22,DMA channel 22 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 21. "MASK_BLOCKINT21,DMA channel 21 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 20. "MASK_BLOCKINT20,DMA channel 20 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. "MASK_BLOCKINT19,DMA channel 19 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 18. "MASK_BLOCKINT18,DMA channel 18 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 17. "MASK_BLOCKINT17,DMA channel 17 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 16. "MASK_BLOCKINT16,DMA channel 16 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 15. "MASK_BLOCKINT15,DMA channel 15 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 14. "MASK_BLOCKINT14,DMA channel 14 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. "MASK_BLOCKINT13,DMA channel 13 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. "MASK_BLOCKINT12,DMA channel 12 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
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|
newline
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bitfld.long 0x00 11. "MASK_BLOCKINT11,DMA channel 11 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
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newline
|
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bitfld.long 0x00 10. "MASK_BLOCKINT10,DMA channel 10 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
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|
newline
|
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bitfld.long 0x00 9. "MASK_BLOCKINT9,DMA channel 9 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
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newline
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bitfld.long 0x00 8. "MASK_BLOCKINT8,DMA channel 8 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
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newline
|
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bitfld.long 0x00 7. "MASK_BLOCKINT7,DMA channel 7 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
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newline
|
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bitfld.long 0x00 6. "MASK_BLOCKINT6,DMA channel 6 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
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newline
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bitfld.long 0x00 5. "MASK_BLOCKINT5,DMA channel 5 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
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newline
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bitfld.long 0x00 4. "MASK_BLOCKINT4,DMA channel 4 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
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|
newline
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bitfld.long 0x00 3. "MASK_BLOCKINT3,DMA channel 3 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
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|
newline
|
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bitfld.long 0x00 2. "MASK_BLOCKINT2,DMA channel 2 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
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newline
|
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bitfld.long 0x00 1. "MASK_BLOCKINT1,DMA channel 1 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
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newline
|
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bitfld.long 0x00 0. "MASK_BLOCKINT0,DMA channel 0 block transfer interrupt mask bit" "0: mask the corresponding block interrupt,1: unmask the corresponding block interrupt"
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group.long 0x04++0x03
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line.long 0x00 "STATUS_BLOCKINT,DMA channel BLOCK TRANSFER INTERRUPT Registers"
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bitfld.long 0x00 31. "STATUS_BLOCKINT31,DMA channel 31 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 30. "STATUS_BLOCKINT30,DMA channel 30 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 29. "STATUS_BLOCKINT29,DMA channel 29 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 28. "STATUS_BLOCKINT28,DMA channel 28 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 27. "STATUS_BLOCKINT27,DMA channel 27 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 26. "STATUS_BLOCKINT26,DMA channel 26 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 25. "STATUS_BLOCKINT25,DMA channel 25 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 24. "STATUS_BLOCKINT24,DMA channel 24 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 23. "STATUS_BLOCKINT23,DMA channel 23 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 22. "STATUS_BLOCKINT22,DMA channel 22 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 21. "STATUS_BLOCKINT21,DMA channel 21 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 20. "STATUS_BLOCKINT20,DMA channel 20 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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newline
|
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bitfld.long 0x00 19. "STATUS_BLOCKINT19,DMA channel 19 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 18. "STATUS_BLOCKINT18,DMA channel 18 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 17. "STATUS_BLOCKINT17,DMA channel 17 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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newline
|
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bitfld.long 0x00 16. "STATUS_BLOCKINT16,DMA channel 16 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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newline
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bitfld.long 0x00 15. "STATUS_BLOCKINT15,DMA channel 15 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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newline
|
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bitfld.long 0x00 14. "STATUS_BLOCKINT14,DMA channel 14 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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newline
|
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bitfld.long 0x00 13. "STATUS_BLOCKINT13,DMA channel 13 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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newline
|
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bitfld.long 0x00 12. "STATUS_BLOCKINT12,DMA channel 12 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
|
bitfld.long 0x00 11. "STATUS_BLOCKINT11,DMA channel 11 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 10. "STATUS_BLOCKINT10,DMA channel 10 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 9. "STATUS_BLOCKINT9,DMA channel 9 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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newline
|
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bitfld.long 0x00 8. "STATUS_BLOCKINT8,DMA channel 8 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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newline
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bitfld.long 0x00 7. "STATUS_BLOCKINT7,DMA channel 7 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 6. "STATUS_BLOCKINT6,DMA channel 6 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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newline
|
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bitfld.long 0x00 5. "STATUS_BLOCKINT5,DMA channel 5 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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newline
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bitfld.long 0x00 4. "STATUS_BLOCKINT4,DMA channel 4 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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newline
|
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bitfld.long 0x00 3. "STATUS_BLOCKINT3,DMA channel 3 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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newline
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bitfld.long 0x00 2. "STATUS_BLOCKINT2,DMA channel 2 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 1. "STATUS_BLOCKINT1,DMA channel 1 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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|
newline
|
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bitfld.long 0x00 0. "STATUS_BLOCKINT0,DMA channel 0 block transfer interrupt bit" "0: DMA block burst/single transfer is not..,1: DMA block burst/single transfer is completed"
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group.long 0x08++0x03
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line.long 0x00 "MASK_TFRINT,DMA Channel transfer completion interrupt mask Registers"
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bitfld.long 0x00 31. "MASK_TFRINT31,DMA channel 31 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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|
newline
|
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bitfld.long 0x00 30. "MASK_TFRINT30,DMA channel 30 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 29. "MASK_TFRINT29,DMA channel 29 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 28. "MASK_TFRINT28,DMA channel 28 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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|
newline
|
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bitfld.long 0x00 27. "MASK_TFRINT27,DMA channel 27 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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|
newline
|
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bitfld.long 0x00 26. "MASK_TFRINT26,DMA channel 26 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 25. "MASK_TFRINT25,DMA channel 25 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 24. "MASK_TFRINT24,DMA channel 24 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
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bitfld.long 0x00 23. "MASK_TFRINT23,DMA channel 23 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
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bitfld.long 0x00 22. "MASK_TFRINT22,DMA channel 22 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 21. "MASK_TFRINT21,DMA channel 21 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
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bitfld.long 0x00 20. "MASK_TFRINT20,DMA channel 20 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 19. "MASK_TFRINT19,DMA channel 19 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 18. "MASK_TFRINT18,DMA channel 18 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 17. "MASK_TFRINT17,DMA channel 17 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 16. "MASK_TFRINT16,DMA channel 16 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 15. "MASK_TFRINT15,DMA channel 15 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 14. "MASK_TFRINT14,DMA channel 14 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 13. "MASK_TFRINT13,DMA channel 13 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 12. "MASK_TFRINT12,DMA channel 12 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
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bitfld.long 0x00 11. "MASK_TFRINT11,DMA channel 11 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 10. "MASK_TFRINT10,DMA channel 10 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 9. "MASK_TFRINT9,DMA channel 9 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 8. "MASK_TFRINT8,DMA channel 8 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 7. "MASK_TFRINT7,DMA channel 7 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 6. "MASK_TFRINT6,DMA channel 6 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 5. "MASK_TFRINT5,DMA channel 5 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 4. "MASK_TFRINT4,DMA channel 4 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 3. "MASK_TFRINT3,DMA channel 3 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 2. "MASK_TFRINT2,DMA channel 2 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 1. "MASK_TFRINT1,DMA channel 1 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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newline
|
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bitfld.long 0x00 0. "MASK_TFRINT0,DMA channel 0 transfer completion interrupt mask bit" "0: mask the corresponding transfer completion..,1: unmask the corresponding transfer completion.."
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group.long 0x0C++0x03
|
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line.long 0x00 "STATUS_TFRINT,DMA Channel transfer completion interrupt Registers"
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bitfld.long 0x00 31. "STATUS_TFRINT31,DMA channel 31 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
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|
newline
|
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bitfld.long 0x00 30. "STATUS_TFRINT30,DMA channel 30 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
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|
newline
|
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bitfld.long 0x00 29. "STATUS_TFRINT29,DMA channel 29 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
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|
newline
|
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bitfld.long 0x00 28. "STATUS_TFRINT28,DMA channel 28 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
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|
newline
|
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bitfld.long 0x00 27. "STATUS_TFRINT27,DMA channel 27 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
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|
newline
|
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bitfld.long 0x00 26. "STATUS_TFRINT26,DMA channel 26 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
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|
newline
|
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bitfld.long 0x00 25. "STATUS_TFRINT25,DMA channel 25 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
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|
newline
|
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bitfld.long 0x00 24. "STATUS_TFRINT24,DMA channel 24 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
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|
newline
|
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bitfld.long 0x00 23. "STATUS_TFRINT23,DMA channel 23 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
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|
newline
|
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bitfld.long 0x00 22. "STATUS_TFRINT22,DMA channel 22 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
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bitfld.long 0x00 21. "STATUS_TFRINT21,DMA channel 21 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
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|
newline
|
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bitfld.long 0x00 20. "STATUS_TFRINT20,DMA channel 20 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
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|
newline
|
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bitfld.long 0x00 19. "STATUS_TFRINT19,DMA channel 19 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
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bitfld.long 0x00 18. "STATUS_TFRINT18,DMA channel 18 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
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bitfld.long 0x00 17. "STATUS_TFRINT17,DMA channel 17 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
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bitfld.long 0x00 16. "STATUS_TFRINT16,DMA channel 16 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
|
bitfld.long 0x00 15. "STATUS_TFRINT15,DMA channel 15 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
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bitfld.long 0x00 14. "STATUS_TFRINT14,DMA channel 14 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
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bitfld.long 0x00 13. "STATUS_TFRINT13,DMA channel 13 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
|
bitfld.long 0x00 12. "STATUS_TFRINT12,DMA channel 12 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
|
bitfld.long 0x00 11. "STATUS_TFRINT11,DMA channel 11 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
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bitfld.long 0x00 10. "STATUS_TFRINT10,DMA channel 10 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
|
bitfld.long 0x00 9. "STATUS_TFRINT9,DMA channel 9 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
|
bitfld.long 0x00 8. "STATUS_TFRINT8,DMA channel 8 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
|
bitfld.long 0x00 7. "STATUS_TFRINT7,DMA channel 7 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
|
bitfld.long 0x00 6. "STATUS_TFRINT6,DMA channel 6 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
|
bitfld.long 0x00 5. "STATUS_TFRINT5,DMA channel 5 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
|
bitfld.long 0x00 4. "STATUS_TFRINT4,DMA channel 4 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
|
bitfld.long 0x00 3. "STATUS_TFRINT3,DMA channel 3 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
|
bitfld.long 0x00 2. "STATUS_TFRINT2,DMA channel 2 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
|
bitfld.long 0x00 1. "STATUS_TFRINT1,DMA channel 1 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
newline
|
|
bitfld.long 0x00 0. "STATUS_TFRINT0,DMA channel 0 transfer completion interrupt" "0: transfer is not completed,1: transfer is completed"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MASK_BUSERRINT,DMA Channel bus error interrupt mask Registers"
|
|
bitfld.long 0x00 31. "MASK_BUSERRINT31,DMA Channel 31 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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|
newline
|
|
bitfld.long 0x00 30. "MASK_BUSERRINT30,DMA Channel 30 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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|
newline
|
|
bitfld.long 0x00 29. "MASK_BUSERRINT29,DMA Channel 29 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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|
newline
|
|
bitfld.long 0x00 28. "MASK_BUSERRINT28,DMA Channel 28 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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|
newline
|
|
bitfld.long 0x00 27. "MASK_BUSERRINT27,DMA Channel 27 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
|
|
newline
|
|
bitfld.long 0x00 26. "MASK_BUSERRINT26,DMA Channel 26 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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|
newline
|
|
bitfld.long 0x00 25. "MASK_BUSERRINT25,DMA Channel 25 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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|
newline
|
|
bitfld.long 0x00 24. "MASK_BUSERRINT24,DMA Channel 24 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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|
newline
|
|
bitfld.long 0x00 23. "MASK_BUSERRINT23,DMA Channel 23 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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|
newline
|
|
bitfld.long 0x00 22. "MASK_BUSERRINT22,DMA Channel 22 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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|
newline
|
|
bitfld.long 0x00 21. "MASK_BUSERRINT21,DMA Channel 21 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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|
newline
|
|
bitfld.long 0x00 20. "MASK_BUSERRINT20,DMA Channel 20 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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|
newline
|
|
bitfld.long 0x00 19. "MASK_BUSERRINT19,DMA Channel 19 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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|
newline
|
|
bitfld.long 0x00 18. "MASK_BUSERRINT18,DMA Channel 18 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
|
|
newline
|
|
bitfld.long 0x00 17. "MASK_BUSERRINT17,DMA Channel 17 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
|
|
newline
|
|
bitfld.long 0x00 16. "MASK_BUSERRINT16,DMA Channel 16 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
|
|
newline
|
|
bitfld.long 0x00 15. "MASK_BUSERRINT15,DMA Channel 15 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
|
|
newline
|
|
bitfld.long 0x00 14. "MASK_BUSERRINT14,DMA Channel 14 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
|
|
newline
|
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bitfld.long 0x00 13. "MASK_BUSERRINT13,DMA Channel 13 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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newline
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bitfld.long 0x00 12. "MASK_BUSERRINT12,DMA Channel 12 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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newline
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bitfld.long 0x00 11. "MASK_BUSERRINT11,DMA Channel 11 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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newline
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bitfld.long 0x00 10. "MASK_BUSERRINT10,DMA Channel 10 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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newline
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bitfld.long 0x00 9. "MASK_BUSERRINT9,DMA Channel 9 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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newline
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bitfld.long 0x00 8. "MASK_BUSERRINT8,DMA Channel 8 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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newline
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bitfld.long 0x00 7. "MASK_BUSERRINT7,DMA Channel 7 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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newline
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bitfld.long 0x00 6. "MASK_BUSERRINT6,DMA Channel 6 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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newline
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bitfld.long 0x00 5. "MASK_BUSERRINT5,DMA Channel 5 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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newline
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bitfld.long 0x00 4. "MASK_BUSERRINT4,DMA Channel 4 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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newline
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bitfld.long 0x00 3. "MASK_BUSERRINT3,DMA Channel 3 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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newline
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bitfld.long 0x00 2. "MASK_BUSERRINT2,DMA Channel 2 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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newline
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bitfld.long 0x00 1. "MASK_BUSERRINT1,DMA Channel 1 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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newline
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bitfld.long 0x00 0. "MASK_BUSERRINT0,DMA Channel 0 bus error interrupt mask bit" "0: mask the corresponding bus error interrupt,1: unmask the corresponding bus error interrupt"
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group.long 0x14++0x03
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line.long 0x00 "STATUS_BUSERRINT,DMA Channel bus error interrupt mask Registers"
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bitfld.long 0x00 31. "STATUS_BUSERRINT31,DMA channel 31 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 30. "STATUS_BUSERRINT30,DMA channel 30 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 29. "STATUS_BUSERRINT29,DMA channel 29 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 28. "STATUS_BUSERRINT28,DMA channel 28 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 27. "STATUS_BUSERRINT27,DMA channel 27 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 26. "STATUS_BUSERRINT26,DMA channel 26 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 25. "STATUS_BUSERRINT25,DMA channel 25 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 24. "STATUS_BUSERRINT24,DMA channel 24 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 23. "STATUS_BUSERRINT23,DMA channel 23 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 22. "STATUS_BUSERRINT22,DMA channel 22 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 21. "STATUS_BUSERRINT21,DMA channel 21 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 20. "STATUS_BUSERRINT20,DMA channel 20 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 19. "STATUS_BUSERRINT19,DMA channel 19 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 18. "STATUS_BUSERRINT18,DMA channel 18 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 17. "STATUS_BUSERRINT17,DMA channel 17 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 16. "STATUS_BUSERRINT16,DMA channel 16 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 15. "STATUS_BUSERRINT15,DMA channel 15 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 14. "STATUS_BUSERRINT14,DMA channel 14 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 13. "STATUS_BUSERRINT13,DMA channel 13 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 12. "STATUS_BUSERRINT12,DMA channel 12 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 11. "STATUS_BUSERRINT11,DMA channel 11 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 10. "STATUS_BUSERRINT10,DMA channel 10 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 9. "STATUS_BUSERRINT9,DMA channel 9 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 8. "STATUS_BUSERRINT8,DMA channel 8 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 7. "STATUS_BUSERRINT7,DMA channel 7 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 6. "STATUS_BUSERRINT6,DMA channel 6 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 5. "STATUS_BUSERRINT5,DMA channel 5 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 4. "STATUS_BUSERRINT4,DMA channel 4 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 3. "STATUS_BUSERRINT3,DMA channel 3 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 2. "STATUS_BUSERRINT2,DMA channel 2 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 1. "STATUS_BUSERRINT1,DMA channel 1 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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newline
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bitfld.long 0x00 0. "STATUS_BUSERRINT0,DMA channel 0 bus error interrupt bit" "0: no bus error interrupt is generated,1: bus error interrupt is generated"
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group.long 0x18++0x03
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line.long 0x00 "MASK_ADDRERRINT,DMA Channel source/target address alignment error interrupt mask Registers"
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bitfld.long 0x00 31. "MASK_ADDRERRINT31,DMA Channel 31 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 30. "MASK_ADDRERRINT30,DMA Channel 30 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 29. "MASK_ADDRERRINT29,DMA Channel 29 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 28. "MASK_ADDRERRINT28,DMA Channel 28 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 27. "MASK_ADDRERRINT27,DMA Channel 27 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 26. "MASK_ADDRERRINT26,DMA Channel 26 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 25. "MASK_ADDRERRINT25,DMA Channel 25 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 24. "MASK_ADDRERRINT24,DMA Channel 24 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 23. "MASK_ADDRERRINT23,DMA Channel 23 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 22. "MASK_ADDRERRINT22,DMA Channel 22 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 21. "MASK_ADDRERRINT21,DMA Channel 21 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 20. "MASK_ADDRERRINT20,DMA Channel 20 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 19. "MASK_ADDRERRINT19,DMA Channel 19 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 18. "MASK_ADDRERRINT18,DMA Channel 18 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 17. "MASK_ADDRERRINT17,DMA Channel 17 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
|
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bitfld.long 0x00 16. "MASK_ADDRERRINT16,DMA Channel 16 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 15. "MASK_ADDRERRINT15,DMA Channel 15 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 14. "MASK_ADDRERRINT14,DMA Channel 14 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 13. "MASK_ADDRERRINT13,DMA Channel 13 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 12. "MASK_ADDRERRINT12,DMA Channel 12 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 11. "MASK_ADDRERRINT11,DMA Channel 11 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 10. "MASK_ADDRERRINT10,DMA Channel 10 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 9. "MASK_ADDRERRINT9,DMA Channel 9 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 8. "MASK_ADDRERRINT8,DMA Channel 8 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 7. "MASK_ADDRERRINT7,DMA Channel 7 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 6. "MASK_ADDRERRINT6,DMA Channel 6 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 5. "MASK_ADDRERRINT5,DMA Channel 5 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 4. "MASK_ADDRERRINT4,DMA Channel 4 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 3. "MASK_ADDRERRINT3,DMA Channel 3 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 2. "MASK_ADDRERRINT2,DMA Channel 2 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
|
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bitfld.long 0x00 1. "MASK_ADDRERRINT1,DMA Channel 1 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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newline
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bitfld.long 0x00 0. "MASK_ADDRERRINT0,DMA Channel 0 source/target address alignment error interrupt mask bit" "0: mask the corresponding address error interrupt,1: unmask the corresponding address error.."
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group.long 0x1C++0x03
|
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line.long 0x00 "STATUS_ADDRERRINT,DMA Channel source/target address alignment error interrupt Registers"
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bitfld.long 0x00 31. "STATUS_ADDRERRINT31,DMA Channel 31 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 30. "STATUS_ADDRERRINT30,DMA Channel 30 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
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bitfld.long 0x00 29. "STATUS_ADDRERRINT29,DMA Channel 29 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 28. "STATUS_ADDRERRINT28,DMA Channel 28 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 27. "STATUS_ADDRERRINT27,DMA Channel 27 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 26. "STATUS_ADDRERRINT26,DMA Channel 26 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 25. "STATUS_ADDRERRINT25,DMA Channel 25 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 24. "STATUS_ADDRERRINT24,DMA Channel 24 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 23. "STATUS_ADDRERRINT23,DMA Channel 23 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 22. "STATUS_ADDRERRINT22,DMA Channel 22 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 21. "STATUS_ADDRERRINT21,DMA Channel 21 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 20. "STATUS_ADDRERRINT20,DMA Channel 20 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 19. "STATUS_ADDRERRINT19,DMA Channel 19 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 18. "STATUS_ADDRERRINT18,DMA Channel 18 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 17. "STATUS_ADDRERRINT17,DMA Channel 17 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 16. "STATUS_ADDRERRINT16,DMA Channel 16 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 15. "STATUS_ADDRERRINT15,DMA Channel 15 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 14. "STATUS_ADDRERRINT14,DMA Channel 14 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 13. "STATUS_ADDRERRINT13,DMA Channel 13 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 12. "STATUS_ADDRERRINT12,DMA Channel 12 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 11. "STATUS_ADDRERRINT11,DMA Channel 11 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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|
newline
|
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bitfld.long 0x00 10. "STATUS_ADDRERRINT10,DMA Channel 10 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 9. "STATUS_ADDRERRINT9,DMA Channel 9 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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|
newline
|
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bitfld.long 0x00 8. "STATUS_ADDRERRINT8,DMA Channel 8 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 7. "STATUS_ADDRERRINT7,DMA Channel 7 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 6. "STATUS_ADDRERRINT6,DMA Channel 6 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 5. "STATUS_ADDRERRINT5,DMA Channel 5 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 4. "STATUS_ADDRERRINT4,DMA Channel 4 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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|
newline
|
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bitfld.long 0x00 3. "STATUS_ADDRERRINT3,DMA Channel 3 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 2. "STATUS_ADDRERRINT2,DMA Channel 2 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 1. "STATUS_ADDRERRINT1,DMA Channel 1 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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newline
|
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bitfld.long 0x00 0. "STATUS_ADDRERRINT0,DMA Channel 0 source/target address alignment error interrupt bit" "0: no address error interrupt is generated,1: address error interrupt is generated"
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rgroup.long 0x20++0x03
|
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line.long 0x00 "STATUS_CHLINT,DMA CHANNEL INTERRUPT REGISTER"
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bitfld.long 0x00 31. "STATUS_CHLINT31,DMA channel 31 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 30. "STATUS_CHLINT30,DMA channel 30 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 29. "STATUS_CHLINT29,DMA channel 29 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 28. "STATUS_CHLINT28,DMA channel 28 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 27. "STATUS_CHLINT27,DMA channel 27 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 26. "STATUS_CHLINT26,DMA channel 26 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 25. "STATUS_CHLINT25,DMA channel 25 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 24. "STATUS_CHLINT24,DMA channel 24 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 23. "STATUS_CHLINT23,DMA channel 23 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 22. "STATUS_CHLINT22,DMA channel 22 interrupt" "0,1"
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|
newline
|
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bitfld.long 0x00 21. "STATUS_CHLINT21,DMA channel 21 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 20. "STATUS_CHLINT20,DMA channel 20 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 19. "STATUS_CHLINT19,DMA channel 19 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 18. "STATUS_CHLINT18,DMA channel 18 interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x00 17. "STATUS_CHLINT17,DMA channel 17 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 16. "STATUS_CHLINT16,DMA channel 16 interrupt" "0,1"
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newline
|
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bitfld.long 0x00 15. "STATUS_CHLINT15,DMA channel 15 interrupt" "0,1"
|
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|
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bitfld.long 0x00 14. "STATUS_CHLINT14,DMA channel 14 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "STATUS_CHLINT13,DMA channel 13 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "STATUS_CHLINT12,DMA channel 12 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "STATUS_CHLINT11,DMA channel 11 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "STATUS_CHLINT10,DMA channel 10 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "STATUS_CHLINT9,DMA channel 9 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "STATUS_CHLINT8,DMA channel 8 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "STATUS_CHLINT7,DMA channel 7 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "STATUS_CHLINT6,DMA channel 6 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "STATUS_CHLINT5,DMA channel 5 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "STATUS_CHLINT4,DMA channel 4 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "STATUS_CHLINT3,DMA channel 3 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "STATUS_CHLINT2,DMA channel 2 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "STATUS_CHLINT1,DMA channel 1 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "STATUS_CHLINT0,DMA channel 0 interrupt" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "HPROT,THE PROTECTION CONTROL SIGNALS REGISTERS"
|
|
bitfld.long 0x00 0.--3. "HPROT,protection control signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SADR0,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TADR0,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CTRLA0,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "CTRLB0,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CHL_EN0,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CHL_STOP0,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "SADR1,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TADR1,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CTRLA1,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "CTRLB1,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CHL_EN1,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CHL_STOP1,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "SADR2,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TADR2,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CTRLA2,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "CTRLB2,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CHL_EN2,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CHL_STOP2,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "SADR3,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TADR3,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CTRLA3,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "CTRLB3,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CHL_EN3,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CHL_STOP3,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "SADR4,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "TADR4,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "CTRLA4,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "CTRLB4,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "CHL_EN4,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "CHL_STOP4,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "SADR5,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "TADR5,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "CTRLA5,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "CTRLB5,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CHL_EN5,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "CHL_STOP5,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "SADR6,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "TADR6,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "CTRLA6,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "CTRLB6,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "CHL_EN6,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "CHL_STOP6,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "SADR7,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "TADR7,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "CTRLA7,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "CTRLB7,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "CHL_EN7,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "CHL_STOP7,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "SADR8,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "TADR8,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "CTRLA8,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "CTRLB8,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "CHL_EN8,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "CHL_STOP8,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "SADR9,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "TADR9,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "CTRLA9,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "CTRLB9,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "CHL_EN9,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "CHL_STOP9,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "SADR10,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "TADR10,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "CTRLA10,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "CTRLB10,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "CHL_EN10,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "CHL_STOP10,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "SADR11,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "TADR11,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "CTRLA11,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "CTRLB11,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "CHL_EN11,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "CHL_STOP11,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "SADR12,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "TADR12,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "CTRLA12,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "CTRLB12,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "CHL_EN12,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "CHL_STOP12,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "SADR13,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x374++0x03
|
|
line.long 0x00 "TADR13,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "CTRLA13,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x37C++0x03
|
|
line.long 0x00 "CTRLB13,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "CHL_EN13,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "CHL_STOP13,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "SADR14,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "TADR14,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "CTRLA14,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "CTRLB14,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "CHL_EN14,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "CHL_STOP14,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "SADR15,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "TADR15,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x3D8++0x03
|
|
line.long 0x00 "CTRLA15,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x3DC++0x03
|
|
line.long 0x00 "CTRLB15,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "CHL_EN15,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x3E4++0x03
|
|
line.long 0x00 "CHL_STOP15,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "SADR16,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "TADR16,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "CTRLA16,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "CTRLB16,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "CHL_EN16,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "CHL_STOP16,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "SADR17,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "TADR17,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "CTRLA17,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "CTRLB17,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "CHL_EN17,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "CHL_STOP17,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "SADR18,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "TADR18,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "CTRLA18,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "CTRLB18,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "CHL_EN18,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "CHL_STOP18,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "SADR19,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "TADR19,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "CTRLA19,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "CTRLB19,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "CHL_EN19,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "CHL_STOP19,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "SADR20,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "TADR20,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "CTRLA20,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "CTRLB20,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "CHL_EN20,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "CHL_STOP20,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "SADR21,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "TADR21,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "CTRLA21,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "CTRLB21,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "CHL_EN21,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "CHL_STOP21,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "SADR22,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "TADR22,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "CTRLA22,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "CTRLB22,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "CHL_EN22,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "CHL_STOP22,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "SADR23,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "TADR23,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "CTRLA23,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "CTRLB23,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "CHL_EN23,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "CHL_STOP23,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "SADR24,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "TADR24,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "CTRLA24,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "CTRLB24,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "CHL_EN24,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "CHL_STOP24,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "SADR25,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "TADR25,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "CTRLA25,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "CTRLB25,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "CHL_EN25,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x5C4++0x03
|
|
line.long 0x00 "CHL_STOP25,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "SADR26,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x5E4++0x03
|
|
line.long 0x00 "TADR26,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x5E8++0x03
|
|
line.long 0x00 "CTRLA26,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x5EC++0x03
|
|
line.long 0x00 "CTRLB26,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5F0++0x03
|
|
line.long 0x00 "CHL_EN26,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x5F4++0x03
|
|
line.long 0x00 "CHL_STOP26,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SADR27,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "TADR27,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "CTRLA27,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "CTRLB27,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "CHL_EN27,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "CHL_STOP27,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SADR28,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "TADR28,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "CTRLA28,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "CTRLB28,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "CHL_EN28,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "CHL_STOP28,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SADR29,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "TADR29,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "CTRLA29,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "CTRLB29,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "CHL_EN29,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "CHL_STOP29,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SADR30,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "TADR30,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "CTRLA30,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "CTRLB30,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "CHL_EN30,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "CHL_STOP30,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SADR31,DMA SOURCE ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "SRCADDR,SOURCE ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SRCADDR0,SRCADDR0" "0,1,2,3"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "TADR31,DMA TARGET ADDRESS REGISTERS"
|
|
hexmask.long 0x00 2.--31. 1. "TRGADDR,TARGET ADDRESS"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRGADDR0,TRGADDR0" "0,1,2,3"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "CTRLA31,DMA CONTROL REGISTERS A"
|
|
bitfld.long 0x00 30. "INCSRCADDR,Source address increment" "0: do not increment source address,1: stop the running channel"
|
|
newline
|
|
bitfld.long 0x00 29. "INCTRGADDR,Target address increment" "0: do not increment target address,1: increment target address"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "TRAN_TYPE,Source to target transfer type" "0: zero,1: one,2: two,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TRAN_SIZE,Size" "0: zero,1: one,2: two,3: three"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "WIDTH,Width" "?,1: 1 byte,2: half-word (2 bytes),3: word (4 bytes)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "LEN,Length of the transfer in bytes"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "CTRLB31,DMA CONTROL REGISTERS B"
|
|
bitfld.long 0x00 0.--5. "PERNUM,peripheral number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "CHL_EN31,DMA CHANNEL ENABLE REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_EN,Enable/Disable the channel" "0: disable the channel,1: enable the channel"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "CHL_STOP31,DMA CHANNEL STOP REGISTERS"
|
|
bitfld.long 0x00 31. "CHL_STOP,Stop the running channel" "0: no impact on the channel,1: stop the running channel"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "ACK_DELAY,DMA ACK DELAY CYCLE for single transfer in M2P transfer type Registers"
|
|
hexmask.long.word 0x00 0.--9. 1. "ACK_DELAY_NUM,DMA ACK DELAY CYCLE for single write transaction to peripheral"
|
|
rgroup.long 0x900++0x03
|
|
line.long 0x00 "ERR_INFO0,DMA ERROR INFORMATION REGISTER 0"
|
|
hexmask.long 0x00 0.--31. 1. "ERR_ADDR,ADDRESS INFORMATION RELATED ERROR"
|
|
rgroup.long 0x904++0x03
|
|
line.long 0x00 "ERR_INFO1,DMA ERROR INFORMATION REGISTER 1"
|
|
bitfld.long 0x00 27.--31. "ERR_CHLNUM,CHANNEL ID INFORMATION RELATED ERROR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x908++0x03
|
|
line.long 0x00 "DIAGNOSE_INFO0,DMA DIAGNOSE INFORMATION REGISTER 0"
|
|
hexmask.long 0x00 0.--31. 1. "DIAGNOSE_ADDR,ADDRESS INFORMATION RELATED DIAGNOSE"
|
|
rgroup.long 0x90C++0x03
|
|
line.long 0x00 "DIAGNOSE_INFO1,DMA DIAGNOSE INFORMATION REGISTER 1"
|
|
bitfld.long 0x00 31. "DIAGNOSE_REQ_CHL_DATA,INDICATE WHETHER THERE IS A VALID REQUEST" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 18.--30. 1. "DIAGNOSE_REST_LEN,INDICATE THE REMAINING DATA LENGTH OF THE SELESTED CHANNEL"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "DIAGNOSE_REQ_CHL_DATA_CHLNUM,INDICATE WHICH CHANNEL IS IN SERVICE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x910++0x03
|
|
line.long 0x00 "DIAGNOSE_INFO2,DMA DIAGNOSE INFORMATION REGISTER 2"
|
|
bitfld.long 0x00 28.--31. "DIAGNOSE_CHL_STATE,INDICATE THE CHANNEL STATE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x914++0x03
|
|
line.long 0x00 "DIAGNOSE_INFO3,DMA DIAGNOSE INFORMATION REGISTER 3"
|
|
hexmask.long 0x00 2.--31. 1. "DIAGNOSE_SRC_ADDR,INDICATE THE SOURCE ADDRESS OF THE SELECTED CHANNEL"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DIAGNOSE_SRC_ADDR0,INDICATE THE SOURCE ADDRESS 0 OF THE SELECTED CHANNEL" "0,1,2,3"
|
|
rgroup.long 0x918++0x03
|
|
line.long 0x00 "DIAGNOSE_INFO4,DMA DIAGNOSE INFORMATION REGISTER 4"
|
|
hexmask.long 0x00 2.--31. 1. "DIAGNOSE_TRG_ADDR,INDICATE THE TARGET ADDRESS OF THE SELECTED CHANNEL"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DIAGNOSE_TRG_ADDR0,INDICATE THE TARGET ADDRESS 0 OF THE SELECTED CHANNEL" "0,1,2,3"
|
|
rgroup.long 0x91C++0x03
|
|
line.long 0x00 "DIAGNOSE_INFO5,DMA DIAGNOSE INFORMATION REGISTER 5"
|
|
bitfld.long 0x00 31. "DIAGNOSE_CHL_EN,INDICATE THE CHANNEL ENABLE STATE OF THE SELECTED CHANNEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DIAGNOSE_INCRSRCADDR,INDICATE WHETHER TO INCREASE THE SRC ADDRESS OF THE SELECTED CHANNEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "DIAGNOSE_INCRTRGADDR,INDICATE WHETHER TO INCREASE THE TRG ADDRESS OF THE SELECTED CHANNEL" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 16.--28. 1. "DIAGNOSE_CTRL_LEN,INDICATE THE LENGTH INFORMATION OF THE SELECTED CHANNEL"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "DIAGNOSE_CTRL_TRANSIZE,INDICATE THE TRANSFER SIZE INFORMATION OF THE SELECTED CHANNEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "DIAGNOSE_CTRL_TRANTYPE,INDICATE THE TRANSFER TYPE INFORMATION OF THE SELECTED CHANNEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DIAGNOSE_CTRL_WIDTH,INDICATE THE WIDTH INFORMATION OF THE SELECTED CHANNEL" "0,1,2,3"
|
|
rgroup.long 0x920++0x03
|
|
line.long 0x00 "DIAGNOSE_INFO6,DMA DIAGNOSE INFORMATION REGISTER 6"
|
|
bitfld.long 0x00 31. "DIAGNOSE_MAS_READ,INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DIAGNOSE_MAS_WRITE,INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "DIAGNOSE_AHB_SIZE,INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "DIAGNOSE_AHB_BURST,INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 19.--25. 1. "DIAGNOSE_SLICECNT,INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH"
|
|
newline
|
|
bitfld.long 0x00 18. "DIAGNOSE_SPLIT_WORD,INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DIAGNOSE_SPLIT_HALFWORD,INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH" "0,1"
|
|
rgroup.long 0x924++0x03
|
|
line.long 0x00 "DIAGNOSE_INFO7,DMA DIAGNOSE INFORMATION REGISTER 7"
|
|
bitfld.long 0x00 29.--31. "DIAGNOSE_AHB_BURST,INDICATE SOME AHB MASTER INFO" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "DIAGNOSE_AHB_TRANS,INDICATE SOME AHB MASTER INFO" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "DIAGNOSE_AHB_SIZE,INDICATE SOME AHB MASTER INFO" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. "DIAGNOSE_AHB_HREADY,INDICATE SOME AHB MASTER INFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIAGNOSE_AHB_HRESP,INDICATE SOME AHB MASTER INFO" "0,1"
|
|
tree.end
|
|
tree "FLASHC"
|
|
base ad:0x44003000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCCR,Flash Controller Configuration Register"
|
|
bitfld.long 0x00 31. "FLASHC_PAD_EN,Flashc pad enable" "0: APB QSPI connects to the Flash device,1: Flashc connects to the Flash device"
|
|
bitfld.long 0x00 30. "CACHE_EN,Flash cache enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "CACHE_LINE_FLUSH,Cache Line Flush" "0,1"
|
|
bitfld.long 0x00 28. "SRAM_MODE_EN,SRAM Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "CLK_PHA,Serial Interface Clock Phase" "0: Data is captured on the rising edge of the..,1: Data is captured on the falling edge of the.."
|
|
bitfld.long 0x00 14. "CLK_POL,Serial Interface Clock Polarity" "0: Serial Interface clock is LOW when inactive,1: Serial Interface clock is HIGH when inactive"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "CLK_PRESCALE,Serial interface clock prescaler (from base SPI clock)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. "CMD_TYPE,Serial Flash Command typeclocks (based on this Command Type field for Winbond devices)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "FCTR,Flash Controller Timing Register"
|
|
bitfld.long 0x00 4. "CLK_CAPT_EDGE,Serial Interface data capture clock edge" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FCSR,Flash Controller Status Register"
|
|
bitfld.long 0x00 0. "CONT_RD_MD_EXIT_DONE,Continuous Read Mode Exit status" "0: continuous read mode exit not complete,1: continuous read mode exit complete"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FCACR,Flash Controller Auxiliary Configuration Register"
|
|
bitfld.long 0x00 3. "OFFSET_EN,Address Offset Enable" "0: All Flash Memory accesses Do not use Address..,1: Using Address Offset defined in FAOFFR is.."
|
|
bitfld.long 0x00 2. "ADDR_MATCH_EN,Address Match Enable" "0: disable Counting of Misses to a specific..,1: enable Counting of Misses to a specific.."
|
|
newline
|
|
bitfld.long 0x00 1. "MISS_CNT_EN,Miss Count Enable" "0: Disable the counting of misses,1: Enable the counting of number of misses to.."
|
|
bitfld.long 0x00 0. "HIT_CNT_EN,Miss Count Enable" "0: Disable the counting of hits,1: Enable the counting of number of hits to the.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FCHCR,Flash Controller Hit Count Register"
|
|
hexmask.long 0x00 0.--31. 1. "HIT_COUNT,Hit Counter"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FCMCR,Flash Controller Miss Count Register"
|
|
hexmask.long 0x00 0.--31. 1. "MISS_COUNT,Hit Counter"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FAOFFR,Flash Address Offset Register"
|
|
hexmask.long 0x00 0.--31. 1. "OFFSET_VAL,Flash Address Offset value"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FADDMAT,Flash Address Match register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Flash Memory address to compare and match"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FWAITR,Flash Wait Register"
|
|
bitfld.long 0x00 0. "ZWAIT,Zero Wait" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FCCR2,Flash Controller Configurationb Register2"
|
|
bitfld.long 0x00 31. "USE_CFG_OVRD,Use Configuration Override" "0: Use FCCR.CMD_TYPE to determine/build Flash..,1: Use Configuration FCCR2 to determine/build.."
|
|
bitfld.long 0x00 29.--30. "DATA_PIN,Data transfer pins" "0: Use 1 pin for data,1: Use 2 pins for data,2: Use 4 pins for data,?..."
|
|
newline
|
|
bitfld.long 0x00 28. "ADDR_PIN,Address transfer pins" "0: Use one pin,1: Use number of pins as indicated by DATA_PIN.."
|
|
bitfld.long 0x00 27. "BYTE_LEN,Byte length" "0: 1 byte,1: 4 bytes"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "DUMMY_CNT,Dummy count" "0: 0 bytes,1: 1 byte,2: 2 bytes,?..."
|
|
bitfld.long 0x00 8.--9. "RM_CNT,Read Mode Count" "0: 0 bytes,1: 1 byte,2: 2 bytes,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "ADDR_CNT,Address Count" "0: 0 bytes,1: 1 byte,2: 2 bytes,3: 3 bytes,4: 4 bytes,?..."
|
|
bitfld.long 0x00 0.--1. "INSTR_CNT,Instruction Count" "0: 0 bytes,1: 1 byte,2: 2 bytes,?..."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FINSTR,Flash Instruction Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "INSTR,Flash Instruction"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "FRMR,Flash Read Mode Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDMODE,Flash Read Mode"
|
|
tree.end
|
|
tree "GPIO"
|
|
base ad:0x46060000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "GPIO_GPLR_REG0,GPIO Pin Level Register0"
|
|
hexmask.long 0x00 0.--31. 1. "GPLR_REG0,GPLR Reg0"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "GPIO_GPLR_REG1,GPIO Pin Level Register1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "GPLR_REG1,GPLR Reg1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_GPDR_REG0,GPIO Pin Direction Register0"
|
|
hexmask.long 0x00 0.--31. 1. "GPDR_REG0,GPDR Reg0"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPIO_GPDR_REG1,GPIO Pin Direction Register1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "GPDR_REG1,GPDR Reg1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "GPIO_GPSR_REG0,GPIO Pin Output Set Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "GPSR_REG0,GPSR Reg0"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "GPIO_GPSR_REG1,GPIO Pin Output Set Register 1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "GPSR_REG1,GPSR Reg1"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "GPIO_GPCR_REG0,GPIO Pin Output Clear Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "GPCR_REG0,GPCR Reg0"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIO_GPCR_REG1,GPIO Pin Output Clear Register 1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "GPCR_REG1,GPCR Reg1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "GPIO_GRER_REG0,GPIO Rising Edge detect Enable Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "GRER_REG0,GRER Reg0"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "GPIO_GRER_REG1,GPIO Rising Edge detect Enable Register 1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "GRER_REG1,GRER Reg1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "GPIO_GFER_REG0,GPIO Falling Edge detect Enable Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "GFER_REG0,GFER Reg0"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_GFER_REG1,GPIO Falling Edge detect Enable Register 1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "GFER_REG1,GFER Reg1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GPIO_GEDR_REG0,GPIO Edge detect Status Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "GEDR_REG0,GEDR Reg0"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_GEDR_REG1,GPIO Edge detect Status Register 1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "GEDR_REG1,GEDR Reg1"
|
|
wgroup.long 0x54++0x03
|
|
line.long 0x00 "GPIO_GSDR_REG0,GPIO Pin Bitwise Set Direction Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "GSDR_REG0,GSDR Reg0"
|
|
wgroup.long 0x58++0x03
|
|
line.long 0x00 "GPIO_GSDR_REG1,GPIO Pin Bitwise Set Direction Register 1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "GSDR_REG1,GSDR Reg1"
|
|
wgroup.long 0x60++0x03
|
|
line.long 0x00 "GPIO_GCDR_REG0,GPIO Pin Bitwise Clear Direction Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "GCDR_REG0,GCDR Reg0"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "GPIO_GCDR_REG1,GPIO Pin Bitwise Clear Direction Register 1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "GCDR_REG1,GCDR Reg1"
|
|
wgroup.long 0x6C++0x03
|
|
line.long 0x00 "GPIO_GSRER_REG0,GPIO Bitwise Set Rising Edge detect Enable Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "GSRER_REG0,GSRER Reg0"
|
|
wgroup.long 0x70++0x03
|
|
line.long 0x00 "GPIO_GSRER_REG1,GPIO Bitwise set Rising Edge detect Enable Register 1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "GSRER_REG1,GSRER Reg1"
|
|
wgroup.long 0x78++0x03
|
|
line.long 0x00 "GPIO_GCRER_REG0,GPIO Bitwise Clear Rising Edge detect Enable Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "GCRER_REG0,GCRER Reg0"
|
|
wgroup.long 0x7C++0x03
|
|
line.long 0x00 "GPIO_GCRER_REG1,GPIO Bitwise Clear Rising Edge detect Enable Register 1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "GCRER_REG1,GCRER Reg1"
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "GPIO_GSFER_REG0,GPIO Bitwise Set Falling Edge detect Enable Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "GSFER_REG0,GSFER Reg0"
|
|
wgroup.long 0x88++0x03
|
|
line.long 0x00 "GPIO_GSFER_REG1,GPIO Bitwise set Falling Edge detect Enable Register 1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "GSFER_REG1,GSFER Reg1"
|
|
wgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_GCFER_REG0,GPIO Bitwise Clear Falling Edge detect Enable Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "GCFER_REG0,GCFER Reg0"
|
|
wgroup.long 0x94++0x03
|
|
line.long 0x00 "GPIO_GCFER_REG1,GPIO Bitwise Clear Falling Edge detect Enable Register 1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "GCFER_REG1,GCFER Reg1"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "APMASK_REG0,GPIO Bitwise mask of Edge detect Status Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "APMASK_REG0,APMASK Reg0"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "APMASK_REG1,GPIO Bitwise mask of Edge detect Status Register 1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "APMASK_REG1,APMASK Reg1"
|
|
tree.end
|
|
tree "GPT"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x46070000 ad:0x46080000 ad:0x48070000 ad:0x48080000)
|
|
tree "GPT$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNT_EN_REG,Counter Enable Register"
|
|
rbitfld.long 0x00 18. "STS_RESETN,System Reset Status" "0: Indicates that the system reset is still..,1: Indicates that the system reset is deasserted"
|
|
rbitfld.long 0x00 17. "CNT_RST_DONE,Counter Reset Done Status" "0: Indicates that the counter is still resetting,1: Indicates that the counter has been reset"
|
|
newline
|
|
rbitfld.long 0x00 16. "CNT_RUN,Counter Enabled Status" "0: Counter is disabled,1: Counter is enabled"
|
|
bitfld.long 0x00 2. "CNT_RESET,Counter Reset" "0: No action,1: Reset the counter (counter is reset to 0.."
|
|
newline
|
|
bitfld.long 0x00 1. "CNT_STOP,Counter Stop" "0: No action,1: Disable the counter (poll CNT_RUN for 0 to.."
|
|
bitfld.long 0x00 0. "CNT_START,Counter Start" "0: No action,1: Enable the counter (poll CNT_RUN for 1 to.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "STS_REG,Status Register"
|
|
bitfld.long 0x00 25. "DMA1_OF_STS,See DMA0_OF_STS" "0,1"
|
|
bitfld.long 0x00 24. "DMA0_OF_STS,DMA Overflow Status" "0: Status cleared,1: Indicates that there has been a new input.."
|
|
newline
|
|
bitfld.long 0x00 16. "CNT_UPP_STS,Counter-Reach-Upper Status" "0,1"
|
|
bitfld.long 0x00 13. "CH5_ERR_STS,See CH0_ERR_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "CH4_ERR_STS,See CH0_ERR_STS" "0,1"
|
|
bitfld.long 0x00 11. "CH3_ERR_STS,See CH0_ERR_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH2_ERR_STS,See CH0_ERR_STS" "0,1"
|
|
bitfld.long 0x00 9. "CH1_ERR_STS,See CH0_ERR_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH0_ERR_STS,Channel Error Status" "0: Status cleared,1: An error has occurred in this channel"
|
|
bitfld.long 0x00 5. "CH5_STS,See CH0_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CH4_STS,See CH0_STS" "0,1"
|
|
bitfld.long 0x00 3. "CH3_STS,See CH0_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CH2_STS,See CH0_STS" "0,1"
|
|
bitfld.long 0x00 1. "CH1_STS,See CH0_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CH0_STS,Channel Status" "0: Status cleared,1: Status bit for this channel has been set"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "INT_REG,Interrupt Register"
|
|
bitfld.long 0x00 25. "DMA1_OF_INTR,Masked signal of DMA1_OF_STS" "0,1"
|
|
bitfld.long 0x00 24. "DMA0_OF_INTR,Masked signal of DMA0_OF_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CNT_UPP_INTR,Masked signal of CNT_UPP_STS" "0,1"
|
|
bitfld.long 0x00 13. "CH5_ERR_INTR,Masked signal of CH5_ERR_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "CH4_ERR_INTR,Masked signal of CH4_ERR_STS" "0,1"
|
|
bitfld.long 0x00 11. "CH3_ERR_INTR,Masked signal of CH3_ERR_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH2_ERR_INTR,Masked signal of CH2_ERR_STS" "0,1"
|
|
bitfld.long 0x00 9. "CH1_ERR_INTR,Masked signal of CH1_ERR_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH0_ERR_INTR,Masked signal of CH0_ERR_STS" "0,1"
|
|
bitfld.long 0x00 5. "CH5_INTR,Masked signal of CH5_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CH4_INTR,Masked signal of CH4_STS" "0,1"
|
|
bitfld.long 0x00 3. "CH3_INTR,Masked signal of CH3_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CH2_INTR,Masked signal of CH2_STS" "0,1"
|
|
bitfld.long 0x00 1. "CH1_INTR,Masked signal of CH1_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CH0_INTR,Masked signal of CH0_STS" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "INT_MSK_REG,Interrupt Mask Register"
|
|
bitfld.long 0x00 25. "DMA1_OF_MSK,See DMA0_OF_MSK" "0,1"
|
|
bitfld.long 0x00 24. "DMA0_OF_MSK,DMA Channel Overflow Mask" "0: Do not mask DMA0_OF_STS,1: Mask DMA0_OF_STS"
|
|
newline
|
|
bitfld.long 0x00 16. "CNT_UPP_MSK,Upper Value Interrupt Mask" "0: Do not mask CNT_UPP_STS,1: Mask CNT_UPP_STS"
|
|
bitfld.long 0x00 13. "CH5_ERR_MSK,See CH0_ERR_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "CH4_ERR_MSK,See CH0_ERR_STS" "0,1"
|
|
bitfld.long 0x00 11. "CH3_ERR_MSK,See CH0_ERR_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH2_ERR_MSK,See CH0_ERR_STS" "0,1"
|
|
bitfld.long 0x00 9. "CH1_ERR_MSK,See CH0_ERR_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH0_ERR_MSK,Channel Error Interrupt Mask" "0: Do not mask CH0_ERR_STS,1: Mask CH0_ERR_STS"
|
|
bitfld.long 0x00 5. "CH5_MSK,See CH0_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CH4_MSK,See CH0_STS" "0,1"
|
|
bitfld.long 0x00 3. "CH3_MSK,See CH0_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CH2_MSK,See CH0_STS" "0,1"
|
|
bitfld.long 0x00 1. "CH1_MSK,See CH0_STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CH0_MSK,Channel Interrupt Mask" "0: Do not mask CH0_STS,1: Mask CH0_STS"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CNT_CNTL_REG,Counter Control Register"
|
|
bitfld.long 0x00 8.--9. "CNT_UPDT_MOD,Counter Value Update Mode" "0: Auto-update normal (can be used for any clock..,1: Auto-update fast (use when counter clock is..,?,3: Update off (of CNT_VAL does not need to be.."
|
|
bitfld.long 0x00 4. "CNT_DBG_ACT,Counter Debug Mode Action Mask" "0: In debug mode stop the counter,1: In debug mode the counter is not affected"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "CNT_VAL_REG,Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "CNT_VAL,Counter Value"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CNT_UPP_VAL_REG,Counter Upper Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "UPP_VAL,Counter Upper Value"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CLK_CNTL_REG,Clock Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CLK_PRE,Clock Pre-Scalar"
|
|
bitfld.long 0x00 8.--11. "CLK_DIV,Clock Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "CLK_SRC,Counter Clock Select" "0: Select clock 0,1: Select clock 1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "IC_CNTL_REG,Input Capture Control Register"
|
|
bitfld.long 0x00 4.--6. "CHx_IC_DIV,Input Capture Sampling Clock Divider" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CHx_IC_WIDTH,Input Capture Filter Width" "0: No filtering (1 cycle),1: 2 cycles,2: 3 cycles,3: 4 cycles,4: 5 cycles,5: 6 cycles,6: 7 cycles,?..."
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DMA_CNTL_EN_REG,DMA Control Enable Register"
|
|
bitfld.long 0x00 1. "DMA1_EN,See DMA0_EN" "0,1"
|
|
bitfld.long 0x00 0. "DMA0_EN,DMA Channel Enable" "0: Disable this DMA channel,1: Enable this DMA channel"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "DMA_CNTL_CH_REG,DMA Control Channel Register"
|
|
bitfld.long 0x00 4.--6. "DMA1_CH,See DMA0_CH" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "DMA0_CH,DMA Channel Select" "0: Connect to channel 0,1: Connect to channel 1,2: Connect to channel 2,3: Connect to channel 3,4: Connect to channel 4,5: Connect to channel 5,?..."
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "ADCT_REG,ADC Trigger Control Register"
|
|
bitfld.long 0x00 8. "ADCT_EN,ADC Trigger Enable" "0: Disable the ADC trigger,1: Enable the ADC trigger"
|
|
bitfld.long 0x00 0.--2. "ADCT_CHSEL,ADC Trigger Channel Select" "0: Connect to channel 0,1: Connect to channel 1,2: Connect to channel 2,3: Connect to channel 3,4: Connect to channel 4,5: Connect to channel 5,?..."
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "ADCT_DLY_REG,ADC Trigger Delay Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADCT_DLY,ADC Trigger Delay"
|
|
wgroup.long 0xF0++0x03
|
|
line.long 0x00 "USER_REQ_REG,User Request Register"
|
|
bitfld.long 0x00 21. "CH5_CMR_UPDT,See CH0_CMR_UPDT" "0,1"
|
|
bitfld.long 0x00 20. "CH4_CMR_UPDT,See CH0_CMR_UPDT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CH3_CMR_UPDT,See CH0_CMR_UPDT" "0,1"
|
|
bitfld.long 0x00 18. "CH2_CMR_UPDT,See CH0_CMR_UPDT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CH1_CMR_UPDT,See CH0_CMR_UPDT" "0,1"
|
|
bitfld.long 0x00 16. "CH0_CMR_UPDT,Channel CMR Update" "0: No action,1: Update CMR0 and CMR1 to the internal shadow.."
|
|
newline
|
|
bitfld.long 0x00 13. "CH5_RST,See CH0_RST" "0,1"
|
|
bitfld.long 0x00 12. "CH4_RST,See CH0_RST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CH3_RST,See CH0_RST" "0,1"
|
|
bitfld.long 0x00 10. "CH2_RST,See CH0_RST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH1_RST,See CH0_RST" "0,1"
|
|
bitfld.long 0x00 8. "CH0_RST,Channel Reset" "0: No action,1: Reset this channel"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5_USER_ITRIG,See CH0_USER_ITRIG" "0,1"
|
|
bitfld.long 0x00 4. "CH4_USER_ITRIG,See CH0_USER_ITRIG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3_USER_ITRIG,See CH0_USER_ITRIG" "0,1"
|
|
bitfld.long 0x00 2. "CH2_USER_ITRIG,See CH0_USER_ITRIG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1_USER_ITRIG,See CH0_USER_ITRIG" "0,1"
|
|
bitfld.long 0x00 0. "CH0_USER_ITRIG,User Input Trigger" "0: No action,1: If this channel (channel 0) is configured to.."
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CH0_CNTL_REG,Channel 0 Control Register"
|
|
bitfld.long 0x00 16. "POL,Channel Polarity" "0: Reset to 0,1: Reset to 1"
|
|
bitfld.long 0x00 12.--14. "IC_EDGE,Channel Input Capture Edge" "0: Capture rising edge in CMR0,1: Capture falling edge in CMR0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "CHx_IO,Channel Mode" "0: No function,1: Input capture mode,?,?,4: One-shot mode (pulse),5: One-shot mode (edge),6: PWM mode (edge-aligned),7: PWM mode (center-aligned)"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "CH0_CMR0_REG,Channel 0 Counter Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "CMR0,Channel Counter Match Register 0"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "CH0_STS_REG,Channel 0 Status Register 0"
|
|
bitfld.long 0x00 0. "OUT_ST,Channel Output State" "0,1"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "CH0_CMR1_REG,Channel 0 Counter Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "CMR1,Channel Counter Match Register 1"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "CH1_CNTL_REG,Channel 1 Control Register"
|
|
bitfld.long 0x00 16. "POL,Channel Polarity" "0: Reset to 0,1: Reset to 1"
|
|
bitfld.long 0x00 12.--14. "IC_EDGE,Channel Input Capture Edge" "0: Capture rising edge in CMR0,1: Capture falling edge in CMR0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "CHx_IO,Channel Mode" "0: No function,1: Input capture mode,?,?,4: One-shot mode (pulse),5: One-shot mode (edge),6: PWM mode (edge-aligned),7: PWM mode (center-aligned)"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "CH1_CMR0_REG,Channel 1 Counter Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "CMR0,Channel Counter Match Register 0"
|
|
rgroup.long 0x254++0x03
|
|
line.long 0x00 "CH1_STS_REG,Channel 1 Status Register 0"
|
|
bitfld.long 0x00 0. "OUT_ST,Channel Output State" "0,1"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "CH1_CMR1_REG,Channel 1 Counter Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "CMR1,Channel Counter Match Register 1"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "CH2_CNTL_REG,Channel 2 Control Register"
|
|
bitfld.long 0x00 16. "POL,Channel Polarity" "0: Reset to 0,1: Reset to 1"
|
|
bitfld.long 0x00 12.--14. "IC_EDGE,Channel Input Capture Edge" "0: Capture rising edge in CMR0,1: Capture falling edge in CMR0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "CHx_IO,Channel Mode" "0: No function,1: Input capture mode,?,?,4: One-shot mode (pulse),5: One-shot mode (edge),6: PWM mode (edge-aligned),7: PWM mode (center-aligned)"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "CH2_CMR0_REG,Channel 2 Counter Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "CMR0,Channel Counter Match Register 0"
|
|
rgroup.long 0x294++0x03
|
|
line.long 0x00 "CH2_STS_REG,Channel 2 Status Register 0"
|
|
bitfld.long 0x00 0. "OUT_ST,Channel Output State" "0,1"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "CH2_CMR1_REG,Channel 2 Counter Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "CMR1,Channel Counter Match Register 1"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "CH3_CNTL_REG,Channel 3 Control Register"
|
|
bitfld.long 0x00 16. "POL,Channel Polarity" "0: Reset to 0,1: Reset to 1"
|
|
bitfld.long 0x00 12.--14. "IC_EDGE,Channel Input Capture Edge" "0: Capture rising edge in CMR0,1: Capture falling edge in CMR0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "CHx_IO,Channel Mode" "0: No function,1: Input capture mode,?,?,4: One-shot mode (pulse),5: One-shot mode (edge),6: PWM mode (edge-aligned),7: PWM mode (center-aligned)"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "CH3_CMR0_REG,Channel 3 Counter Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "CMR0,Channel Counter Match Register 0"
|
|
rgroup.long 0x2D4++0x03
|
|
line.long 0x00 "CH3_STS_REG,Channel 3 Status Register 0"
|
|
bitfld.long 0x00 0. "OUT_ST,Channel Output State" "0,1"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "CH3_CMR1_REG,Channel 3 Counter Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "CMR1,Channel Counter Match Register 1"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "CH4_CNTL_REG,Channel 4 Control Register"
|
|
bitfld.long 0x00 16. "POL,Channel Polarity" "0: Reset to 0,1: Reset to 1"
|
|
bitfld.long 0x00 12.--14. "IC_EDGE,Channel Input Capture Edge" "0: Capture rising edge in CMR0,1: Capture falling edge in CMR0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "CHx_IO,Channel Mode" "0: No function,1: Input capture mode,?,?,4: One-shot mode (pulse),5: One-shot mode (edge),6: PWM mode (edge-aligned),7: PWM mode (center-aligned)"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "CH4_CMR0_REG,Channel 4 Counter Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "CMR0,Channel Counter Match Register 0"
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "CH4_STS_REG,Channel 4 Status Register 0"
|
|
bitfld.long 0x00 0. "OUT_ST,Channel Output State" "0,1"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "CH4_CMR1_REG,Channel 4 Counter Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "CMR1,Channel Counter Match Register 1"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "CH5_CNTL_REG,Channel 5 Control Register"
|
|
bitfld.long 0x00 16. "POL,Channel Polarity" "0: Reset to 0,1: Reset to 1"
|
|
bitfld.long 0x00 12.--14. "IC_EDGE,Channel Input Capture Edge" "0: Capture rising edge in CMR0,1: Capture falling edge in CMR0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "CHx_IO,Channel Mode" "0: No function,1: Input capture mode,?,?,4: One-shot mode (pulse),5: One-shot mode (edge),6: PWM mode (edge-aligned),7: PWM mode (center-aligned)"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "CH5_CMR0_REG,Channel 5 Counter Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "CMR0,Channel Counter Match Register 0"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "CH5_STS_REG,Channel 5 Status Register 0"
|
|
bitfld.long 0x00 0. "OUT_ST,Channel Output State" "0,1"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "CH5_CMR1_REG,Channel 5 Counter Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "CMR1,Channel Counter Match Register 1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "I2C"
|
|
repeat 2. (list 0. 1.) (list ad:0x46000000 ad:0x48050000)
|
|
tree "I2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "IC_CON,Name: I2C Control Register Size: 7 bits Address Offset: 0x00 Read/Write Access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0 all bits are Read/"
|
|
bitfld.long 0x00 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled which means once the presetn signal is applied then this bit takes on the value of the configuration parameter IC_SLAVE_DISABLE" "0: slave is enabled,1: slave is disabled"
|
|
newline
|
|
bitfld.long 0x00 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when acting as a master" "0: disable,1: enable"
|
|
newline
|
|
rbitfld.long 0x00 4. "IC_10BITADDR_MASTER_rd_only,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is set to 'No' (0) this bit is named IC_10BITADDR_MASTER and controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master" "0: 7-bit addressing,1: 10-bit addressing"
|
|
newline
|
|
bitfld.long 0x00 3. "IC_10BITADDR_SLAVE,When acting as a slave this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses" "0: 7-bit addressing,1: 10-bit addressing"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates its setting is relevant only if one is operating the DW_apb_i2c in master mode" "?,1: standard mode (100 kbit/s),2: fast mode (400 kbit/s),3: high speed mode (3.4 Mbit/s)"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled" "0: master disabled,1: master enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IC_TAR,Name: I2C Target Address Register Size: 12 bits or 13 bits 13 bits only when I2C_DYNAMIC_TAR_UPDATE = 1 Address Offset: 0x04 Read/Write Access: Read/Write If the configuration parameter I2C_DYNAMIC_TAR_UPDATE is set to 'No' (0) this register is.."
|
|
bitfld.long 0x00 12. "IC_10BITADDR_MASTER,This bit controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master" "0: 7-bit addressing,1: 10-bit addressing"
|
|
newline
|
|
bitfld.long 0x00 11. "SPECIAL,This bit indicates whether software performs a General Call or START BYTE command" "0: ignore bit 10 GC_OR_START and use IC_TAR..,1: perform special I2C command as specified in.."
|
|
newline
|
|
bitfld.long 0x00 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c" "0: General Call Address after issuing a General..,1: START BYTE"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "IC_TAR,This is the target address for any master transaction"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IC_SAR,Name: I2C Slave Address Register Size: 10 bits Address Offset: 0x08 Read/Write Access: Read/"
|
|
hexmask.long.word 0x00 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IC_HS_MADDR,Name: I2C High Speed Master Mode Code Address Register Size: 3 bits Address Offset: 0x0c Read/Write Access: Read/"
|
|
bitfld.long 0x00 0.--2. "IC_HS_MAR,This bit field holds the value of the I2C HS mode master code" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IC_DATA_CMD,Name: I2C Rx/Tx Data Buffer and Command Register this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO Size: 9 bits (writes) 8 bits (reads) Address Offset: 0x10 Read/Write.."
|
|
bitfld.long 0x00 8. "CMD,This bit controls whether a read or a write is performed" "0: ,1: "
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IC_SS_SCL_HCNT,Name: Standard Speed I2C Clock SCL High Count Register Size: 16 bits Address Offset: 0x14 Read/Write Access: Read/"
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hexmask.long.word 0x00 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
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group.long 0x18++0x03
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line.long 0x00 "IC_SS_SCL_LCNT,Name: Standard Speed I2C Clock SCL Low Count Register Size: 16 bits Address Offset: 0x18 Read/Write Access: Read/"
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hexmask.long.word 0x00 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
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group.long 0x1C++0x03
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line.long 0x00 "IC_FS_SCL_HCNT,Name: Fast Speed I2C Clock SCL High Count Register Size: 16 bits Address Offset: 0x1c Read/Write Access: Read/"
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hexmask.long.word 0x00 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
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group.long 0x20++0x03
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line.long 0x00 "IC_FS_SCL_LCNT,Name: Fast Speed I2C Clock SCL Low Count Register Size: 16 bits Address Offset: 0x20 Read/Write Access: Read/"
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hexmask.long.word 0x00 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
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group.long 0x24++0x03
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line.long 0x00 "IC_HS_SCL_HCNT,Name: High Speed I2C Clock SCL High Count Register Size: 16 bits Address Offset: 0x24 Read/Write Access: Read/"
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hexmask.long.word 0x00 0.--15. 1. "IC_HS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
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group.long 0x28++0x03
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line.long 0x00 "IC_HS_SCL_LCNT,Name: High Speed I2C Clock SCL Low Count Register Size: 16 bits Address Offset: 0x28 Read/Write Access: Read/"
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hexmask.long.word 0x00 0.--15. 1. "IC_HS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
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rgroup.long 0x2C++0x03
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line.long 0x00 "IC_INTR_STAT,Name: I2C Interrupt Status Register Size: 12 bits Address Offset: 0x2C Read/Write Access: Read Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register"
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bitfld.long 0x00 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
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bitfld.long 0x00 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode" "0,1"
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bitfld.long 0x00 9. "R_STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode" "0,1"
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bitfld.long 0x00 8. "R_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared" "0,1"
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bitfld.long 0x00 7. "R_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
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bitfld.long 0x00 6. "R_TX_ABRT,This bit indicates if DW_apb_i2c as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
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bitfld.long 0x00 5. "R_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c" "0,1"
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bitfld.long 0x00 4. "R_TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register" "0,1"
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bitfld.long 0x00 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
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bitfld.long 0x00 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register" "0,1"
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bitfld.long 0x00 1. "R_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device" "0,1"
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bitfld.long 0x00 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
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group.long 0x30++0x03
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line.long 0x00 "IC_INTR_MASK,Name: I2C Interrupt Mask Register Size: 12 bits Address Offset: 0x30 Read/Write Access: Read/Write These bits mask their corresponding interrupt status bits"
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bitfld.long 0x00 11. "M_GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
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bitfld.long 0x00 10. "M_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode" "0,1"
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bitfld.long 0x00 9. "M_STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode" "0,1"
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bitfld.long 0x00 8. "M_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared" "0,1"
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bitfld.long 0x00 7. "M_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
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bitfld.long 0x00 6. "M_TX_ABRT,This bit indicates if DW_apb_i2c as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
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bitfld.long 0x00 5. "M_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c" "0,1"
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bitfld.long 0x00 4. "M_TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register" "0,1"
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bitfld.long 0x00 3. "M_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
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bitfld.long 0x00 2. "M_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register" "0,1"
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bitfld.long 0x00 1. "M_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device" "0,1"
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bitfld.long 0x00 0. "M_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
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rgroup.long 0x34++0x03
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line.long 0x00 "IC_RAW_INTR_STAT,Name: I2C Raw Interrupt Status Register Size: 12 bits Address Offset: 0x34 Read/Write Access: Read Unlike the IC_INTR_STAT register these bits are not masked so they always show the true status of the DW_apb_i2c"
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bitfld.long 0x00 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
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bitfld.long 0x00 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode" "0,1"
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bitfld.long 0x00 9. "STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode" "0,1"
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bitfld.long 0x00 8. "ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared" "0,1"
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bitfld.long 0x00 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
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bitfld.long 0x00 6. "TX_ABRT,This bit indicates if DW_apb_i2c as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
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bitfld.long 0x00 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c" "0,1"
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bitfld.long 0x00 4. "TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register" "0,1"
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bitfld.long 0x00 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
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bitfld.long 0x00 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register" "0,1"
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bitfld.long 0x00 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device" "0,1"
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bitfld.long 0x00 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
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group.long 0x38++0x03
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line.long 0x00 "IC_RX_TL,Name: I2C Receive FIFO Threshold Register Size: 8bits Address Offset: 0x38 Read/Write Access: Read/"
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hexmask.long.byte 0x00 0.--7. 1. "RX_TL,Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register)"
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group.long 0x3C++0x03
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line.long 0x00 "IC_TX_TL,Name: I2C Transmit FIFO Threshold Register Size: 8 bits Address Offset: 0x3c Read/Write Access: Read/"
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hexmask.long.byte 0x00 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register)"
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rgroup.long 0x40++0x03
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line.long 0x00 "IC_CLR_INTR,Name: Clear Combined and Individual Interrupt Register Size: 1 bit Address Offset: 0x40 Read/Write Access: Read"
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bitfld.long 0x00 0. "CLR_INTR,Read this register to clear the combined interrupt all individual interrupts and the IC_TX_ABRT_SOURCE register" "0,1"
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rgroup.long 0x44++0x03
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line.long 0x00 "IC_CLR_RX_UNDER,Name: Clear RX_UNDER Interrupt Register Size: 1 bit Address Offset: 0x44 Read/Write Access: Read"
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bitfld.long 0x00 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register" "0,1"
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rgroup.long 0x48++0x03
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line.long 0x00 "IC_CLR_RX_OVER,Name: Clear RX_OVER Interrupt Register Size: 1 bit Address Offset: 0x48 Read/Write Access: Read"
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bitfld.long 0x00 0. "CLR_RX_OVER,Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register" "0,1"
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rgroup.long 0x4C++0x03
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line.long 0x00 "IC_CLR_TX_OVER,Name: Clear TX_OVER Interrupt Register Size: 1 bit Address Offset: 0x4c Read/Write Access: Read"
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bitfld.long 0x00 0. "CLR_TX_OVER,Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register" "0,1"
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rgroup.long 0x50++0x03
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line.long 0x00 "IC_CLR_RD_REQ,Name: Clear RD_REQ Interrupt Register Size: 1 bit Address Offset: 0x50 Read/Write Access: Read"
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bitfld.long 0x00 0. "CLR_RD_REQ,Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register" "0,1"
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rgroup.long 0x54++0x03
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line.long 0x00 "IC_CLR_TX_ABRT,Name: Clear TX_ABRT Interrupt Register Size: 1 bit Address Offset: 0x54 Read/Write Access: Read"
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bitfld.long 0x00 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register and the IC_TX_ABRT_SOURCE register" "0,1"
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rgroup.long 0x58++0x03
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line.long 0x00 "IC_CLR_RX_DONE,Name: Clear RX_DONE Interrupt Register Size: 1 bit Address Offset: 0x58 Read/Write Access: Read"
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bitfld.long 0x00 0. "CLR_RX_DONE,Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register" "0,1"
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rgroup.long 0x5C++0x03
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line.long 0x00 "IC_CLR_ACTIVITY,Name: Clear ACTIVITY Interrupt Register Size: 1 bit Address Offset: 0x5c Read/Write Access: Read"
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bitfld.long 0x00 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore" "0,1"
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rgroup.long 0x60++0x03
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line.long 0x00 "IC_CLR_STOP_DET,Name: Clear STOP_DET Interrupt Register Size: 1 bit Address Offset: 0x60 Read/Write Access: Read"
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bitfld.long 0x00 0. "CLR_STOP_DET,Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register" "0,1"
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rgroup.long 0x64++0x03
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line.long 0x00 "IC_CLR_START_DET,Name: Clear START_DET Interrupt Register Size: 1 bit Address Offset: 0x64 Read/Write Access: Read"
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bitfld.long 0x00 0. "CLR_START_DET,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register" "0,1"
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rgroup.long 0x68++0x03
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line.long 0x00 "IC_CLR_GEN_CALL,Name: Clear GEN_CALL Interrupt Register Size: 1 bit Address Offset: 0x68 Read/Write Access: Read"
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bitfld.long 0x00 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register" "0,1"
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group.long 0x6C++0x03
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line.long 0x00 "IC_ENABLE,Name: I2C Enable Register Size: 1 bit Address Offset: 0x6c Read/Write Access: Read/"
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bitfld.long 0x00 0. "ENABLE,Controls whether the DW_apb_i2c is enabled" "0: Disables DW_apb_i2c (TX and RX FIFOs are held..,1: Enables DW_apb_i2c Software can disable.."
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rgroup.long 0x70++0x03
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line.long 0x00 "IC_STATUS,Name: I2C Status Register Size: 7 bits Address Offset: 0x70 Read/Write Access: Read This is a read-only register used to indicate the current transfer status and FIFO status"
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bitfld.long 0x00 6. "SLV_ACTIVITY,Slave FSM Activity Status" "0: Slave FSM is in IDLE state so the Slave part..,1: Slave FSM is not in IDLE state so the Slave.."
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bitfld.long 0x00 5. "MST_ACTIVITY,Master FSM Activity Status" "0: Master FSM is in IDLE state so the Master..,1: Master FSM is not in IDLE state so the Master.."
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bitfld.long 0x00 4. "RFF,Receive FIFO Completely Full" "0: Receive FIFO is not full,1: Receive FIFO is full"
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bitfld.long 0x00 3. "RFNE,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty"
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bitfld.long 0x00 2. "TFE,Transmit FIFO Completely Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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bitfld.long 0x00 1. "TFNF,Transmit FIFO Not Full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x00 0. "ACTIVITY,I2C Activity Status" "0,1"
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rgroup.long 0x74++0x03
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line.long 0x00 "IC_TXFLR,Name: I2C Transmit FIFO Level Register Size: TX_ABW + 1 Address Offset: 0x74 Read/Write Access: Read This register contains the number of valid data entries in the transmit FIFO buffer"
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bitfld.long 0x00 0.--4. "TXFLR,Transmit FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rgroup.long 0x78++0x03
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line.long 0x00 "IC_RXFLR,Name: I2C Receive FIFO Level Register Size: RX_ABW + 1 Address Offset: 0x78 Read/Write Access: Read This register contains the number of valid data entries in the receive FIFO buffer"
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bitfld.long 0x00 0.--4. "RXFLR,Receive FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x7C++0x03
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line.long 0x00 "IC_SDA_HOLD,Name: I2C SDA Hold Register Size: 16 bits Address Offset: 0x7c Read/Write Access: Read/Write This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the falling edge of SCL relative to SDA.."
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hexmask.long.word 0x00 0.--15. 1. "IC_SDA_HOLD,SDA Hold"
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rgroup.long 0x80++0x03
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line.long 0x00 "IC_TX_ABRT_SOURCE,Name: I2C Transmit Abort Source Register Size: 16 bits Address Offset: 0x80 Read/Write Access: Read/Write This register has 16 bits that indicate the source of the TX_ABRT bit"
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bitfld.long 0x00 15. "ABRT_SLVRD_INTX," "?,1: When the processor side responds to a slave.."
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bitfld.long 0x00 14. "ABRT_SLV_ARBLOST," "?,1: Slave lost the bus while transmitting data to.."
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bitfld.long 0x00 13. "ABRT_SLVFLUSH_TXFIFO," "?,1: Slave has received a read command and some.."
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bitfld.long 0x00 12. "ARB_LOST," "?,1: Master has lost arbitration or if.."
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bitfld.long 0x00 11. "ABRT_MASTER_DIS," "?,1: User tries to initiate a Master operation.."
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bitfld.long 0x00 10. "ABRT_10B_RD_NORSTRT," "?,1: The restart is disabled (IC_RESTART_EN bit.."
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bitfld.long 0x00 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9 the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (IC_CON[5]=1) the SPECIAL bit must be cleared (IC_TAR[11]) or the GC_OR_START bit must be cleared (IC_TAR[10])" "?,1: The restart is disabled (IC_RESTART_EN bit.."
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bitfld.long 0x00 8. "ABRT_HS_NORSTRT," "?,1: The restart is disabled (IC_RESTART_EN bit.."
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bitfld.long 0x00 7. "ABRT_SBYTE_ACKDET," "?,1: Master has sent a START Byte and the START.."
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bitfld.long 0x00 6. "ABRT_HS_ACKDET," "?,1: Master is in High Speed mode and the High.."
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bitfld.long 0x00 5. "ABRT_GCALL_READ," "?,1: DW_apb_i2c in master mode sent a General Call.."
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bitfld.long 0x00 4. "ABRT_GCALL_NOACK," "?,1: DW_apb_i2c in master mode sent a General Call.."
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bitfld.long 0x00 3. "ABRT_TXDATA_NOACK," "?,1: This is a master-mode only bit"
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bitfld.long 0x00 2. "ABRT_10ADDR2_NOACK," "?,1: Master is in 10-bit address mode and the.."
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bitfld.long 0x00 1. "ABRT_10ADDR1_NOACK," "?,1: Master is in 10-bit address mode and the.."
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bitfld.long 0x00 0. "ABRT_7B_ADDR_NOACK," "?,1: Master is in 7-bit addressing mode and the.."
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group.long 0x84++0x03
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line.long 0x00 "IC_SLV_DATA_NACK_ONLY,Name: Generate Slave Data NACK Register Size: 1 bit Address Offset: 0x84 Read/Write Access: Read/Write The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver"
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bitfld.long 0x00 0. "NACK,Generate NACK" "0: generate NACK/ACK normally,1: generate NACK after data byte received"
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group.long 0x88++0x03
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line.long 0x00 "IC_DMA_CR,Name: DMA Control Register Size: 2 bits Address Offset: 0x88 Read/Write Access: Read/Write This register is only valid when DW_apb_i2c is configured with a set of DMA Controller interface signals (IC_HAS_DMA = 1)"
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bitfld.long 0x00 1. "TDMAE,Transmit DMA Enable" "0: Transmit DMA disabled,1: Transmit DMA enabled"
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bitfld.long 0x00 0. "RDMAE,Receive DMA Enable" "0: Receive DMA disabled,1: Receive DMA enabled"
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group.long 0x8C++0x03
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line.long 0x00 "IC_DMA_TDLR,Name: DMA Transmit Data Level Register Size: 2 bits Address Offset: 0x8c Read/Write Access: Read/Write This register is only valid when the DW_apb_i2c is configured with a set of DMA interface signals (IC_HAS_DMA = 1)"
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bitfld.long 0x00 0.--3. "DMATDL,Transmit Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x90++0x03
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line.long 0x00 "IC_DMA_RDLR,Name: I2C Receive Data Level Register Size: 2 bits Address Offset: 0x90 Read/Write Access: Read/Write This register is only valid when DW_apb_i2c is configured with a set of DMA interface signals (IC_HAS_DMA = 1)"
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bitfld.long 0x00 0.--3. "DMARDL,Receive Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x94++0x03
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line.long 0x00 "IC_SDA_SETUP,Name: I2C SDA Setup Register Size: 8 bits Address Offset: 0x94 Read/Write Access: Read/Write This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL relative to SDA.."
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hexmask.long.byte 0x00 0.--7. 1. "SDA_SETUP,SDA Setup"
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group.long 0x98++0x03
|
|
line.long 0x00 "IC_ACK_GENERAL_CALL,Name: I2C ACK General Call Register Size: 1 bit Address Offset: 0x98 Read/Write Access: Read/Write The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address"
|
|
bitfld.long 0x00 0. "ACK_GEN_CALL,ACK General Call" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "IC_ENABLE_STATUS,Name: I2C Enable Status Register Size: 3 bits Address Offset: 0x9C Read/Write Access: Read The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE register is set from 1 to 0 that is when DW_apb_i2c is disabled"
|
|
bitfld.long 0x00 2. "SLV_RX_DATA_LOST,Slave Received Data Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit Receive)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IC_EN,ic_en Status" "0,1"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "IC_FS_SPKLEN,Name: I2C SS and FS spike suppression limit Size: 8 bits Address: 0xA0 Read/Write Access: Read/Write This register is used to store the duration measured in ic_clk cycles of the longest spike that is filtered out by the spike suppression.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "IC_HS_SPKLEN,Name: I2C HS spike suppression limit Size: 8 bits Address: 0xA4 Read/Write Access: Read/Write This register is used to store the duration measured in ic_clk cycles of the longest spike that is filtered out by the spike suppression logic w.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "IC_HS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "IC_COMP_PARAM_1,Name: Component Parameter Register 1 Size: 32 bits Address Offset: 0xf4 Read/Write Access: Read Note This is a constant read-only register that contains encoded information about the component's parameter settings"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived from the IC_TX_BUFFER_DEPTH coreConsultant parameter"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is derived from the IC_RX_BUFFER_DEPTH coreConsultant parameter"
|
|
newline
|
|
bitfld.long 0x00 7. "ADD_ENCODED_PARAMS,The value of this register is derived from the IC_ADD_ENCODED_PARAMS coreConsultant parameter" "0: False,1: True"
|
|
newline
|
|
bitfld.long 0x00 6. "HAS_DMA,The value of this register is derived from the IC_HAS_DMA coreConsultant parameter" "0: False,1: True"
|
|
newline
|
|
bitfld.long 0x00 5. "INTR_IO,The value of this register is derived from the IC_INTR_IO coreConsultant parameter" "0: Individual,1: Combined"
|
|
newline
|
|
bitfld.long 0x00 4. "HC_COUNT_VALUES,The value of this register is derived from the IC_HC_COUNT VALUES coreConsultant parameter" "0: False,1: True"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "MAX_SPEED_MODE,The value of this register is derived from the IC_MAX_SPEED_MODE coreConsultant parameter" "?,1: Standard,2: Fast,3: High"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "APB_DATA_WIDTH,The value of this register is derived from the APB_DATA_WIDTH coreConsultant parameter" "0: 8 bits,1: 16 bits,2: 32 bits,?..."
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "IC_COMP_VERSION,Name: I2C Component Version Register Size: 32 bits Address Offset: 0xf8 Read/Write Access: Read"
|
|
hexmask.long 0x00 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are described in the Releases Table in the DW_apb_i2c Release Notes"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "IC_COMP_TYPE,Name: I2C Component Type Register Size: 32 bits Address Offset: 0xfc Read/Write Access: Read"
|
|
hexmask.long 0x00 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number = 0x44_57_01_40"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PINMUX"
|
|
base ad:0x48010000
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "_GPIO$1,padring pin Register"
|
|
bitfld.long 0x00 15. "PIO_PULL_SEL,custom pull-up and -down configuration control" "0: pull-up and pull-down from io_mux,1: pull-up and pull-down from bits [14:13]"
|
|
bitfld.long 0x00 14. "PIO_PULL_UP,pull-up enable" "0: pull-up disabled,1: pull-up enabled"
|
|
bitfld.long 0x00 13. "PIO_PULL_DN,pull-down enable" "0: pull-down disabled,1: pull-down enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "SLP_OE,reserved for test purpose" "0,1"
|
|
bitfld.long 0x00 4. "SLP_VAL,reserved for test purpose" "0,1"
|
|
bitfld.long 0x00 3. "DI_EN,input enable control" "0: receiver will be tri-stated,1: receive data from PAD"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FSEL,padring function select" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "_GPIO$1,padring pin Register"
|
|
bitfld.long 0x00 15. "PIO_PULL_SEL,custom pull-up and -down configuration control" "0: pull-up and pull-down from io_mux,1: pull-up and pull-down from bits [14:13]"
|
|
bitfld.long 0x00 14. "PIO_PULL_UP,pull-up enable" "0: pull-up disabled,1: pull-up enabled"
|
|
bitfld.long 0x00 13. "PIO_PULL_DN,pull-down enable" "0: pull-down disabled,1: pull-down enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "SLP_OE,reserved for test purpose" "0,1"
|
|
bitfld.long 0x00 4. "SLP_VAL,reserved for test purpose" "0,1"
|
|
bitfld.long 0x00 3. "DI_EN,input enable control" "0: receiver will be tri-stated,1: receive data from PAD"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FSEL,padring function select" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "_GPIO$1,padring pin Register"
|
|
bitfld.long 0x00 15. "PIO_PULL_SEL,custom pull-up and -down configuration control" "0: pull-up and pull-down from io_mux,1: pull-up and pull-down from bits [14:13]"
|
|
bitfld.long 0x00 14. "PIO_PULL_UP,pull-up enable" "0: pull-up disabled,1: pull-up enabled"
|
|
bitfld.long 0x00 13. "PIO_PULL_DN,pull-down enable" "0: pull-down disabled,1: pull-down enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "SLP_OE,reserved for test purpose" "0,1"
|
|
bitfld.long 0x00 4. "SLP_VAL,reserved for test purpose" "0,1"
|
|
bitfld.long 0x00 3. "DI_EN,input enable control" "0: receiver will be tri-stated,1: receive data from PAD"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FSEL,padring function select" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 2. (strings "48" "49" )(list 0x0 0x4 )
|
|
group.long ($2+0xC0)++0x03
|
|
line.long 0x00 "_GPIO$1,padring pin Register"
|
|
bitfld.long 0x00 15. "PIO_PULL_SEL,custom pull-up and -down configuration control" "0: pull-up and pull-down from io_mux,1: pull-up and pull-down from bits [14:13]"
|
|
bitfld.long 0x00 14. "PIO_PULL_UP,pull-up enable" "0: pull-up disabled,1: pull-up enabled"
|
|
bitfld.long 0x00 13. "PIO_PULL_DN,pull-down enable" "0: pull-down disabled,1: pull-down enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "SLP_OE,reserved for test purpose" "0,1"
|
|
bitfld.long 0x00 4. "SLP_VAL,reserved for test purpose" "0,1"
|
|
bitfld.long 0x00 3. "DI_EN,input enable control" "0: receiver will be tri-stated,1: receive data from PAD"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FSEL,padring function select" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
tree.end
|
|
tree "PMU"
|
|
base ad:0x480A0000
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "PWR_MODE,Power mode control register"
|
|
bitfld.long 0x00 0.--1. "pwr_mode,Power mode switch" "0: PM0 or PM1,1: no description available,2: no description available,3: no description available"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BOOT_JTAG,BOOT_JTAG register"
|
|
bitfld.long 0x00 0. "jtag_en,JTAG Enable" "0: disable JTAG,1: enable JTAG"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "LAST_RST_CAUSE,Last Reset Cause Register"
|
|
bitfld.long 0x00 5. "wdt_rst,WDT Reset" "0: reset cause is not watchdog timer,1: reset cause is watchdog timer"
|
|
bitfld.long 0x00 4. "cm4_lockup,CM3 Lockup" "0: reset cause is not lockup,1: reset cause is lockup"
|
|
newline
|
|
bitfld.long 0x00 3. "cm4_sysresetreq,CM3 System software reset request" "0: reset cause is not system software reset..,1: reset cause is system software reset request"
|
|
bitfld.long 0x00 2. "brownout_av18,AV18 power brownout" "0: AV18 power brownout not detected,1: AV18 power brownout detected"
|
|
newline
|
|
bitfld.long 0x00 1. "brownout_v12,AV12 power brownout" "0: AV12 power brownout not detected,1: AV12 power brownout detected"
|
|
bitfld.long 0x00 0. "brownout_vbat,VBAT power brownout" "0: VBAT power brownout not detected,1: VBAT power brownout detected"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LAST_RST_CLR,Last Reset Cause Clear Register"
|
|
bitfld.long 0x00 5. "wdt_rst_clr,Clear watchdog timer reset request" "0,1"
|
|
bitfld.long 0x00 4. "cm4_lockup_clr,Clear lockup request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "cm4_sysresetreq_clr,Clear system reset request" "0,1"
|
|
bitfld.long 0x00 2. "brownout_av18_clr,Brownout V18 Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "brownout_v12_clr,Brownout V12 Clear" "0,1"
|
|
bitfld.long 0x00 0. "brownout_vbat_clr,Brownout VBAT Clear" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "WAKE_SRC_CLR,Wake up source clear register"
|
|
bitfld.long 0x00 4. "clr_comp_int,Clear PMIP comp interrupt request" "0,1"
|
|
bitfld.long 0x00 3. "clr_rtc_int,Clear RTC interrupt request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "clr_wl_int,Clear WL interrupt request" "0,1"
|
|
bitfld.long 0x00 1. "clr_pin1_int,Clear Pin1 interrupt request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "clr_pin0_int,Clear Pin0 interrupt request" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PWR_MODE_STATUS,Power mode status register"
|
|
bitfld.long 0x00 0.--1. "pwr_mode_status,Power mode status" "0: reset the power system,1: do not reset the power system,?..."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CLK_SRC,Clock source selection register"
|
|
bitfld.long 0x00 0.--1. "sys_clk_sel,System Clock Select" "0: PLL 128 MHz clock,1: RC 32 MHz clock,2: XTAL 32 MHz clock,3: RC 32 MHz clock"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "WAKEUP_STATUS,Wakeup status register"
|
|
bitfld.long 0x00 4. "pmip_comp_wakeup_status,pmip_comp wakeup status" "0,1"
|
|
bitfld.long 0x00 3. "rtc_wakeup_status,RTC wakeup status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "wlint_wakeup_status,WLAN interrupt wakeup status" "0,1"
|
|
bitfld.long 0x00 1. "pin1_wakeup_status,External Pin1 wakeup status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "pin0_wakeup_status,External Pin0 wakeup status" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PMIP_BRN_INT_SEL,PMIP Brown Interrupt Select"
|
|
bitfld.long 0x00 0. "pmip_brn_int_sel,PMIP Brownout Interrupt Select" "0: generate an interrupt when VBAT brownout,1: reset chip when VBAT brownout"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "CLK_RDY,Clock ready register"
|
|
bitfld.long 0x00 6. "xtal32m_clk_rdy,XTAL32M Clock Ready" "0,1"
|
|
bitfld.long 0x00 4. "pll_audio_rdy,PLL audio ready" "0: PLL audio clock not ready for use,1: PLL audio clock ready for use"
|
|
newline
|
|
bitfld.long 0x00 3. "x32k_rdy,XTAL 32k Ready" "0: XTAL 32k clock not ready for use,1: XTAL 32k clock ready for use"
|
|
bitfld.long 0x00 2. "rc32m_rdy,RC 32M Ready" "0: RC 32M clock not ready for use,1: RC 32M clock ready for use"
|
|
newline
|
|
bitfld.long 0x00 0. "pll_clk_rdy,PLL clock ready" "0: PLL clock not ready for use,1: PLL clock ready for use"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RC32M_CTRL,RC 32M control Register"
|
|
bitfld.long 0x00 1. "cal_allow,Allow calibration command from PMU" "0,1"
|
|
rbitfld.long 0x00 0. "cal_in_progress,Asserts high when calibration in progress" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SFLL_CTRL1,SFLL control register 1"
|
|
bitfld.long 0x00 31. "reg_pll_pu_int,PLL PU Int" "0,1"
|
|
hexmask.long.byte 0x00 23.--30. 1. "sfll_reserve_in,SFLL Reserved Input"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "sfll_div_sel,Post divider" "0: divide by 1 (bypass),1: divide by 2,2: divide by 4,3: divide by 8"
|
|
bitfld.long 0x00 9.--11. "sfll_test_ana,DC points Testing control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "sfll_refdiv,Reference clock divider select"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ANA_GRP_CTRL0,Analog group control register"
|
|
bitfld.long 0x00 2. "PU,Power-up signal for whole block" "0,1"
|
|
bitfld.long 0x00 1. "PU_XTAL,Power-up signal for XTAL circuit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PU_OSC,Power-up signal for OSC circuit" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SFLL_CTRL0,SFLL control register 2"
|
|
rbitfld.long 0x00 26. "sfll_lock,SFLL Lock" "0: PLL module unlocked,1: PLL module locked"
|
|
bitfld.long 0x00 25. "sfll_refclk_sel,Reference clock source select" "0: RC 32M,1: XTAL 32M from WLAN"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "sfll_kvco,Select VCO Running Range Default value for output clock=200M" "0,1,2,3"
|
|
hexmask.long.word 0x00 7.--15. 1. "sfll_fbdiv,Feedback clock divider select"
|
|
newline
|
|
bitfld.long 0x00 0. "sfll_pu,Power-up signal for the Flock" "0: power down,1: power up"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PWR_CFG,Power configuration register"
|
|
hexmask.long.byte 0x00 4.--10. 1. "PM3_RET_MEM_CFG,Retention memory enable register in PM3 mode"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "PWR_STAT,Power status register"
|
|
bitfld.long 0x00 7. "av18_rdy,av18_rdy" "0,1"
|
|
bitfld.long 0x00 1. "v12_ldo_rdy,v12_ldo_rdy" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "WF_OPT0,WF OPT Power-Saving register 0"
|
|
bitfld.long 0x00 2. "mem_ctrl,sram_memory control" "0: normal mode,1: limit SRAM to 192K"
|
|
bitfld.long 0x00 1. "max_freq_ctrl,maximum frequency control" "0: normal mode,1: maximum frequency is 125 MHz"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "WF_OPT1,WF OPT Power-Saving register 1"
|
|
bitfld.long 0x00 2.--3. "spare,Spare" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PMIP_BRN_CFG,Brownout configuration register"
|
|
bitfld.long 0x00 3. "brndet_av18_rst_en,Brownout AV18 Reset Enable" "0,1"
|
|
bitfld.long 0x00 1. "brndet_vbat_rst_en,Brownout VBAT Reset Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "brndet_v12_rst_en,Brownout AV12 Reset Enable" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "AUPLL_LOCK,AUPLL lock status register"
|
|
hexmask.long 0x00 3.--31. 1. "Reserved_out_1,Reserved Out 1"
|
|
rbitfld.long 0x00 2. "aupll_lock,AUPLL Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "Reserved_out_0,Reserved Out 0" "0,1,2,3"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "ANA_GRP_CTRL1,BG control register"
|
|
bitfld.long 0x00 10. "BYPASS,XTAL OSC bypass control signal" "0,1"
|
|
bitfld.long 0x00 7.--9. "TEST,Analog test control bits" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "BG_SEL,Selects the Bandgap Voltage" "0,1,2,3"
|
|
bitfld.long 0x00 4. "R_ORIEN_SEL,RPP resister orientation selection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "GAINX2,OSC gain control" "0,1"
|
|
bitfld.long 0x00 0.--2. "bg_ctrl,bandgap control" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PMIP_PWR_CONFIG,Power Configuration register"
|
|
bitfld.long 0x00 2. "av18_ext,AV18 External" "0,1"
|
|
bitfld.long 0x00 0.--1. "status_del_sel,Control counter in delay for rdy/rdy<0> handshaking" "0,1,2,3"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PMIP_TEST,PMIP test register"
|
|
bitfld.long 0x00 9. "pmu_pmip_test_en,Enable test mux" "0,1"
|
|
bitfld.long 0x00 5.--8. "pmu_pmip_test,Test mux input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4. "pmip_test_en,PMIP Test Enable" "0: disable PMIP analog test mux,1: enable PMIP analog test mux"
|
|
bitfld.long 0x00 0.--3. "pmip_test,Test mux output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "AUPLL_CTRL0,Audio PLL control register"
|
|
bitfld.long 0x00 20. "PU,Power-up signal for the PLL" "0,1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "FRACT,Fractional Part of PLL feedback divider"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PERI_CLK_EN,Peripheral clock enable register"
|
|
bitfld.long 0x00 31. "sdio_ahb_clk_en,AHB SDIO clock enable" "0,1"
|
|
bitfld.long 0x00 30. "usbc_ahb_clk_en,AHB USBC clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "usbc_clk_en,USBC clock enable" "0,1"
|
|
bitfld.long 0x00 26. "adc_clk_en,ADC clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "sdio_clk_en,SDIO clock enable" "0,1"
|
|
bitfld.long 0x00 23. "wdt_clk_en,WDT clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "gpt3_clk_en,GPT3 clock enable" "0,1"
|
|
bitfld.long 0x00 21. "gpt2_clk_en,GPT2 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "i2c2_clk_en,I2C2 clock enable" "0,1"
|
|
bitfld.long 0x00 19. "i2c1_clk_en,I2C1 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "ssp2_clk_en,SSP2 clock enable" "0,1"
|
|
bitfld.long 0x00 16. "uart3_clk_en,UART3 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "uart2_clk_en,UART2 clock enable" "0,1"
|
|
bitfld.long 0x00 11. "gpt1_clk_en,GPT1 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "gpt0_clk_en,GPT0 clock enable" "0,1"
|
|
bitfld.long 0x00 9. "ssp1_clk_en,SSP1 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ssp0_clk_en,SSP0 clock enable" "0,1"
|
|
bitfld.long 0x00 7. "i2c0_clk_en,I2C0 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "uart1_clk_en,UART1 clock enable" "0,1"
|
|
bitfld.long 0x00 5. "uart0_clk_en,UART0 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "gpio_clk_en,GPIO clock enable" "0,1"
|
|
bitfld.long 0x00 1. "qspi0_clk_en,QSPI0 clock enable" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "UART_FAST_CLK_DIV,UART fast clock div register"
|
|
hexmask.long.word 0x00 11.--23. 1. "nominator,13-Bit nominator for fraction divider"
|
|
hexmask.long.word 0x00 0.--10. 1. "denominator,11-Bit denominator for fractional divider"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "UART_SLOW_CLK_DIV,UART slow clock div register"
|
|
hexmask.long.word 0x00 11.--23. 1. "nominator,13-Bit nominator for fraction divider"
|
|
hexmask.long.word 0x00 0.--10. 1. "denominator,11-Bit denominator for fractional divider"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "UART_CLK_SEL,UART clock select register"
|
|
bitfld.long 0x00 3. "uart3_clk_sel,UART3 APB1 UART clock select" "0: no description available,1: no description available"
|
|
bitfld.long 0x00 2. "uart2_clk_sel,UART2 APB1 UART clock select" "0: no description available,1: no description available"
|
|
newline
|
|
bitfld.long 0x00 1. "uart1_clk_sel,UART1 APB0 UART clock select" "0: no description available,1: no description available"
|
|
bitfld.long 0x00 0. "uart0_clk_sel,UART0 APB0 UART clock select" "0: no description available,1: no description available"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "MCU_CORE_CLK_DIV,MCU CORE clock divider ratio register"
|
|
bitfld.long 0x00 0.--5. "fclk_div,FCLK divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PERI0_CLK_DIV,Peripheral0 clock divider ratio register"
|
|
bitfld.long 0x00 16.--19. "sdio_clk_div,SDIO clock divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--14. "ssp2_clk_div,SSP2 APB1 clock divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "ssp1_clk_div,SSP1 APB0 clock divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "ssp0_clk_div,SSP0 APB0 clock divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PERI1_CLK_DIV,Peripheral1 clock divider ratio register"
|
|
bitfld.long 0x00 8.--10. "qspi0_clk_div,QSPI0 APB0 clock divisor" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "flash_clk_div,Flash QSPI clock divisor" "0,1,2,3,4,5,6,7"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PERI2_CLK_DIV,Peripheral2 Clock Divider Ratio Register"
|
|
bitfld.long 0x00 28. "wdt_clk_div_2_2,See bit[25:24]" "0,1"
|
|
bitfld.long 0x00 24.--25. "wdt_clk_div_1_0,WDT clock divisor" "0: (divisor = 1),?..."
|
|
newline
|
|
bitfld.long 0x00 20.--21. "i2c_clk_div,i2c function clock divisor divisor = i2c_clk_div" "0: (divisor = 1),?..."
|
|
bitfld.long 0x00 12.--14. "gpt3_clk_div_5_3,See bit[10:8]" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "gpt3_clk_div_2_0,GPT3 clock divisor[2:0]" "0: (divisor = 1),?..."
|
|
bitfld.long 0x00 4.--6. "wdt_clk_div_5_3,See bit[25:24]" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "gpt_sample_clk_div,GPT sample clock divisor" "0,1,2,3,4,5,6,7"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "GAU_CLK_SEL,select signal for GAU MCLK register"
|
|
bitfld.long 0x00 2. "gau_sw_gate,gate signal for gau mclk" "0,1"
|
|
bitfld.long 0x00 0.--1. "gau_clk_sel,select signal for gau mclk" "0: 192M PLL clock,1: RC32 MHz clock,2: XTAL32 MHz clock,3: AUDIO PLL clock"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "LOW_PWR_CTRL,low power control in PM3/PM4 mode register"
|
|
bitfld.long 0x00 4. "RC_OSC_SEL,RC32k and XTAL32k output clock selection" "0,1"
|
|
bitfld.long 0x00 3. "SLP_CTRL,32k output clock enable signal" "0: PU enabled while PD disabled,1: PU disabled while PD enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "cache_line_flush,flushes the cache" "0,1"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "IO_PAD_PWR_CFG,I/O Pad Power configuration register"
|
|
bitfld.long 0x00 19. "GPIO_AON_PDB,Always on PAD group power down mode control" "0: power down mode,1: normal mode"
|
|
bitfld.long 0x00 18. "GPIO_AON_V18,Always on PAD group voltage select signal" "0: 2.5V or 3.3V,1: 1.8V"
|
|
newline
|
|
bitfld.long 0x00 17. "GPIO_AON_V25,Always on PAD group voltage select signal" "0: 3.3V,1: 2.5V"
|
|
bitfld.long 0x00 15. "GPIO3_LOW_VDDB,GPIO3 PAD group power switch signal" "0: Power off,1: Power on"
|
|
newline
|
|
bitfld.long 0x00 14. "GPIO2_LOW_VDDB,GPIO2 PAD group power switch signal" "0: Power off,1: Power on"
|
|
bitfld.long 0x00 13. "GPIO1_LOW_VDDB,GPIO1 PAD group power switch signal" "0: Power off,1: Power on"
|
|
newline
|
|
bitfld.long 0x00 12. "GPIO0_LOW_VDDB,GPIO0 PAD group power switch signal" "0: Power off,1: Power on"
|
|
bitfld.long 0x00 11. "GPIO3_V18,GPIO3 PAD group voltage select signal" "0: 2.5V or 3.3V,1: 1.8V"
|
|
newline
|
|
bitfld.long 0x00 10. "GPIO2_V18,GPIO2 PAD group voltage select signal" "0: 2.5V or 3.3V,1: 1.8V"
|
|
bitfld.long 0x00 9. "GPIO1_V18,GPIO1 PAD group voltage select signal" "0: 2.5V or 3.3V,1: 1.8V"
|
|
newline
|
|
bitfld.long 0x00 8. "GPIO0_V18,GPIO0 PAD group voltage select signal" "0: 2.5V or 3.3V,1: 1.8V"
|
|
bitfld.long 0x00 7. "GPIO3_V25,GPIO3 PAD group voltage select signal" "0: 3.3V,1: 2.5V"
|
|
newline
|
|
bitfld.long 0x00 6. "GPIO2_V25,GPIO2 PAD group voltage select signal" "0: 3.3V,1: 2.5V"
|
|
bitfld.long 0x00 5. "GPIO1_V25,GPIO1 PAD group voltage select signal" "0: 3.3V,1: 2.5V"
|
|
newline
|
|
bitfld.long 0x00 4. "GPIO0_V25,GPIO0 PAD group voltage select signal" "0: 3.3V,1: 2.5V"
|
|
bitfld.long 0x00 3. "GPIO3_PDB,GPIO3 PAD group power switch signal" "0: Power off,1: Power on"
|
|
newline
|
|
bitfld.long 0x00 2. "GPIO2_PDB,GPIO2 PAD group power switch signal" "0: Power off,1: Power on"
|
|
bitfld.long 0x00 1. "GPIO1_PDB,GPIO1 PAD group power switch signal" "0: Power off,1: Power on"
|
|
newline
|
|
bitfld.long 0x00 0. "GPIO0_PDB,GPIO0 PAD group power switch signal" "0: Power off,1: Power on"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "EXT_SEL_REG0,extra interrupt select register 0"
|
|
bitfld.long 0x00 24. "SEL_58,select signal for extra interrupt 58" "0: from GPIO_48,1: from GPIO_49"
|
|
bitfld.long 0x00 23. "SEL_57,select signal for extra interrupt 57" "0: from GPIO_46,1: from GPIO_47"
|
|
newline
|
|
bitfld.long 0x00 22. "SEL_56,select signal for extra interrupt 56" "0: from GPIO_44,1: from GPIO_45"
|
|
bitfld.long 0x00 21. "SEL_55,select signal for extra interrupt 55" "0: from GPIO_42,1: from GPIO_43"
|
|
newline
|
|
bitfld.long 0x00 20. "SEL_54,select signal for extra interrupt 54" "0: from GPIO_40,1: from GPIO_41"
|
|
bitfld.long 0x00 19. "SEL_53,select signal for extra interrupt 53" "0: from GPIO_38,1: from GPIO_39"
|
|
newline
|
|
bitfld.long 0x00 18. "SEL_52,select signal for extra interrupt 52" "0: from GPIO_36,1: from GPIO_37"
|
|
bitfld.long 0x00 17. "SEL_51,select signal for extra interrupt 51" "0: from GPIO_34,1: from GPIO_35"
|
|
newline
|
|
bitfld.long 0x00 16. "SEL_50,select signal for extra interrupt 50" "0: from GPIO_32,1: from GPIO_33"
|
|
bitfld.long 0x00 15. "SEL_49,select signal for extra interrupt 49" "0: from GPIO_30,1: from GPIO_31"
|
|
newline
|
|
bitfld.long 0x00 14. "SEL_48,select signal for extra interrupt 48" "0: from GPIO_28,1: from GPIO_29"
|
|
bitfld.long 0x00 13. "SEL_47,select signal for extra interrupt 47" "0: from GPIO_26,1: from GPIO_27"
|
|
newline
|
|
bitfld.long 0x00 12. "SEL_46,select signal for extra interrupt 46" "0: from GPIO_24,1: from GPIO_25"
|
|
bitfld.long 0x00 11. "SEL_45,select signal for extra interrupt 45" "0: from GPIO_22,1: from GPIO_23"
|
|
newline
|
|
bitfld.long 0x00 10. "SEL_44,select signal for extra interrupt 44" "0: from GPIO_20,1: from GPIO_21"
|
|
bitfld.long 0x00 9. "SEL_43,select signal for extra interrupt 43" "0: from GPIO_18,1: from GPIO_19"
|
|
newline
|
|
bitfld.long 0x00 8. "SEL_42,select signal for extra interrupt 42" "0: from GPIO_16,1: from GPIO_17"
|
|
bitfld.long 0x00 7. "SEL_41,select signal for extra interrupt 41" "0: from GPIO_14,1: from GPIO_15"
|
|
newline
|
|
bitfld.long 0x00 6. "SEL_40,select signal for extra interrupt 40" "0: from GPIO_12,1: from GPIO_13"
|
|
bitfld.long 0x00 5. "SEL_39,select signal for extra interrupt 39" "0: from GPIO_10,1: from GPIO_11"
|
|
newline
|
|
bitfld.long 0x00 4. "SEL_38,select signal for extra interrupt 38" "0: from GPIO_8,1: from GPIO_9"
|
|
bitfld.long 0x00 3. "SEL_37,select signal for extra interrupt 37" "0: from GPIO_6,1: from GPIO_7"
|
|
newline
|
|
bitfld.long 0x00 2. "SEL_36,select signal for extra interrupt 36" "0: from GPIO_4,1: from GPIO_5"
|
|
bitfld.long 0x00 1. "SEL_35,select signal for extra interrupt 35" "0: from GPIO_2,1: from GPIO_3"
|
|
newline
|
|
bitfld.long 0x00 0. "SEL_34,select signal for extra interrupt 34" "0: from GPIO_0,1: from GPIO_1"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "AUPLL_CTRL1,USB and audio PLL control register"
|
|
bitfld.long 0x00 29. "EN_VCOX2,Enable or Disable VCOCLK_X2" "0,1"
|
|
bitfld.long 0x00 22.--23. "DIG_TSTPNT,Digital test select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "ANA_TSTPNT,Analog test select" "0,1,2,3"
|
|
bitfld.long 0x00 14.--19. "DIV_FBCCLK,FBC divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 10.--13. "DIV_MCLK,MCLK divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7.--9. "DIV_OCLK_MODULO,Output clock divider control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "DIV_OCLK_PATTERN,Output clock divider control" "0,1,2,3"
|
|
bitfld.long 0x00 4. "ENA_DITHER,ENA Dither" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "ICP,Charge-Pump current control bits" "0,1,2,3"
|
|
bitfld.long 0x00 1. "REFCLK_SEL,Reference clock selection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD_OVPROT,Enable Over-Voltage protection on VCO" "0,1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "GAU_CTRL,GAU Control Register"
|
|
bitfld.long 0x00 4. "gau_bg_mclk_en,gau_bg module main clock enable signal" "0: do not enable,1: no description available"
|
|
bitfld.long 0x00 3. "gau_gpadc0_mclk_en,gau_gpadc0 module main clock enable signal" "0: do not enable,1: no description available"
|
|
newline
|
|
bitfld.long 0x00 1. "gau_gpdac_mclk_en,gau_gpdac module main clock enable signal" "0: do not enable,1: no description available"
|
|
bitfld.long 0x00 0. "gau_acomp_mclk_en,gau_acomp module main clock enable signal" "0: do not enable,1: no description available"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "RC32K_CTRL0,RC32k Control 0 Register"
|
|
bitfld.long 0x00 15. "rc32k_pd,Power down 32k oscillator" "0,1"
|
|
bitfld.long 0x00 14. "rc32k_cal_en,Enable calibration of 32k oscillator" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--13. 1. "rc32k_code_fr_ext,External code In for frequency setting"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "RC32K_CTRL1,RC32k Control 1 Register"
|
|
bitfld.long 0x00 23. "rc32k_ext_code_en,Allow external code in to go into the ckt" "0,1"
|
|
bitfld.long 0x00 22. "rc32k_refclk32k,RC32k Reference Clock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "rc32k_cal_div,Divider for the clock step during calibration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "rc32k_allow_cal,Allow calibration to be performed (monitor system clock)" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 4.--17. 1. "rc32k_code_fr_cal,After calibration hold calibrated code"
|
|
rbitfld.long 0x00 3. "rc32k_cal_inprogress,Asserts high when calibration is in progress" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 2. "rc32k,RC32k" "0,1"
|
|
rbitfld.long 0x00 1. "rc32k_rdy,Asserts high when 32k clock is ready upon pwrup" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "rc32k_cal_done,Asserts high when calibration is done" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "XTAL32K_CTRL,XTAL32k Control Register"
|
|
bitfld.long 0x00 13.--14. "x32k_dly_sel,32k Delay Select" "0,1,2,3"
|
|
bitfld.long 0x00 12. "x32k_en,Enable 32k oscillator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "x32k_ext_osc_en,Enable external oscillator mode for outside clock" "0,1"
|
|
bitfld.long 0x00 9.--10. "x32k_vddxo_cntl,Control VDDXO level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "x32k_tmode,Test mode enabling for 32k xtal ckt" "0,1,2,3"
|
|
bitfld.long 0x00 4. "x32k_test_en,Test enabling for 32k xtal ckt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "x32k_stup_assist,Use startup assist ckt for 32 kHz xosc" "0,1,2,3"
|
|
rbitfld.long 0x00 1. "xclk32k,xclk32k" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "x32k_rdy,Assert high when ready" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "PMIP_CMP_CTRL,PMIP Comparator Control Register"
|
|
bitfld.long 0x00 9. "gau_ref_en,CAU Reference Enable" "0,1"
|
|
bitfld.long 0x00 7.--8. "comp_hyst,Control of comparator hysteresis" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6. "comp_en,Enable AON domain comparator" "0,1"
|
|
bitfld.long 0x00 5. "comp_diff_en,Enable Differential mode for AON comparator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--4. "comp_ref_sel,Select comparator reference for single-ended mode" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 1. "comp_rdy,Ready to use AON domain comparator" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "comp_out,Output of AON domain comparator" "0,1"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PMIP_BRNDET_AV18,PMIP Brownout AV18 Register"
|
|
bitfld.long 0x00 18.--19. "del_av18_hyst,Del av18 Hysteresis" "0,1,2,3"
|
|
bitfld.long 0x00 17. "brndet_av18_en,Enable av18 brown-out detector" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--16. "brntrig_av18_cntl,Control trigger voltage of av18 brndet" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--13. "brnhyst_av18_cntl,Control of av18 brown-out detector hysteresis" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "brndet_av18_filt,Select filtering level for av18 pulse to av18 brndet" "0,1,2,3"
|
|
rbitfld.long 0x00 9. "brndet_av18_rdy,Assert high if av18 brnout is rdy --> out can be taken" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8. "brndet_av18_out,Assert high if av18 brnout happened" "0,1"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "PMIP_BRNDET_VBAT,PMIP Brownout VBAT Register"
|
|
bitfld.long 0x00 19. "brndet_vbat_en,Enable vbat brown-out detector" "0,1"
|
|
bitfld.long 0x00 16.--18. "brntrig_vbat_cntl,Control trigger voltage of vbat brndet" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "brnhyst_vbat_cntl,Control of vbat brown-out detector hysteresis" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "brndet_vbat_filt,Select filtering level for vbat pulse to vbat brndet" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 11. "brndet_vbat_rdy,Assert high if vbat brnout is rdy--> out can be taken" "0,1"
|
|
rbitfld.long 0x00 10. "brndet_vbat_out,Assert high if vbat brnout happened" "0,1"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "PMIP_BRNDET_V12,PMIP Brownout V12 Register"
|
|
bitfld.long 0x00 14. "brndet_v12_en,Enable v12 brown-out detector" "0,1"
|
|
bitfld.long 0x00 11.--13. "brntrig_v12_cntl,Control trigger voltage of v12 brndet" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "brnhyst_v12_cntl,Control of v12 brown-out detector hysteresis" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "brndet_v12_filt,Select filtering level for v12 pulse to v12 brndet" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 6. "brndet_v12_rdy,Assert high if v12 brnout is rdy--> out can be taken" "0,1"
|
|
rbitfld.long 0x00 5. "brndet_v12_out,Assert high if v12 brnout happened" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--4. "ldo_aon_v12_sel,Select output voltage of ldo_aon_v12" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "ldo_aon_v12_hyst,Control of ldo_aon_v12 hysteresis" "0,1,2,3"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PMIP_LDO_CTRL,PMIP LDO Control Register"
|
|
bitfld.long 0x00 11. "ldo_av18_en,Enable ldo_av18" "0,1"
|
|
bitfld.long 0x00 5. "ldo_v12_en,Enable ldo_v12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--4. "ldo_v12_vout_sel,Select output voltage for v12" "0,1,2,3,4,5,6,7"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "PERI_CLK_SRC,PERI Clock Source Register"
|
|
bitfld.long 0x00 11. "gpt3_int_sel,GPT3 Int Select" "0,1"
|
|
bitfld.long 0x00 10. "gpt2_int_sel,GPT2 Int Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "gpt1_int_sel,GPT1 Int Select" "0,1"
|
|
bitfld.long 0x00 8. "gpt0_int_sel,GPT0 Int Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "gpt_int_sel3,GPT Int Select 3" "0,1"
|
|
bitfld.long 0x00 6. "gpt_int_sel2,GPT Int Select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "gpt_int_sel1,GPT Int Select 1" "0,1"
|
|
bitfld.long 0x00 4. "gpt_int_sel0,GPT Int Select 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ssp2_audio_sel,SSP2 Audio Select" "0: divided by system clock,1: audio PLL clock"
|
|
bitfld.long 0x00 1. "ssp1_audio_sel,SSP1 Audio Select" "0: divided by system clock,1: audio PLL clock"
|
|
newline
|
|
bitfld.long 0x00 0. "ssp0_audio_sel,SSP0 Audio Select" "0: divided by system clock,1: audio PLL clock"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "PMIP_RSVD,Unused Register"
|
|
rbitfld.long 0x00 10.--15. "reserve_out,Unused" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "reserve_in,Unused"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "GPT0_CTRL,GPT0 Control Register"
|
|
bitfld.long 0x00 9.--10. "gpt0_clk_sel0,select signal for mux before frequency divisor" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "gpt0_clk_sel1,select signal for mux after frequency divisor" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6. "gpt0_freq_change,frequency change enable" "0,1"
|
|
bitfld.long 0x00 0.--5. "gpt0_clk_div,clock divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "GPT1_CTRL,GPT1 Control Register"
|
|
bitfld.long 0x00 9.--10. "gpt1_clk_sel0,select signal for mux before frequency divisor" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "gpt1_clk_sel1,select signal for mux after frequency divisor" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6. "gpt1_freq_change,frequency change enable" "0,1"
|
|
bitfld.long 0x00 0.--5. "gpt1_clk_div,clock divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "GPT2_CTRL,GPT2 Control Register"
|
|
bitfld.long 0x00 9.--10. "gpt2_clk_sel0,select signal for mux before frequency divisor" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "gpt2_clk_sel1,select signal for mux after frequency divisor" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6. "gpt2_freq_change,frequency change enable" "0,1"
|
|
bitfld.long 0x00 0.--5. "gpt2_clk_div,clock divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "GPT3_CTRL,GPT3 Control Register"
|
|
bitfld.long 0x00 9.--10. "gpt3_clk_sel0,select signal for mux before frequency divisor" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "gpt3_clk_sel1,select signal for mux after frequency divisor" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6. "gpt3_freq_change,frequency change enable" "0,1"
|
|
bitfld.long 0x00 0.--5. "gpt3_clk_div,clock divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "WAKEUP_EDGE_DETECT,Wakeup Edge Detect Register"
|
|
bitfld.long 0x00 1. "wakeup1,external pin1 wakeup_edge_detect" "0,1"
|
|
bitfld.long 0x00 0. "wakeup0,external pin0 wakeup_edge_detect" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "AON_CLK_CTRL,AON Clock Control Register"
|
|
bitfld.long 0x00 9.--10. "apb1_clk_div,APB1 clock divisor" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "apb0_clk_div,APB0 clock divisor" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6. "dma_clk_gate_en,DMA Clock Gate Enable" "0,1"
|
|
bitfld.long 0x00 5. "rtc_int_sel,RTC Interrupt Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "rtc_clk_en,RTC clock enable" "0,1"
|
|
bitfld.long 0x00 0.--3. "pmu_clk_div,PMU clock divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "PERI3_CTRL,PERI3 Control Register"
|
|
bitfld.long 0x00 18. "rc32m_gate,RC32M reference clock gate" "0,1"
|
|
bitfld.long 0x00 13.--17. "rc32m_div,RC32M clock div ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "gau_div,GAU clock div ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "wakeup_mask,Wakeup Mask Interrupt Register"
|
|
bitfld.long 0x00 7. "wl_wakeup_mask,WLAN Wakeup Mask" "0: mask WLAN wakeup interrupt,1: unmask WLAN wakeup interrupt"
|
|
bitfld.long 0x00 6. "pmip_comp_wakeup_mask,PMIP Comparator Wakeup Mask" "0: mask PMIP comparator wakeup interrupt,1: unmask PMIP comparator wakeup interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. "rtc_wakeup_mask,RTC Wakeup Mask" "0: mask RTC wakeup interrupt,1: unmask RTC wakeup interrupt"
|
|
bitfld.long 0x00 4. "pin1_wakeup_mask,Pin1 Wakeup Mask" "0: mask pin1 wakeup interrupt,1: unmask pin1 wakeup interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. "pin0_wakeup_mask,Pin0 Wakeup Mask" "0: mask pin0 wakeup interrupt,1: unmask pin0 wakeup interrupt"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "wlan_ctrl,WLAN Control Register"
|
|
hexmask.long.word 0x00 7.--17. 1. "wl_pd_del_cfg,count for 30ms"
|
|
rbitfld.long 0x00 6. "refclk_usb_rdy,WLAN reference clock ready" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 5. "refclk_aud_rdy,WLAN reference clock ready" "0,1"
|
|
rbitfld.long 0x00 4. "refclk_sys_rdy,WLAN reference clock ready" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "refclk_usb_req,WLAN USB reference clock request" "0,1"
|
|
bitfld.long 0x00 2. "refclk_aud_req,WLAN AUD reference clock request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "refclk_sys_req,WLAN SYS reference clock request" "0,1"
|
|
bitfld.long 0x00 0. "pd,WLAN power down function" "0,1"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "wlan_ctrl1,WLAN Control 1 Register"
|
|
bitfld.long 0x00 11. "MCI_WL_WAKEUP,MCI_WL_WAKEUP" "0,1"
|
|
tree.end
|
|
tree "QSPI"
|
|
base ad:0x46010000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "Cntl,Serial Interface Control Register"
|
|
rbitfld.long 0x00 11. "WFIFO_OVERFLW,Write FIFO Overflow" "0: Write FIFO is not overflowed,1: Write FIFO is overflowed"
|
|
rbitfld.long 0x00 10. "WFIFO_UNDRFLW,Write FIFO Underflow" "0: Write FIFO is not underflowed,1: Write FIFO is underflowed"
|
|
newline
|
|
rbitfld.long 0x00 9. "RFIFO_OVRFLW,Read FIFO Overflow" "0: Read FIFO is not overflowed,1: Read FIFO is overflowed"
|
|
rbitfld.long 0x00 8. "RFIFO_UNDRFLW,Read FIFO Underflow" "0: Read FIFO is not underflowed,1: Read FIFO is underflowed"
|
|
newline
|
|
rbitfld.long 0x00 7. "WFIFO_FULL,Write FIFO Full" "0: Write FIFO is not fulled,1: Write FIFO is fulled"
|
|
rbitfld.long 0x00 6. "WFIFO_EMPTY,Write FIFO Empty" "0: Write FIFO is not emptied,1: Write FIFO is emptied"
|
|
newline
|
|
rbitfld.long 0x00 5. "RFIFO_FULL,Read FIFO Full" "0: Read FIFO is not fulled,1: Read FIFO is fulled"
|
|
rbitfld.long 0x00 4. "RFIFO_EMPTY,Read FIFO Empty" "0: Read FIFO is not emptied,1: Read FIFO is emptied"
|
|
newline
|
|
rbitfld.long 0x00 1. "XFER_RDY,Serial Interface Transfer Ready" "0: Serial Interface is currently transferring data,1: Serial Interface is ready for a new transfer"
|
|
bitfld.long 0x00 0. "SS_EN,Serial Select Enable" "0: Serial select is de-activated ss_n (serial..,1: Serial select is activated ss_n (serial.."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "Conf,Serial Interface Configuration Register"
|
|
bitfld.long 0x00 15. "XFER_START,Transfer Start" "0: Transfer has completed,1: Transfer has started"
|
|
bitfld.long 0x00 14. "XFER_STOP,Transfer Stop" "0: Continue current transfer,1: Stop current transfer"
|
|
newline
|
|
bitfld.long 0x00 13. "RW_EN,Read Write Enable" "0: Read data from the serial interface,1: Write data to the serial interface"
|
|
bitfld.long 0x00 12. "ADDR_PIN,Address Transfer Pin" "0: Use one serial interface pin,1: Use the number of pins as indicated in.."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DATA_PIN,Data Transfer Pin" "0: Use 1 serial interface pin (use in single mode),1: Use 2 serial interface pins (use in dual mode),2: Use 4 serial interface pins (use in quad mode),?..."
|
|
bitfld.long 0x00 9. "FIFO_FLUSH,Flush Read and Write FIFOs" "0: Read and Write FIFOs are not flushed,1: Read and Write FIFOs are flushed"
|
|
newline
|
|
bitfld.long 0x00 8. "CLK_POL,Serial Interface Clock Polarity" "0: Serial interface clock is low when inactive,1: Serial interface clock is high when inactive"
|
|
bitfld.long 0x00 7. "CLK_PHA,Serial Interface Clock Phase" "0: Data is latched at the rising edge of the..,1: Data is latched at the falling edge of the.."
|
|
newline
|
|
bitfld.long 0x00 5. "BYTE_LEN,Byte Length" "0: 1 byte,1: 4 bytes"
|
|
bitfld.long 0x00 0.--4. "CLK_PRESCALE,Serial Interface Clock Prescaler (from SPI clock)" "0: SPI clock/1,1: SPI clock/1,2: SPI clock/2,3: SPI clock/3,4: SPI clock/4,5: SPI clock/5,?,?,?,?,?,?,?,13: SPI clock/13,14: SPI clock/14,15: SPI clock/15,16: SPI clock/2,17: SPI clock/2,18: SPI clock/4,19: SPI clock/6,20: SPI clock/8,21: SPI clock/10,?,?,?,?,?,?,?,29: SPI clock/26,30: SPI clock/28,31: SPI clock/30"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "Dout,Serial Interface Data Out Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA_OUT,Serial Interface Data Out"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "Din,Serial Interface Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA_IN,Serial Interface Data In"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "Instr,Serial Interface Instruction Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "INSTR,Instruction"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "Addr,Serial Interface Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Serial Interface Address"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RdMode,Serial Interface Read Mode Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RMODE,Serial Interface Read Mode"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HdrCnt,Serial Interface Header Count Register"
|
|
bitfld.long 0x00 12.--13. "DUMMY_CNT,Dummy Count" "0: 0 byte,1: 1 byte,2: 2 bytes,3: 3 bytes"
|
|
bitfld.long 0x00 8.--9. "RM_CNT,Read Mode Count" "0: 0 byte,1: 1 byte,2: 2 bytes,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "ADDR_CNT,Address Count" "0: 0 byte,1: 1 byte,2: 2 bytes,3: 3 bytes,4: 4 bytes,?..."
|
|
bitfld.long 0x00 0.--1. "INSTR_CNT,Instruction Count" "0: 0 byte,1: 1 byte,2: 2 bytes,?..."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DInCnt,Serial Interface Data Input Count Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "DATA_IN_CNT,Serial Interface Data In Count"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "Timing,Serial Interface Timing Register"
|
|
bitfld.long 0x00 8.--9. "CLK_OUT_DLY,Serial Interface Clock Out Delay" "0: No delay,1: Add 0.2 ns delay,2: Add 0.4 ns delay,3: Add 0.6 ns delay"
|
|
bitfld.long 0x00 6. "CLK_CAPT_EDGE,Serial Interface Capture Clock Edge" "0: rising edge,1: falling edge"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "Conf2,Serial Interface Configuration 2 Register"
|
|
bitfld.long 0x00 12.--13. "DMA_WR_BURST,DMA Write Burst" "0: 1 data,1: 4 data,2: 8 data,?..."
|
|
bitfld.long 0x00 8.--9. "DMA_RD_BURST,DMA Read Burst" "0: 1 data,1: 4 data,2: 8 data,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "DMA_WR_EN,DMA Write Enable" "0: DMA write is disabled,1: DMA write is enabled"
|
|
bitfld.long 0x00 1. "DMA_RD_EN,DMA Read Enable" "0: DMA read is disabled,1: DMA read is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "SRST,Soft Reset" "0: Hardware is not in reset,1: Hardware is in reset"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "ISR,Serial Interface Interrupt Status Register"
|
|
bitfld.long 0x00 11. "WFIFO_OVRFLW_IS,Write FIFO Overflow Interrupt Status" "0: Write FIFO is not overflowed after masking,1: Write FIFO is overflowed after masking"
|
|
bitfld.long 0x00 10. "WFIFO_UNDRFLW_IS,Write FIFO Underflow Interrupt Status" "0: Write FIFO is not underflowed after masking,1: Write FIFO is underflowed after masking"
|
|
newline
|
|
bitfld.long 0x00 9. "RFIFO_OVRFLW_IS,Read FIFO Overflow Interrupt Status" "0: Read FIFO is not overflowed after masking,1: Read FIFO is overflowed after masking"
|
|
bitfld.long 0x00 8. "RFIFO_UNDRFLW_IS,Read FIFO Underflow Interrupt Status" "0: Read FIFO is not underflowed after masking,1: Read FIFO is underflowed after masking"
|
|
newline
|
|
bitfld.long 0x00 7. "WFIFO_FULL_IS,Write FIFO Full Interrupt Status" "0: Write FIFO is not fulled after masking,1: Write FIFO is fulled after masking"
|
|
bitfld.long 0x00 6. "WFIFO_EMPTY_IS,Write FIFO Empty Interrupt Status" "0: Write FIFO is not emptied after masking,1: Write FIFO is emptied after masking"
|
|
newline
|
|
bitfld.long 0x00 5. "RFIFO_FULL_IS,Read FIFO Full Interrupt Status" "0: Read FIFO is not fulled after masking,1: Read FIFO is fulled after masking"
|
|
bitfld.long 0x00 4. "RFIFO_EMPTY_IS,Read FIFO Empty Interrupt Status" "0: Read FIFO is not emptied after masking,1: Read FIFO is empty after masking"
|
|
newline
|
|
bitfld.long 0x00 3. "WFIFO_DMA_BURST_IS,Write FIFO DMA burst Interrupt Status" "0: Number of unused entries in the Write FIFO is..,1: Number of unused entries in the Write FIFO is.."
|
|
bitfld.long 0x00 2. "RFIFO_DMA_BURST_IS,Read FIFO DMA Burst Interrupt Status" "0: Number of available data in the Read FIFO is..,1: Number of available data in the Read FIFO is.."
|
|
newline
|
|
bitfld.long 0x00 1. "XFER_RDY_IS,Serial Interface Transfer Ready Interrupt Status" "0: Serial interface is currently transferring..,1: Serial interface is ready for a new transfer.."
|
|
bitfld.long 0x00 0. "XFER_DONE_IS,Transfer Done Interrupt Status" "0: Transfer has not completed after masking,1: Transfer has completed after masking"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IMR,Serial Interface Interrupt Mask Register"
|
|
bitfld.long 0x00 11. "WFIFO_OVRFLW_IM,Write FIFO Overflow Interrupt Mask" "0: Write FIFO overflow interrupt is not masked,1: Write FIFO overflow interrupt is masked"
|
|
bitfld.long 0x00 10. "WFIFO_UNDRFLW_IM,Write FIFO Underflow Interrupt Mask" "0: Write FIFO underflow interrupt is not masked,1: Write FIFO underflow interrupt is masked"
|
|
newline
|
|
bitfld.long 0x00 9. "RFIFO_OVRFLW_IM,Read FIFO Overflow Interrupt Mask" "0: Read FIFO overflow interrupt is not masked,1: Read FIFO overflow interrupt is masked"
|
|
bitfld.long 0x00 8. "RFIFO_UNDRFLW_IM,Read FIFO Underflow Interrupt Mask" "0: Read FIFO underflow interrupt is not masked,1: Read FIFO underflow interrupt is masked"
|
|
newline
|
|
bitfld.long 0x00 7. "WFIFO_FULL_IM,Write FIFO Full Interrupt Mask" "0: Write FIFO full interrupt is not masked,1: Write FIFO full interrupt is masked"
|
|
bitfld.long 0x00 6. "WFIFO_EMPTY_IM,Write FIFO Empty Interrupt Mask" "0: Write FIFO empty interrupt is not masked,1: Write FIFO empty interrupt is masked"
|
|
newline
|
|
bitfld.long 0x00 5. "RFIFO_FULL_IM,Read FIFO Full Interrupt Mask" "0: Read FIFO full interrupt is not masked,1: Read FIFO full interrupt is masked"
|
|
bitfld.long 0x00 4. "RFIFO_EMPTY_IM,Read FIFO Empty Interrupt Mask" "0: Read FIFO empty interrupt is not masked,1: Read FIFO empty interrupt is masked"
|
|
newline
|
|
bitfld.long 0x00 3. "WFIFO_DMA_BURST_IM,Write FIFO DMA Burst Interrupt Mask" "0: Write FIFO DMA burst interrupt is not masked,1: Write FIFO DMA burst interrupt is masked"
|
|
bitfld.long 0x00 2. "RFIFO_DMA_BURST_IM,Read FIFO DMA Burst Interrupt Mask" "0: Read FIFO DMA burst interrupt is not masked,1: Read FIFO DMA burst interrupt is masked"
|
|
newline
|
|
bitfld.long 0x00 1. "XFER_RDY_IM,Serial Interface Transfer Ready Mask" "0: Transfer ready interrupt is not masked,1: Transfer ready interrupt is masked"
|
|
bitfld.long 0x00 0. "XFER_DONE_IM,Transfer Done Interrupt Mask" "0: Transfer done interrupt is not masked,1: Transfer done interrupt is masked"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "IRSR,Serial Interface Interrupt Raw Status Register"
|
|
bitfld.long 0x00 11. "WFIFO_OVRFLW_IR,Write FIFO Overflow Interrupt Raw" "0: Write FIFO is not overflowed before masking,1: Write FIFO is overflowed before masking"
|
|
bitfld.long 0x00 10. "WFIFO_UNDRFLW_IR,Write FIFO Underflow Interrupt Raw" "0: Write FIFO is not underflowed before masking,1: Write FIFO is underflowed before masking"
|
|
newline
|
|
bitfld.long 0x00 9. "RFIFO_OVRFLW_IR,Read FIFO Overflow Interrupt Raw" "0: Read FIFO is not overflowed before masking,1: Read FIFO is overflowed before masking"
|
|
bitfld.long 0x00 8. "RFIFO_UNDRFLW_IR,Read FIFO Underflow Interrupt Raw" "0: Read FIFO is not underflowed before masking,1: Read FIFO is underflowed before masking"
|
|
newline
|
|
bitfld.long 0x00 7. "WFIFO_FULL_IR,Write FIFO Full Interrupt Raw" "0: Write FIFO is not fulled before masking,1: Write FIFO is fulled before masking"
|
|
bitfld.long 0x00 6. "WFIFO_EMPTY_IR,Write FIFO Empty Interrupt Raw" "0: Write FIFO is not emptied before masking,1: Write FIFO is emptied before masking"
|
|
newline
|
|
bitfld.long 0x00 5. "RFIFO_FULL_IR,Read FIFO Full Interrupt Raw" "0: Read FIFO is not fulled before masking,1: Read FIFO is fulled before masking"
|
|
bitfld.long 0x00 4. "RFIFO_EMPTY_IR,Read FIFO Empty Interrupt Raw" "0: Read FIFO is not emptied before masking,1: Read FIFO is empty before masking"
|
|
newline
|
|
bitfld.long 0x00 3. "WFIFO_DMA_BURST_IR,Write FIFO DMA Burst Interrupt Raw" "0: Number of unused entries in the Write FIFO is..,1: Number of unused entries in the Write FIFO is.."
|
|
bitfld.long 0x00 2. "RFIFO_DMA_BURST_IR,Read FIFO DMA Burst Interrupt Raw" "0: Number of available data in the Read FIFO is..,1: Number of available data in the Read FIFO is.."
|
|
newline
|
|
bitfld.long 0x00 1. "XFER_RDY_IR,Serial Interface Transfer Ready Raw" "0: Serial interface is currently transferring..,1: Serial interface is ready for a new transfer.."
|
|
bitfld.long 0x00 0. "XFER_DONE_IR,Transfer Done Interrupt Raw" "0: Transfer has not completed before masking,1: Transfer has completed before masking"
|
|
wgroup.long 0x38++0x03
|
|
line.long 0x00 "ISC,Serial Interface Interrupt Clear Register"
|
|
bitfld.long 0x00 0. "XFER_DONE_IC,Transfer Done Interrupt Clear" "0: Transfer done interrupt is not cleared,1: Transfer done interrupt is cleared"
|
|
tree.end
|
|
tree "RC32"
|
|
base ad:0x460A0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ctrl,Control Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. "code_fr_ext,External code input for calibration"
|
|
bitfld.long 0x00 3. "pd,Clock Power down" "0: Power up,1: Power down"
|
|
bitfld.long 0x00 2. "ext_code_en,Calibration code from external enable" "0: calibration code from internal,1: calibration code from external"
|
|
newline
|
|
bitfld.long 0x00 1. "cal_en,Calibration enable" "0: no description available,1: no description available"
|
|
bitfld.long 0x00 0. "en,Calibration reference clock enable" "0: no description available,1: no description available"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "status,Status Register"
|
|
hexmask.long.byte 0x00 2.--9. 1. "code_fr_cal,Calibration code"
|
|
bitfld.long 0x00 1. "cal_done,Calibration finish flag" "0: calibration not done,1: calibration done"
|
|
bitfld.long 0x00 0. "clk_rdy,Clock Ready" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "isr,Interrupt Status Register"
|
|
bitfld.long 0x00 1. "ckrdy_int,Clock Ready Interrupt" "0,1"
|
|
bitfld.long 0x00 0. "caldon_int,Calibration Done Interrupt" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "imr,Interrupt Mask Register"
|
|
bitfld.long 0x00 1. "ckrdy_int_msk,Clock Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 0. "caldon_int_msk,Calibration Done Interrupt Mask" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "irsr,Interrupt Raw Status Register"
|
|
bitfld.long 0x00 1. "ckrdy_int_raw,Clock Ready Interrupt Raw" "0,1"
|
|
bitfld.long 0x00 0. "caldon_int_raw,Calibration Done Interrupt Raw" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "icr,Interrupt Clear Register"
|
|
bitfld.long 0x00 1. "ckrdy_int_clr,Clock Ready Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 0. "caldon_int_clr,Calibration Done Interrupt Raw" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "clk,Clock Register"
|
|
bitfld.long 0x00 3. "soft_clk_rst,Soft reset for clock divider" "0: No action,1: no description available"
|
|
bitfld.long 0x00 2. "ref_sel,Reference clock frequency select" "0: Half-divided reference clock,1: Original reference clock"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "rst,Soft Reset Register"
|
|
bitfld.long 0x00 0. "soft_rst,Soft reset for module active high" "0: No action,1: no description available"
|
|
tree.end
|
|
tree "RTC"
|
|
base ad:0x48090000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNT_EN_REG,Counter Enable Register"
|
|
rbitfld.long 0x00 18. "STS_RESETN,System Reset Status" "0: Indicates that the system reset is still..,1: Indicates that the system reset is deasserted"
|
|
rbitfld.long 0x00 17. "CNT_RST_DONE,Counter Reset Done Status" "0: Indicates that the counter is still resetting,1: Indicates that the counter has been reset"
|
|
newline
|
|
rbitfld.long 0x00 16. "CNT_RUN,Counter Enabled Status" "0: Counter is disabled,1: Counter is enabled"
|
|
bitfld.long 0x00 2. "CNT_RESET,Counter Reset" "0: No action,1: Reset the counter (counter is reset to 0.."
|
|
newline
|
|
bitfld.long 0x00 1. "CNT_STOP,Counter Disable" "0: No action,1: Disable the counter (poll CNT_RUN for 0 to.."
|
|
bitfld.long 0x00 0. "CNT_START,Counter Enable" "0: No action,1: Enable the counter (poll CNT_RUN for 1 to.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "INT_RAW_REG,Interrupt Raw Register"
|
|
bitfld.long 0x00 16. "CNT_UPP_INT,Counter-Reach-Upper Interrupt Status" "0: Status cleared,1: Counter has reached UPP_VAL"
|
|
bitfld.long 0x00 15. "CNT_ALARM_INT,Counter-Reach-Alarm Interrupt Status" "0: Status cleared,1: Counter has reached ALARM_VAL"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "INT_REG,Interrupt Register"
|
|
bitfld.long 0x00 16. "CNT_UPP_INTR,Masked Signal of CNT_UPP_INT" "0,1"
|
|
bitfld.long 0x00 15. "CNT_ALARM_INTR,Masked Signal of CNT_ALARM_INT" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "INT_MSK_REG,Interrupt Mask Register"
|
|
bitfld.long 0x00 16. "CNT_UPP_MSK,CNT_UPP_INT Interrupt Mask" "0: Do not mask CNT_UPP_INT,1: Mask interrupt CNT_UPP_INT"
|
|
bitfld.long 0x00 15. "CNT_ALARM_MSK,CNT_ALARM_INT Interrupt Mask" "0: Do not mask CNT_ALARM_INT,1: Mask interrupt CNT_ALARM_INT"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CNT_CNTL_REG,Counter Control Register"
|
|
bitfld.long 0x00 8.--9. "CNT_UPDT_MOD,Counter Update Mode" "0: Update off,?,2: Auto-update (use when counter clock is at..,?..."
|
|
bitfld.long 0x00 4. "CNT_DBG_ACT,Counter Debug Mode Action Mask" "0: In debug mode stop the counters,1: In debug mode counters are not affected"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "CNT_VAL_REG,Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "CNT_VAL,Counter Value"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CNT_UPP_VAL_REG,Counter Upper Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "UPP_VAL,Counter Upper Value"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CNT_ALARM_VAL_REG,Counter Alarm Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "ALARM_VAL,Counter Alarm Value"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CLK_CNTL_REG,Clock control register"
|
|
bitfld.long 0x00 8.--11. "CLK_DIV,Clock Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "SDIO"
|
|
base ad:0x44002000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MMC4_SYSADDR,MMC4 System Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SYSADDR,SYSADDR"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MMC4_BLK_CNTL,MMC4 Block Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "BLK_CNT,BLK_CNT"
|
|
bitfld.long 0x00 12.--14. "DMA_BUFSZ,DMA_BUFSZ" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--11. 1. "XFR_BLKSZ,XFR_BLKSZ"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MMC4_ARG,MMC4 Command Argument Register"
|
|
hexmask.long 0x00 0.--31. 1. "ARG,ARG"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MMC4_CMD_XFRMD,MMC4 Command and Transfer Mode Register"
|
|
bitfld.long 0x00 24.--29. "CMD_IDX,CMD_IDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 22.--23. "CMD_TYPE,CMD_TYPE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "DPSEL,DPSEL" "0,1"
|
|
bitfld.long 0x00 20. "IDXCHKEN,IDXCHKEN" "0,1"
|
|
bitfld.long 0x00 19. "CRCCHKEN,CRCCHKEN" "0,1"
|
|
bitfld.long 0x00 16.--17. "RES_TYPE,RES_TYPE" "0,1,2,3"
|
|
bitfld.long 0x00 6. "CMD_COMP_ATA,CMD_COMP_ATA" "0,1"
|
|
bitfld.long 0x00 5. "MS_BLKSEL,MS_BLKSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DXFRDIR,DXFRDIR" "0,1"
|
|
bitfld.long 0x00 2. "AUTOCMD12,AUTOCMD12" "0,1"
|
|
bitfld.long 0x00 1. "BLKCNTEN,BLKCNTEN" "0,1"
|
|
bitfld.long 0x00 0. "DMA_EN,DMA_EN" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "MMC4_RESP0,MMC4 Command Response Register0"
|
|
hexmask.long 0x00 0.--31. 1. "RESP_31_0,RESP[31:0]"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "MMC4_RESP1,MMC4 Command Response Register1"
|
|
hexmask.long 0x00 0.--31. 1. "RESP_63_32,RESP[63:32]"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "MMC4_RESP2,MMC4 Command Response Register2"
|
|
hexmask.long 0x00 0.--31. 1. "RESP_95_64,RESP[95:64]"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "MMC4_RESP3,MMC4 Command Response Register3"
|
|
hexmask.long 0x00 0.--31. 1. "RESP_127_96,RESP[127:96]"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MMC4_DP,MMC4 Buffer Data Port Register"
|
|
hexmask.long 0x00 0.--31. 1. "BFR_DATA,BFR_DATA"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "MMC4_STATE,MMC4 Present State Register"
|
|
bitfld.long 0x00 25.--28. "UPRDATLVL,UPRDATLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24. "CMDLVL,CMDLVL" "0,1"
|
|
bitfld.long 0x00 20.--23. "LWRDATLVL,LWRDATLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "WPSWLVL,WPSWLVL" "0,1"
|
|
bitfld.long 0x00 18. "CDDETLVL,CDDETLVL" "0,1"
|
|
bitfld.long 0x00 17. "CDSTBL,CDSTBL" "0,1"
|
|
bitfld.long 0x00 16. "CDINSTD,CDINSTD" "0,1"
|
|
bitfld.long 0x00 11. "BUFRDEN,BUFRDEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "BUFWREN,BUFWREN" "0,1"
|
|
bitfld.long 0x00 9. "RDACTV,RDACTV" "0,1"
|
|
bitfld.long 0x00 8. "WRACTV,WRACTV" "0,1"
|
|
bitfld.long 0x00 2. "DATACTV,DATACTV" "0,1"
|
|
bitfld.long 0x00 1. "DCMDINHBT,DCMDINHBT" "0,1"
|
|
bitfld.long 0x00 0. "CCMDINHBT,CCMDINHBT" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MMC4_CNTL1,MMC4 Host Control Register 1"
|
|
bitfld.long 0x00 19. "BGIRQEN,BGIRQEN" "0,1"
|
|
bitfld.long 0x00 18. "RDWTCNTL,RDWTCNTL" "0,1"
|
|
bitfld.long 0x00 17. "CONTREQ,CONTREQ" "0,1"
|
|
bitfld.long 0x00 16. "BGREQSTP,BGREQSTP" "0,1"
|
|
bitfld.long 0x00 9.--11. "VLTGSEL,VLTGSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. "BUSPWR,BUSPWR" "0,1"
|
|
bitfld.long 0x00 5. "_8BITMD,8BITMD" "0,1"
|
|
bitfld.long 0x00 2. "HISPEED,HISPEED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "_4BITMD,4BITMD" "0,1"
|
|
bitfld.long 0x00 0. "LEDCNTL,LEDCNTL" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MMC4_CNTL2,MMC4 Host Control Register 2"
|
|
bitfld.long 0x00 26. "DATSWRST,DATSWRST" "0,1"
|
|
bitfld.long 0x00 25. "CMDSWRST,CMDSWRST" "0,1"
|
|
bitfld.long 0x00 24. "MSWRST,MSWRST" "0,1"
|
|
bitfld.long 0x00 16.--19. "DTOCNTR,DTOCNTR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SDFREQ,SDFREQ"
|
|
bitfld.long 0x00 2. "MM4CLKEN,MM4CLKEN" "0,1"
|
|
bitfld.long 0x00 0. "INTCLKEN,INTCLKEN" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MMC4_I_STAT,MMC4 Align Detection Timeout Value Register"
|
|
bitfld.long 0x00 28. "AHBTERR,AHBTERR" "0,1"
|
|
bitfld.long 0x00 24. "AC12ERR,AC12ERR" "0,1"
|
|
bitfld.long 0x00 23. "ILMTERR,ILMTERR" "0,1"
|
|
bitfld.long 0x00 22. "DENDERR,DENDERR" "0,1"
|
|
bitfld.long 0x00 21. "DCRCERR,DCRCERR" "0,1"
|
|
bitfld.long 0x00 20. "DTOERR,DTOERR" "0,1"
|
|
bitfld.long 0x00 19. "CIDXERR,CIDXERR" "0,1"
|
|
bitfld.long 0x00 18. "CENDERR,CENDERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CCRCERR,CCRCERR" "0,1"
|
|
bitfld.long 0x00 16. "CTOERR,CTOERR" "0,1"
|
|
rbitfld.long 0x00 15. "ERRINT,ERRINT" "0,1"
|
|
rbitfld.long 0x00 8. "CDINT,CDINT" "0,1"
|
|
bitfld.long 0x00 7. "CDREM,CDREM" "0,1"
|
|
bitfld.long 0x00 6. "CDINS,CDINS" "0,1"
|
|
bitfld.long 0x00 5. "BUFRDRDY,BUFRDRDY" "0,1"
|
|
bitfld.long 0x00 4. "BUFWRRDY,BUFWRRDY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DMAINT,DMAINT" "0,1"
|
|
bitfld.long 0x00 2. "BGEVNT,BGEVNT" "0,1"
|
|
bitfld.long 0x00 1. "XFRCOMP,XFRCOMP" "0,1"
|
|
bitfld.long 0x00 0. "CMDCOMP,CMDCOMP" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MMC4_I_STAT_EN,MMC4 Interrupt Status Enable Register"
|
|
bitfld.long 0x00 28. "ATERRSTEN,ATERRSTEN" "0,1"
|
|
bitfld.long 0x00 24. "AC12STEN,AC12STEN" "0,1"
|
|
bitfld.long 0x00 23. "ILMTSTEN,ILMTSTEN" "0,1"
|
|
bitfld.long 0x00 22. "DENDSTEN,DENDSTEN" "0,1"
|
|
bitfld.long 0x00 21. "DCRCSTEN,DCRCSTEN" "0,1"
|
|
bitfld.long 0x00 20. "DTOSTEN,DTOSTEN" "0,1"
|
|
bitfld.long 0x00 19. "CIDXSTEN,CIDXSTEN" "0,1"
|
|
bitfld.long 0x00 18. "CENDSTEN,CENDSTEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CCRCSTEN,CCRCSTEN" "0,1"
|
|
bitfld.long 0x00 16. "CTOSTEN,CTOSTEN" "0,1"
|
|
bitfld.long 0x00 8. "CDINTSTEN,CDINTSTEN" "0,1"
|
|
bitfld.long 0x00 7. "CDREMSTEN,CDREMSTEN" "0,1"
|
|
bitfld.long 0x00 6. "CDINSSTEN,CDINSSTEN" "0,1"
|
|
bitfld.long 0x00 5. "BUFRDRDYSTEN,BUFRDRDYSTEN" "0,1"
|
|
bitfld.long 0x00 4. "BUFWRRDYSTEN,BUFWRRDYSTEN" "0,1"
|
|
bitfld.long 0x00 3. "DMAINTSTEN,DMAINTSTEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "BGEVNTSTEN,BGEVNTSTEN" "0,1"
|
|
bitfld.long 0x00 1. "XFRCOMPSTEN,XFRCOMPSTEN" "0,1"
|
|
bitfld.long 0x00 0. "CMDCOMPSTEN,CMDCOMPSTEN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "MMC4_I_SIG_EN,MMC4 Interrupt Signal Enable Register"
|
|
bitfld.long 0x00 28. "ATERRSGEN,ATERRSGEN" "0,1"
|
|
bitfld.long 0x00 24. "AC12SGEN,AC12SGEN" "0,1"
|
|
bitfld.long 0x00 23. "ILMTSGEN,ILMTSGEN" "0,1"
|
|
bitfld.long 0x00 22. "DENDSGEN,DENDSGEN" "0,1"
|
|
bitfld.long 0x00 21. "DCRCSGEN,DCRCSGEN" "0,1"
|
|
bitfld.long 0x00 20. "DTOSGEN,DTOSGEN" "0,1"
|
|
bitfld.long 0x00 19. "CIDXSGEN,CIDXSGEN" "0,1"
|
|
bitfld.long 0x00 18. "CENDSGEN,CENDSGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CCRCSGEN,CCRCSGEN" "0,1"
|
|
bitfld.long 0x00 16. "CTOSGEN,CTOSGEN" "0,1"
|
|
bitfld.long 0x00 8. "CDINTSGEN,CDINTSGEN" "0,1"
|
|
bitfld.long 0x00 7. "CDREMSGEN,CDREMSGEN" "0,1"
|
|
bitfld.long 0x00 6. "CDINSSGEN,CDINSSGEN" "0,1"
|
|
bitfld.long 0x00 5. "BUFRDRDYSGEN,BUFRDRDYSGEN" "0,1"
|
|
bitfld.long 0x00 4. "BUFWRRDYSGEN,BUFWRRDYSGEN" "0,1"
|
|
bitfld.long 0x00 3. "DMAINTSGEN,DMAINTSGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "BGEVNTSGEN,BGEVNTSGEN" "0,1"
|
|
bitfld.long 0x00 1. "XFRCOMPSGEN,XFRCOMPSGEN" "0,1"
|
|
bitfld.long 0x00 0. "CMDCOMPSGEN,CMDCOMPSGEN" "0,1"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "MMC4_ACMD12_ER,MMC4 Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. "CMDNISUD,CMDNISUD" "0,1"
|
|
bitfld.long 0x00 4. "AC12IDXER,AC12IDXER" "0,1"
|
|
bitfld.long 0x00 3. "AC12ENDER,AC12ENDER" "0,1"
|
|
bitfld.long 0x00 2. "AC12CRCER,AC12CRCER" "0,1"
|
|
bitfld.long 0x00 1. "AC12TOER,AC12TOER" "0,1"
|
|
bitfld.long 0x00 0. "AC12NEXE,AC12NEXE" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MMC4_CAP0,MMC4 Capabilities Register 0"
|
|
bitfld.long 0x00 27. "IRQMODE,IRQMODE" "0,1"
|
|
bitfld.long 0x00 26. "_1_8VSPRT,1.8VSPRT" "0,1"
|
|
bitfld.long 0x00 25. "_3_0VSPRT,3.0VSPRT" "0,1"
|
|
bitfld.long 0x00 24. "_3_3VSPRT,3.3VSPRT" "0,1"
|
|
bitfld.long 0x00 23. "SUSP_RES,SUSP/RES" "0,1"
|
|
bitfld.long 0x00 22. "DMASPRT,DMASPRT" "0,1"
|
|
bitfld.long 0x00 21. "HISPDSPRT,HISPDSPRT" "0,1"
|
|
bitfld.long 0x00 16.--17. "MAXBLEN,MAXBLEN" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "BSCLKFREQ,BSCLKFREQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 7. "TOCLKUNIT,TOCLKUNIT" "0,1"
|
|
bitfld.long 0x00 0.--5. "TOCLKFREQ,TOCLKFREQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "MMC4_CUR_CAP0,MMC4 Maximum Current Capabilities Register 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. "_1_8VMAXI,1.8VMAXI"
|
|
hexmask.long.byte 0x00 8.--15. 1. "_3_0VMAXI,3.0VMAXI"
|
|
hexmask.long.byte 0x00 0.--7. 1. "_3_3VMAXI,3.3VMAXI"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "MMC4_VER,MMC4 Controller Version Status"
|
|
hexmask.long.byte 0x00 24.--31. 1. "VNDRVER,VNDRVER"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SPECVER,SPECVER"
|
|
tree.end
|
|
tree "SSP"
|
|
repeat 3. (list 0. 1. 2.) (list ad:0x46020000 ad:0x460D0000 ad:0x48000000)
|
|
tree "SSP$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSP_SSCR0,SSP Control Register 0"
|
|
bitfld.long 0x00 31. "MOD,Mode" "0: Normal SSP mode,1: Network mode"
|
|
bitfld.long 0x00 30. "ACS,Audio Clock Select" "0: Clock selection is determined by the <Network..,1: Audio clock (and audio clock divider) are.."
|
|
newline
|
|
bitfld.long 0x00 29. "FPCKE,FIFO Packing Enable" "0: FIFO packing mode disabled,1: FIFO packing mode enabled"
|
|
bitfld.long 0x00 28. "RHCD,RX half cycle delay" "0: not seclect RX half cycle delay,1: receive data delay half cycle"
|
|
newline
|
|
bitfld.long 0x00 27. "MCRT,Master Clock Return" "0: not seclect master return_clock,1: master clock delay"
|
|
bitfld.long 0x00 24.--26. "FRDC,Frame Rate Divider Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. "TIM,Transmit FIFO Underrun Interrupt Mask" "0: TUR events generate an SSP interrupt,1: TUR events do NOT generate an SSP interrupt"
|
|
bitfld.long 0x00 22. "RIM,Receive FIFO Overrun Interrupt Mask" "0: ROR events generate an SSP interrupt,1: ROR events do NOT generate an SSP interrupt"
|
|
newline
|
|
bitfld.long 0x00 20. "EDSS,Extended Data Size Select" "0: A 0 is pre-appended to the DSS value to set..,1: A 1 is pre-appended to the DSS value to set.."
|
|
bitfld.long 0x00 7. "SSE,Synchronous Serial Port Enable" "0: SSPx port is disabled,1: SSPx port is enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "FRF,Frame Format" "0: Motorola* Serial Peripheral Interface (SPI),1: Texas Instruments* Synchronous Serial..,2: National Semiconductor Microwire*,3: Programmable Serial Protocol (PSP)"
|
|
bitfld.long 0x00 0.--3. "DSS,Data Size Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP_SSCR1,SSP Control Register 1"
|
|
bitfld.long 0x00 31. "TTELP,TXD Three-state Enable On Last Phase" "0: TXDx is three-stated 1/2 clock cycle after..,1: TXDx output signal is three-stated on the.."
|
|
bitfld.long 0x00 30. "TTE,TXD Three-State Enable" "0: TXDx output signal is not three-stated,1: TXD is three-stated when not transmitting data"
|
|
newline
|
|
bitfld.long 0x00 29. "EBCEI,Enable Bit Count Error Interrupt" "0: Interrupt due to a bit count error is disabled,1: Interrupt due to a bit count error is enabled"
|
|
bitfld.long 0x00 28. "SCFR,Slave Clock Free Running" "0: Clock input to SSPSCLKx is continuously running,1: Clock input to SSPSCLKx is only active during.."
|
|
newline
|
|
bitfld.long 0x00 27. "ECRA,Enable Clock Request A" "0: Clock request from other SSPx is disabled,1: Clock request from other SSPx is enabled"
|
|
bitfld.long 0x00 26. "ECRB,Enable Clock Request B" "0: Clock request from other SSPx is disabled,1: Clock request from other SSPx is enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "SCLKDIR,SSP Serial Bit Rate Clock (SSPSCLKx) Direction" "0: Master mode SSPx port drives SSPSCLKx,1: Slave mode SSPx port receives SSPSCLKx"
|
|
bitfld.long 0x00 24. "SFRMDIR,SSP Frame (SSPSFRMx) Direction" "0: Master mode SSPx port drives SSPSFRMx,1: Slave mode SSPx port receives SSPSFRMx"
|
|
newline
|
|
bitfld.long 0x00 23. "RWOT,Receive Without Transmit" "0: Transmit/Receive mode,1: Receive without Transmit mode"
|
|
bitfld.long 0x00 22. "TRAIL,Trailing Byte" "0: Trailing bytes are handled by the Aspen..,1: Trailing bytes are handled by DMA bursts"
|
|
newline
|
|
bitfld.long 0x00 21. "TSRE,Transmit Service Request Enable" "0: DMA service request is disabled,1: DMA service request is enabled"
|
|
bitfld.long 0x00 20. "RSRE,Receive Service Request Enable" "0: DMA service request is disabled,1: DMA service request is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "IFS,Invert Frame Signal" "0: SSPSFRMx polarity is determined by the PSP..,1: SSPSFRMx is inverted from normal-SSPSFRMx (as.."
|
|
bitfld.long 0x00 15. "STRF,Select FIFO For Efwr" "0: TXFIFO is selected for both writes and reads..,1: RXFIFO is selected for both writes and reads.."
|
|
newline
|
|
bitfld.long 0x00 14. "EFWR,Enable FIFO Write/read" "0: FIFO write/read special function is disabled..,1: FIFO write/read special function is enabled"
|
|
bitfld.long 0x00 10.--13. "RFT,RXFIFO Trigger Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--9. "TFT,TXFIFO Trigger Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. "SPH,Motorola SPI SSPSCLK phase setting" "0: SSPSCLKx is inactive until one cycle after..,1: SSPSCLKx is inactive until 1/2 cycle after.."
|
|
newline
|
|
bitfld.long 0x00 3. "SPO,Motorola SPI SSPSCLK Polarity Setting" "0: The inactive or idle state of SSPSCLKx is low,1: The inactive or idle state of SSPSCLKx is high"
|
|
bitfld.long 0x00 2. "LBM,Loopback Mode" "0: Normal serial port operation is enabled,1: Output of TX serial shifter is internally.."
|
|
newline
|
|
bitfld.long 0x00 1. "TIE,Transmit FIFO Interrupt Enable" "0: TXFIFO threshold-level-reached interrupt is..,1: TXFIFO threshold-level-reached interrupt is.."
|
|
bitfld.long 0x00 0. "RIE,Receive FIFO Interrupt Enable" "0: RXFIFO threshold-level-reached interrupt is..,1: RXFIFO threshold-level-reached interrupt is.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSP_SSSR,SSP Status Register"
|
|
rbitfld.long 0x00 31. "OSS,Odd Sample Status" "0: RxFIFO entry has 2 samples,1: RxFIFO entry has 1 sample"
|
|
rbitfld.long 0x00 30. "TX_OSS,TX FIFO Odd Sample Status" "0: TxFIFO entry has an even number of samples,1: TxFIFO entry has an odd number of sample"
|
|
newline
|
|
bitfld.long 0x00 23. "BCE,Bit Count Error" "0: The SSPx port has not experienced a bit count..,1: The SSPSFRMx signal was asserted when the bit.."
|
|
rbitfld.long 0x00 22. "CSS,Clock Synchronization Status" "0: The SSPx port is ready for slave clock..,1: The SSPx port is currently busy synchronizing.."
|
|
newline
|
|
bitfld.long 0x00 21. "TUR,Transmit FIFO Underrun" "0: The TXFIFO has not experienced an underrun,1: A read from the TXFIFO was attempted when the.."
|
|
rbitfld.long 0x00 12.--15. "RFL,Receive FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TFL,Transmit FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "ROR,Receive FIFO Overrun" "0: RXFIFO has not experienced an overrun,1: Attempted data write to full RXFIFO causes an.."
|
|
newline
|
|
rbitfld.long 0x00 6. "RFS,Receive FIFO Service Request" "0: RXFIFO level is at or below RFT threshold..,1: RXFIFO level exceeds RFT threshold (RFT).."
|
|
rbitfld.long 0x00 5. "TFS,Transmit FIFO Service Request" "0: TX FIFO level exceeds the TFT threshold (TFT..,1: TXFIFO level is at or below TFT threshold.."
|
|
newline
|
|
rbitfld.long 0x00 4. "BSY,SSP Busy" "0: SSPx port is idle or disabled,1: SSPx port is currently transmitting or.."
|
|
rbitfld.long 0x00 3. "RNE,Receive FIFO Not Empty" "0: RXFIFO is empty,1: RXFIFO is not empty"
|
|
newline
|
|
rbitfld.long 0x00 2. "TNF,Transmit FIFO Not Full" "0: TXFIFO is full,1: TXFIFO is not full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SSP_SSITR,SSP Interrupt Test Register"
|
|
bitfld.long 0x00 7. "TROR,Test RXFIFO Overrun" "0: No RXFIFO-overrun service request,1: Generates a non-maskable RXFIFO-overrun.."
|
|
bitfld.long 0x00 6. "TRFS,Test RXFIFO Service Request" "0: No RXFIFO-service request,1: Generates a non-maskable RXFIFO-service.."
|
|
newline
|
|
bitfld.long 0x00 5. "TTFS,Test TXFIFO Service Request" "0: No TXFIFO-service request,1: Generates a non-maskable TXFIFO-service.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SSP_SSDR,SSP Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,DATA"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SSP_SSPSP,SSP Programmable Serial Protocol Register"
|
|
bitfld.long 0x00 28.--30. "EDMYSTOP,Extended Dummy Stop" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26.--27. "EDMYSTRT,Extended Dummy Start" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 25. "FSRT,Frame Sync Relative Timing Bit" "0: Next frame is asserted after the end of the..,1: Next frame is asserted with the LSB of the.."
|
|
bitfld.long 0x00 23.--24. "DMYSTOP,Dummy Stop" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SFRMWDTH,Serial Frame Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 9.--15. 1. "SFRMDLY,Serial Frame Delay"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "DMYSTRT,Dummy Start" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. "STRTDLY,Start Delay" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "ETDS,End Of Transfer Data State" "0,1"
|
|
bitfld.long 0x00 2. "SFRMP,Serial Frame Polarity" "0: SSPSFRMx is active low (0b0),1: SSPSFRMx is active high (0b1)"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SCMODE,Serial Bit-rate Clock Mode" "0: Data Driven (Falling) Data Sampled (Rising)..,1: Data Driven (Rising) Data Sampled (Falling)..,2: Data Driven (Rising) Data Sampled (Falling)..,3: Data Driven (Falling) Data Sampled (Rising).."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SSP_SSTSA,SSP TX Time Slot Active Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TTSA,TX Time Slot Active"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SSP_SSRSA,SSP RX Time Slot Active Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RTSA,RX Time Slot Active"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SSP_SSTSS,SSP Time Slot Status Register"
|
|
bitfld.long 0x00 31. "NMBSY,Network Mode Busy" "0: SSPx port is in network mode and no frame is..,1: SSPx port is in network mode and a frame is.."
|
|
bitfld.long 0x00 0.--2. "TSS,Time Slot Status" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SYS_CTL"
|
|
base ad:0x480B0000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REV_ID,Chip Revision Register"
|
|
hexmask.long 0x00 0.--31. 1. "REV_ID,Chip revision ID"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RAM0,RAM0 Control Register"
|
|
bitfld.long 0x00 2.--3. "WTC,WTC" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RTC,RTC" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RAM1,RAM1 Control Register"
|
|
bitfld.long 0x00 2.--3. "WTC,WTC" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RTC,RTC" "0,1,2,3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RAM2,RAM2 Control Register"
|
|
bitfld.long 0x00 2.--3. "WTC,WTC" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RTC,RTC" "0,1,2,3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RAM3,RAM3 Control Register"
|
|
bitfld.long 0x00 2.--3. "WTC,WTC" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RTC,RTC" "0,1,2,3"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ROM,ROM Control Register"
|
|
bitfld.long 0x00 3.--4. "RTC_REF,RTC Reference" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. "RTC,RTC Reference" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "AON_MEM,AON_MEM Control Register"
|
|
bitfld.long 0x00 2.--3. "WTC,WTC" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RTC,RTC" "0,1,2,3"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "GPT_in,GPT Pin-in Selection Register"
|
|
bitfld.long 0x00 0. "sel,Select GPT Pin" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CAL,Calibration channel selection register"
|
|
bitfld.long 0x00 1. "RTC_Trig,RTC Trigger" "0,1"
|
|
bitfld.long 0x00 0. "RTC_Duty,RTC Duty" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PERI_SW_RST,Peripheral Software Reset register"
|
|
bitfld.long 0x00 26. "gau_rstn_en,GAU Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 20. "qspi0_rstn_en,QSPI0 Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 18. "flash_qspi_rstn_en,Flash QSPI Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 17. "uart0_rstn_en,UART0 Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 15. "uart2_rstn_en,UART2 Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 14. "uart3_rstn_en,UART3 Reset_n Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "i2c0_rstn_en,I2C0 Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 12. "i2c1_rstn_en,I2C1 Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 10. "ssp0_rstn_en,SSP0 Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 9. "ssp1_rstn_en,SSP01 Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 8. "ssp2_rstn_en,SSP2 Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 7. "gpt0_rstn_en,GPT0 Reset_n Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "gpt1_rstn_en,GPT1 Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 5. "gpt2_rstn_en,GPT2 Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 4. "gpt3_rstn_en,GPT3 Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 1. "usb_rstn_en,USB Reset_n Enable" "0,1"
|
|
bitfld.long 0x00 0. "wdt_rstn_en,WDT Reset_n Enable" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "USB_CTRL,USB Control Register"
|
|
bitfld.long 0x00 22. "mac_ctrl_sel,MAC Control Select" "0,1"
|
|
bitfld.long 0x00 21. "soft_utmi_iddig,Soft UTMI iddig" "0,1"
|
|
bitfld.long 0x00 20. "soft_utmi_xvalid,Soft UTMI xvalid" "0,1"
|
|
bitfld.long 0x00 19. "soft_utmi_sessend,Soft UTMI sessend" "0,1"
|
|
bitfld.long 0x00 18. "phy_reset_sel,PHY Reset Select" "0,1"
|
|
bitfld.long 0x00 17. "soft_phy_reset,Soft PHY Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "iddq_test,iddq Test" "0,1"
|
|
rbitfld.long 0x00 15. "usb_resume,USB Resume" "0,1"
|
|
bitfld.long 0x00 13.--14. "reg_tx_buf_wtc,reg_tx_buf_wtc" "0,1,2,3"
|
|
bitfld.long 0x00 11.--12. "reg_tx_buf_rtc,reg_tx_buf_rtc" "0,1,2,3"
|
|
bitfld.long 0x00 9.--10. "reg_rx_buf_wtc,reg_rx_buf_wtc" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "reg_rx_buf_rtc,reg_rx_buf_rtc" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6. "reg_tx_pdlvmc,reg_tx_pdlvmc" "0,1"
|
|
bitfld.long 0x00 5. "reg_tx_pdfvssm,reg_tx_pdfvssm" "0,1"
|
|
bitfld.long 0x00 4. "reg_rx_pdlvmc,reg_rx_pdlvmc" "0,1"
|
|
bitfld.long 0x00 3. "reg_rx_pdfvssm,reg_rx_pdfvssm" "0,1"
|
|
bitfld.long 0x00 2. "usb_PU,USB PU" "0,1"
|
|
bitfld.long 0x00 1. "usb_PU_OTG,USB PU OTG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "usb_PU_PLL,USB PU PLL" "0,1"
|
|
tree.end
|
|
tree "UART"
|
|
repeat 3. (list 0. 1. 2.) (list ad:0x46040000 ad:0x460C0000 ad:0x48020000)
|
|
tree "UART$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DLL,Divisor Latch Low Byte Registers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DLL,DLL Low-byte compare value to generate baud rate"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RBR,Receive Buffer Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_3,Byte 3(valid only in 32-bit peripheral bus mode)"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_2,Byte 2(valid only in 32-bit peripheral bus mode)"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_1,Byte 1(valid only in 32-bit peripheral bus mode)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_0,Byte 0"
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_3,Byte 3 (valid only in 32-bit peripheral bus mode)"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_2,Byte 2 (valid only in 32-bit peripheral bus mode)"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_1,Byte 1 (valid only in 32-bit peripheral bus mode)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_0,Byte 0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DLH,Divisor Latch High Byte Registers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DLH,DLH High-byte compare value to generate baud rate"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 8. "HSE,High Speed UART Enable (HSE)" "0,1"
|
|
bitfld.long 0x00 7. "DMAE,DMA Requests Enable" "0: DMA requests are disabled,1: DMA requests are enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "UUE,UART Unit Enable" "0: the unit is disabled,1: the unit is enabled"
|
|
bitfld.long 0x00 5. "NRZE,NRZ Coding Enable" "0: NRZ coding disabled,1: NRZ coding enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "RTOIE,Receiver Time-out Interrupt Enable (Source IIR[TOD])" "0: Receiver data time-out interrupt disabled,1: Receiver data time-out interrupt enabled"
|
|
bitfld.long 0x00 3. "MIE,Modem Interrupt Enable (Source IIR[IID])" "0: Modem status interrupt disabled,1: Modem status interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "RLSE,Receiver Line Status Interrupt Enable (Source IIR[IID])" "0: Receiver line status interrupt disabled,1: Receiver line status interrupt enabled"
|
|
bitfld.long 0x00 1. "TIE,Transmit Data Request Interrupt Enable(Source IIR[IID])" "0: Transmit FIFO data request interrupt disabled,1: Transmit FIFO data request interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "RAVIE,Receiver Data Available Interrupt Enable (Source IIR[IID])" "0: Receiver data availble(trigger threshold..,1: Receiver data availble(trigger threshold.."
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x00 6.--7. "ITL,Interrupt Trigger Level" "0: 1 byte or more in FIFO causes interrupt (Not..,1: 8 bytes or more in FIFO cause interrupt and..,2: 16 bytes or more in FIFO causes interrupt and..,3: 32 bytes or more in FIFO causes interrupt and.."
|
|
bitfld.long 0x00 5. "BUS,32-Bit Peripheral Bus" "0: 8-bit peripheral bus,1: 32-bit peripheral bus Transmit and Receive.."
|
|
newline
|
|
bitfld.long 0x00 3. "TIL,Transmitter Interrupt Level" "0: Interrupt/DMA request when FIFO is half empty,1: Interrupt/DMA request when FIFO is empty"
|
|
bitfld.long 0x00 2. "RESETTF,Reset Transmit FIFO" "0: Writing 0 has no effect,1: The transmit FIFO is cleared"
|
|
newline
|
|
bitfld.long 0x00 1. "RESETRF,Reset Receive FIFO" "0: Writing 0 has no effect,1: The receive FIFO is cleared"
|
|
bitfld.long 0x00 0. "TRFIFOE,Transmit and Receive FIFO Enable" "0: FIFOs are disabled,1: FIFOs are enabled"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.long 0x00 6.--7. "FIFOES10,FIFO Mode Enable Status" "0: Non-FIFO mode is selected,?,?,3: FIFO mode is selected"
|
|
bitfld.long 0x00 5. "EOC,DMA End of Descriptor Chain" "0: DMA has not signaled the end of its..,1: DMA has signaled the end of its programmed.."
|
|
newline
|
|
bitfld.long 0x00 4. "ABL,Auto-baud Lock" "0: Auto-baud circuitry has not programmed..,1: Divisor Latch registers (DLR) programmed by.."
|
|
bitfld.long 0x00 3. "TOD,Timeout Detected" "0: No timeout interrupt is pending,1: Timeout interrupt is pending (FIFO mode only)"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "IID10,Interrupt Source Encoded" "0: Modern Status (CTS),1: Transmit FIFO request data,2: Receive data available,3: Receive error (overrun)"
|
|
bitfld.long 0x00 0. "NIP,Interrupt is pending" "0: Interrupt is pending (active low),1: No interrupt is pending"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. "DLAB,Divisor Latch Access" "0: access Transmit Holding Register Receive..,1: access Divisor Latch Registers"
|
|
bitfld.long 0x00 6. "SB,Set Break" "0: no effect on TXD output,1: forces TXD output to 0"
|
|
newline
|
|
bitfld.long 0x00 5. "STKYP,Sticky Parity" "0: no effect on parity bit,1: forces parity bit to be opposite of EPS bit.."
|
|
bitfld.long 0x00 4. "EPS,Even Parity Select" "0: Sends or checks for odd parity,1: Sends or checks for even parity"
|
|
newline
|
|
bitfld.long 0x00 3. "PEN,Parity Enable" "0: No parity,1: no description available"
|
|
bitfld.long 0x00 2. "STB,Stop Bits" "0: 1 stop bit,1: 2 stop bit"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "WLS10,World Length Select" "0: 5-bit character,1: 6-bit character,2: 7-bit character,3: 8-bit character"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,Modem Control Register"
|
|
bitfld.long 0x00 5. "AFE,Auto-flow Control Enable" "0: auto-RTS and auto-CTS are disabled,1: auto-RTS and auto-CTS are enabled"
|
|
bitfld.long 0x00 4. "LOOP,Loopback Mode" "0: normal UART operation,1: loopback mode UART operation"
|
|
newline
|
|
bitfld.long 0x00 3. "OUT2,OUT2 Signal Control" "0: UART interrupt is disabled when loop is clear..,1: UART interrupt is enabled when loop is clear.."
|
|
bitfld.long 0x00 1. "RTS,Request to Send" "0: non-auto-flow mode,1: auto-flow mode"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "LSR,Line Status Register"
|
|
bitfld.long 0x00 7. "FIFOE,FIFO Error Status" "0: No FIFO or no errors in receive FIFO,1: At least one character in receive FIFO has.."
|
|
bitfld.long 0x00 6. "TEMT,Transmitter Empty" "0: There is data in the transmit shift register..,1: All the data in the transmitter has been.."
|
|
newline
|
|
bitfld.long 0x00 5. "TDRQ,Transmit Data Request" "0: There is data in the holding register or FIFO..,1: transmit FIFO has half or less then half data"
|
|
bitfld.long 0x00 4. "BI,Break Interrupt" "0: No break signal has been received,1: Break signal received"
|
|
newline
|
|
bitfld.long 0x00 3. "FE,Framing Error" "0: No Framing error,1: Invalid stop bit has been detected"
|
|
bitfld.long 0x00 2. "PE,Parity Error" "0: No parity error,1: Parity error has been detected"
|
|
newline
|
|
bitfld.long 0x00 1. "OE,Overrun Error" "0: No data has been lost,1: Receive data has been lost"
|
|
bitfld.long 0x00 0. "DR,Data Ready" "0: No data has been received,1: Data is available in RBR or the FIFO"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "MSR,Modem Status Register"
|
|
bitfld.long 0x00 4. "CTS,Clear to Send" "0: nCTS pin is 1,1: nCTS pin is 0"
|
|
bitfld.long 0x00 0. "DCTS,Delta Clear to Send" "0: No change in nCTS pin since last read of MSR,1: nCTS pin has changed state"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SCR,Scratchpad Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCRATCHPAD,No effect on UART functions"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ISR,Infrared Selection Register"
|
|
bitfld.long 0x00 4. "RXPL,Receive Data Polarity" "0: SIR decoder takes positive pulses as 0s,1: SIR decoder takes negative pulses as 0s"
|
|
bitfld.long 0x00 3. "TXPL,Transmit Data Polarity" "0: SIR encoder generates a positive pulse for a..,1: SIR encoder generates a negetive pulse for a.."
|
|
newline
|
|
bitfld.long 0x00 2. "XMODE,Transmit Pulse Width Select" "0: Transmit pulse width is 3/16 of a bit time wide,1: Transmit pulse width is 1.6 ms"
|
|
bitfld.long 0x00 1. "RCVEIR,Receiver SIR Enable" "0: Receiver is in UART mode,1: Receiver is in infrared mode"
|
|
newline
|
|
bitfld.long 0x00 0. "XMITIR,Transmitter SIR Enable" "0: Transmitter is in UART mode,1: Transmitter is in infrared mode"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RFOR,Receive FIFO Occupancy Register"
|
|
bitfld.long 0x00 0.--5. "BYTE_COUNT,Number of bytes (0-63) remaining in receive FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ABR,Auto-Baud Control Register"
|
|
bitfld.long 0x00 3. "ABT,Auto-Baud table" "0: Formula used to calculate baud rates,1: Table used to calculate baud rates which.."
|
|
bitfld.long 0x00 2. "ABUP,Auto-baud programmer select" "0: CPU programs Divisor Latch register,1: UART programs Divisor Latch register"
|
|
newline
|
|
bitfld.long 0x00 1. "ABLIE,Auto-baud-lock interrupt enable" "0: auto-baud-lock interrupt is disabled,1: auto-baud-lock interrupt is enabled"
|
|
bitfld.long 0x00 0. "ABE,Auto-baud enable" "0: auto-baud disabled,1: auto-baud enabled"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "ACR,Auto-Baud Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT_VALUE,Number of 14.857 MHz clock cycles within a Start-Bit pulse"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "USBC"
|
|
base ad:0x44001000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ID,no description available"
|
|
bitfld.long 0x00 29.--31. "CIVERSION,no description available" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 25.--28. "VERSION,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21.--24. "REVISION,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. "TAG,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "NID,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "ID,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "HWGENERAL,no description available"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,no description available"
|
|
bitfld.long 0x00 10.--11. "SM,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 6.--9. "PHYM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. "PHYW,no description available" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3. "BWT,no description available" "0,1"
|
|
bitfld.long 0x00 1.--2. "CLKC,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RT,no description available" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "HWHOST,no description available"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TTPER,no description available"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TTASY,no description available"
|
|
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,no description available"
|
|
bitfld.long 0x00 1.--3. "NPORT,no description available" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "HC,no description available" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "HWDEVICE,no description available"
|
|
hexmask.long 0x00 6.--31. 1. "Reserved_6,no description available"
|
|
bitfld.long 0x00 1.--5. "DEVEP,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. "DC,no description available" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "HWTXBUF,no description available"
|
|
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,no description available"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TXCHANADD,no description available"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TXADD,no description available"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXBURST,no description available"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "HWRXBUF,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,no description available"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXADD,no description available"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RXBURST,no description available"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "HWTXBUF$1,no description available"
|
|
hexmask.long 0x00 0.--31. 1. "TXBURST,no description available"
|
|
repeat.end
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPTIMER0LD,no description available"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,no description available"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTLD,no description available"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GPTIMER0CTRL,no description available"
|
|
bitfld.long 0x00 31. "GPTRUN,no description available" "0,1"
|
|
rbitfld.long 0x00 30. "GPTRST,no description available" "0,1"
|
|
rbitfld.long 0x00 25.--29. "Reserved_25,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. "GPTMODE,no description available" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTCNT,no description available"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "GPTTIMER1LD,no description available"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,no description available"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTLD,no description available"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "GPTIMER1CTRL,no description available"
|
|
bitfld.long 0x00 31. "GPTRUN,no description available" "0,1"
|
|
rbitfld.long 0x00 30. "GPTRST,no description available" "0,1"
|
|
rbitfld.long 0x00 25.--29. "Reserved_25,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. "GPTMODE,no description available" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTCNT,no description available"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "SBUSCFG,no description available"
|
|
hexmask.long 0x00 3.--31. 1. "Reserved_3,no description available"
|
|
bitfld.long 0x00 0.--2. "AHBBRST,no description available" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CAPLENGTH,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "HCIVERSION,no description available"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPLENGTH,no description available"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "HCSPARAMS,no description available"
|
|
bitfld.long 0x00 28.--31. "Reserved_28,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "N_TT,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "N_PTT,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 17.--19. "Reserved_17,no description available" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "PI,no description available" "0,1"
|
|
bitfld.long 0x00 12.--15. "N_CC,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "N_PCC,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5.--7. "Reserved_5,no description available" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4. "PPC,no description available" "0,1"
|
|
bitfld.long 0x00 0.--3. "N_PORTS,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "HCCPARAMS,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,no description available"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EECP,no description available"
|
|
bitfld.long 0x00 4.--7. "IST,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. "Reserved_3,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ASP,no description available" "0,1"
|
|
bitfld.long 0x00 1. "PFL,no description available" "0,1"
|
|
bitfld.long 0x00 0. "ADC,no description available" "0,1"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "DCIVERSION,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "DCIVERSION,no description available"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "DCCPARAMS,no description available"
|
|
bitfld.long 0x00 31. "LPM_EN,no description available" "0,1"
|
|
hexmask.long.tbyte 0x00 9.--30. 1. "Reserved_9,no description available"
|
|
bitfld.long 0x00 8. "HC,no description available" "0,1"
|
|
bitfld.long 0x00 7. "DC,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "Reserved_5,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "DEN,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DevLPMCSR,no description available"
|
|
rbitfld.long 0x00 30.--31. "LPM_RSP,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 29. "LPM_PHCD_only,no description available" "0,1"
|
|
rbitfld.long 0x00 28. "BRMTWAKE,no description available" "0,1"
|
|
rbitfld.long 0x00 24.--27. "LINKSTATE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "HIRD,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 18.--19. "Reserved_18,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 17. "LPM_ANY_EP,no description available" "0,1"
|
|
bitfld.long 0x00 16. "HST_RSM_EN,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "LPM_ON,no description available" "0,1"
|
|
bitfld.long 0x00 14. "ALWAYS_LOG,no description available" "0,1"
|
|
bitfld.long 0x00 13. "MIN_SLP_EN,no description available" "0,1"
|
|
bitfld.long 0x00 12. "STALL_OK,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "ACK_OK,no description available" "0,1"
|
|
bitfld.long 0x00 10. "IE_L1STATE,no description available" "0,1"
|
|
bitfld.long 0x00 9. "L1STATE,no description available" "0,1"
|
|
bitfld.long 0x00 8. "RWAKE_EN,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IE_LPMERR,no description available" "0,1"
|
|
bitfld.long 0x00 6. "IE_LPMACK,no description available" "0,1"
|
|
bitfld.long 0x00 5. "IE_LPMPKT,no description available" "0,1"
|
|
bitfld.long 0x00 4. "IE_L1RSM,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INT_LPMERR,no description available" "0,1"
|
|
bitfld.long 0x00 2. "INT_LPMACK,no description available" "0,1"
|
|
bitfld.long 0x00 1. "INT_LPMPKT,no description available" "0,1"
|
|
bitfld.long 0x00 0. "INT_L1RSM,no description available" "0,1"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "USBCMD,no description available"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,no description available"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ITC,no description available"
|
|
bitfld.long 0x00 15. "FS2,HOST only" "0,1"
|
|
bitfld.long 0x00 14. "ATDTW,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "SUTW,no description available" "0,1"
|
|
rbitfld.long 0x00 12. "Reserved_12,no description available" "0,1"
|
|
bitfld.long 0x00 11. "ASPE,HOST only" "0,1"
|
|
rbitfld.long 0x00 10. "Reserved_10,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ASP1,HOST only" "0,1"
|
|
bitfld.long 0x00 8. "ASP0,HOST only" "0,1"
|
|
rbitfld.long 0x00 7. "LR,no description available" "0,1"
|
|
bitfld.long 0x00 6. "IAA,HOST only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ASE,HOST only" "0,1"
|
|
bitfld.long 0x00 4. "PSE,HOST only" "0,1"
|
|
bitfld.long 0x00 3. "FS1,HOST only" "0,1"
|
|
bitfld.long 0x00 2. "FS0,HOST only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,no description available" "0,1"
|
|
bitfld.long 0x00 0. "RS,no description available" "0,1"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "USBSTS,no description available"
|
|
rbitfld.long 0x00 26.--31. "Reserved_26,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 25. "TI1,rwc" "0,1"
|
|
bitfld.long 0x00 24. "TI0,rwc" "0,1"
|
|
bitfld.long 0x00 20.--23. "Reserved_20,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19. "UPI,rwc" "0,1"
|
|
bitfld.long 0x00 18. "UAI,rwc" "0,1"
|
|
rbitfld.long 0x00 17. "Reserved_17,no description available" "0,1"
|
|
rbitfld.long 0x00 16. "NAKI,no description available" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 15. "AS,no description available" "0,1"
|
|
rbitfld.long 0x00 14. "PS,no description available" "0,1"
|
|
rbitfld.long 0x00 13. "RCL,no description available" "0,1"
|
|
rbitfld.long 0x00 12. "HCH,HOST only" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 11. "Reserved_11,no description available" "0,1"
|
|
bitfld.long 0x00 10. "ULPII,rwc" "0,1"
|
|
rbitfld.long 0x00 9. "Reserved_9,no description available" "0,1"
|
|
bitfld.long 0x00 8. "SLI,rwc" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "SRI,rwc" "0,1"
|
|
bitfld.long 0x00 6. "URI,rwc" "0,1"
|
|
bitfld.long 0x00 5. "AAI,rwc" "0,1"
|
|
bitfld.long 0x00 4. "SEI,rwc" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "FRI,rwc" "0,1"
|
|
bitfld.long 0x00 2. "PCI,rwc" "0,1"
|
|
bitfld.long 0x00 1. "UEI,rwc" "0,1"
|
|
bitfld.long 0x00 0. "UI,rwc" "0,1"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "USBINTR,no description available"
|
|
rbitfld.long 0x00 26.--31. "Reserved_26,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 25. "TIE1,no description available" "0,1"
|
|
bitfld.long 0x00 24. "TIE0,no description available" "0,1"
|
|
rbitfld.long 0x00 20.--23. "Reserved_20,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19. "UPE,Not use in Device mode" "0,1"
|
|
bitfld.long 0x00 18. "UAE,Not use in Device mode" "0,1"
|
|
rbitfld.long 0x00 17. "Reserved_17,no description available" "0,1"
|
|
rbitfld.long 0x00 16. "NAKE,no description available" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 15. "Reserved_15,Not define in DUT AS" "0,1"
|
|
rbitfld.long 0x00 14. "Reserved_14,Not define in DUT PS" "0,1"
|
|
rbitfld.long 0x00 13. "Reserved_13,Not define in DUT RCL" "0,1"
|
|
bitfld.long 0x00 12. "Reserved_12,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "Reserved_11,no description available" "0,1"
|
|
bitfld.long 0x00 10. "ULPE,ONLY used VUSB_HS_PHY_ULPI =1" "0,1"
|
|
bitfld.long 0x00 9. "Reserved_9,no description available" "0,1"
|
|
bitfld.long 0x00 8. "SLE,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "SRE,no description available" "0,1"
|
|
bitfld.long 0x00 6. "URE,no description available" "0,1"
|
|
bitfld.long 0x00 5. "AAE,HOST only" "0,1"
|
|
bitfld.long 0x00 4. "SEE,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "FRE,HOST only" "0,1"
|
|
bitfld.long 0x00 2. "PCE,no description available" "0,1"
|
|
bitfld.long 0x00 1. "UEE,rwc" "0,1"
|
|
bitfld.long 0x00 0. "UE,no description available" "0,1"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "FRINDEX,no description available"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,no description available"
|
|
hexmask.long.word 0x00 0.--13. 1. "FRINDEX,device RO Host RW"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "PERIODICLISTBASE,no description available"
|
|
hexmask.long.byte 0x00 25.--31. 1. "USBADR,no description available"
|
|
bitfld.long 0x00 24. "USBADRA,no description available" "0,1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "Reserved_0,no description available"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "ASYNCLISTADDR,no description available"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "EPBASE,no description available"
|
|
hexmask.long.word 0x00 0.--10. 1. "Reserved_0,no description available"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "TTCTRL,no description available"
|
|
rbitfld.long 0x00 31. "Reserved_31,no description available" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. "TTHA,no description available"
|
|
hexmask.long.tbyte 0x00 2.--23. 1. "Reserved_2,no description available"
|
|
bitfld.long 0x00 1. "TTAC,no description available" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "TTAS,no description available" "0,1"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "BURSTSIZE,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,no description available"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TXPBURST,no description available"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RXPBURST,no description available"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TXFILLTUNING,no description available"
|
|
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,no description available"
|
|
bitfld.long 0x00 16.--21. "TXFIFOTHRES,Only use in HOST & MPH mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 13.--15. "Reserved_13,no description available" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. "TXSCHHEALTH,Only use in HOST & MPH mode rwc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 7. "Reserved_7,no description available" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "TXSCHOH,Only use in HOST & MPH mode"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "TXTTFILLTUNING,no description available"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,no description available"
|
|
bitfld.long 0x00 8.--12. "TXTTSCHHEALTJ,Only use in HOST & MPH mode rwc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 5.--7. "Reserved_5,no description available" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "TXTTSCHOH,Only use in HOST & MPH mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "IC_USB,no description available"
|
|
bitfld.long 0x00 31. "IC8,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
|
|
bitfld.long 0x00 28.--30. "IC_VDD8,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 27. "IC7,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
|
|
bitfld.long 0x00 24.--26. "IC_VDD7,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. "IC6,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
|
|
bitfld.long 0x00 20.--22. "IC_VDD6,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19. "IC5,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
|
|
bitfld.long 0x00 16.--18. "IC_VDD5,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "IC4,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
|
|
bitfld.long 0x00 12.--14. "IC_VDD4,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "IC3,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
|
|
bitfld.long 0x00 8.--10. "IC_VDD3,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. "IC2,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
|
|
bitfld.long 0x00 4.--6. "IC_VDD2,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "IC1,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
|
|
bitfld.long 0x00 0.--2. "IC_VDD1,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "ULPI_VIEWPORT,no description available"
|
|
bitfld.long 0x00 31. "ULPIWU,Not available" "0,1"
|
|
bitfld.long 0x00 30. "ULPIRUN,Not available" "0,1"
|
|
bitfld.long 0x00 29. "ULPIRW,Not available" "0,1"
|
|
bitfld.long 0x00 28. "Reserved_28,Not available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "ULPISS,Not available" "0,1"
|
|
bitfld.long 0x00 24.--26. "ULPIPORT,Not available" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ULPIADDR,Not available"
|
|
hexmask.long.byte 0x00 8.--15. 1. "ULPIDATRD,Not available"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "ULPIDATWR,Not available"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "ENDPTNAK,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "EPTN,rwc"
|
|
hexmask.long.word 0x00 0.--15. 1. "EPRN,rwc"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "ENDPTNAKEN,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "EPTNE,Only 3 PHY max"
|
|
hexmask.long.word 0x00 0.--15. 1. "EPRNE,Only 3 PHY max"
|
|
repeat 8. (strings "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x184)++0x03
|
|
line.long 0x00 "PORTSC$1,no description available"
|
|
bitfld.long 0x00 30.--31. "PTS,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 29. "STS,no description available" "0,1"
|
|
bitfld.long 0x00 28. "PTW,no description available" "0,1"
|
|
rbitfld.long 0x00 26.--27. "PSPD,no description available" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 25. "PTS2,no description available" "0,1"
|
|
bitfld.long 0x00 24. "PFSC,no description available" "0,1"
|
|
bitfld.long 0x00 23. "PHCD,no description available" "0,1"
|
|
bitfld.long 0x00 22. "WKOC,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WKDS,no description available" "0,1"
|
|
bitfld.long 0x00 20. "WKCN,no description available" "0,1"
|
|
bitfld.long 0x00 16.--19. "PTC,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "PIC,no description available" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 13. "PO,no description available" "0,1"
|
|
bitfld.long 0x00 12. "PP,no description available" "0,1"
|
|
rbitfld.long 0x00 10.--11. "LS,no description available" "0,1,2,3"
|
|
rbitfld.long 0x00 9. "HSP,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PR,no description available" "0,1"
|
|
bitfld.long 0x00 7. "SUSP,no description available" "0,1"
|
|
bitfld.long 0x00 6. "FPR,no description available" "0,1"
|
|
bitfld.long 0x00 5. "OCC,no description available" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4. "OCA,no description available" "0,1"
|
|
rbitfld.long 0x00 3. "PEC,rwc" "0,1"
|
|
rbitfld.long 0x00 2. "PE,rwc" "0,1"
|
|
rbitfld.long 0x00 1. "CSC,rwc" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "CCS,no description available" "0,1"
|
|
repeat.end
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "OTGSC,no description available"
|
|
rbitfld.long 0x00 31. "Reserved_31,OTG not enable" "0,1"
|
|
bitfld.long 0x00 30. "DPIE,OTG not enable" "0,1"
|
|
bitfld.long 0x00 29. "OTGSC_1msE,OTG not enable" "0,1"
|
|
bitfld.long 0x00 28. "BSEIE,OTG not enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "BSVIE,OTG not enable" "0,1"
|
|
bitfld.long 0x00 26. "ASVIE,OTG not enable" "0,1"
|
|
bitfld.long 0x00 25. "AVVIE,OTG not enable" "0,1"
|
|
bitfld.long 0x00 24. "IDIE,OTG not enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23. "Reserved_23,OTG not enable" "0,1"
|
|
rbitfld.long 0x00 22. "DPIS,rwc" "0,1"
|
|
rbitfld.long 0x00 21. "OTGSC_1msS,rwc" "0,1"
|
|
rbitfld.long 0x00 20. "BSEIS,rwc" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 19. "BSVIS,rwc" "0,1"
|
|
rbitfld.long 0x00 18. "ASVIS,rwc" "0,1"
|
|
rbitfld.long 0x00 17. "AVVIS,rwc" "0,1"
|
|
rbitfld.long 0x00 16. "IDIS,rwc" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 15. "Reserved_15,OTG not enable" "0,1"
|
|
rbitfld.long 0x00 14. "DPS,OTG not enable" "0,1"
|
|
rbitfld.long 0x00 13. "OTGSC_1msT,OTG not enable" "0,1"
|
|
rbitfld.long 0x00 12. "BSE,OTG not enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 11. "BSV,OTG not enable" "0,1"
|
|
rbitfld.long 0x00 10. "ASV,OTG not enable" "0,1"
|
|
rbitfld.long 0x00 9. "AVV,OTG not enable" "0,1"
|
|
rbitfld.long 0x00 8. "ID,OTG not enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "HABA,OTG not enable" "0,1"
|
|
bitfld.long 0x00 6. "HADP,OTG not enable" "0,1"
|
|
bitfld.long 0x00 5. "IDPU,OTG not enable" "0,1"
|
|
bitfld.long 0x00 4. "DP,OTG not enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "OT,OTG not enable" "0,1"
|
|
bitfld.long 0x00 2. "HAAR,OTG not enable" "0,1"
|
|
bitfld.long 0x00 1. "VC,OTG not enable" "0,1"
|
|
bitfld.long 0x00 0. "VD,OTG not enable" "0,1"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "USBMODE,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,no description available"
|
|
bitfld.long 0x00 15. "SRT,no description available" "0,1"
|
|
bitfld.long 0x00 12.--14. "TXHSD,no description available" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 6.--11. "Reserved_6,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "VBPS,Only used in Host" "0,1"
|
|
bitfld.long 0x00 4. "SDIS,no description available" "0,1"
|
|
bitfld.long 0x00 3. "SLOM,no description available" "0,1"
|
|
bitfld.long 0x00 2. "ES,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CM,fix device mode" "0,1,2,3"
|
|
rgroup.long 0x1AC++0x03
|
|
line.long 0x00 "ENDPTSETUPSTAT,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "ENDPTSETUPSTAT,rwc"
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "ENDPTPRIME,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "PETB,rws"
|
|
hexmask.long.word 0x00 0.--15. 1. "PERB,rws"
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "ENDPTFLUSH,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "FETB,rws"
|
|
hexmask.long.word 0x00 0.--15. 1. "FERB,rws"
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "ENDPTSTAT,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "ETBR,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "ERBR,no description available"
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "ENDPTCOMPLETE,no description available"
|
|
hexmask.long.word 0x00 16.--31. 1. "ETCE,rwc"
|
|
hexmask.long.word 0x00 0.--15. 1. "ERCE,rwc"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "ENDPTCTRL0,no description available"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,no description available"
|
|
rbitfld.long 0x00 23. "TXE,no description available" "0,1"
|
|
rbitfld.long 0x00 20.--22. "Reserved_20,no description available" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 18.--19. "TXT,no description available" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 17. "Reserved_17,no description available" "0,1"
|
|
bitfld.long 0x00 16. "TXS,no description available" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,no description available"
|
|
rbitfld.long 0x00 7. "RXE,no description available" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "Reserved_4,no description available" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 2.--3. "RXT,no description available" "0,1,2,3"
|
|
rbitfld.long 0x00 1. "Reserved_1,no description available" "0,1"
|
|
bitfld.long 0x00 0. "RXS,no description available" "0,1"
|
|
repeat 15. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0x1C4)++0x03
|
|
line.long 0x00 "ENDPTCTRL$1,no description available"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,no description available"
|
|
bitfld.long 0x00 23. "TXE,no description available" "0,1"
|
|
rbitfld.long 0x00 22. "TXR,ws" "0,1"
|
|
bitfld.long 0x00 21. "TXI,no description available" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20. "Reserved_20,no description available" "0,1"
|
|
bitfld.long 0x00 18.--19. "TXT,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 17. "TXD,no description available" "0,1"
|
|
bitfld.long 0x00 16. "TXS,no description available" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,no description available"
|
|
bitfld.long 0x00 7. "RXE,no description available" "0,1"
|
|
rbitfld.long 0x00 6. "RXR,ws" "0,1"
|
|
bitfld.long 0x00 5. "RXI,no description available" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4. "Reserved_4,no description available" "0,1"
|
|
bitfld.long 0x00 2.--3. "RXT,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 1. "RXD,no description available" "0,1"
|
|
bitfld.long 0x00 0. "RXS,no description available" "0,1"
|
|
repeat.end
|
|
rgroup.long 0x200++0x03
|
|
line.long 0x00 "PHY_ID,no description available"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CID1,no description available"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CID0,no description available"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "PLL_Control_0,no description available"
|
|
bitfld.long 0x00 14.--15. "PLLVDD18,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 9.--13. "REFDIV,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--8. 1. "FBDIV,no description available"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "PLL_Control_1,no description available"
|
|
rbitfld.long 0x00 15. "PLL_READY,no description available" "0,1"
|
|
bitfld.long 0x00 14. "pll_contrl_by_pin,no description available" "0,1"
|
|
bitfld.long 0x00 13. "pu_pll,no description available" "0,1"
|
|
bitfld.long 0x00 12. "PLL_LOCK_BYPASS,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "DLL_RESET_BLK,no description available" "0,1"
|
|
bitfld.long 0x00 8.--10. "ICP,no description available" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "KVCO_EXT,no description available" "0,1"
|
|
bitfld.long 0x00 4.--6. "KVCO,no description available" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "CLK_BLK_EN,no description available" "0,1"
|
|
bitfld.long 0x00 2. "VCOCAL_START,no description available" "0,1"
|
|
bitfld.long 0x00 0.--1. "PLLCAL12,no description available" "0,1,2,3"
|
|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "Reserved_Addr3,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "Reserved_Bit_15_0,no description available"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "Tx_Channel_Contrl_0,no description available"
|
|
rbitfld.long 0x00 15. "ND,no description available" "0,1"
|
|
bitfld.long 0x00 14. "TXDATA_BLOCK_EN,no description available" "0,1"
|
|
bitfld.long 0x00 13. "RCAL_START,no description available" "0,1"
|
|
bitfld.long 0x00 12. "EXT_HS_RCAL_EN,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_FS_RCAL_EN,no description available" "0,1"
|
|
bitfld.long 0x00 8.--10. "IMPCAL_VTH,no description available" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--7. "EXT_HS_RCAL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "EXT_FS_RCAL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "Tx_Channel_Contrl_1,no description available"
|
|
rbitfld.long 0x00 12.--15. "ND,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "TXVDD15,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "TXVDD12,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 7. "LOWVDD_EN,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "AMP,no description available" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "CK60_PHSEL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "Tx_Channel_Contrl_2,no description available"
|
|
rbitfld.long 0x00 12.--15. "ND,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "DRV_SLEWRATE,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "IMP_CAL_DLY,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "FSDRV_EN,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "HSDRV_EN,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "Reserved_Addr7,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "Reserved_Bit_15_0,no description available"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "Rx_Channel_Contrl_0,no description available"
|
|
bitfld.long 0x00 15. "PHASE_FREEZE_DLY,no description available" "0,1"
|
|
bitfld.long 0x00 14. "USQ_LENGTH,no description available" "0,1"
|
|
bitfld.long 0x00 12.--13. "ACQ_LENGTH,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "SQ_LENGTH,no description available" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "DISCON_THRESH,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "SQ_THRESH,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "LPF_COEF,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "INTPI,no description available" "0,1,2,3"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "Rx_Channel_Contrl_1,no description available"
|
|
rbitfld.long 0x00 14.--15. "ND,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 13. "EARLY_VOS_ON_EN,no description available" "0,1"
|
|
bitfld.long 0x00 12. "RXDATA_BLOCK_EN,no description available" "0,1"
|
|
bitfld.long 0x00 11. "EDGE_DET_EN,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "CAP_SEL,no description available" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. "RXDATA_BLOCK_LENGTH,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "EDGE_DET_SEL,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 3. "CDR_COEF_SEL,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CDR_FASTLOCK_EN,no description available" "0,1"
|
|
bitfld.long 0x00 0.--1. "S2TO3_DLY_SEL,no description available" "0,1,2,3"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "Rx_Channel_Contrl_2,no description available"
|
|
hexmask.long.byte 0x00 9.--15. 1. "ND,no description available"
|
|
bitfld.long 0x00 8. "USQ_FILTER,no description available" "0,1"
|
|
bitfld.long 0x00 7. "SQ_CM_SEL,no description available" "0,1"
|
|
bitfld.long 0x00 6. "SAMPLER_CTRL,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SQ_BUFFER_EN,no description available" "0,1"
|
|
bitfld.long 0x00 4. "SQ_ALWAYS_ON,no description available" "0,1"
|
|
bitfld.long 0x00 2.--3. "RXVDD18,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RXVDD12,no description available" "0,1,2,3"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "Ana_Contrl_0,no description available"
|
|
rbitfld.long 0x00 10.--15. "ND,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--9. "BG_VSEL,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "DIG_SEL,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "TOPVDD18,no description available" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3. "VDD_USB2_DIG_TOP_SEL,no description available" "0,1"
|
|
bitfld.long 0x00 0.--2. "IPTAT_SEL,no description available" "0,1,2,3,4,5,6,7"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "Ana_Contrl_1,no description available"
|
|
rbitfld.long 0x00 15. "ND,no description available" "0,1"
|
|
bitfld.long 0x00 14. "PU_ANA,no description available" "0,1"
|
|
bitfld.long 0x00 13. "ANA_CONTrL_BY_PIN,no description available" "0,1"
|
|
bitfld.long 0x00 12. "SEL_LPFR,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "V2I_EXT,no description available" "0,1"
|
|
bitfld.long 0x00 8.--10. "V2I,no description available" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "R_ROTATE_SEL,no description available" "0,1"
|
|
bitfld.long 0x00 6. "STRESS_TEST_MODE,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "TESTMON_ANA,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "Reserved_Addr_C,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "Reserved_Bit_15_0,no description available"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "Digital_Control_0,no description available"
|
|
rbitfld.long 0x00 15. "FIFO_UF,no description available" "0,1"
|
|
rbitfld.long 0x00 14. "FIFO_OV,no description available" "0,1"
|
|
bitfld.long 0x00 13. "FS_EOP_MODE,no description available" "0,1"
|
|
bitfld.long 0x00 12. "HOST_DISCON_SEL1,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "HOST_DISCON_SEL0,no description available" "0,1"
|
|
bitfld.long 0x00 10. "FORCE_END_EN,no description available" "0,1"
|
|
bitfld.long 0x00 9. "EARLY_TX_EN,no description available" "0,1"
|
|
bitfld.long 0x00 8. "SYNCDET_WINDOW_EN,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CLK_SUSPEND_EN,no description available" "0,1"
|
|
bitfld.long 0x00 6. "HS_DRIBBLE_EN,no description available" "0,1"
|
|
bitfld.long 0x00 4.--5. "SYNC_NUM,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "FIFO_FILL_NUM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "Digital_Control_1,no description available"
|
|
bitfld.long 0x00 15. "FS_RX_ERROR_MODE2,no description available" "0,1"
|
|
bitfld.long 0x00 14. "FS_RX_ERROR_MODE1,no description available" "0,1"
|
|
bitfld.long 0x00 13. "FS_RX_ERROR_MODE,no description available" "0,1"
|
|
bitfld.long 0x00 12. "CLK_OUT_SEL,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_TX_CLK_SEL,no description available" "0,1"
|
|
bitfld.long 0x00 10. "ARC_DPDM_MODE,no description available" "0,1"
|
|
bitfld.long 0x00 9. "DP_PULLDOWN,no description available" "0,1"
|
|
bitfld.long 0x00 8. "DM_PULLDOWN,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "SYNC_IGNORE_SQ,no description available" "0,1"
|
|
bitfld.long 0x00 6. "SQ_RST_RX,no description available" "0,1"
|
|
bitfld.long 0x00 0.--5. "MON_SEL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "Digital_Control_2,no description available"
|
|
rbitfld.long 0x00 13.--15. "ND_15_13,no description available" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. "PAD_STRENGTH,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 6.--7. "ND,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 5. "LONG_EOP,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "novbus_dpdm00,no description available" "0,1"
|
|
bitfld.long 0x00 3. "DISABLE_EL16,no description available" "0,1"
|
|
bitfld.long 0x00 2. "ALIGN_FS_OUTEN,no description available" "0,1"
|
|
bitfld.long 0x00 1. "HS_HDL_SYNC,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "FS_HDL_OPMD,no description available" "0,1"
|
|
rgroup.long 0x248++0x03
|
|
line.long 0x00 "Reserved_Addr_12H,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "Reserved_Bit_15_0,no description available"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "Test_Contrl_and_Status_0,no description available"
|
|
bitfld.long 0x00 15. "TEST_DIG_LPBK,no description available" "0,1"
|
|
bitfld.long 0x00 14. "TEST_ANA_LPBK,no description available" "0,1"
|
|
bitfld.long 0x00 12.--13. "TEST_LENGTH_1_0,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 11. "TEST_BYPASS,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TEST_MODE_2_0,no description available" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEST_TX_PATTERN,no description available"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "Test_Contrl_and_Status_1,no description available"
|
|
rbitfld.long 0x00 15. "TEST_DONE,no description available" "0,1"
|
|
rbitfld.long 0x00 14. "TEST_FLAG,no description available" "0,1"
|
|
bitfld.long 0x00 13. "TEST_EN,no description available" "0,1"
|
|
bitfld.long 0x00 12. "TEST_RESET,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "ND,no description available" "0,1"
|
|
bitfld.long 0x00 8.--10. "TEST_SKIP_2_0,no description available" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "TEST_UTMI_SEL,no description available" "0,1"
|
|
bitfld.long 0x00 6. "TEST_SUSPENDM,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TEST_TX_BITSTUFF_EN,no description available" "0,1"
|
|
bitfld.long 0x00 4. "TEST_TERM_SELECT,no description available" "0,1"
|
|
bitfld.long 0x00 2.--3. "TEST_OP_MODE,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "TEST_XCVR_SELECT,no description available" "0,1,2,3"
|
|
rgroup.long 0x254++0x03
|
|
line.long 0x00 "Reserved_Addr_15H,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "Reserved_Bit_15_0,no description available"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "PHY_REG_CHGDTC_CONTRL,no description available"
|
|
hexmask.long.word 0x00 4.--15. 1. "ND,no description available"
|
|
bitfld.long 0x00 3. "ENABLE_SWITCH,no description available" "0,1"
|
|
bitfld.long 0x00 2. "PU_CHRG_DTC,no description available" "0,1"
|
|
bitfld.long 0x00 0.--1. "TESTMON_CHRGDTC,no description available" "0,1,2,3"
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "PHY_REG_OTG_CONTROL,no description available"
|
|
hexmask.long.word 0x00 5.--15. 1. "ND,no description available"
|
|
bitfld.long 0x00 4. "OTG_CONTROL_BY_PIN,no description available" "0,1"
|
|
bitfld.long 0x00 3. "PU_OTG,no description available" "0,1"
|
|
bitfld.long 0x00 0.--2. "TESTMON_OTG_2_0,no description available" "0,1,2,3,4,5,6,7"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "usb2_phy_mon0,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "PHY_MON,no description available"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "PHY_REG_CHGDTC_CONTRL_1,no description available"
|
|
bitfld.long 0x00 15. "DP_DM_SWAP_CTRL,no description available" "0,1"
|
|
rbitfld.long 0x00 14. "reserved_14,no description available" "0,1"
|
|
bitfld.long 0x00 12.--13. "PLLVDD12,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "VSRC_CHARGE,no description available" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "VDAT_CHARGE,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ENABLE_SWITCH_DP,no description available" "0,1"
|
|
bitfld.long 0x00 6. "ENABLE_SWITCH_DM,no description available" "0,1"
|
|
bitfld.long 0x00 5. "CDP_DM_AUTO_SWITCH,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PD_EN,no description available" "0,1"
|
|
bitfld.long 0x00 3. "DCP_EN,no description available" "0,1"
|
|
bitfld.long 0x00 2. "CDP_EN,no description available" "0,1"
|
|
rbitfld.long 0x00 0.--1. "reserved_0,no description available" "0,1,2,3"
|
|
rgroup.long 0x268++0x03
|
|
line.long 0x00 "Reserved_Addr_1aH,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "Reserved_Bit_15_0,no description available"
|
|
rgroup.long 0x26C++0x03
|
|
line.long 0x00 "Reserved_Addr_1bH,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "Reserved_Bit_15_0,no description available"
|
|
rgroup.long 0x270++0x03
|
|
line.long 0x00 "Reserved_Addr_1cH,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "Reserved_Bit_15_0,no description available"
|
|
rgroup.long 0x274++0x03
|
|
line.long 0x00 "Reserved_Addr_1dH,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "Reserved_Bit_15_0,no description available"
|
|
rgroup.long 0x278++0x03
|
|
line.long 0x00 "Internal_CID,no description available"
|
|
hexmask.long.byte 0x00 8.--15. 1. "ICID0,no description available"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ICID1,no description available"
|
|
rgroup.long 0x27C++0x03
|
|
line.long 0x00 "usb2_icid_reg1,no description available"
|
|
hexmask.long.byte 0x00 8.--15. 1. "ICID2,no description available"
|
|
bitfld.long 0x00 7. "PHY_OTG,no description available" "0,1"
|
|
bitfld.long 0x00 6. "PHY_CHG_DTC,no description available" "0,1"
|
|
bitfld.long 0x00 5. "PHY_HSIC,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PHY_ULPI,no description available" "0,1"
|
|
bitfld.long 0x00 3. "DIG_REGULATOR,no description available" "0,1"
|
|
bitfld.long 0x00 1.--2. "ND,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 0. "PHY_MULTIPORT,no description available" "0,1"
|
|
tree.end
|
|
tree "WDT"
|
|
base ad:0x48040000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "WDT_CR,Control Register"
|
|
bitfld.long 0x00 2.--4. "RPL,Reset pulse length" "0: 2 pclk cycles,1: 4 pclk cycles,2: 8 pclk cycles,3: 16 pclk cycles,4: 32 pclk cycles,5: 64 pclk cycles,6: 128 pclk cycles,7: 256 pclk cycles"
|
|
bitfld.long 0x00 1. "RMOD,Response mode" "0: Generate a system reset,1: First generate an interrupt and if it is not.."
|
|
newline
|
|
bitfld.long 0x00 0. "WDT_EN,WDT enable" "0: WDT disabled,1: WDT enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "WDT_TORR,Timeout Range Register"
|
|
bitfld.long 0x00 4.--7. "TOP_INIT,Timeout period for initialization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "TOP,Timeout period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "WDT_CCVR,Current Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "wdt_ccvr,This register when read is the current value of the internal counter"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "WDT_CRR,Counter Restart Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "wdt_crr,This register is used to restart the WDT counter"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "WDT_STAT,Interrupt Status Register"
|
|
bitfld.long 0x00 0. "wdt_stat,This register shows the interrupt status of the WDT" "0: Interrupt is inactive,1: Interrupt is active regardless of polarity"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "WDT_EOI,Interrupt Clear Register"
|
|
bitfld.long 0x00 0. "wdt_eoi,Clears the watchdog interrupt" "0,1"
|
|
repeat 4. (strings "5" "4" "3" "2" )(list 0x0 0x4 0x8 0xC )
|
|
rgroup.long ($2+0xE4)++0x03
|
|
line.long 0x00 "WDT_COMP_PARAM_$1,Component Parameters Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "data,no description available"
|
|
repeat.end
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "WDT_COMP_PARAM_1,Component Parameters Register 1"
|
|
bitfld.long 0x00 24.--28. "WDT_CNT_WIDTH,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20.--23. "WDT_DFLT_TOP_INIT,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "WDT_DFLT_TOP,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--12. "WDT_DFLT_RPL,no description available" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "APB_DATA_WIDTH,no description available" "0,1,2,3"
|
|
bitfld.long 0x00 7. "WDT_PAUSE,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "WDT_USE_FIX_TOP,no description available" "0,1"
|
|
bitfld.long 0x00 5. "WDT_HC_TOP,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "WDT_HC_RPL,no description available" "0,1"
|
|
bitfld.long 0x00 3. "WDT_HC_RMOD,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "WDT_DUAL_TOP,no description available" "0,1"
|
|
bitfld.long 0x00 1. "WDT_DFLT_RMOD,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDT_ALWAYS_EN,no description available" "0,1"
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "WDT_COMP_VERSION,Component Version Register"
|
|
hexmask.long 0x00 0.--31. 1. "wdt_comp_version,ASCII value for each number in the version followed by *"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "WDT_COMP_TYPE,Component Type Register"
|
|
hexmask.long 0x00 0.--31. 1. "wdt_comp_type,Component Type Register"
|
|
tree.end
|
|
autoindent.off
|
|
newline
|