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Gen4_R-Car_Trace32/2_Trunk/menxmc71xx.men
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: XMC71XX Specific Menu
; @Props: Released
; @Author: NEJ
; @Changelog: 2023-01-17 NEJ
; @Manufacturer: INFINEON - Infineon Technologies AG
; @Core: Cortex-M7F, Cortex-M0+
; @Chip: XMC7100DE272K4160-CM0+, XMC7100DE272K4160-CM7-0, XMC7100DE272K4160-CM7-1,
; XMC7100DF100K2112-CM0+, XMC7100DF100K2112-CM7-0, XMC7100DF100K2112-CM7-1,
; XMC7100DF100K4160-CM0+, XMC7100DF100K4160-CM7-0, XMC7100DF100K4160-CM7-1,
; XMC7100DF144K2112-CM0+, XMC7100DF144K2112-CM7-0, XMC7100DF144K2112-CM7-1,
; XMC7100DF144K4160-CM0+, XMC7100DF144K4160-CM7-0, XMC7100DF144K4160-CM7-1,
; XMC7100DF176K4160-CM0+, XMC7100DF176K4160-CM7-0, XMC7100DF176K4160-CM7-1,
; XMC7100E272K4160-CM0+, XMC7100E272K4160-CM7, XMC7100F100K1088-CM0+,
; XMC7100F100K1088-CM7, XMC7100F100K2112-CM0+, XMC7100F100K2112-CM7,
; XMC7100F100K4160-CM0+, XMC7100F100K4160-CM7, XMC7100F144K2112-CM0+,
; XMC7100F144K2112-CM7, XMC7100F144K4160-CM0+, XMC7100F144K4160-CM7,
; XMC7100F176K4160-CM0+, XMC7100F176K4160-CM7
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menxmc71xx.men 16339 2023-07-03 13:30:14Z pegold $
add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
if (CORENAME()=="CORTEXM7F")
(
popup "[:chip]Core Registers (Cortex-M7F)"
(
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M7F),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M7F),Memory Protection Unit (MPU)"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M7F),Nested Vectored Interrupt Controller (NVIC)"""
menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M7F),Floating-point Unit (FPU)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M7F),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M7F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M7F),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
)
else
(
popup "[:chip]Core Registers (Cortex-M0+)"
(
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
)
separator
menuitem "BACKUP;SRSS Backup Domain" "per , ""BACKUP (SRSS Backup Domain)"""
popup "CANFD;CAN Controller"
(
menuitem "CANFD0" "per , ""CANFD (CAN Controller),CANFD0"""
menuitem "CANFD1" "per , ""CANFD (CAN Controller),CANFD1"""
)
menuitem "CPUSS;CPU Subsystem" "per , ""CPUSS (CPU Subsystem)"""
menuitem "DMAC" "per , ""DMAC"""
popup "DW;Datawire Controller"
(
menuitem "DW0" "per , ""DW (Datawire Controller),DW0"""
menuitem "DW1" "per , ""DW (Datawire Controller),DW1"""
)
menuitem "EFUSE;EFUSE MXS40 Registers" "per , ""EFUSE (EFUSE MXS40 Registers)"""
menuitem "ETH0;Ethernet Interface" "per , ""ETH0 (Ethernet Interface)"""
menuitem "EVTGEN0;Event Generator" "per , ""EVTGEN0 (Event Generator)"""
menuitem "FAULT;Fault Structures" "per , ""FAULT (Fault Structures)"""
menuitem "FLASHC;Flash Controller" "per , ""FLASHC (Flash Controller)"""
menuitem "GPIO;GPIO Port Control/Configuration" "per , ""GPIO (General Purpose I/O Ports and Peripheral I/O Lines)"""
menuitem "HSIOM;High Speed IO Matrix" "per , ""HSIOM (High Speed IO Matrix)"""
popup "I2S;Inter-Integrated Sound Bus Controller"
(
menuitem "I2S0" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S0"""
menuitem "I2S1" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S1"""
menuitem "I2S2" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S2"""
)
menuitem "IPC" "per , ""IPC (Interprocessor Communication)"""
menuitem "LIN0;LIN" "per , ""LIN0"""
menuitem "PASS0;Programmable Analog Subsystem" "per , ""PASS0 (Programmable Analog Subsystem)"""
menuitem "PERI;Peripheral Interconnect" "per , ""PERI (Peripheral Interconnect)"""
menuitem "PERI_MS;Peripheral Interconnect Master Interface" "per , ""PERI_MS (Peripheral Interconnect Master Interface)"""
menuitem "PERI_PCLK;Peripheral PCLK" "per , ""PERI_PCLK (Peripheral PCLK)"""
menuitem "PROT;Protection" "per , ""PROT (Protection)"""
popup "SCB;Serial Communications Block (SPI/UART/I2C)"
(
menuitem "SCB0" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB0"""
menuitem "SCB1" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB1"""
menuitem "SCB2" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB2"""
menuitem "SCB3" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB3"""
menuitem "SCB4" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB4"""
menuitem "SCB5" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB5"""
menuitem "SCB6" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB6"""
menuitem "SCB7" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB7"""
menuitem "SCB8" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB8"""
menuitem "SCB9" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB9"""
menuitem "SCB10" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB10"""
)
menuitem "SDHC0;SD/eMMC Host Controller" "per , ""SDHC0 (SD/eMMC Host Controller)"""
menuitem "SMARTIO;Programmable IO Configuration" "per , ""SMARTIO (Programmable IO Configuration)"""
menuitem "SMIF0;Serial Memory Interface" "per , ""SMIF0 (Serial Memory Interface)"""
menuitem "SRSS;SRSS Core Registers" "per , ""SRSS (SRSS Core Registers)"""
menuitem "TCPWM0;Timer/Counter/PWM" "per , ""TCPWM0 (Timer/Counter/PWM)"""
)
)
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