455 lines
18 KiB
Plaintext
455 lines
18 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: S32G2-LLCE Specific Menu
|
|
; @Props: Released
|
|
; @Author: CEZ, KWI, DAB
|
|
; @Changelog: 2019-09-12 CEZ
|
|
; 2020-06-03 KWI
|
|
; 2022-02-28 DAB
|
|
; @Manufacturer: NXP - NXP Semiconductors
|
|
; @Core: Cortex-M0P
|
|
; @Chip: S32G233A-M0-0, S32G233A-M0-1, S32G233A-M0-2, S32G233A-M0-3,
|
|
; S32G234M-M0-0, S32G234M-M0-1, S32G234M-M0-2, S32G234M-M0-3,
|
|
; S32G254A-M0-0, S32G254A-M0-1, S32G254A-M0-2, S32G254A-M0-3,
|
|
; S32G274A-M0-0, S32G274A-M0-1, S32G274A-M0-2, S32G274A-M0-3
|
|
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: mens32g2-llce.men 16339 2023-07-03 13:30:14Z pegold $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M0+)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
|
|
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
|
|
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
|
|
menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
separator
|
|
popup "LLCE_BCAN"
|
|
(
|
|
menuitem "LLCE_BCAN_0" "per , ""LLCE_BCAN,LLCE_BCAN_0"""
|
|
menuitem "LLCE_BCAN_1" "per , ""LLCE_BCAN,LLCE_BCAN_1"""
|
|
menuitem "LLCE_BCAN_2" "per , ""LLCE_BCAN,LLCE_BCAN_2"""
|
|
menuitem "LLCE_BCAN_3" "per , ""LLCE_BCAN,LLCE_BCAN_3"""
|
|
menuitem "LLCE_BCAN_4" "per , ""LLCE_BCAN,LLCE_BCAN_4"""
|
|
menuitem "LLCE_BCAN_5" "per , ""LLCE_BCAN,LLCE_BCAN_5"""
|
|
menuitem "LLCE_BCAN_6" "per , ""LLCE_BCAN,LLCE_BCAN_6"""
|
|
menuitem "LLCE_BCAN_7" "per , ""LLCE_BCAN,LLCE_BCAN_7"""
|
|
menuitem "LLCE_BCAN_8" "per , ""LLCE_BCAN,LLCE_BCAN_8"""
|
|
menuitem "LLCE_BCAN_9" "per , ""LLCE_BCAN,LLCE_BCAN_9"""
|
|
menuitem "LLCE_BCAN_10" "per , ""LLCE_BCAN,LLCE_BCAN_10"""
|
|
menuitem "LLCE_BCAN_11" "per , ""LLCE_BCAN,LLCE_BCAN_11"""
|
|
menuitem "LLCE_BCAN_12" "per , ""LLCE_BCAN,LLCE_BCAN_12"""
|
|
menuitem "LLCE_BCAN_13" "per , ""LLCE_BCAN,LLCE_BCAN_13"""
|
|
menuitem "LLCE_BCAN_14" "per , ""LLCE_BCAN,LLCE_BCAN_14"""
|
|
menuitem "LLCE_BCAN_15" "per , ""LLCE_BCAN,LLCE_BCAN_15"""
|
|
)
|
|
menuitem "LLCE_RXLUT" "per , ""LLCE_RXLUT"""
|
|
menuitem "LLCE_INT_CONCENTRATOR" "per , ""LLCE_INTCONC"""
|
|
menuitem "LLCE_IRCM" "per , ""LLCE_IRCM"""
|
|
popup "LLCE_FIFO"
|
|
(
|
|
menuitem "LLCE_BLR_IN_FIFO_0" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_0"""
|
|
menuitem "LLCE_RX_IN_FIFO_0" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_0"""
|
|
menuitem "LLCE_RX_IN_FIFO_1" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_1"""
|
|
menuitem "LLCE_RX_IN_FIFO_2" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_2"""
|
|
menuitem "LLCE_RX_IN_FIFO_3" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_3"""
|
|
menuitem "LLCE_RX_IN_FIFO_4" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_4"""
|
|
menuitem "LLCE_RX_IN_FIFO_5" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_5"""
|
|
menuitem "LLCE_RX_IN_FIFO_6" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_6"""
|
|
menuitem "LLCE_RX_IN_FIFO_7" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_7"""
|
|
menuitem "LLCE_RX_IN_FIFO_8" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_8"""
|
|
menuitem "LLCE_RX_IN_FIFO_9" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_9"""
|
|
menuitem "LLCE_RX_IN_FIFO_10" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_10"""
|
|
menuitem "LLCE_RX_IN_FIFO_11" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_11"""
|
|
menuitem "LLCE_RX_IN_FIFO_12" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_12"""
|
|
menuitem "LLCE_RX_IN_FIFO_13" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_13"""
|
|
menuitem "LLCE_RX_IN_FIFO_14" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_14"""
|
|
menuitem "LLCE_RX_IN_FIFO_15" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_15"""
|
|
menuitem "LLCE_RX_IN_FIFO_16" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_16"""
|
|
menuitem "LLCE_RX_IN_FIFO_17" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_17"""
|
|
menuitem "LLCE_RX_IN_FIFO_18" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_18"""
|
|
menuitem "LLCE_RX_IN_FIFO_19" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_19"""
|
|
menuitem "LLCE_RX_IN_FIFO_20" "per , ""LLCE_FIFO,LLCE_RX_IN_FIFO_20"""
|
|
menuitem "LLCE_RX_OUT_FIFO_0" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_0"""
|
|
menuitem "LLCE_RX_OUT_FIFO_1" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_1"""
|
|
menuitem "LLCE_RX_OUT_FIFO_2" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_2"""
|
|
menuitem "LLCE_RX_OUT_FIFO_3" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_3"""
|
|
menuitem "LLCE_RX_OUT_FIFO_4" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_4"""
|
|
menuitem "LLCE_RX_OUT_FIFO_5" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_5"""
|
|
menuitem "LLCE_RX_OUT_FIFO_6" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_6"""
|
|
menuitem "LLCE_RX_OUT_FIFO_7" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_7"""
|
|
menuitem "LLCE_RX_OUT_FIFO_8" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_8"""
|
|
menuitem "LLCE_RX_OUT_FIFO_9" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_9"""
|
|
menuitem "LLCE_RX_OUT_FIFO_10" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_10"""
|
|
menuitem "LLCE_RX_OUT_FIFO_11" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_11"""
|
|
menuitem "LLCE_RX_OUT_FIFO_12" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_12"""
|
|
menuitem "LLCE_RX_OUT_FIFO_13" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_13"""
|
|
menuitem "LLCE_RX_OUT_FIFO_14" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_14"""
|
|
menuitem "LLCE_RX_OUT_FIFO_15" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_15"""
|
|
menuitem "LLCE_RX_OUT_FIFO_16" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_16"""
|
|
menuitem "LLCE_RX_OUT_FIFO_17" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_17"""
|
|
menuitem "LLCE_RX_OUT_FIFO_18" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_18"""
|
|
menuitem "LLCE_RX_OUT_FIFO_19" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_19"""
|
|
menuitem "LLCE_RX_OUT_FIFO_20" "per , ""LLCE_FIFO,LLCE_RX_OUT_FIFO_20"""
|
|
menuitem "LLCE_GENERIC_FIFO_0" "per , ""LLCE_FIFO,LLCE_GENERIC_FIFO_0"""
|
|
menuitem "LLCE_GENERIC_FIFO_1" "per , ""LLCE_FIFO,LLCE_GENERIC_FIFO_1"""
|
|
menuitem "LLCE_GENERIC_FIFO_2" "per , ""LLCE_FIFO,LLCE_GENERIC_FIFO_2"""
|
|
menuitem "LLCE_GENERIC_FIFO_3" "per , ""LLCE_FIFO,LLCE_GENERIC_FIFO_3"""
|
|
menuitem "LLCE_BLR_IN_FIFO_1" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_1"""
|
|
menuitem "LLCE_BLR_IN_FIFO_2" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_2"""
|
|
menuitem "LLCE_BLR_IN_FIFO_3" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_3"""
|
|
menuitem "LLCE_BLR_IN_FIFO_4" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_4"""
|
|
menuitem "LLCE_BLR_IN_FIFO_5" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_5"""
|
|
menuitem "LLCE_BLR_IN_FIFO_6" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_6"""
|
|
menuitem "LLCE_BLR_IN_FIFO_7" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_7"""
|
|
menuitem "LLCE_BLR_IN_FIFO_8" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_8"""
|
|
menuitem "LLCE_BLR_IN_FIFO_9" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_9"""
|
|
menuitem "LLCE_BLR_IN_FIFO_10" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_10"""
|
|
menuitem "LLCE_BLR_IN_FIFO_11" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_11"""
|
|
menuitem "LLCE_BLR_IN_FIFO_12" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_12"""
|
|
menuitem "LLCE_BLR_IN_FIFO_13" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_13"""
|
|
menuitem "LLCE_BLR_IN_FIFO_14" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_14"""
|
|
menuitem "LLCE_BLR_IN_FIFO_15" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_15"""
|
|
menuitem "LLCE_BLR_IN_FIFO_16" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_16"""
|
|
menuitem "LLCE_BLR_IN_FIFO_17" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_17"""
|
|
menuitem "LLCE_BLR_IN_FIFO_18" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_18"""
|
|
menuitem "LLCE_BLR_IN_FIFO_19" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_19"""
|
|
menuitem "LLCE_BLR_IN_FIFO_20" "per , ""LLCE_FIFO,LLCE_BLR_IN_FIFO_20"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_0" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_0"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_1" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_1"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_2" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_2"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_3" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_3"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_4" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_4"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_5" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_5"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_6" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_6"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_7" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_7"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_8" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_8"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_9" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_9"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_10" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_10"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_11" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_11"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_12" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_12"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_13" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_13"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_14" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_14"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_15" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_15"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_16" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_16"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_17" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_17"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_18" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_18"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_19" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_19"""
|
|
menuitem "LLCE_BLR_OUT_FIFO_20" "per , ""LLCE_FIFO,LLCE_BLR_OUT_FIFO_20"""
|
|
menuitem "LLCE_TX_ACK_FIFO_0" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_0"""
|
|
menuitem "LLCE_TX_ACK_FIFO_1" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_1"""
|
|
menuitem "LLCE_TX_ACK_FIFO_2" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_2"""
|
|
menuitem "LLCE_TX_ACK_FIFO_3" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_3"""
|
|
menuitem "LLCE_TX_ACK_FIFO_4" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_4"""
|
|
menuitem "LLCE_TX_ACK_FIFO_5" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_5"""
|
|
menuitem "LLCE_TX_ACK_FIFO_6" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_6"""
|
|
menuitem "LLCE_TX_ACK_FIFO_7" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_7"""
|
|
menuitem "LLCE_TX_ACK_FIFO_8" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_8"""
|
|
menuitem "LLCE_TX_ACK_FIFO_9" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_9"""
|
|
menuitem "LLCE_TX_ACK_FIFO_10" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_10"""
|
|
menuitem "LLCE_TX_ACK_FIFO_11" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_11"""
|
|
menuitem "LLCE_TX_ACK_FIFO_12" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_12"""
|
|
menuitem "LLCE_TX_ACK_FIFO_13" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_13"""
|
|
menuitem "LLCE_TX_ACK_FIFO_14" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_14"""
|
|
menuitem "LLCE_TX_ACK_FIFO_15" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_15"""
|
|
menuitem "LLCE_TX_ACK_FIFO_16" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_16"""
|
|
menuitem "LLCE_TX_ACK_FIFO_17" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_17"""
|
|
menuitem "LLCE_TX_ACK_FIFO_18" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_18"""
|
|
menuitem "LLCE_TX_ACK_FIFO_19" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_19"""
|
|
menuitem "LLCE_TX_ACK_FIFO_20" "per , ""LLCE_FIFO,LLCE_TX_ACK_FIFO_20"""
|
|
)
|
|
popup "LLCE_TXLUT"
|
|
(
|
|
menuitem "LLCE_TX_LUT_0" "per , ""LLCE_TXLUT,LLCE_TX_LUT_0"""
|
|
menuitem "LLCE_TX_LUT_1" "per , ""LLCE_TXLUT,LLCE_TX_LUT_1"""
|
|
menuitem "LLCE_TX_LUT_2" "per , ""LLCE_TXLUT,LLCE_TX_LUT_2"""
|
|
menuitem "LLCE_TX_LUT_3" "per , ""LLCE_TXLUT,LLCE_TX_LUT_3"""
|
|
menuitem "LLCE_TX_LUT_4" "per , ""LLCE_TXLUT,LLCE_TX_LUT_4"""
|
|
menuitem "LLCE_TX_LUT_5" "per , ""LLCE_TXLUT,LLCE_TX_LUT_5"""
|
|
menuitem "LLCE_TX_LUT_6" "per , ""LLCE_TXLUT,LLCE_TX_LUT_6"""
|
|
menuitem "LLCE_TX_LUT_7" "per , ""LLCE_TXLUT,LLCE_TX_LUT_7"""
|
|
menuitem "LLCE_TX_LUT_8" "per , ""LLCE_TXLUT,LLCE_TX_LUT_8"""
|
|
menuitem "LLCE_TX_LUT_9" "per , ""LLCE_TXLUT,LLCE_TX_LUT_9"""
|
|
menuitem "LLCE_TX_LUT_10" "per , ""LLCE_TXLUT,LLCE_TX_LUT_10"""
|
|
menuitem "LLCE_TX_LUT_11" "per , ""LLCE_TXLUT,LLCE_TX_LUT_11"""
|
|
menuitem "LLCE_TX_LUT_12" "per , ""LLCE_TXLUT,LLCE_TX_LUT_12"""
|
|
menuitem "LLCE_TX_LUT_13" "per , ""LLCE_TXLUT,LLCE_TX_LUT_13"""
|
|
menuitem "LLCE_TX_LUT_14" "per , ""LLCE_TXLUT,LLCE_TX_LUT_14"""
|
|
menuitem "LLCE_TX_LUT_15" "per , ""LLCE_TXLUT,LLCE_TX_LUT_15"""
|
|
)
|
|
popup "LLCE_LPSPI"
|
|
(
|
|
menuitem "LLCE_LPSPI_0" "per , ""LLCE_LPSPI,LLCE_LPSPI_0"""
|
|
menuitem "LLCE_LPSPI_1" "per , ""LLCE_LPSPI,LLCE_LPSPI_1"""
|
|
menuitem "LLCE_LPSPI_2" "per , ""LLCE_LPSPI,LLCE_LPSPI_2"""
|
|
menuitem "LLCE_LPSPI_3" "per , ""LLCE_LPSPI,LLCE_LPSPI_3"""
|
|
)
|
|
popup "LLCE_LINFLEXD"
|
|
(
|
|
menuitem "LLCE_LINFLEXD_0" "per , ""LLCE_LINFLEXD,LLCE_LINFLEXD_0"""
|
|
menuitem "LLCE_LINFLEXD_1" "per , ""LLCE_LINFLEXD,LLCE_LINFLEXD_1"""
|
|
menuitem "LLCE_LINFLEXD_2" "per , ""LLCE_LINFLEXD,LLCE_LINFLEXD_2"""
|
|
menuitem "LLCE_LINFLEXD_3" "per , ""LLCE_LINFLEXD,LLCE_LINFLEXD_3"""
|
|
)
|
|
menuitem "LLCE_FR" "per , ""LLCE_FR"""
|
|
menuitem "LLCE_TS" "per , ""LLCE_TS"""
|
|
menuitem "LLCE_CRC" "per , ""LLCE_CRC"""
|
|
menuitem "LLCE_STM" "per , ""LLCE_STM"""
|
|
menuitem "LLCE_SEMA42" "per , ""LLCE_SEMA42"""
|
|
popup "LLCE_SWT"
|
|
(
|
|
menuitem "LLCE_SWT_0" "per , ""LLCE_SWT,LLCE_SWT_0"""
|
|
menuitem "LLCE_SWT_1" "per , ""LLCE_SWT,LLCE_SWT_1"""
|
|
menuitem "LLCE_SWT_2" "per , ""LLCE_SWT,LLCE_SWT_2"""
|
|
menuitem "LLCE_SWT_3" "per , ""LLCE_SWT,LLCE_SWT_3"""
|
|
)
|
|
menuitem "LLCE_CORE_TO_CORE" "per , ""LLCE_CORE2CORE"""
|
|
menuitem "LLCE_SYSCTRL" "per , ""LLCE_SYSCTRL"""
|
|
menuitem "LLCE_AXBS" "per , ""LLCE_AXBS"""
|
|
)
|
|
)
|