352 lines
9.0 KiB
Plaintext
352 lines
9.0 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: PSoC 4100 Specific Menu
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; @Props: Released
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; @Author: KMB, DAB
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; @Changelog: 2021-08-31 KMB
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; 2022-01-20 DAB
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; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
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; @Core: Cortex-M0+
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; @Chip: CY8C414*
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menpsoc4100.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M0+)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
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menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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if (cpuis("CY8C4147*")||cpuis("CY8C4146A*"))
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(
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menuitem "CAN" "per , ""CAN (CAN Controller),CAN"""
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)
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if (cpuis("CY8C4149*"))
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(
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menuitem "CANFD0" "per , ""CANFD0 (CAN Controller),CANFD0"""
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)
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menuitem "CPUSS" "per , ""CPUSS (CPU Subsystem)"""
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if (cpuis("CY8C4146P*")||cpuis("CY8C4146L*")||cpuis("CY8C4147*")||cpuis("CY8C4146A*")||cpuis("CY8C4148*"))
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(
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menuitem "CSD0" "per , ""CSD0 (Capsense Controller),CSD0"""
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)
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popup "CTBM (Continuous Time Block Mini)"
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(
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menuitem "CTBM0" "per , ""CTBM (Continuous Time Block Mini),CTBM0"""
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if cpuis("CY8C4148*")
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(
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menuitem "CTBM1" "per , ""CTBM (Continuous Time Block Mini),CTBM1"""
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)
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)
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if (cpuis("CY8C4149*")||cpuis("CY8C4147*")||cpuis("CY8C4146A*")||cpuis("CY8C4148*"))
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(
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menuitem "DMAC" "per , ""DMAC (DataWire/DMA Controller),DMAC"""
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menuitem "EXCO" "per , ""EXCO (ECO+PLL as SRSSLT clk_eco external source),EXCO"""
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)
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menuitem "GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"""
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menuitem "HSIOM" "per , ""HSIOM (High Speed IO Matrix (HSIOM))"""
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if (cpuis("CY8C4149*"))
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(
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menuitem "I2S0" "per , ""I2S0 (I2S registers),I2S0"""
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)
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menuitem "LCD" "per , ""LCD (LCD Controller Block),LCD"""
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menuitem "LPCOMP" "per , ""LPCOMP (Low-power Comparator),LPCOMP"""
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if (cpuis("CY8C4148*"))
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(
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popup "MCA (Motor Control Accellerator)"
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(
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menuitem "MCA0" "per , ""MCA (Motor Control Accellerator),MCA0"""
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menuitem "MCA1" "per , ""MCA (Motor Control Accellerator),MCA1"""
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)
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)
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if (cpuis("CY8C4149*"))
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(
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popup "MSC (MultiSense Controller)"
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(
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menuitem "MSC0" "per , ""MSC (MultiSense Controller),MSC0"""
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menuitem "MSC1" "per , ""MSC (MultiSense Controller),MSC1"""
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)
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)
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popup "PASS (PASS top-level MMIO (DSABv2 INTR))"
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(
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menuitem "PASS0" "per , ""PASS (PASS top-level MMIO (DSABv2 INTR)),PASS0"""
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if cpuis("CY8C4148*")
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(
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menuitem "PASS1" "per , ""PASS (PASS top-level MMIO (DSABv2 INTR)),PASS1"""
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)
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)
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menuitem "PERI" "per , ""PERI (Peripheral Interconnect)"""
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menuitem "PRGIO" "per , ""PRGIO (Programmable IO configuration)"""
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popup "SAR (SAR ADC with Sequencer)"
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(
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menuitem "SAR0" "per , ""SAR (SAR ADC with Sequencer),SAR0"""
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if (cpuis("CY8C4148*"))
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(
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menuitem "SAR1" "per , ""SAR (SAR ADC with Sequencer),SAR1"""
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)
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)
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popup "SCB (Serial Communications Block (SPI/UART/I2C))"
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(
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menuitem "SCB0" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB0"""
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menuitem "SCB1" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB1"""
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menuitem "SCB2" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB2"""
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if (cpuis("CY8C4149*")||cpuis("CY8C4147*")||cpuis("CY8C4146A*")||cpuis("CY8C4148*"))
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(
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menuitem "SCB3" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB3"""
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menuitem "SCB4" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB4"""
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)
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)
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menuitem "SPCIF" "per , ""SPCIF (Flash Control Interface)"""
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menuitem "SRSSLT" "per , ""SRSSLT (System Resources Lite Subsystem)"""
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menuitem "TCPWM" "per , ""TCPWM (Timer/Counter/PWM),TCPWM"""
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menuitem "WCO" "per , ""WCO (32KHz Oscillator),WCO"""
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)
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)
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