596 lines
23 KiB
Plaintext
596 lines
23 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: Kinetis L Specific Menu
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; @Props: Released
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; @Author: BIC, KAP, KBR, KRW, PBU, JRK, DPR
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; @Changelog: 2015-06-23 PBU
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; 2016-02-08 JRK
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; 2017-11-07 BGI
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; @Manufacturer: NXP
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; @Core: Cortex-M0P
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; @Chip: KKL03Z32CAF4R, KKL03Z32CBF4R, KKL15Z128CAD4R, KKL17Z256CAL4R,
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; MKL02Z8VFG4, MKL02Z16VFG4, MKL02Z16VFK4, MKL02Z16VFM4,
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; MKL02Z32VFG4, MKL02Z32VFK4, MKL02Z32VFM4, MKL02Z32CAF4,
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; MKL02Z32CAF4R, MKL03Z8VFG4, MKL03Z8VFK4, MKL03Z16VFG4,
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; MKL03Z16VFK4, MKL03Z32VFG4, MKL03Z32VFK4, MKL03Z32CAF4R,
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; MKL04Z8VFK4, MKL04Z8VFM4, MKL04Z8VLC4, MKL04Z16VFK4,
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; MKL04Z16VFM4, MKL04Z16VLC4, MKL04Z16VLF4, MKL04Z32VFK4,
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; MKL04Z32VFM4, MKL04Z32VLC4, MKL04Z32VLF4, MKL05Z8VFK4,
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; MKL05Z8VFM4, MKL05Z8VLC4, MKL05Z16VFK4, MKL05Z16VFM4,
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; MKL05Z16VLC4, MKL05Z16VLF4, MKL05Z32VFK4, MKL05Z32VFM4,
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; MKL05Z32VLC4, MKL05Z32VLF4, MKL13Z32VLH4, MKL13Z32VLK4,
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; MKL13Z64VLH4, MKL13Z64VLK4, MK14LN32VLH4, MK14LN32VLK4,
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; MK14LN32VFM4, MK14LN32VFT4, MK14LN64VLH4, MK14LN64VLK4,
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; MK14LN64VFM4, MK14LN64VFT4, MKL14Z32VLH4, MKL14Z32VLK4,
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; MKL14Z32VFM4, MKL14Z32VFT4, MKL14Z64VLH4, MKL14Z64VLK4,
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; MKL14Z64VFM4, MKL14Z64VFT4, MK15LN32VLH4, MK15LN32VLK4,
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; MK15LN32VFM4, MK15LN32VFT4, MK15LN64VLH4, MK15LN64VLK4,
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; MK15LN64VFM4, MK15LN64VFT4, MK15LN128VLH4, MK15LN128VLK4,
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; MK15LN128VFM4, MK15LN128VFT4, MKL15Z32VLH4, MKL15Z32VLK4,
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; MKL15Z32VFM4, MKL15Z32VFT4, MKL15Z64VLH4, MKL15Z64VLK4,
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; MKL15Z64VFM4, MKL15Z64VFT4, MKL15Z128VLH4, MKL15Z128VLK4,
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; MKL15Z128VFM4, MKL15Z128VFT4, MKL15Z128CAD4R, MKL16Z32VFM4,
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; MKL16Z32VFT4, MKL16Z32VLH4, MKL16Z64VFM4, MKL16Z64VFT4,
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; MKL16Z64VLH4, MKL16Z128VFM4, MKL16Z128VFT4, MKL16Z128VLH4,
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; MKL16Z256VLH4, MKL16Z256VLK4, MKL16Z256VMP4, MKL17Z32VDA4,
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; MKL17Z32VFM4, MKL17Z32VFT4, MKL17Z32VLH4, MKL17Z32VMP4,
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; MKL17Z64VDA4, MKL17Z64VFM4, MKL17Z64VFT4, MKL17Z64VLH4,
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; MKL17Z64VMP4, MKL17Z128VFM4, MKL17Z128VFT4, MKL17Z128VLH4,
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; MKL17Z128VMP4, MKL17Z256VFM4, MKL17Z256VFT4, MKL17Z256VLH4,
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; MKL17Z256VMP4, MKL24Z32VFM4, MKL24Z32VFT4, MKL24Z32VLH4,
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; MKL24Z32VLK4, MKL24Z64VFM4, MKL24Z64VFT4, MKL24Z64VLH4,
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; MKL24Z64VLK4, MKL25Z32VFM4, MKL25Z32VFT4, MKL25Z32VLH4,
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; MKL25Z32VLK4, MKL25Z64VFM4, MKL25Z64VFT4, MKL25Z64VLH4,
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; MKL25Z64VLK4, MKL25Z128VFM4, MKL25Z128VFT4, MKL25Z128VLH4,
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; MKL25Z128VLK4, MKL26Z32VFM4, MKL26Z32VFT4, MKL26Z32VLH4,
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; MKL26Z64VFM4, MKL26Z64VFT4, MKL26Z64VLH4, MKL26Z128VFM4,
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; MKL26Z128VFT4, MKL26Z128VLH4, MKL26Z128VLL4, MKL26Z128VMC4,
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; MKL26Z128VMP4, MKL26Z128CAL4, MKL26Z256VLH4, MKL26Z256VLL4,
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; MKL26Z256VMC4, MKL26Z256VMP4, MKL27Z32VDA4, MKL27Z32VFM4,
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; MKL27Z32VFT4, MKL27Z32VLH4, MKL27Z32VMP4, MKL27Z64VDA4,
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; MKL27Z64VFM4, MKL27Z64VFT4, MKL27Z64VMP4, MKL27Z64VLH4,
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; MKL27Z128VFM4, MKL27Z128VFT4, MKL27Z128VLH4, MKL27Z128VMP4,
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; MKL27Z256VFM4, MKL27Z256VFT4, MKL27Z256VLH4, MKL27Z256VMP4,
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; MKL33Z128VLH4, MKL33Z128VMP4, MKL33Z256VLH4, MKL33Z256VMP4,
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; MKL34Z64VLH4, MKL34Z64VLL4, MKL36Z64VLH4, MKL36Z64VLL4,
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; MKL36Z128VLH4, MKL36Z128VLL4, MKL36Z128VMC4, MKL36Z256VLH4,
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; MKL36Z256VLL4, MKL36Z256VMC4, MKL36Z256VMP4, MKL43Z128VLH4,
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; MKL43Z128VMP4, MKL43Z256VLH4, MKL43Z256VMP4, MKL46Z128VLH4,
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; MKL46Z128VLL4, MKL46Z128VMC4, MKL46Z256VLH4, MKL46Z256VLL4,
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; MKL46Z256VMC4, MKL46Z256VMP4, MKL82Z128VLK7, MKL82Z128VMC7
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; MKL02Z16VFG4R, MKL02Z32VFG4R, MKL02Z32VFK4R, MKL02Z32VFM4R,
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; MKL02Z8VFG4R, MKL03Z16VFG4R, MKL03Z16VFK4R, MKL03Z32CBF4R,
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; MKL03Z32VFG4R, MKL03Z32VFK4R, MKL03Z8VFG4R, MKL04Z16VLC4R,
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; MKL04Z32VFK4R, MKL04Z32VFM4R, MKL04Z32VLC4R, MKL04Z32VLF4R,
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; MKL04Z8VLC4R, MKL05Z32VFK4R, MKL05Z32VFM4R, MKL05Z32VLC4R,
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; MKL05Z32VLF4R, MKL14Z32VFM4R, MKL14Z64VFM4R, MKL14Z64VFT4R,
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; MKL14Z64VLK4R, MKL15Z128VFM4R, MKL15Z128VLH4R, MKL15Z128VLK4R,
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; MKL15Z32VFM4R, MKL15Z64VFM4R, MKL16Z128VFM4R, MKL16Z128VFT4R,
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; MKL16Z128VLH4R, MKL16Z256VLH4R, MKL16Z256VMP4R, MKL16Z32VFT4R,
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; MKL16Z64VFM4R, MKL16Z64VFT4R, MKL16Z64VLH4R, MKL17Z128VFM4R,
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; MKL17Z128VLH4R, MKL17Z128VMP4R, MKL17Z256CAL4R, MKL17Z256VFT4R,
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; MKL17Z256VLH4R, MKL17Z256VMP4R, MKL17Z32VDA4R, MKL17Z32VFM4R,
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; MKL17Z64VDA4R, MKL17Z64VFM4R, MKL26Z128CAL4R, MKL26Z128VLH4R,
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; MKL26Z256VMC4R, MKL26Z64VFT4R, MKL27Z128VFM4R, MKL27Z128VLH4R,
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; MKL27Z256VFM4R, MKL27Z64VDA4R, MKL27Z64VLH4R, MKL28Z512VLL7,
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; MKL33Z128VLH4R, MKL33Z32VLH4, MKL33Z32VLK4, MKL33Z64VLH4,
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; MKL33Z64VLK4, MKL36Z128VLL4R, MKL36Z256VLL4R, MKL81Z128CBH7R,
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; MKL81Z128VLK7, MKL81Z128VMC7, MKL81Z128VMC7R, MKL82Z128VLK7R
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menkinetisl.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M0+)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
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menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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if cpuis("MKL0*")
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(
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popup "PORT;Port control and interrupts"
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(
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menuitem "PORT_A" "per , ""PORT (Port control and interrupts),PORT_A"""
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menuitem "PORT_B" "per , ""PORT (Port control and interrupts),PORT_B"""
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)
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)
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if cpuis("MKL1*")||cpuis("MKL2*")||cpuis("MKL3*")||cpuis("MKL4*")||cpuis("MKL8*")
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(
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popup "PORT;Port control and interrupts"
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(
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menuitem "PORT_A" "per , ""PORT (Port control and interrupts),PORT_A"""
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menuitem "PORT_B" "per , ""PORT (Port control and interrupts),PORT_B"""
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menuitem "PORT_C" "per , ""PORT (Port control and interrupts),PORT_C"""
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menuitem "PORT_D" "per , ""PORT (Port control and interrupts),PORT_D"""
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menuitem "PORT_E" "per , ""PORT (Port control and interrupts),PORT_E"""
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)
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)
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menuitem "SIM;System Integration Module" "per , ""SIM (System Integration Module)"""
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menuitem "SMC;System Mode Controller" "per , ""SMC (System Mode Controller)"""
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menuitem "PMC;Power Management Controller" "per , ""PMC (Power Management Controller)"""
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if !cpuis("MKL02*")
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(
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menuitem "LLWU;Low-Leakage Wake-up Unit" "per , ""LLWU (Low-Leakage Wake-up Unit)"""
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)
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menuitem "RCM;Reset Control Module" "per , ""RCM (Reset Control Module)"""
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menuitem "MCM;Miscellaneous Control Module" "per , ""MCM (Miscellaneous Control Module)"""
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if cpuis("MKL82Z*")
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(
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menuitem "MPU;Memory Protection Unit" "per , ""MPU (Memory Protection Unit)"""
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)
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popup "MTB;Micro Trace Buffer"
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(
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menuitem "MTB_RAM" "per , ""MTB (Micro Trace Buffer),MTB_RAM"""
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menuitem "MTB_DWT" "per , ""MTB (Micro Trace Buffer),MTB_DWT"""
|
|
menuitem "SYSTEM_ROM" "per , ""MTB (Micro Trace Buffer),SYSTEM_ROM"""
|
|
)
|
|
if !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
(
|
|
menuitem "DMAMUX;Direct Memory Access Multiplexer" "per , ""DMAMUX (Direct Memory Access Multiplexer)"""
|
|
if cpuis("MKL28*")||cpuis("MKL82*")
|
|
(
|
|
menuitem "eDMA;Enhanced Direct Memory Access " "per , ""eDMA (Enhanced Direct Memory Access)"""
|
|
)
|
|
else
|
|
(
|
|
popup "DMA;Direct Memory Access Controller Module"
|
|
(
|
|
menuitem "Channel_0" "per , ""DMA (Direct Memory Access Controller Module),Channel_0"""
|
|
menuitem "Channel_1" "per , ""DMA (Direct Memory Access Controller Module),Channel_1"""
|
|
menuitem "Channel_2" "per , ""DMA (Direct Memory Access Controller Module),Channel_2"""
|
|
menuitem "Channel_3" "per , ""DMA (Direct Memory Access Controller Module),Channel_3"""
|
|
)
|
|
)
|
|
)
|
|
if !cpuis("MKL28*")
|
|
(
|
|
menuitem "MCG;Multipurpose Clock Generator" "per , ""MCG (Multipurpose Clock Generator)"""
|
|
menuitem "OSC;Oscillator" "per , ""OSC (Oscillator)"""
|
|
)
|
|
menuitem "FTFA;Flash Memory Module" "per , ""FTFA (Flash Memory Module)"""
|
|
menuitem "ADC;Analog-to-Digital Converter" "per , ""ADC (Analog-to-Digital Converter)"""
|
|
menuitem "CMP;Comparator" "per , ""CMP (Comparator)"""
|
|
if cpuis("MKL03Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL28Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82Z*")
|
|
(
|
|
menuitem "VREF;Voltage Reference" "per , ""VREF (Voltage Reference)"""
|
|
)
|
|
if cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")||cpuis("MKL82Z*")||cpuis("KKL15*")||cpuis("MKL28*")
|
|
(
|
|
menuitem "DAC;Digital-to-Analog Converter" "per , ""DAC (Digital-to-Analog Converter)"""
|
|
)
|
|
popup "TPM;Timer / PWM Module"
|
|
(
|
|
menuitem "TPM_0" "per , ""TPM (Timer/PWM Module),TPM_0"""
|
|
menuitem "TPM_1" "per , ""TPM (Timer/PWM Module),TPM_1"""
|
|
if (cpuis("MKL13*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL17Z*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL34Z*"))||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")||cpuis("MKL28Z*")||cpuis("MKL82Z*")||cpuis("KKL15*")
|
|
(
|
|
menuitem "TPM_2" "per , ""TPM (Timer/PWM Module),TPM_2"""
|
|
)
|
|
)
|
|
if !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
(
|
|
menuitem "PIT;Periodic Interrupt Timer" "per , ""PIT (Periodic Interrupt Timer)"""
|
|
)
|
|
if cpuis("MKL28Z*")
|
|
(
|
|
menuitem "LPIT;Low Power Interrupt Timer" "per , ""LPIT (Low Power Interrupt Timer)"""
|
|
)
|
|
menuitem "LPTMR;Low Power Timer" "per , ""LPTMR (Low Power Timer)"""
|
|
if cpuis("MKL13*")||cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")||cpuis("MKL28Z*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")||cpuis("MKL82Z*")
|
|
(
|
|
menuitem "CRC;Cyclic Redundancy Check" "per , ""CRC (Cyclic Redundancy Check)"""
|
|
)
|
|
if cpuis("MKL82Z*")
|
|
(
|
|
menuitem "LTC;LP Trusted Cryptography" "per , ""LTC (LP Trusted Cryptography)"""
|
|
)
|
|
if !cpuis("MKL02*")
|
|
(
|
|
menuitem "RTC;Real Time Clock" "per , ""RTC (Real Time Clock)"""
|
|
)
|
|
if cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26Z*")||cpuis("MKL46Z*")||cpuis("MKL28Z*")
|
|
(
|
|
menuitem "USBOTG;Universal Serial Bus OTG Controller" "per , ""USBOTG (Universal Serial Bus OTG Controller)"""
|
|
)
|
|
if cpuis("MKL27Z*")||cpuis("MKL43Z*")
|
|
(
|
|
menuitem "USB-FS;Universal Serial Bus FS Subsystem" "per , ""USB-FS (Universal Serial Bus FS Subsystem)"""
|
|
)
|
|
if !cpuis("MKL28*")
|
|
(
|
|
popup "SPI;Serial Peripheral Interface"
|
|
(
|
|
menuitem "SPI_0" "per , ""SPI (Serial Peripheral Interface),SPI_0"""
|
|
if !cpuis("MKL02Z*")&&!cpuis("MKL03Z*")
|
|
(
|
|
menuitem "SPI_1" "per , ""SPI (Serial Peripheral Interface),SPI_1"""
|
|
)
|
|
)
|
|
)
|
|
if cpuis("MKL28*")
|
|
(
|
|
menuitem "LPI2C;Low Power Inter-Integrated Circuit" "per , ""LPI2C (Low Power Inter-Integrated Circuit)"""
|
|
)
|
|
else
|
|
(
|
|
popup "I2C;Inter-Integrated Circuit"
|
|
(
|
|
menuitem "I2C_0" "per , ""I2C (Inter-Integrated Circuit),I2C_0"""
|
|
if (!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*"))
|
|
(
|
|
menuitem "I2C_1" "per , ""I2C (Inter-Integrated Circuit),I2C_1"""
|
|
)
|
|
)
|
|
)
|
|
if cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82*")
|
|
(
|
|
popup "LPUART;Low Power UART"
|
|
(
|
|
menuitem "LPUART_0" "per , ""LPUART (Low Power UART),LPUART_0"""
|
|
if !cpuis("MKL03Z*")
|
|
(
|
|
menuitem "LPUART_1" "per , ""LPUART (Low Power UART),LPUART_1"""
|
|
)
|
|
if cpuis("MKL82Z*")
|
|
(
|
|
menuitem "LPUART_2" "per , ""LPUART (Low Power UART),LPUART_2"""
|
|
)
|
|
)
|
|
if !cpuis("MKL03Z*")
|
|
(
|
|
popup "UART;Universal Asynchronous Receiver/Transmitter"
|
|
(
|
|
menuitem "UART_2" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART_2"""
|
|
)
|
|
)
|
|
)
|
|
else if cpuis("MKL28Z*")
|
|
(
|
|
menuitem "LPUART;Low Power UART" "per , ""LPUART (Low Power UART)"""
|
|
)
|
|
if !cpuis("MKL03Z*")&&!cpuis("MKL17Z*")&&!cpuis("MKL27Z*")&&!cpuis("MKL33Z*")&&!cpuis("MKL43Z*")&&!cpuis("MKL28Z*")&&!cpuis("MKL82*")
|
|
(
|
|
popup "UART;Universal Asynchronous Receiver/Transmitter"
|
|
(
|
|
menuitem "UART_0" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART_0"""
|
|
if (!cpuis("MKL02*")&&!cpuis("MKL04*")&&!cpuis("MKL05*"))
|
|
(
|
|
menuitem "UART_1" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART_1"""
|
|
menuitem "UART_2" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART_2"""
|
|
)
|
|
)
|
|
)
|
|
if cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82Z*")
|
|
(
|
|
menuitem "FLEXIO" "per , ""FLEXIO"""
|
|
)
|
|
if cpuis("MKL16*")||cpuis("MKL26*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
(
|
|
menuitem "I2S;Integrated Interchip Sound" "per , ""I2S (Integrated Interchip Sound)"""
|
|
)
|
|
if cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")||cpuis("MKL43Z*")
|
|
(
|
|
menuitem "SAI (I2S);Synchronous Audio Interface" "per , ""SAI (I2S) (Synchronous Audio Interface)"""
|
|
)
|
|
if cpuis("MKL0*")
|
|
(
|
|
popup "GPIO;General-Purpose Input/Output"
|
|
(
|
|
menuitem "GPIO_A" "per , ""GPIO (General-Purpose Input/Output),GPIO_A"""
|
|
menuitem "GPIO_B" "per , ""GPIO (General-Purpose Input/Output),GPIO_B"""
|
|
)
|
|
)
|
|
if cpuis("MKL1*")||cpuis("MKL2*")||cpuis("MKL3*")||cpuis("MKL4*")||cpuis("MKL8*")||cpuis("KKL15Z*")
|
|
(
|
|
popup "GPIO;General-Purpose Input/Output"
|
|
(
|
|
menuitem "GPIO_A" "per , ""GPIO (General-Purpose Input/Output),GPIO_A"""
|
|
menuitem "GPIO_B" "per , ""GPIO (General-Purpose Input/Output),GPIO_B"""
|
|
menuitem "GPIO_C" "per , ""GPIO (General-Purpose Input/Output),GPIO_C"""
|
|
menuitem "GPIO_D" "per , ""GPIO (General-Purpose Input/Output),GPIO_D"""
|
|
menuitem "GPIO_E" "per , ""GPIO (General-Purpose Input/Output),GPIO_E"""
|
|
)
|
|
)
|
|
if !cpuis("MKL17Z*")&&!cpuis("MKL27Z*")&&!cpuis("MKL33Z*")&&!cpuis("MKL43Z*")
|
|
(
|
|
if cpuis("MKL0*")
|
|
(
|
|
popup "FGPIO;Fast General-Purpose Input/Output"
|
|
(
|
|
menuitem "FGPIO_A" "per , ""FGPIO (Fast General-Purpose Input/Output),FGPIO_A"""
|
|
menuitem "FGPIO_B" "per , ""FGPIO (Fast General-Purpose Input/Output),FGPIO_B"""
|
|
)
|
|
)
|
|
if cpuis("MKL1*")||cpuis("MKL2*")||cpuis("MKL3*")||cpuis("MKL4*")||cpuis("MKL8*")||cpuis("KKL15Z*")
|
|
(
|
|
popup "FGPIO;Fast General-Purpose Input/Output"
|
|
(
|
|
menuitem "FGPIO_A" "per , ""FGPIO (Fast General-Purpose Input/Output),FGPIO_A"""
|
|
menuitem "FGPIO_B" "per , ""FGPIO (Fast General-Purpose Input/Output),FGPIO_B"""
|
|
menuitem "FGPIO_C" "per , ""FGPIO (Fast General-Purpose Input/Output),FGPIO_C"""
|
|
menuitem "FGPIO_D" "per , ""FGPIO (Fast General-Purpose Input/Output),FGPIO_D"""
|
|
menuitem "FGPIO_E" "per , ""FGPIO (Fast General-Purpose Input/Output),FGPIO_E"""
|
|
)
|
|
)
|
|
)
|
|
if cpuis("MKL05Z*")||cpuis("MK15*")||cpuis("MKL15Z*")||cpuis("MKL16Z*")||cpuis("MKL25Z*")||cpuis("MKL26Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MKL28Z*")||cpuis("MKL82Z*")||cpuis("KKL15Z*")
|
|
(
|
|
menuitem "TSI;Touch Sense Input" "per , ""TSI (Touch Sense Input)"""
|
|
)
|
|
if cpuis("MKL34Z*")||cpuis("MKL33Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
(
|
|
menuitem "SLCD;LCD Controller" "per , ""SLCD (LCD Controller)"""
|
|
)
|
|
if cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
(
|
|
if cpuis("MKL28Z*")
|
|
(
|
|
menuitem "CAU;Cryptographic Acceleration Unit" "per , ""CAU (Cryptographic Acceleration Unit)"""
|
|
)
|
|
menuitem "EMV_SIM;Smart Card Interface Module" "per , ""EMV SIM (Smart Card Interface Module)"""
|
|
menuitem "INTMUX;Interrupt Multiplexer" "per , ""INTMUX (Interrupt Multiplexer)"""
|
|
menuitem "MMDVSQ;Memory-Mapped Divide and Square Root" "per , ""MMDVSQ (Memory-Mapped Divide and Square Root)"""
|
|
if cpuis("MKL28Z*")
|
|
(
|
|
menuitem "PCC;Peripheral Clock Controller" "per , ""PCC (Peripheral Clock Controller)"""
|
|
menuitem "SCG;System Clock Generator" "per , ""SCG (System Clock Generator)"""
|
|
menuitem "TRGMUX;Trigger MUX" "per , ""TRGMUX (Trigger MUX)"""
|
|
menuitem "SA-TRNG;True Random Number Generator" "per , ""SA-TRNG (Standalone True Random Number Generator)"""
|
|
)
|
|
if cpuis("MKL82Z*")
|
|
(
|
|
menuitem "TRNG;True Random Number Generator" "per , ""TRNG (True Random Number Generator)"""
|
|
)
|
|
menuitem "TSTMR;Time Stamp Timer Module" "per , ""TSTMR (Time Stamp Timer Module)"""
|
|
menuitem "USBFSOTG;Universal Serial Bus Full Speed" "per , ""USBFSOTG (Universal Serial Bus Full Speed OTG Controller)"""
|
|
menuitem "WDOG;Watchdog timer" "per , ""WDOG (Watchdog timer)"""
|
|
)
|
|
)
|
|
)
|