809 lines
25 KiB
Plaintext
809 lines
25 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: K32L Specific Menu
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; @Props: Released
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; @Author: KMB, PIW
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; @Changelog: 2021-09-10 KMB
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; 2022-02-23 PIW
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; @Manufacturer: NXP - NXP Semiconductors
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; @Core: Cortex-M4, Cortex-M0+
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; @Chip: K32L2A31VLH1A, K32L2A31VLL1A, K32L2A41VLH1A, K32L2A41VLL1A,
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; K32L2B11VFM0A ,K32L2B11VFT0A, K32L2B11VLH0A, K32L2B11VMP0A,
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; K32L2B21VFM0A, K32L2B21VFT0A, K32L2B21VLH0A, K32L2B21VMP0A,
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; K32L2B31VFM0A, K32L2B31VFT0A, K32L2B31VLH0A, K32L2B31VMP0A,
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; K32L3A60VPJ1A-CM0+, K32L3A60VPJ1A-CM4
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; @Copyright: (C) 1989-2021 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menkinetisk32l.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXM0+")
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(
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popup "[:chip]Core Registers (Cortex-M0+)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
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menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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else if (CORENAME()=="CORTEXM4")
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(
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popup "[:chip]Core Registers (Cortex-M4)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4),Nested Vectored Interrupt Controller"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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separator
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
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(
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menuitem "ADC0" "per , ""ADC0 (Analog-to-Digital Converter),ADC0"""
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)
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if (cpuis("K32L3A*-CM4"))
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(
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menuitem "AXBS0" "per , ""AXBS,AXBS0"""
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)
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
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(
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popup "CAU (Memory Mapped Cryptographic Acceleration Unit (MMCAU))"
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(
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menuitem "CAU0" "per , ""CAU (Memory Mapped Cryptographic Acceleration Unit (MMCAU)),CAU0"""
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if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
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(
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menuitem "CAU3" "per , ""CAU (Memory Mapped Cryptographic Acceleration Unit (MMCAU)),CAU3"""
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)
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)
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)
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if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
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(
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popup "CMP (High-Speed Comparator (CMP) Voltage Reference (VREF) Digital-to-Analog Converter (DAC) and Analog Mux (ANMUX))"
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(
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
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(
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menuitem "CMP0" "per , ""CMP (High-Speed Comparator (CMP) Voltage Reference (VREF) Digital-to-Analog Converter (DAC) and Analog Mux (ANMUX)),CMP0"""
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)
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
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(
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menuitem "CMP1" "per , ""CMP (High-Speed Comparator (CMP) Voltage Reference (VREF) Digital-to-Analog Converter (DAC) and Analog Mux (ANMUX)),CMP1"""
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)
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)
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)
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if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
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(
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menuitem "COREDEBUG" "per , ""COREDEBUG (Core Debug Registers),COREDEBUG"""
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)
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
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(
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menuitem "CRC" "per , ""CRC,CRC"""
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)
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
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(
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menuitem "DAC0" "per , ""DAC0 (12-Bit Digital-to-Analog Converter),DAC0"""
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)
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
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(
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popup "DMA (DMA Controller)"
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(
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if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
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(
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menuitem "DMA" "per , ""DMA (DMA Controller),DMA"""
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)
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM4"))
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(
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menuitem "DMA0" "per , ""DMA (DMA Controller),DMA0"""
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)
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if (cpuis("K32L3A*-CM0+"))
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(
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menuitem "DMA1" "per , ""DMA (DMA Controller),DMA1"""
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)
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)
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)
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
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(
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popup "DMAMUX (DMA_CH_MUX)"
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(
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM4"))
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(
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menuitem "DMAMUX0" "per , ""DMAMUX (DMA_CH_MUX),DMAMUX0"""
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)
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if (cpuis("K32L3A*-CM0+"))
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(
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menuitem "DMAMUX1" "per , ""DMAMUX (DMA_CH_MUX),DMAMUX1"""
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)
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)
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)
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if (cpuis("K32L3A*-CM4"))
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(
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menuitem "DWT" "per , ""DWT (Data Watchpoint and Trace Unit Registers),DWT"""
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)
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
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(
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popup "EMVSIM"
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(
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
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(
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menuitem "EMVSIM0" "per , ""EMVSIM,EMVSIM0"""
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)
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)
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)
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if (cpuis("K32L3A*-CM4"))
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(
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menuitem "ETM" "per , ""ETM (Embedded Trace Macrocell Registers),ETM"""
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)
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if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
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(
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menuitem "EWM" "per , ""EWM,EWM"""
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)
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if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+"))
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(
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popup "FGPIO (General Purpose Input/Output)"
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(
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if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
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(
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menuitem "FGPIOA" "per , ""FGPIO (General Purpose Input/Output),FGPIOA"""
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menuitem "FGPIOB" "per , ""FGPIO (General Purpose Input/Output),FGPIOB"""
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menuitem "FGPIOC" "per , ""FGPIO (General Purpose Input/Output),FGPIOC"""
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menuitem "FGPIOD" "per , ""FGPIO (General Purpose Input/Output),FGPIOD"""
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)
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menuitem "FGPIOE" "per , ""FGPIO (General Purpose Input/Output),FGPIOE"""
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)
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)
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
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(
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menuitem "FGPIOA" "per , ""FGPIOA (General Purpose Input/Output),FGPIOA"""
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)
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if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
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(
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menuitem "FB" "per , ""FLEXBUS (FB),FB"""
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)
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
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(
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popup "FLEXIO (The FLEXIO Memory Map/Register Definition can be found here.)"
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(
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if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
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(
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menuitem "FLEXIO" "per , ""FLEXIO (The FLEXIO Memory Map/Register Definition can be found here.),FLEXIO"""
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)
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
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(
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menuitem "FLEXIO0" "per , ""FLEXIO (The FLEXIO Memory Map/Register Definition can be found here.),FLEXIO0"""
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)
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)
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)
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if (cpuis("K32L3A*-CM4"))
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(
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menuitem "FPB" "per , ""FPB (Flash Patch and Breakpoint Unit Registers),FPB"""
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)
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if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
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(
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menuitem "FTFA" "per , ""FTFA (Flash Memory Interface),FTFA"""
|
|
menuitem "FTFA_FLASHCONFIG" "per , ""FTFA_FLASHCONFIG (Flash configuration field),FTFA_FLASHCONFIG"""
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "FTFE" "per , ""FTFE (Flash),FTFE"""
|
|
)
|
|
popup "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
|
|
(
|
|
menuitem "GPIOA" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOA"""
|
|
menuitem "GPIOB" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOB"""
|
|
menuitem "GPIOC" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOC"""
|
|
menuitem "GPIOD" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOD"""
|
|
menuitem "GPIOE" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOE"""
|
|
)
|
|
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
popup "I2C (Inter-Integrated Circuit)"
|
|
(
|
|
menuitem "I2C0" "per , ""I2C (Inter-Integrated Circuit),I2C0"""
|
|
menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit),I2C1"""
|
|
)
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "I2S0" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S0"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
|
|
(
|
|
popup "INTMUX (Interrupt Multiplexer)"
|
|
(
|
|
menuitem "INTMUX0" "per , ""INTMUX (Interrupt Multiplexer),INTMUX0"""
|
|
if (cpuis("K32L3A*-CM0+"))
|
|
(
|
|
menuitem "INTMUX1" "per , ""INTMUX (Interrupt Multiplexer),INTMUX1"""
|
|
)
|
|
)
|
|
)
|
|
if (cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "ITM" "per , ""ITM (Instrumentation Trace Macrocell Registers),ITM"""
|
|
)
|
|
if (cpuis("K32L2B11*")||cpuis("K32L2B31*"))
|
|
(
|
|
menuitem "LCD" "per , ""LCD (Segment Liquid Crystal Display),LCD"""
|
|
)
|
|
popup "LLWU (Low leakage wakeup unit)"
|
|
(
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
menuitem "LLWU" "per , ""LLWU (Low leakage wakeup unit),LLWU"""
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "LLWU0" "per , ""LLWU (Low leakage wakeup unit),LLWU0"""
|
|
menuitem "LLWU1" "per , ""LLWU (Low leakage wakeup unit),LLWU1"""
|
|
)
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "LPADC0" "per , ""LPADC,LPADC0"""
|
|
popup "LPCMP"
|
|
(
|
|
menuitem "LPCMP0" "per , ""LPCMP,LPCMP0"""
|
|
menuitem "LPCMP1" "per , ""LPCMP,LPCMP1"""
|
|
)
|
|
menuitem "LPDAC0" "per , ""LPDAC,LPDAC0"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
popup "LPI2C (The LPI2C Memory Map/Register Definition can be found here.)"
|
|
(
|
|
menuitem "LPI2C0" "per , ""LPI2C (The LPI2C Memory Map/Register Definition can be found here.),LPI2C0"""
|
|
menuitem "LPI2C1" "per , ""LPI2C (The LPI2C Memory Map/Register Definition can be found here.),LPI2C1"""
|
|
menuitem "LPI2C2" "per , ""LPI2C (The LPI2C Memory Map/Register Definition can be found here.),LPI2C2"""
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "LPI2C3" "per , ""LPI2C (The LPI2C Memory Map/Register Definition can be found here.),LPI2C3"""
|
|
)
|
|
)
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
|
|
(
|
|
popup "LPIT"
|
|
(
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "LPIT0" "per , ""LPIT,LPIT0"""
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "LPIT1" "per , ""LPIT,LPIT1"""
|
|
)
|
|
)
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
popup "LPSPI (The LPSPI Memory Map/Register Definition can be found here.)"
|
|
(
|
|
menuitem "LPSPI0" "per , ""LPSPI (The LPSPI Memory Map/Register Definition can be found here.),LPSPI0"""
|
|
menuitem "LPSPI1" "per , ""LPSPI (The LPSPI Memory Map/Register Definition can be found here.),LPSPI1"""
|
|
menuitem "LPSPI2" "per , ""LPSPI (The LPSPI Memory Map/Register Definition can be found here.),LPSPI2"""
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "LPSPI3" "per , ""LPSPI (The LPSPI Memory Map/Register Definition can be found here.),LPSPI3"""
|
|
)
|
|
)
|
|
)
|
|
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
popup "LPTMR (Low Power Timer)"
|
|
(
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "LPTMR0" "per , ""LPTMR (Low Power Timer),LPTMR0"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "LPTMR1" "per , ""LPTMR (Low Power Timer),LPTMR1"""
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "LPTMR2" "per , ""LPTMR (Low Power Timer),LPTMR2"""
|
|
)
|
|
)
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
popup "LPTPM (TPM)"
|
|
(
|
|
menuitem "TPM0" "per , ""LPTPM (TPM),TPM0"""
|
|
menuitem "TPM1" "per , ""LPTPM (TPM),TPM1"""
|
|
menuitem "TPM2" "per , ""LPTPM (TPM),TPM2"""
|
|
menuitem "TPM3" "per , ""LPTPM (TPM),TPM3"""
|
|
)
|
|
)
|
|
popup "LPUART"
|
|
(
|
|
menuitem "LPUART0" "per , ""LPUART,LPUART0"""
|
|
menuitem "LPUART1" "per , ""LPUART,LPUART1"""
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "LPUART2" "per , ""LPUART,LPUART2"""
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "LPUART3" "per , ""LPUART,LPUART3"""
|
|
)
|
|
)
|
|
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
menuitem "MCG" "per , ""MCG (Multipurpose Clock Generator Lite),MCG"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
|
|
(
|
|
popup "MCM (Core Platform Miscellaneous Control Module)"
|
|
(
|
|
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
menuitem "MCM" "per , ""MCM (Core Platform Miscellaneous Control Module),MCM"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "MCM0" "per , ""MCM (Core Platform Miscellaneous Control Module),MCM0"""
|
|
)
|
|
if (cpuis("K32L3A*-CM0+"))
|
|
(
|
|
menuitem "MCM1" "per , ""MCM (Core Platform Miscellaneous Control Module),MCM1"""
|
|
)
|
|
)
|
|
popup "MMDVSQ (Divide and Square Root)"
|
|
(
|
|
menuitem "MMDVSQ0" "per , ""MMDVSQ (Divide and Square Root),MMDVSQ0"""
|
|
if (cpuis("K32L3A*-CM0+"))
|
|
(
|
|
menuitem "MMDVSQ1" "per , ""MMDVSQ (Divide and Square Root),MMDVSQ1"""
|
|
)
|
|
)
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "MSCM" "per , ""MSCM,MSCM"""
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
popup "MSMC (crr_cmc0)"
|
|
(
|
|
menuitem "SMC0" "per , ""MSMC (crr_cmc0),SMC0"""
|
|
menuitem "SMC1" "per , ""MSMC (crr_cmc0),SMC1"""
|
|
)
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
|
|
(
|
|
popup "MTB (Micro Trace Buffer)"
|
|
(
|
|
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+"))
|
|
(
|
|
menuitem "MTB" "per , ""MTB (Micro Trace Buffer),MTB"""
|
|
)
|
|
menuitem "MTB0" "per , ""MTB (Micro Trace Buffer),MTB0"""
|
|
)
|
|
menuitem "MTB0_DWT" "per , ""MTB0_DWT (MTB data watchpoint and trace),MTB0_DWT"""
|
|
menuitem "MTB0_ROM" "per , ""MTB0_ROM (System ROM),MTB0_ROM"""
|
|
)
|
|
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+"))
|
|
(
|
|
menuitem "MTBDWT" "per , ""MTBDWT (DWT),MTBDWT"""
|
|
)
|
|
if (cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "MUA" "per , ""MUA (Messaging Unit Processor A-side),MUA"""
|
|
)
|
|
if (cpuis("K32L3A*-CM0+"))
|
|
(
|
|
menuitem "MUB" "per , ""MUB (Messaging Unit Processor B-side),MUB"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
|
|
(
|
|
popup "NVIC (Nested Vectored Interrupt Controller)"
|
|
(
|
|
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "NVIC" "per , ""NVIC (Nested Vectored Interrupt Controller),NVIC"""
|
|
)
|
|
menuitem "NVIC0" "per , ""NVIC (Nested Vectored Interrupt Controller),NVIC0"""
|
|
)
|
|
)
|
|
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
menuitem "OSC0" "per , ""OSC0 (Oscillator),OSC0"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
popup "PCC"
|
|
(
|
|
menuitem "PCC0" "per , ""PCC,PCC0"""
|
|
menuitem "PCC1" "per , ""PCC,PCC1"""
|
|
)
|
|
)
|
|
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
menuitem "PIT" "per , ""PIT (Periodic Interrupt Timer),PIT"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
menuitem "PMC" "per , ""PMC (Power Management Controller),PMC"""
|
|
)
|
|
popup "PORT (Pin Control and Interrupts)"
|
|
(
|
|
menuitem "PORTA" "per , ""PORT (Pin Control and Interrupts),PORTA"""
|
|
menuitem "PORTB" "per , ""PORT (Pin Control and Interrupts),PORTB"""
|
|
menuitem "PORTC" "per , ""PORT (Pin Control and Interrupts),PORTC"""
|
|
menuitem "PORTD" "per , ""PORT (Pin Control and Interrupts),PORTD"""
|
|
menuitem "PORTE" "per , ""PORT (Pin Control and Interrupts),PORTE"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
menuitem "RCM" "per , ""RCM (Reset Control Module),RCM"""
|
|
menuitem "RFSYS" "per , ""RFSYS (System register file),RFSYS"""
|
|
)
|
|
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+"))
|
|
(
|
|
menuitem "ROM" "per , ""ROM,ROM"""
|
|
)
|
|
menuitem "RTC" "per , ""RTC (Real-time Counter),RTC"""
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "SYSTEMCONTROL" "per , ""SCB (System Control Block),SYSTEMCONTROL"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "SCG" "per , ""SCG,SCG"""
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
popup "SEMA42 (sema42_ips)"
|
|
(
|
|
menuitem "SEMA420" "per , ""SEMA42 (sema42_ips),SEMA420"""
|
|
menuitem "SEMA421" "per , ""SEMA42 (sema42_ips),SEMA421"""
|
|
)
|
|
)
|
|
menuitem "SIM" "per , ""SIM,SIM"""
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
menuitem "SMC" "per , ""SMC (System Mode Controller),SMC"""
|
|
)
|
|
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
popup "SPI (Serial Peripheral Interface)"
|
|
(
|
|
menuitem "SPI0" "per , ""SPI (Serial Peripheral Interface),SPI0"""
|
|
menuitem "SPI1" "per , ""SPI (Serial Peripheral Interface),SPI1"""
|
|
)
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "SPM" "per , ""SPM,SPM"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
menuitem "SYSTEMCONTROL" "per , ""SYSTEMCONTROL (System Control Block),SYSTEMCONTROL"""
|
|
)
|
|
menuitem "SYSTICK" "per , ""SYSTICK (System timer)"""
|
|
if (cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "TPIU" "per , ""TPIU (Trace Port Interface Unit Registers),TPIU"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
popup "TPM (Timer/PWM Module)"
|
|
(
|
|
menuitem "TPM0" "per , ""TPM (Timer/PWM Module),TPM0"""
|
|
menuitem "TPM1" "per , ""TPM (Timer/PWM Module),TPM1"""
|
|
menuitem "TPM2" "per , ""TPM (Timer/PWM Module),TPM2"""
|
|
)
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
popup "TRGMUX"
|
|
(
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "TRGMUX0" "per , ""TRGMUX,TRGMUX0"""
|
|
menuitem "TRGMUX1" "per , ""TRGMUX,TRGMUX1"""
|
|
)
|
|
)
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "TRNG" "per , ""TRNG,TRNG"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
|
|
(
|
|
menuitem "TSI0" "per , ""TSI0 (Touch sense input),TSI0"""
|
|
menuitem "TSTMR0" "per , ""TSTMR0 (Timestamp Timer),TSTMR0"""
|
|
)
|
|
if (cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "TSTMRA" "per , ""TSTMRA,TSTMRA"""
|
|
)
|
|
if (cpuis("K32L3A*-CM0+"))
|
|
(
|
|
menuitem "TSTMRB" "per , ""TSTMRB,TSTMRB"""
|
|
)
|
|
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
menuitem "UART2" "per , ""UART2 (Serial Communication Interface),UART2"""
|
|
)
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
|
|
(
|
|
menuitem "USB0" "per , ""USB0 (Universal Serial Bus OTG Capable Controller),USB0"""
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "USB0" "per , ""USBFSOTG (USB),USB0"""
|
|
menuitem "USBVREG" "per , ""USBVREG,USBVREG"""
|
|
menuitem "USDHC0" "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC0"""
|
|
)
|
|
menuitem "VREF" "per , ""VREF,VREF"""
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
|
|
(
|
|
popup "WDOG (Watchdog Timer Unit)"
|
|
(
|
|
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "WDOG0" "per , ""WDOG (Watchdog Timer Unit),WDOG0"""
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "WDOG1" "per , ""WDOG (Watchdog Timer Unit),WDOG1"""
|
|
)
|
|
)
|
|
)
|
|
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
|
|
(
|
|
menuitem "XRDC" "per , ""XRDC,XRDC"""
|
|
)
|
|
)
|
|
)
|