598 lines
24 KiB
Plaintext
598 lines
24 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: IMX8ULP Specific Menu
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; @Props: Released
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; @Author: KWI, KMB, JON
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; @Changelog: 2020-07-30 KWI
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; 2020-10-15 KWI
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; 2021-04-07 KWI
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; 2021-08-11 KMB
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; 2022-01-25 JON
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; @Manufacturer: NXP - NXP Semiconductors
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; @Core: Cortex-A35, Cortex-M33F
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; @Chip: IMX8UD3, IMX8UD3-CM33, IMX8UD5, IMX8UD5-CM33,
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; IMX8UD7, IMX8UD7-CM33, IMX8US3, IMX8US3-CM33,
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; IMX8US5, IMX8US5-CM33
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menimx8ulp.men 17486 2024-02-13 16:49:15Z jhuang $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXA35")
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(
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popup "[:chip]Core Registers (Cortex-A35)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller System Registers[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Generic Interrupt Controller System Registers"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller System Registers[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Generic Interrupt Controller System Registers"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A35),Interrupt Controller (GIC-500)"""
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)
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)
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else
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(
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popup "[:chip]Core Registers (Cortex-M33F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M33F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M33F),Memory Protection Unit (MPU)"""
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menuitem "[:chip]SAU;Security Attribution Unit" "per , ""Core Registers (Cortex-M33F),Security Attribution Unit (SAU)"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M33F),Nested Vectored Interrupt Controller (NVIC)"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M33F),Floating-point Unit (FPU)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M33F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M33F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M33F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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separator
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popup "ADC"
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(
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menuitem "ADC0" "per , ""ADC,ADC0"""
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menuitem "ADC1" "per , ""ADC,ADC1"""
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)
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popup "AHB_ADDR_REMAP"
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(
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menuitem "ADDR_REMAP0" "per , ""AHB_ADDR_REMAP,ADDR_REMAP0"""
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menuitem "ADDR_REMAP1" "per , ""AHB_ADDR_REMAP,ADDR_REMAP1"""
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)
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popup "AXBS"
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(
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menuitem "AXBS0" "per , ""AXBS,AXBS0"""
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menuitem "AXBS1" "per , ""AXBS,AXBS1"""
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)
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menuitem "BBNSM" "per , ""BBNSM"""
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popup "CAC (XCACHE)"
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(
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menuitem "CACHE64_CTRL0" "per , ""CAC (XCACHE),CACHE64_CTRL0"""
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menuitem "CACHE64_CTRL1" "per , ""CAC (XCACHE),CACHE64_CTRL1"""
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)
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menuitem "CAN0" "per , ""CAN"""
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menuitem "CASPER" "per , ""CASPER"""
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popup "CGC (AD_CGC)"
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(
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menuitem "CGC_AD" "per , ""CGC (AD_CGC),CGC_AD"""
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menuitem "CGC_LPAV" "per , ""CGC (AD_CGC),CGC_LPAV"""
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menuitem "CGC_RTD" "per , ""CGC (AD_CGC),CGC_RTD"""
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)
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popup "CMC (CMC1)"
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(
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menuitem "CMC_AD" "per , ""CMC (CMC1),CMC_AD"""
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menuitem "CMC_LPAC" "per , ""CMC (CMC1),CMC_LPAC"""
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menuitem "CMC_RTD" "per , ""CMC (CMC1),CMC_RTD"""
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)
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popup "CMP"
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(
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menuitem "CMP0" "per , ""CMP,CMP0"""
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menuitem "CMP1" "per , ""CMP,CMP1"""
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)
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menuitem "MIPI_CSI2RX" "per , ""CSI_PHY_REG (CSI2_RX)"""
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popup "DAC"
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(
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menuitem "DAC0" "per , ""DAC,DAC0"""
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menuitem "DAC1" "per , ""DAC,DAC1"""
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)
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menuitem "LCDIF" "per , ""DCNANO (LCDIF)"""
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menuitem "MIPI_DSI" "per , ""DSI_HOST"""
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menuitem "DSI_REG__DSI_HOST_APB_PKT_IF" "per , ""DSI_HOST_APB_PKT_IF"""
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menuitem "DSI_REG__DSI_HOST_DBI_INTFC" "per , ""DSI_HOST_DBI_INTFC"""
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menuitem "DSI_REG__DSI_HOST_DPI_INTFC" "per , ""DSI_HOST_DPI_INTFC"""
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menuitem "DSI_REG__DSI_HOST_NXP_IP2B_DPHY_INTFC" "per , ""DSI_HOST_NXP_IP2B_DPHY_INTFC"""
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menuitem "DMA0" "per , ""EDMA0_MP (DMA MP)"""
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menuitem "DMA0_TCD" "per , ""EDMA0_TCD (DMA TCD)"""
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menuitem "DMA1" "per , ""EDMA1_MP (DMA MP)"""
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menuitem "DMA1_TCD" "per , ""EDMA1_TCD (DMA TCD)"""
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menuitem "DMA2" "per , ""EDMA2_MP (DMA MP)"""
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menuitem "DMA2_TCD" "per , ""EDMA2_TCD (DMA TCD)"""
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menuitem "ENET" "per , ""ENET (Ethernet MAC)"""
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if cpuis("IMX8UD3-CM33")||cpuis("IMX8UD3")||cpuis("IMX8UD7")||cpuis("IMX8UD7-CM33")||cpuis("IMX8US3")||cpuis("IMX8US3-CM33")
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(
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menuitem "EPDC" "per , ""EPDC,EPDC"""
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)
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menuitem "EWM0" "per , ""EWM"""
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popup "FLEXIO"
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(
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menuitem "FLEXIO0" "per , ""FLEXIO,FLEXIO0"""
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menuitem "FLEXIO1" "per , ""FLEXIO,FLEXIO1"""
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)
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popup "FLEXSPI (FlexSPI)"
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(
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menuitem "FLEXSPI0" "per , ""FLEXSPI (FlexSPI),FLEXSPI0"""
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menuitem "FLEXSPI1" "per , ""FLEXSPI (FlexSPI),FLEXSPI1"""
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menuitem "FLEXSPI2" "per , ""FLEXSPI (FlexSPI),FLEXSPI2"""
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)
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popup "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
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(
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menuitem "GPIOA" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOA"""
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menuitem "GPIOB" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOB"""
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menuitem "GPIOC" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOC"""
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menuitem "GPIOD" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOD"""
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menuitem "GPIOE" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOE"""
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menuitem "GPIOF" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOF"""
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)
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popup "I3C"
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(
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menuitem "I3C0" "per , ""I3C,I3C0"""
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menuitem "I3C1" "per , ""I3C,I3C1"""
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menuitem "I3C2" "per , ""I3C,I3C2"""
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)
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popup "IOMUX (IOMUXC rtd)"
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(
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menuitem "IOMUXC0" "per , ""IOMUX (IOMUXC rtd),IOMUXC0"""
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menuitem "IOMUXC1" "per , ""IOMUX (IOMUXC rtd),IOMUXC1"""
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)
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menuitem "ISI0" "per , ""ISI (ISI Memory Map)"""
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menuitem "LPDDR" "per , ""LPDDR (DATABAHN_REGS)"""
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popup "LPI2C"
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(
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menuitem "LPI2C0" "per , ""LPI2C,LPI2C0"""
|
|
menuitem "LPI2C1" "per , ""LPI2C,LPI2C1"""
|
|
menuitem "LPI2C2" "per , ""LPI2C,LPI2C2"""
|
|
menuitem "LPI2C3" "per , ""LPI2C,LPI2C3"""
|
|
menuitem "LPI2C4" "per , ""LPI2C,LPI2C4"""
|
|
menuitem "LPI2C5" "per , ""LPI2C,LPI2C5"""
|
|
menuitem "LPI2C6" "per , ""LPI2C,LPI2C6"""
|
|
menuitem "LPI2C7" "per , ""LPI2C,LPI2C7"""
|
|
)
|
|
popup "LPIT"
|
|
(
|
|
menuitem "LPIT0" "per , ""LPIT,LPIT0"""
|
|
menuitem "LPIT1" "per , ""LPIT,LPIT1"""
|
|
)
|
|
popup "LPSPI"
|
|
(
|
|
menuitem "LPSPI0" "per , ""LPSPI,LPSPI0"""
|
|
menuitem "LPSPI1" "per , ""LPSPI,LPSPI1"""
|
|
menuitem "LPSPI2" "per , ""LPSPI,LPSPI2"""
|
|
menuitem "LPSPI3" "per , ""LPSPI,LPSPI3"""
|
|
menuitem "LPSPI4" "per , ""LPSPI,LPSPI4"""
|
|
menuitem "LPSPI5" "per , ""LPSPI,LPSPI5"""
|
|
)
|
|
popup "LPTMR"
|
|
(
|
|
menuitem "LPTMR0" "per , ""LPTMR,LPTMR0"""
|
|
menuitem "LPTMR1" "per , ""LPTMR,LPTMR1"""
|
|
)
|
|
popup "LPUART"
|
|
(
|
|
menuitem "LPUART0" "per , ""LPUART,LPUART0"""
|
|
menuitem "LPUART1" "per , ""LPUART,LPUART1"""
|
|
menuitem "LPUART2" "per , ""LPUART,LPUART2"""
|
|
menuitem "LPUART3" "per , ""LPUART,LPUART3"""
|
|
menuitem "LPUART4" "per , ""LPUART,LPUART4"""
|
|
menuitem "LPUART5" "per , ""LPUART,LPUART5"""
|
|
menuitem "LPUART6" "per , ""LPUART,LPUART6"""
|
|
menuitem "LPUART7" "per , ""LPUART,LPUART7"""
|
|
)
|
|
menuitem "MCM" "per , ""MCM"""
|
|
menuitem "MIPI_CSI_CSR" "per , ""MIPI_CSI_CSR (MIPI CSI CSR module)"""
|
|
menuitem "MRT0" "per , ""MRT (Multi-Rate Timer (MRT))"""
|
|
popup "MU (MUA)"
|
|
(
|
|
if cpuis("IMX8UD3-CM33")||cpuis("IMX8UD5-CM33")||cpuis("IMX8UD7-CM33")||cpuis("IMX8US3-CM33")||cpuis("IMX8US5-CM33")
|
|
(
|
|
menuitem "MU0_MUA" "per , ""MU (MUA),MU0_MUA"""
|
|
)
|
|
if cpuis("IMX8UD3")||cpuis("IMX8UD5")||cpuis("IMX8UD7")||cpuis("IMX8US3")||cpuis("IMX8US5")
|
|
(
|
|
menuitem "MU0_MUB" "per , ""MU (MUA),MU0_MUB"""
|
|
)
|
|
if cpuis("IMX8UD3-CM33")||cpuis("IMX8UD5-CM33")||cpuis("IMX8UD7-CM33")||cpuis("IMX8US3-CM33")||cpuis("IMX8US5-CM33")
|
|
(
|
|
menuitem "MU1_MUA" "per , ""MU (MUA),MU1_MUA"""
|
|
)
|
|
if cpuis("IMX8UD3")||cpuis("IMX8UD5")||cpuis("IMX8UD7")||cpuis("IMX8US3")||cpuis("IMX8US5")
|
|
(
|
|
menuitem "MU1_MUB" "per , ""MU (MUA),MU1_MUB"""
|
|
)
|
|
if cpuis("IMX8UD3-CM33")||cpuis("IMX8UD5-CM33")||cpuis("IMX8UD7-CM33")||cpuis("IMX8US3-CM33")||cpuis("IMX8US5-CM33")
|
|
(
|
|
menuitem "MU2_MUA" "per , ""MU (MUA),MU2_MUA"""
|
|
)
|
|
if cpuis("IMX8UD3")||cpuis("IMX8UD5")||cpuis("IMX8UD7")||cpuis("IMX8US3")||cpuis("IMX8US5")
|
|
(
|
|
menuitem "MU2_MUB" "per , ""MU (MUA),MU2_MUB"""
|
|
)
|
|
if cpuis("IMX8UD3-CM33")||cpuis("IMX8UD5-CM33")||cpuis("IMX8UD7-CM33")||cpuis("IMX8US3-CM33")||cpuis("IMX8US5-CM33")
|
|
(
|
|
menuitem "MU3_MUA" "per , ""MU (MUA),MU3_MUA"""
|
|
)
|
|
if cpuis("IMX8UD3")||cpuis("IMX8UD5")||cpuis("IMX8UD7")||cpuis("IMX8US3")||cpuis("IMX8US5")
|
|
(
|
|
menuitem "MU3_MUB" "per , ""MU (MUA),MU3_MUB"""
|
|
)
|
|
)
|
|
menuitem "OCOTP_CTRL" "per , ""OCOTP_CTRL (OCOTP Controller)"""
|
|
popup "PCC"
|
|
(
|
|
menuitem "PCC0" "per , ""PCC,PCC0"""
|
|
menuitem "PCC1" "per , ""PCC,PCC1"""
|
|
menuitem "PCC2" "per , ""PCC,PCC2"""
|
|
menuitem "PCC3" "per , ""PCC,PCC3"""
|
|
menuitem "PCC4" "per , ""PCC,PCC4"""
|
|
menuitem "PCC5" "per , ""PCC,PCC5"""
|
|
)
|
|
menuitem "PDM" "per , ""PDM (Pulse Density Modulation (Digital Microphone) Interface)"""
|
|
popup "PHY (USBPHY)"
|
|
(
|
|
menuitem "USB0_PHY" "per , ""PHY (USBPHY),USB0_PHY"""
|
|
menuitem "USB1_PHY" "per , ""PHY (USBPHY),USB1_PHY"""
|
|
)
|
|
menuitem "POWERQ" "per , ""POWERQ (PowerQuad)"""
|
|
menuitem "PXP" "per , ""PXP"""
|
|
popup "SAI"
|
|
(
|
|
menuitem "SAI0" "per , ""SAI,SAI0"""
|
|
menuitem "SAI1" "per , ""SAI,SAI1"""
|
|
menuitem "SAI2" "per , ""SAI,SAI2"""
|
|
menuitem "SAI3" "per , ""SAI,SAI3"""
|
|
menuitem "SAI4" "per , ""SAI,SAI4"""
|
|
menuitem "SAI5" "per , ""SAI,SAI5"""
|
|
menuitem "SAI6" "per , ""SAI,SAI6"""
|
|
menuitem "SAI7" "per , ""SAI,SAI7"""
|
|
)
|
|
popup "SEMA42"
|
|
(
|
|
menuitem "SEMA42_0" "per , ""SEMA42,SEMA42_0"""
|
|
menuitem "SEMA42_1" "per , ""SEMA42,SEMA42_1"""
|
|
menuitem "SEMA42_2" "per , ""SEMA42,SEMA42_2"""
|
|
)
|
|
popup "SFA (Signal Frequency Analyser)"
|
|
(
|
|
menuitem "SFA0" "per , ""SFA (Signal Frequency Analyser),SFA0"""
|
|
menuitem "SFA1" "per , ""SFA (Signal Frequency Analyser),SFA1"""
|
|
menuitem "SFA2" "per , ""SFA (Signal Frequency Analyser),SFA2"""
|
|
)
|
|
popup "SIM (APD_SIM)"
|
|
(
|
|
menuitem "SIM_AD" "per , ""SIM (APD_SIM),SIM_AD"""
|
|
menuitem "SIM_LPAV" "per , ""SIM (APD_SIM),SIM_LPAV"""
|
|
menuitem "SIM_RTD" "per , ""SIM (APD_SIM),SIM_RTD"""
|
|
)
|
|
menuitem "SPDIF" "per , ""SPDIF (Sony/Philips Digital Interface)"""
|
|
popup "SYSPM"
|
|
(
|
|
menuitem "SYSPM0" "per , ""SYSPM,SYSPM0"""
|
|
menuitem "SYSPM1" "per , ""SYSPM,SYSPM1"""
|
|
)
|
|
popup "TPM"
|
|
(
|
|
menuitem "TPM0" "per , ""TPM,TPM0"""
|
|
menuitem "TPM1" "per , ""TPM,TPM1"""
|
|
menuitem "TPM2" "per , ""TPM,TPM2"""
|
|
menuitem "TPM3" "per , ""TPM,TPM3"""
|
|
menuitem "TPM4" "per , ""TPM,TPM4"""
|
|
menuitem "TPM5" "per , ""TPM,TPM5"""
|
|
menuitem "TPM6" "per , ""TPM,TPM6"""
|
|
menuitem "TPM7" "per , ""TPM,TPM7"""
|
|
menuitem "TPM8" "per , ""TPM,TPM8"""
|
|
)
|
|
menuitem "TRDC" "per , ""TRDC"""
|
|
popup "TRGMUX_ (TRGMUX)"
|
|
(
|
|
menuitem "TRGMUX0" "per , ""TRGMUX_ (TRGMUX),TRGMUX0"""
|
|
menuitem "TRGMUX1" "per , ""TRGMUX_ (TRGMUX),TRGMUX1"""
|
|
)
|
|
popup "TSTMR (TIMESTAMP)"
|
|
(
|
|
menuitem "TSTMR0__TIMESTAMP0" "per , ""TSTMR (TIMESTAMP),TSTMR0__TIMESTAMP0"""
|
|
menuitem "TSTMR1__TIMESTAMP0" "per , ""TSTMR (TIMESTAMP),TSTMR1__TIMESTAMP0"""
|
|
)
|
|
menuitem "USB_XBAR" "per , ""USB_XBAR (USB)"""
|
|
menuitem "USBNC_XBAR" "per , ""USB_XBARNC (USBNC)"""
|
|
menuitem "USB0" "per , ""USB0C (USB)"""
|
|
menuitem "USBNC0" "per , ""USB0NC (USBNC)"""
|
|
menuitem "USB1" "per , ""USB1C (USB)"""
|
|
menuitem "USBNC1" "per , ""USB1NC (USBNC)"""
|
|
popup "USBDCD"
|
|
(
|
|
menuitem "USBDCD0" "per , ""USBDCD,USBDCD0"""
|
|
menuitem "USBDCD1" "per , ""USBDCD,USBDCD1"""
|
|
)
|
|
popup "USDHC (Ultra Secured Digital Host Controller)"
|
|
(
|
|
menuitem "USDHC0" "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC0"""
|
|
menuitem "USDHC1" "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC1"""
|
|
menuitem "USDHC2" "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC2"""
|
|
)
|
|
popup "WDOG (Watchdog Timer Unit)"
|
|
(
|
|
menuitem "WDOG0" "per , ""WDOG (Watchdog Timer Unit),WDOG0"""
|
|
menuitem "WDOG1" "per , ""WDOG (Watchdog Timer Unit),WDOG1"""
|
|
menuitem "WDOG2" "per , ""WDOG (Watchdog Timer Unit),WDOG2"""
|
|
menuitem "WDOG3" "per , ""WDOG (Watchdog Timer Unit),WDOG3"""
|
|
menuitem "WDOG4" "per , ""WDOG (Watchdog Timer Unit),WDOG4"""
|
|
menuitem "WDOG5" "per , ""WDOG (Watchdog Timer Unit),WDOG5"""
|
|
)
|
|
popup "WUU"
|
|
(
|
|
menuitem "WUU0" "per , ""WUU,WUU0"""
|
|
menuitem "WUU1" "per , ""WUU,WUU1"""
|
|
)
|
|
menuitem "XRDC" "per , ""XRDC"""
|
|
)
|
|
)
|