659 lines
39 KiB
Plaintext
659 lines
39 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: AM62x Specific Menu
|
|
; @Props: Released
|
|
; @Author: NEJ
|
|
; @Changelog: 2022-09-07 NEJ
|
|
; @Manufacturer: TI - Texas Instruments
|
|
; @Core: CortexA53, CortexR5F, CortexM4F, PRU
|
|
; @Chip: AM623X, AM623X-CR5, AM623X-CM4-BLAZAR, AM623X-CM4-SMS0,
|
|
; AM623X-CM4-SMS1, AM623X-ICSS0, AM625X, AM625X-CR5,
|
|
; AM625X-CM4-BLAZAR, AM625X-CM4-SMS0, AM625X-CM4-SMS1, AM625X-ICSS0
|
|
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: menam62x.men 16339 2023-07-03 13:30:14Z pegold $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
if (!cpuis("AM62*X-ICSS0"))
|
|
(
|
|
if (CORENAME()=="CORTEXA53")
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-A53)"
|
|
(
|
|
menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,ID Registers"""
|
|
menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration"""
|
|
menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit"""
|
|
menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions"""
|
|
menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration"""
|
|
menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor"""
|
|
menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers"""
|
|
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface"""
|
|
separator
|
|
menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers"""
|
|
separator
|
|
menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers"""
|
|
menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers"""
|
|
separator
|
|
menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,ID Registers"""
|
|
menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration"""
|
|
menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit"""
|
|
menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions"""
|
|
menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration"""
|
|
menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor"""
|
|
menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers"""
|
|
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface"""
|
|
separator
|
|
menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers"""
|
|
separator
|
|
menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers"""
|
|
menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers"""
|
|
)
|
|
)
|
|
else if (CORENAME()=="CORTEXR5F")
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-R5F)"
|
|
(
|
|
menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R5F),ID Registers"""
|
|
menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R5F),System Control and Configuration"""
|
|
menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R5F),MPU Control and Configuration"""
|
|
menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R5F),Cache Control and Configuration"""
|
|
menuitem "[:chip]TCM Control and Configuration" "per , ""Core Registers (Cortex-R5F),TCM Control and Configuration"""
|
|
menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R5F),System Performance Monitor"""
|
|
separator
|
|
menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R5F),Debug Registers"""
|
|
menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R5F),Breakpoint Registers"""
|
|
menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-R5F),Watchpoint Control Registers"""
|
|
)
|
|
)
|
|
else if (CORENAME()=="CORTEXM4F")
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M4F)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
|
|
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
|
|
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
|
|
menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
|
|
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
)
|
|
)
|
|
separator
|
|
if (cpuis("AM62*X"))
|
|
(
|
|
menuitem "A53_RS_BW_LIMITER0_REGS" "per , ""A53_RS_BW_LIMITER0_REGS"""
|
|
menuitem "A53_WS_BW_LIMITER1_REGS" "per , ""A53_WS_BW_LIMITER1_REGS"""
|
|
menuitem "A53SS0_CORE0_CTI" "per , ""A53SS0_CORE0_CTI"""
|
|
menuitem "A53SS0_CORE0_DBG" "per , ""A53SS0_CORE0_DBG"""
|
|
menuitem "A53SS0_CORE0_ECC_AGGR" "per , ""A53SS0_CORE0_ECC_AGGR"""
|
|
menuitem "A53SS0_CORE0_ETM" "per , ""A53SS0_CORE0_ETM"""
|
|
menuitem "A53SS0_CORE0_PMU" "per , ""A53SS0_CORE0_PMU"""
|
|
menuitem "A53SS0_CORE1_CTI" "per , ""A53SS0_CORE1_CTI"""
|
|
menuitem "A53SS0_CORE1_DBG" "per , ""A53SS0_CORE1_DBG"""
|
|
menuitem "A53SS0_CORE1_ECC_AGGR" "per , ""A53SS0_CORE1_ECC_AGGR"""
|
|
menuitem "A53SS0_CORE1_ETM" "per , ""A53SS0_CORE1_ETM"""
|
|
menuitem "A53SS0_CORE1_PMU" "per , ""A53SS0_CORE1_PMU"""
|
|
menuitem "A53SS0_CORE2_CTI" "per , ""A53SS0_CORE2_CTI"""
|
|
menuitem "A53SS0_CORE2_DBG" "per , ""A53SS0_CORE2_DBG"""
|
|
menuitem "A53SS0_CORE2_ECC_AGGR" "per , ""A53SS0_CORE2_ECC_AGGR"""
|
|
menuitem "A53SS0_CORE2_ETM" "per , ""A53SS0_CORE2_ETM"""
|
|
menuitem "A53SS0_CORE2_PMU" "per , ""A53SS0_CORE2_PMU"""
|
|
menuitem "A53SS0_CORE3_CTI" "per , ""A53SS0_CORE3_CTI"""
|
|
menuitem "A53SS0_CORE3_DBG" "per , ""A53SS0_CORE3_DBG"""
|
|
menuitem "A53SS0_CORE3_ECC_AGGR" "per , ""A53SS0_CORE3_ECC_AGGR"""
|
|
menuitem "A53SS0_CORE3_ETM" "per , ""A53SS0_CORE3_ETM"""
|
|
menuitem "A53SS0_CORE3_PMU" "per , ""A53SS0_CORE3_PMU"""
|
|
menuitem "A53SS0_SS_ECC_AGGR" "per , ""A53SS0_SS_ECC_AGGR"""
|
|
menuitem "A53SS0_SS_ROM" "per , ""A53SS0_SS_ROM"""
|
|
menuitem "CBASS0_ERR" "per , ""CBASS0_ERR"""
|
|
menuitem "CBASS0_FW" "per , ""CBASS0_FW"""
|
|
menuitem "CBASS0_GLB" "per , ""CBASS0_GLB"""
|
|
menuitem "CBASS0_ISC" "per , ""CBASS0_ISC"""
|
|
menuitem "CBASS0_QOS" "per , ""CBASS0_QOS"""
|
|
menuitem "CBASS_CENTRAL2_ERR" "per , ""CBASS_CENTRAL2_ERR"""
|
|
menuitem "CBASS_CENTRAL2_FW" "per , ""CBASS_CENTRAL2_FW"""
|
|
menuitem "CBASS_CENTRAL2_GLB" "per , ""CBASS_CENTRAL2_GLB"""
|
|
menuitem "CBASS_CENTRAL2_ISC" "per , ""CBASS_CENTRAL2_ISC"""
|
|
menuitem "CBASS_CENTRAL2_QOS" "per , ""CBASS_CENTRAL2_QOS"""
|
|
menuitem "CBASS_DBG0_ERR" "per , ""CBASS_DBG0_ERR"""
|
|
menuitem "CBASS_FW0_ERR" "per , ""CBASS_FW0_ERR"""
|
|
menuitem "CBASS_INFRA1_ERR" "per , ""CBASS_INFRA1_ERR"""
|
|
menuitem "CBASS_IPCSS0_ERR" "per , ""CBASS_IPCSS0_ERR"""
|
|
menuitem "CBASS_IPCSS0_FW" "per , ""CBASS_IPCSS0_FW"""
|
|
menuitem "CBASS_IPCSS0_GLB" "per , ""CBASS_IPCSS0_GLB"""
|
|
menuitem "CBASS_MCASP0_ERR" "per , ""CBASS_MCASP0_ERR"""
|
|
menuitem "CBASS_MISC_PERI0_ERR" "per , ""CBASS_MISC_PERI0_ERR"""
|
|
menuitem "CMP_EVENT_INTROUTER0_INTR_ROUTER_CFG" "per , ""CMP_EVENT_INTROUTER0_INTR_ROUTER_CFG"""
|
|
menuitem "COMPUTE_CLUSTER0_PBIST_0_PBIST" "per , ""COMPUTE_CLUSTER0_PBIST_0_PBIST"""
|
|
menuitem "CPSW0_ECC" "per , ""CPSW0_ECC"""
|
|
menuitem "CPSW0_NUSS" "per , ""CPSW0_NUSS"""
|
|
menuitem "csi_rx_if0_CP_INTD_CFG_INTD_CFG" "per , ""csi_rx_if0_CP_INTD_CFG_INTD_CFG"""
|
|
menuitem "csi_rx_if0_ECC_AGGR_CFG" "per , ""csi_rx_if0_ECC_AGGR_CFG"""
|
|
menuitem "csi_rx_if0_RX_SHIM_VBUSP_MMR_CSI2RXIF" "per , ""csi_rx_if0_RX_SHIM_VBUSP_MMR_CSI2RXIF"""
|
|
menuitem "csi_rx_if0_VBUS2APB_WRAP_VBUSP_APB_CSI2RX" "per , ""csi_rx_if0_VBUS2APB_WRAP_VBUSP_APB_CSI2RX"""
|
|
menuitem "CTRL_MMR0_CFG0" "per , ""CTRL_MMR0_CFG0"""
|
|
menuitem "DCC0" "per , ""DCC0"""
|
|
menuitem "DCC1" "per , ""DCC1"""
|
|
menuitem "DCC2" "per , ""DCC2"""
|
|
menuitem "DCC3" "per , ""DCC3"""
|
|
menuitem "DCC4" "per , ""DCC4"""
|
|
menuitem "DCC5" "per , ""DCC5"""
|
|
menuitem "DCC6" "per , ""DCC6"""
|
|
menuitem "DDR16SS0_REGS_SS_CFG_SSCFG" "per , ""DDR16SS0_REGS_SS_CFG_SSCFG"""
|
|
menuitem "DFTSS0" "per , ""DFTSS0"""
|
|
menuitem "DMASS0_BCDMA_0_BCDMA_BCHAN" "per , ""DMASS0_BCDMA_0_BCDMA_BCHAN"""
|
|
menuitem "DMASS0_BCDMA_0_BCDMA_BCHANRT" "per , ""DMASS0_BCDMA_0_BCDMA_BCHANRT"""
|
|
menuitem "DMASS0_BCDMA_0_BCDMA_CRED" "per , ""DMASS0_BCDMA_0_BCDMA_CRED"""
|
|
menuitem "DMASS0_BCDMA_0_BCDMA_GCFG" "per , ""DMASS0_BCDMA_0_BCDMA_GCFG"""
|
|
menuitem "DMASS0_BCDMA_0_BCDMA_RCHAN" "per , ""DMASS0_BCDMA_0_BCDMA_RCHAN"""
|
|
menuitem "DMASS0_BCDMA_0_BCDMA_RCHANRT" "per , ""DMASS0_BCDMA_0_BCDMA_RCHANRT"""
|
|
menuitem "DMASS0_BCDMA_0_BCDMA_RING" "per , ""DMASS0_BCDMA_0_BCDMA_RING"""
|
|
menuitem "DMASS0_BCDMA_0_BCDMA_RINGRT" "per , ""DMASS0_BCDMA_0_BCDMA_RINGRT"""
|
|
menuitem "DMASS0_BCDMA_0_BCDMA_TCHAN" "per , ""DMASS0_BCDMA_0_BCDMA_TCHAN"""
|
|
menuitem "DMASS0_BCDMA_0_BCDMA_TCHANRT" "per , ""DMASS0_BCDMA_0_BCDMA_TCHANRT"""
|
|
menuitem "DMASS0_ECC_AGGR_0_ECCAGGR" "per , ""DMASS0_ECC_AGGR_0_ECCAGGR"""
|
|
menuitem "DMASS0_INTAGGR_0_INTAGGR_CFG" "per , ""DMASS0_INTAGGR_0_INTAGGR_CFG"""
|
|
menuitem "DMASS0_INTAGGR_0_INTAGGR_GCNTCFG" "per , ""DMASS0_INTAGGR_0_INTAGGR_GCNTCFG"""
|
|
menuitem "DMASS0_INTAGGR_0_INTAGGR_GCNTRTI" "per , ""DMASS0_INTAGGR_0_INTAGGR_GCNTRTI"""
|
|
menuitem "DMASS0_INTAGGR_0_INTAGGR_IMAP" "per , ""DMASS0_INTAGGR_0_INTAGGR_IMAP"""
|
|
menuitem "DMASS0_INTAGGR_0_INTAGGR_INTR" "per , ""DMASS0_INTAGGR_0_INTAGGR_INTR"""
|
|
menuitem "DMASS0_INTAGGR_0_INTAGGR_L2G" "per , ""DMASS0_INTAGGR_0_INTAGGR_L2G"""
|
|
menuitem "DMASS0_INTAGGR_0_INTAGGR_MCAST" "per , ""DMASS0_INTAGGR_0_INTAGGR_MCAST"""
|
|
menuitem "DMASS0_INTAGGR_0_INTAGGR_UNMAP" "per , ""DMASS0_INTAGGR_0_INTAGGR_UNMAP"""
|
|
menuitem "DMASS0_PKTDMA_0_PKTDMA_CRED" "per , ""DMASS0_PKTDMA_0_PKTDMA_CRED"""
|
|
menuitem "DMASS0_PKTDMA_0_PKTDMA_GCFG" "per , ""DMASS0_PKTDMA_0_PKTDMA_GCFG"""
|
|
menuitem "DMASS0_PKTDMA_0_PKTDMA_RCHAN" "per , ""DMASS0_PKTDMA_0_PKTDMA_RCHAN"""
|
|
menuitem "DMASS0_PKTDMA_0_PKTDMA_RCHANRT" "per , ""DMASS0_PKTDMA_0_PKTDMA_RCHANRT"""
|
|
menuitem "DMASS0_PKTDMA_0_PKTDMA_RFLOW" "per , ""DMASS0_PKTDMA_0_PKTDMA_RFLOW"""
|
|
menuitem "DMASS0_PKTDMA_0_PKTDMA_RING" "per , ""DMASS0_PKTDMA_0_PKTDMA_RING"""
|
|
menuitem "DMASS0_PKTDMA_0_PKTDMA_RINGRT" "per , ""DMASS0_PKTDMA_0_PKTDMA_RINGRT"""
|
|
menuitem "DMASS0_PKTDMA_0_PKTDMA_TCHAN" "per , ""DMASS0_PKTDMA_0_PKTDMA_TCHAN"""
|
|
menuitem "DMASS0_PKTDMA_0_PKTDMA_TCHANRT" "per , ""DMASS0_PKTDMA_0_PKTDMA_TCHANRT"""
|
|
menuitem "DMASS0_PSILCFG_0_PSILCFG_PROXY" "per , ""DMASS0_PSILCFG_0_PSILCFG_PROXY"""
|
|
menuitem "DMASS0_PSILSS_0_ETLSW_MMRS" "per , ""DMASS0_PSILSS_0_ETLSW_MMRS"""
|
|
menuitem "DMASS0_PSILSS_0_PSILSS_MMRS" "per , ""DMASS0_PSILSS_0_PSILSS_MMRS"""
|
|
menuitem "DMASS0_RINGACC_0_RINGACC_CFG" "per , ""DMASS0_RINGACC_0_RINGACC_CFG"""
|
|
menuitem "DMASS0_RINGACC_0_RINGACC_GCFG" "per , ""DMASS0_RINGACC_0_RINGACC_GCFG"""
|
|
menuitem "DMASS0_RINGACC_0_RINGACC_RT" "per , ""DMASS0_RINGACC_0_RINGACC_RT"""
|
|
menuitem "DPHY_RX0_MMR_SLV_K3_DPHY_WRAP" "per , ""DPHY_RX0_MMR_SLV_K3_DPHY_WRAP"""
|
|
menuitem "DPHY_RX0_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX" "per , ""DPHY_RX0_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX"""
|
|
menuitem "DSS0_COMMON" "per , ""DSS0_COMMON"""
|
|
menuitem "DSS0_COMMON1" "per , ""DSS0_COMMON1"""
|
|
menuitem "DSS0_OVR1" "per , ""DSS0_OVR1"""
|
|
menuitem "DSS0_OVR2" "per , ""DSS0_OVR2"""
|
|
menuitem "DSS0_VID" "per , ""DSS0_VID"""
|
|
menuitem "DSS0_VIDL1" "per , ""DSS0_VIDL1"""
|
|
menuitem "DSS0_VP1" "per , ""DSS0_VP1"""
|
|
menuitem "DSS0_VP2" "per , ""DSS0_VP2"""
|
|
menuitem "ECAP0_CTL_STS" "per , ""ECAP0_CTL_STS"""
|
|
menuitem "ECAP1_CTL_STS" "per , ""ECAP1_CTL_STS"""
|
|
menuitem "ECAP2_CTL_STS" "per , ""ECAP2_CTL_STS"""
|
|
menuitem "EFUSE0" "per , ""EFUSE0"""
|
|
menuitem "ELM0" "per , ""ELM0"""
|
|
menuitem "EPWM0_EPWM" "per , ""EPWM0_EPWM"""
|
|
menuitem "EPWM1_EPWM" "per , ""EPWM1_EPWM"""
|
|
menuitem "EPWM2_EPWM" "per , ""EPWM2_EPWM"""
|
|
menuitem "EQEP0_REG" "per , ""EQEP0_REG"""
|
|
menuitem "EQEP1_REG" "per , ""EQEP1_REG"""
|
|
menuitem "EQEP2_REG" "per , ""EQEP2_REG"""
|
|
menuitem "ESM0_CFG" "per , ""ESM0_CFG"""
|
|
menuitem "FSS0_CFG" "per , ""FSS0_CFG"""
|
|
menuitem "FSS0_FSAS_0_DAT_REG0" "per , ""FSS0_FSAS_0_DAT_REG0"""
|
|
menuitem "FSS0_FSAS_0_DAT_REG1" "per , ""FSS0_FSAS_0_DAT_REG1"""
|
|
menuitem "FSS0_FSAS_0_DAT_REG3" "per , ""FSS0_FSAS_0_DAT_REG3"""
|
|
menuitem "FSS0_FSAS_0_FSAS_CFG" "per , ""FSS0_FSAS_0_FSAS_CFG"""
|
|
menuitem "FSS0_FSAS_0_OTFA_CFG" "per , ""FSS0_FSAS_0_OTFA_CFG"""
|
|
menuitem "FSS0_OSPI_0_OSPI0_CTRL" "per , ""FSS0_OSPI_0_OSPI0_CTRL"""
|
|
menuitem "FSS0_OSPI_0_OSPI0_ECC_AGGR" "per , ""FSS0_OSPI_0_OSPI0_ECC_AGGR"""
|
|
menuitem "FSS0_OSPI_0_OSPI0_SS_CFG" "per , ""FSS0_OSPI_0_OSPI0_SS_CFG"""
|
|
menuitem "GICSS0_GIC" "per , ""GICSS0_GIC"""
|
|
menuitem "GICSS0_GIC_TRANSLATER" "per , ""GICSS0_GIC_TRANSLATER"""
|
|
menuitem "GICSS0_REGS" "per , ""GICSS0_REGS"""
|
|
menuitem "GPIO0" "per , ""GPIO0"""
|
|
menuitem "GPIO1" "per , ""GPIO1"""
|
|
menuitem "GPMC0_CFG" "per , ""GPMC0_CFG"""
|
|
menuitem "I2C0_CFG" "per , ""I2C0_CFG"""
|
|
menuitem "I2C1_CFG" "per , ""I2C1_CFG"""
|
|
menuitem "I2C2_CFG" "per , ""I2C2_CFG"""
|
|
menuitem "I2C3_CFG" "per , ""I2C3_CFG"""
|
|
menuitem "ICSSM0_DRAM0_SLV_RAM" "per , ""ICSSM0_DRAM0_SLV_RAM"""
|
|
menuitem "ICSSM0_DRAM1_SLV_RAM" "per , ""ICSSM0_DRAM1_SLV_RAM"""
|
|
menuitem "ICSSM0_ECC_AGGR" "per , ""ICSSM0_ECC_AGGR"""
|
|
menuitem "ICSSM0_IEP0" "per , ""ICSSM0_IEP0"""
|
|
menuitem "ICSSM0_PR1_CFG_SLV" "per , ""ICSSM0_PR1_CFG_SLV"""
|
|
menuitem "ICSSM0_PR1_ICSS_ECAP0_ECAP_SLV" "per , ""ICSSM0_PR1_ICSS_ECAP0_ECAP_SLV"""
|
|
menuitem "ICSSM0_PR1_ICSS_INTC_INTC_SLV" "per , ""ICSSM0_PR1_ICSS_INTC_INTC_SLV"""
|
|
menuitem "ICSSM0_PR1_ICSS_UART_UART_SLV" "per , ""ICSSM0_PR1_ICSS_UART_UART_SLV"""
|
|
menuitem "ICSSM0_PR1_MDIO_V1P7_MDIO" "per , ""ICSSM0_PR1_MDIO_V1P7_MDIO"""
|
|
menuitem "ICSSM0_PR1_MII_RT_PR1_MII_RT_CFG" "per , ""ICSSM0_PR1_MII_RT_PR1_MII_RT_CFG"""
|
|
menuitem "ICSSM0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G" "per , ""ICSSM0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G"""
|
|
menuitem "ICSSM0_PR1_PDSP0_IRAM" "per , ""ICSSM0_PR1_PDSP0_IRAM"""
|
|
menuitem "ICSSM0_PR1_PDSP0_IRAM_DEBUG" "per , ""ICSSM0_PR1_PDSP0_IRAM_DEBUG"""
|
|
menuitem "ICSSM0_PR1_PDSP0_IRAM_RAM" "per , ""ICSSM0_PR1_PDSP0_IRAM_RAM"""
|
|
menuitem "ICSSM0_PR1_PDSP1_IRAM" "per , ""ICSSM0_PR1_PDSP1_IRAM"""
|
|
menuitem "ICSSM0_PR1_PDSP1_IRAM_DEBUG" "per , ""ICSSM0_PR1_PDSP1_IRAM_DEBUG"""
|
|
menuitem "ICSSM0_PR1_PDSP1_IRAM_RAM" "per , ""ICSSM0_PR1_PDSP1_IRAM_RAM"""
|
|
menuitem "ICSSM0_PR1_PROT_SLV" "per , ""ICSSM0_PR1_PROT_SLV"""
|
|
menuitem "ICSSM0_RAM_SLV_RAM" "per , ""ICSSM0_RAM_SLV_RAM"""
|
|
menuitem "ICSSM0_RAT_SLICE0_CFG" "per , ""ICSSM0_RAT_SLICE0_CFG"""
|
|
menuitem "ICSSM0_RAT_SLICE1_CFG" "per , ""ICSSM0_RAT_SLICE1_CFG"""
|
|
menuitem "MAILBOX0_CLUSTER_0_REGS0" "per , ""MAILBOX0_CLUSTER_0_REGS0"""
|
|
menuitem "MAIN_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG" "per , ""MAIN_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG"""
|
|
menuitem "MCAN0_CFG" "per , ""MCAN0_CFG"""
|
|
menuitem "MCAN0_ECC_AGGR" "per , ""MCAN0_ECC_AGGR"""
|
|
menuitem "MCAN0_MSGMEM_RAM" "per , ""MCAN0_MSGMEM_RAM"""
|
|
menuitem "MCAN0_SS" "per , ""MCAN0_SS"""
|
|
menuitem "MCASP0_CFG" "per , ""MCASP0_CFG"""
|
|
menuitem "MCASP1_CFG" "per , ""MCASP1_CFG"""
|
|
menuitem "MCASP2_CFG" "per , ""MCASP2_CFG"""
|
|
menuitem "MCRC64_0_REGS" "per , ""MCRC64_0_REGS"""
|
|
menuitem "MCSPI0_CFG" "per , ""MCSPI0_CFG"""
|
|
menuitem "MCSPI1_CFG" "per , ""MCSPI1_CFG"""
|
|
menuitem "MCSPI2_CFG" "per , ""MCSPI2_CFG"""
|
|
menuitem "MCU_CBASS0_ERR" "per , ""MCU_CBASS0_ERR"""
|
|
menuitem "MCU_CBASS0_GLB" "per , ""MCU_CBASS0_GLB"""
|
|
menuitem "MCU_CBASS0_ISC" "per , ""MCU_CBASS0_ISC"""
|
|
menuitem "MCU_CBASS0_QOS" "per , ""MCU_CBASS0_QOS"""
|
|
menuitem "MCU_DCC0" "per , ""MCU_DCC0"""
|
|
menuitem "MCU_GPIO0" "per , ""MCU_GPIO0"""
|
|
menuitem "MCU_I2C0_CFG" "per , ""MCU_I2C0_CFG"""
|
|
menuitem "MCU_M4FSS0_DRAM_0_DRAM" "per , ""MCU_M4FSS0_DRAM_0_DRAM"""
|
|
menuitem "MCU_M4FSS0_ECC_AGGR_0_ECC_AGGR" "per , ""MCU_M4FSS0_ECC_AGGR_0_ECC_AGGR"""
|
|
menuitem "MCU_M4FSS0_IRAM_0_IRAM" "per , ""MCU_M4FSS0_IRAM_0_IRAM"""
|
|
menuitem "MCU_M4FSS0_RAT_0_RAT" "per , ""MCU_M4FSS0_RAT_0_RAT"""
|
|
menuitem "MCU_MCAN0_CFG" "per , ""MCU_MCAN0_CFG"""
|
|
menuitem "MCU_MCAN0_ECC_AGGR" "per , ""MCU_MCAN0_ECC_AGGR"""
|
|
menuitem "MCU_MCAN0_MSGMEM_RAM" "per , ""MCU_MCAN0_MSGMEM_RAM"""
|
|
menuitem "MCU_MCAN0_SS" "per , ""MCU_MCAN0_SS"""
|
|
menuitem "MCU_MCAN1_CFG" "per , ""MCU_MCAN1_CFG"""
|
|
menuitem "MCU_MCAN1_ECC_AGGR" "per , ""MCU_MCAN1_ECC_AGGR"""
|
|
menuitem "MCU_MCAN1_MSGMEM_RAM" "per , ""MCU_MCAN1_MSGMEM_RAM"""
|
|
menuitem "MCU_MCAN1_SS" "per , ""MCU_MCAN1_SS"""
|
|
menuitem "MCU_MCSPI0_CFG" "per , ""MCU_MCSPI0_CFG"""
|
|
menuitem "MCU_MCSPI1_CFG" "per , ""MCU_MCSPI1_CFG"""
|
|
menuitem "MCU_RTI0_CFG" "per , ""MCU_RTI0_CFG"""
|
|
menuitem "MCU_TIMEOUT0_CFG" "per , ""MCU_TIMEOUT0_CFG"""
|
|
menuitem "MCU_TIMEOUT1_CFG" "per , ""MCU_TIMEOUT1_CFG"""
|
|
menuitem "MCU_TIMER0_CFG" "per , ""MCU_TIMER0_CFG"""
|
|
menuitem "MCU_TIMER1_CFG" "per , ""MCU_TIMER1_CFG"""
|
|
menuitem "MCU_TIMER2_CFG" "per , ""MCU_TIMER2_CFG"""
|
|
menuitem "MCU_TIMER3_CFG" "per , ""MCU_TIMER3_CFG"""
|
|
menuitem "MCU_UART0" "per , ""MCU_UART0"""
|
|
menuitem "MMCSD0_CTL_CFG" "per , ""MMCSD0_CTL_CFG"""
|
|
menuitem "MMCSD0_ECC_AGGR_RXMEM" "per , ""MMCSD0_ECC_AGGR_RXMEM"""
|
|
menuitem "MMCSD0_ECC_AGGR_TXMEM" "per , ""MMCSD0_ECC_AGGR_TXMEM"""
|
|
menuitem "MMCSD0_SS_CFG" "per , ""MMCSD0_SS_CFG"""
|
|
menuitem "MMCSD1_CTL_CFG" "per , ""MMCSD1_CTL_CFG"""
|
|
menuitem "MMCSD1_ECC_AGGR_RXMEM" "per , ""MMCSD1_ECC_AGGR_RXMEM"""
|
|
menuitem "MMCSD1_ECC_AGGR_TXMEM" "per , ""MMCSD1_ECC_AGGR_TXMEM"""
|
|
menuitem "MMCSD1_SS_CFG" "per , ""MMCSD1_SS_CFG"""
|
|
menuitem "MMCSD2_CTL_CFG" "per , ""MMCSD2_CTL_CFG"""
|
|
menuitem "MMCSD2_ECC_AGGR_RXMEM" "per , ""MMCSD2_ECC_AGGR_RXMEM"""
|
|
menuitem "MMCSD2_ECC_AGGR_TXMEM" "per , ""MMCSD2_ECC_AGGR_TXMEM"""
|
|
menuitem "MMCSD2_SS_CFG" "per , ""MMCSD2_SS_CFG"""
|
|
menuitem "PADCFG_CTRL0_CFG0" "per , ""PADCFG_CTRL0_CFG0"""
|
|
menuitem "PBIST0" "per , ""PBIST0"""
|
|
menuitem "PBIST1" "per , ""PBIST1"""
|
|
menuitem "PDMA0" "per , ""PDMA0"""
|
|
menuitem "PDMA1" "per , ""PDMA1"""
|
|
menuitem "PLL0_CFG" "per , ""PLL0_CFG"""
|
|
menuitem "PSC0" "per , ""PSC0"""
|
|
menuitem "PSC0_ECC_AGGR_0_REGS" "per , ""PSC0_ECC_AGGR_0_REGS"""
|
|
menuitem "PSC0_FW_0_FW" "per , ""PSC0_FW_0_FW"""
|
|
menuitem "PSC0_FW_0_GLB" "per , ""PSC0_FW_0_GLB"""
|
|
menuitem "PSRAMECC0_ECC_AGGR" "per , ""PSRAMECC0_ECC_AGGR"""
|
|
menuitem "PSRAMECC0_RAM" "per , ""PSRAMECC0_RAM"""
|
|
menuitem "PSRAMECC_16K0_ECC_AGGR" "per , ""PSRAMECC_16K0_ECC_AGGR"""
|
|
menuitem "PSRAMECC_16K0_RAM" "per , ""PSRAMECC_16K0_RAM"""
|
|
menuitem "RTI0_CFG" "per , ""RTI0_CFG"""
|
|
menuitem "RTI15_CFG" "per , ""RTI15_CFG"""
|
|
menuitem "RTI1_CFG" "per , ""RTI1_CFG"""
|
|
menuitem "RTI2_CFG" "per , ""RTI2_CFG"""
|
|
menuitem "RTI3_CFG" "per , ""RTI3_CFG"""
|
|
menuitem "SPINLOCK0" "per , ""SPINLOCK0"""
|
|
menuitem "STM0_CTI_CSCTI" "per , ""STM0_CTI_CSCTI"""
|
|
menuitem "STM0_CXSTM" "per , ""STM0_CXSTM"""
|
|
menuitem "TIMER0_CFG" "per , ""TIMER0_CFG"""
|
|
menuitem "TIMER1_CFG" "per , ""TIMER1_CFG"""
|
|
menuitem "TIMER2_CFG" "per , ""TIMER2_CFG"""
|
|
menuitem "TIMER3_CFG" "per , ""TIMER3_CFG"""
|
|
menuitem "TIMER4_CFG" "per , ""TIMER4_CFG"""
|
|
menuitem "TIMER5_CFG" "per , ""TIMER5_CFG"""
|
|
menuitem "TIMER6_CFG" "per , ""TIMER6_CFG"""
|
|
menuitem "TIMER7_CFG" "per , ""TIMER7_CFG"""
|
|
menuitem "TIMESYNC_EVENT_ROUTER0_INTR_ROUTER_CFG" "per , ""TIMESYNC_EVENT_ROUTER0_INTR_ROUTER_CFG"""
|
|
menuitem "UART0" "per , ""UART0"""
|
|
menuitem "UART1" "per , ""UART1"""
|
|
menuitem "UART2" "per , ""UART2"""
|
|
menuitem "UART3" "per , ""UART3"""
|
|
menuitem "UART4" "per , ""UART4"""
|
|
menuitem "UART5" "per , ""UART5"""
|
|
menuitem "UART6" "per , ""UART6"""
|
|
menuitem "WKUP_CBASS0_ERR" "per , ""WKUP_CBASS0_ERR"""
|
|
menuitem "WKUP_CBASS0_FW" "per , ""WKUP_CBASS0_FW"""
|
|
menuitem "WKUP_CBASS0_GLB" "per , ""WKUP_CBASS0_GLB"""
|
|
menuitem "WKUP_CBASS0_ISC" "per , ""WKUP_CBASS0_ISC"""
|
|
menuitem "WKUP_CBASS0_QOS" "per , ""WKUP_CBASS0_QOS"""
|
|
menuitem "WKUP_CTRL_MMR1_CFG0" "per , ""WKUP_CTRL_MMR1_CFG0"""
|
|
menuitem "WKUP_ESM0_CFG" "per , ""WKUP_ESM0_CFG"""
|
|
menuitem "WKUP_I2C0_CFG" "per , ""WKUP_I2C0_CFG"""
|
|
menuitem "WKUP_MCU_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG" "per , ""WKUP_MCU_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG"""
|
|
menuitem "WKUP_PADCFG_CTRL0_CFG0" "per , ""WKUP_PADCFG_CTRL0_CFG0"""
|
|
menuitem "WKUP_PBIST0" "per , ""WKUP_PBIST0"""
|
|
menuitem "WKUP_PLL0_CFG" "per , ""WKUP_PLL0_CFG"""
|
|
menuitem "WKUP_PSC0" "per , ""WKUP_PSC0"""
|
|
menuitem "WKUP_RTI0_CFG" "per , ""WKUP_RTI0_CFG"""
|
|
menuitem "WKUP_TIMER0_CFG" "per , ""WKUP_TIMER0_CFG"""
|
|
menuitem "WKUP_TIMER1_CFG" "per , ""WKUP_TIMER1_CFG"""
|
|
menuitem "WKUP_UART0" "per , ""WKUP_UART0"""
|
|
)
|
|
if (cpuis("AM62*X-CR5"))
|
|
(
|
|
menuitem "CBASS_MISC_PERI0_ERR" "per , ""CBASS_MISC_PERI0_ERR"""
|
|
menuitem "CTRL_MMR0_CFG0" "per , ""CTRL_MMR0_CFG0"""
|
|
menuitem "ECAP0_CTL_STS" "per , ""ECAP0_CTL_STS"""
|
|
menuitem "ECAP1_CTL_STS" "per , ""ECAP1_CTL_STS"""
|
|
menuitem "ECAP2_CTL_STS" "per , ""ECAP2_CTL_STS"""
|
|
menuitem "ELM0" "per , ""ELM0"""
|
|
menuitem "EPWM0_EPWM" "per , ""EPWM0_EPWM"""
|
|
menuitem "EPWM1_EPWM" "per , ""EPWM1_EPWM"""
|
|
menuitem "EPWM2_EPWM" "per , ""EPWM2_EPWM"""
|
|
menuitem "EQEP0_REG" "per , ""EQEP0_REG"""
|
|
menuitem "EQEP1_REG" "per , ""EQEP1_REG"""
|
|
menuitem "EQEP2_REG" "per , ""EQEP2_REG"""
|
|
menuitem "GPIO0" "per , ""GPIO0"""
|
|
menuitem "GPIO1" "per , ""GPIO1"""
|
|
menuitem "I2C0_CFG" "per , ""I2C0_CFG"""
|
|
menuitem "I2C1_CFG" "per , ""I2C1_CFG"""
|
|
menuitem "I2C2_CFG" "per , ""I2C2_CFG"""
|
|
menuitem "I2C3_CFG" "per , ""I2C3_CFG"""
|
|
menuitem "MAILBOX0_CLUSTER_0_REGS0" "per , ""MAILBOX0_CLUSTER_0_REGS0"""
|
|
menuitem "MCAN0_CFG" "per , ""MCAN0_CFG"""
|
|
menuitem "MCAN0_ECC_AGGR" "per , ""MCAN0_ECC_AGGR"""
|
|
menuitem "MCAN0_MSGMEM_RAM" "per , ""MCAN0_MSGMEM_RAM"""
|
|
menuitem "MCAN0_SS" "per , ""MCAN0_SS"""
|
|
menuitem "MCSPI0_CFG" "per , ""MCSPI0_CFG"""
|
|
menuitem "MCSPI1_CFG" "per , ""MCSPI1_CFG"""
|
|
menuitem "MCSPI2_CFG" "per , ""MCSPI2_CFG"""
|
|
menuitem "MCU_GPIO0" "per , ""MCU_GPIO0"""
|
|
menuitem "MCU_TIMER0_CFG" "per , ""MCU_TIMER0_CFG"""
|
|
menuitem "MCU_TIMER1_CFG" "per , ""MCU_TIMER1_CFG"""
|
|
menuitem "MCU_TIMER2_CFG" "per , ""MCU_TIMER2_CFG"""
|
|
menuitem "MCU_TIMER3_CFG" "per , ""MCU_TIMER3_CFG"""
|
|
menuitem "SPINLOCK0" "per , ""SPINLOCK0"""
|
|
menuitem "PADCFG_CTRL0_CFG0" "per , ""PADCFG_CTRL0_CFG0"""
|
|
menuitem "UART0" "per , ""UART0"""
|
|
menuitem "UART1" "per , ""UART1"""
|
|
menuitem "UART2" "per , ""UART2"""
|
|
menuitem "UART3" "per , ""UART3"""
|
|
menuitem "UART4" "per , ""UART4"""
|
|
menuitem "UART5" "per , ""UART5"""
|
|
menuitem "UART6" "per , ""UART6"""
|
|
menuitem "VIM_CFG" "per , ""VIM_CFG"""
|
|
menuitem "WKUP_CBASS0_ERR" "per , ""WKUP_CBASS0_ERR"""
|
|
menuitem "WKUP_I2C0_CFG" "per , ""WKUP_I2C0_CFG"""
|
|
menuitem "WKUP_PBIST0" "per , ""WKUP_PBIST0"""
|
|
menuitem "WKUP_RTI0_CFG" "per , ""WKUP_RTI0_CFG"""
|
|
menuitem "WKUP_TIMER0_CFG" "per , ""WKUP_TIMER0_CFG"""
|
|
menuitem "WKUP_TIMER1_CFG" "per , ""WKUP_TIMER1_CFG"""
|
|
menuitem "WKUP_UART0" "per , ""WKUP_UART0"""
|
|
)
|
|
if (cpuis("AM62*X-ICSS0"))
|
|
(
|
|
menuitem "ICSSM0_IEP0" "per , ""ICSSM0_IEP0"""
|
|
menuitem "ICSSM0_PR1_CFG_SLV" "per , ""ICSSM0_PR1_CFG_SLV"""
|
|
menuitem "ICSSM0_PR1_ICSS_ECAP0_ECAP_SLV" "per , ""ICSSM0_PR1_ICSS_ECAP0_ECAP_SLV"""
|
|
menuitem "ICSSM0_PR1_ICSS_INTC_INTC_SLV" "per , ""ICSSM0_PR1_ICSS_INTC_INTC_SLV"""
|
|
menuitem "ICSSM0_PR1_ICSS_UART_UART_SLV" "per , ""ICSSM0_PR1_ICSS_UART_UART_SLV"""
|
|
menuitem "ICSSM0_PR1_MDIO_V1P7_MDIO" "per , ""ICSSM0_PR1_MDIO_V1P7_MDIO"""
|
|
menuitem "ICSSM0_PR1_MII_RT_PR1_MII_RT_CFG" "per , ""ICSSM0_PR1_MII_RT_PR1_MII_RT_CFG"""
|
|
menuitem "ICSSM0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G" "per , ""ICSSM0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G"""
|
|
menuitem "ICSSM0_PR1_PROT_SLV" "per , ""ICSSM0_PR1_PROT_SLV"""
|
|
menuitem "ICSSM0_RAT_SLICE0_CFG" "per , ""ICSSM0_RAT_SLICE0_CFG"""
|
|
menuitem "ICSSM0_RAT_SLICE1_CFG" "per , ""ICSSM0_RAT_SLICE1_CFG"""
|
|
)
|
|
)
|
|
)
|