183 lines
5.6 KiB
Plaintext
183 lines
5.6 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: TWR-VF65GS10 VYBRID TOWER SYSTEM MODULE SPI FLASH Program script
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; @Description:
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; The S25FL128 (Spansion SPI flash) is on the QuadSPI0_A controller
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; Prerequisites:
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; * set BootMode to SD-Card J22[1..5]=0y10110
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; * Or set BootMode to QSPI J22[1..5]=0y10000
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; * remove SD-Card - device will stop in BootROM
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;
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; SRAM: 0x3F001000
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; QuadSPI(controller) Base: 0x40044000
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; FLASH BASE ADDRESS: 0x20000000
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;
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; @Author: jjeong
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; @Chip: VF7*
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; @Keywords: S25FL128 Spansion Flash SPI QuadSPI
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: vybridqspi-spi64.cmm 11733 2023-01-16 08:55:12Z bschroefel $
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LOCAL &arg1
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ENTRY &arg1
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&arg1=STRing.UPpeR("&arg1") // for example "PREPAREONLY"
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LOCAL &QSPI_BASE
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&QSPI_BASE=0x20000000 ; QSPI0_A_base=0x20000000, QSPI0_B_base=0x28000000
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// Basic settings for system.up
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RESet
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SYStem.RESet
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SYStem.CPU VF6XX-CA5
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SYStem.CONFIG CORE 1. 1.
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SYStem.CONFIG SLAVE OFF
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; disable Trace for connection phase - TPIU may be clock-gated
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ETM.OFF
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ITM.OFF
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Trace.DISable
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; Avoid touching areas which react badly
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MAP.DenyAccess 0x30000000--0x3effffff
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MAP.DenyAccess 0x80000000--0xdfffffff
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SYStem.Up
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PER.Set.simple C15:0x1 %LE %Long (Data.Long(C15:0x1)&~(0x5)) ; disable interrupt and mmu
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//CCM config
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Data.Set A:0x4006B048 %LE %Long 0xFFFFFFFF
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Data.Set A:0x4006B04C %LE %Long 0xFFFFFFFF
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//QuadSPI0 Clk configuration
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Data.Set A:0x4006B000 %LE %Long 0x11057
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Data.Set A:0x4006B008 %LE %Long 0x80040824 ;CCSR
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Data.Set A:0x4006B010 %LE %Long 0x400000 ; CCM->CSCMR1 |= CCM_CSCMR1_QSPI1_CLK_SEL(0x0);
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Data.Set A:0x4006B01C %LE %Long 0x1d1d ; CCM->CSCDR3 |= CCM_CSCDR3_QSPI1_X4_DIV(0x1)|CCM_CSCDR3_QSPI1_X2_DIV_MASK|CCM_CSCDR3_QSPI1_DIV_MASK|CCM_CSCDR3_QSPI1_EN_MASK;
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//QuadSPI0_A
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Data.Set A:0x4004813C %LE %Long 0x001030C3 ;PTD0
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Data.Set A:0x40048140 %LE %Long 0x001030FF ;PTD1
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Data.Set A:0x40048144 %LE %Long 0x001030C3 ;PTD2
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Data.Set A:0x40048148 %LE %Long 0x001030C3 ;PTD3
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Data.Set A:0x4004814C %LE %Long 0x001030C3 ;PTD4
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Data.Set A:0x40048150 %LE %Long 0x001030C3 ;PTD5
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//QuadSPI0_B
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if &QSPI_BASE==0x28000000 ; enabled QSPI0_B
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(
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Data.Set A:0x40048158 %LE %LONG 0x001030C3 ;PTD7
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Data.Set A:0x4004815C %LE %LONG 0x001030FF ;PTD8
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Data.Set A:0x40048160 %LE %LONG 0x001030C3 ;PTD9
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Data.Set A:0x40048164 %LE %LONG 0x001030C3 ;PTD10
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Data.Set A:0x40048168 %LE %LONG 0x001030C3 ;PTD11
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Data.Set A:0x4004816C %LE %LONG 0x001030C3 ;PTD12
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)
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Data.Set A:0x40044000 %LE %Long 0xF4000 ; QuadSPI0->MCR = QuadSPI_MCR_MDIS_MASK;
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Data.Set A:0x4004400C %LE %Long 0x0303 ; QuadSPI0->FLSHCR = QuadSPI_FLSHCR_TCSH(3) | QuadSPI_FLSHCR_TCSS(3);
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Data.Set A:0x40044010 %LE %Long 0x0 ; QuadSPI0->BUF0CR = QuadSPI_BUF0CR_MSTRID(0) | QuadSPI_BUF0CR_ADATSZ(0);
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Data.Set A:0x40044014 %LE %Long 0x0 ; QuadSPI0->BUF1CR = QuadSPI_BUF1CR_MSTRID(0) | QuadSPI_BUF1CR_ADATSZ(0);
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Data.Set A:0x40044018 %LE %Long 0x0
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Data.Set A:0x4004401C %LE %Long 0x80000000 ; QuadSPI0->BUF3CR = QuadSPI_BUF3CR_MSTRID(0) | QuadSPI_BUF3CR_ADATSZ(0) | QuadSPI_BUF3CR_ALLMST_MASK;
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Data.Set A:0x40044030 %LE %Long 0x0 ; QuadSPI0->BUF0IND = 0x0;
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Data.Set A:0x40044000 %LE %Long 0xF4000 ; QuadSPI0->MCR |= QuadSPI_MCR_MDIS_MASK;
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Data.Set A:0x40044108 %LE %Long 0x00010000 ; // for 33MHz clock , QuadSPI0->SMPR = 0x10000;
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Data.Set A:0x40044180 %LE %Long 0x24000000 ;QuadSPI0->SFA1AD
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Data.Set A:0x40044184 %LE %Long 0x28000000
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Data.Set A:0x40044188 %LE %Long 0x2C000000
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Data.Set A:0x4004418C %LE %Long 0x30000000
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Data.Set A:0x40044000 %Long 0xF0000 ; QuadSPI0->MCR &= ~QuadSPI_MCR_MDIS_MASK ; Enable QuadSPI0 controller with Quad SPI DDR MODE
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//FLASH READ ID TEST
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AREA.CLEAR
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AREA.view
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GOSUB READ_ID_TEST
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DIALOG.YESNO "the flash id is correct on AREA window?"
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ENTRY &result
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IF !&result
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(
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PRINT "pls, check your register configuration to enable your flash controller"
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ENDDO
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)
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//S(D)RAM TEST for algorithm file
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GOSUB SDRAM_INIT
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Data.Test 0x3f001000++0x7FFF /Prime ;s(d)ram test
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IF FOUND()
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(
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PRINT "s(d)ram is NOT initialized around 0x" ADDRESS.OFFSET(TRACK.ADDRESS())
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ENDDO
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)
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programFlash:
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Break.RESet
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FLASHFILE.RESet
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//FLASHFILE.CONFIG <QuadSPI Base> <FLASH_BASE_ADDR>
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FLASHFILE.CONFIG 0x40044000 &QSPI_BASE
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//FLASHFILE.TARGET <Code_range> <Data_range> <Algorithm file>
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FLASHFILE.TARGET 0x3f001000++0x2FFF 0x3f004000++0x1FFF ~~/demo/arm/flash/byte/spi64_vybridqspi.bin /KEEP
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FLASHFILE.GETID
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//End of the test prepareonly
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IF "&arg1"=="PREPAREONLY"
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ENDDO
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FLASHFILE.UNLOCK 0x0--0xFFFFFF
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FLASHFILE.DUMP 0x0
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//Erase Serial FLASH
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;FLASHFILE.ERASE 0x0--0xFFFFF
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//Write
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;FLASHFILE.LOAD * 0x0
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;FLASHFILE.LOAD * 0x0 /ComPare ;verify
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ENDDO
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READ_ID_TEST:
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&temp=Data.Long(A:0x40044000)
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Data.Set A:0x40044000 %Long (&temp|0x0c00) //clear Tx/Rx buffer
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Data.Set A:0x40044300 %LE %Long 0x5AF05AF0 ; LUTKEY
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Data.Set A:0x40044304 %LE %Long 0x2 ; LCKCR
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//SEQID 5. LUT 5*4
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Data.Set A:0x40044360 %LE %Long 0x1c04049f ; LUT0, SEQID0
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Data.Set A:0x40044364 %LE %Long 0x0
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Data.Set A:0x40044368 %LE %Long 0x0
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Data.Set A:0x4004436C %LE %Long 0x0
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Data.Set A:0x40044100 %Long &QSPI_BASE ; SFAR , FLASH BASE ADDRESS
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// assert Read id command
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Data.Set A:0x40044008 %Long (5.<<24.) ; (5.<<24.)
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WAIT 100.ms
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&temp=Data.Long(A:0x40044000)
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Data.Set A:0x40044000 %Long (&temp|0x0800) //clear Tx buffer
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PRINT "1st 0x" Data.Long(A:0x40044200)>>24. " (Manufacturer)"
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PRINT "2nd 0x" (Data.Long(A:0x40044200)>>16.)&0xFF " (Device ID)"
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PRINT "3rd 0x" (Data.Long(A:0x40044200)>>8.)&0xFF
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PRINT "4th 0x" Data.Long(A:0x40044200)&0xFF
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RETURN
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SDRAM_INIT:
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RETURN
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