102 lines
2.5 KiB
Plaintext
102 lines
2.5 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: eMMC FLASH Programming script for STA2065
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; @Description:
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; eMMC FLASH is connected
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;
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; Internal SRAM: 0xA0000000
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; SD/MMC Controller Register : 0x101F6000
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;
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; @Author: jjeong
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; @Chip: sta2065
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; @Keywords: STM eMMC
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; --------------------------------------------------------------------------------
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; $Id: sta2065-emmc.cmm 10516 2022-02-02 11:39:30Z bschroefel $
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LOCAL &arg1
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ENTRY &arg1
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&arg1=STRing.UPpeR("&arg1") // for example "PREPAREONLY"
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SYStem.RESet
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SYStem.CPU sta2065
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SYStem.Option.ResBreak OFF
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SYStem.Option.WaitReset 10.ms
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SYStem.Mode Up
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&MMC_BASE=0x101F6000
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Data.Set C15:0x1 %Long 0x452a7a ;disable cache and mmu
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Data.Set ASD:0x101E1008 %Long 0x0 ;wdog disable
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GOSUB pll_setting
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//clk enable
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Data.Set ASD:0x101E0024 %Long (0x1<<8.) //PCKEN0, PCLKSDI
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Data.Set ZSD:0x101E0034 %LE %Long (0x1<<8.) //PCKEN1, SDICLK
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Data.Set ASD:0x101E0048 %Long (0x3<<1.) //PCKEN2
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//SDIO controller configuration
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Data.Set A:&MMC_BASE %Long 0x3 ;power on
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Data.Set A:&MMC_BASE+0x24 %Long 0xFFFFFFFF
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Data.Set A:&MMC_BASE+0x28 %Long 0x200
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Data.Set A:&MMC_BASE+0x2C %Long 0x0 ;0x4099
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Data.Set A:&MMC_BASE+0x04 %Long 0x176 ;clk 400Khz ; 0x7401
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Break.RESet
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FLASHFILE.RESet
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FLASHFILE.CONFIG &MMC_BASE 0x0 0x0 0x0
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// FLASHFILE.TARGET <<code range>> <<data range>> <<algorithm file>>
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FLASHFILE.TARGET A:0xA0000000++0x1fff A:0xA0002000++0x1fff ~~/demo/arm/flash/byte/emmc_stm32.bin /KEEP ;for mmc
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Data.Set A:&MMC_BASE+0x04 %Long 0x176 ; clk 400Khz
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FLASHFILE.GETID
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Data.Set A:&MMC_BASE+0x04 %Long 0x107 ; speed up the clk
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FLASHFILE.GETEXTCSD
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//End of the test prepareonly
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IF "&arg1"=="PREPAREONLY"
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ENDDO
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FLASHFILE.DUMP 0x0
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ENDDO
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pll_setting:
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; Going to Slow Mode
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Data.Set ZSD:0x101E0000 %LE %Long 0x00021003
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WAIT 200.ms
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Data.Set ZSD:0x101E0010 %LE %Long 0x00
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Data.Set ZSD:0x101E0000 %LE %Long 0x1A93
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; (PLL1 PHIB)/2-->HCLK = 208 MHz
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; DDR Synch mode
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; HCLK-->DCLK
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; Normal Mode
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Data.Set ZSD:0x101E0000 %LE %Long 0x4001A93
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;HCLKDIV = 1 ==> Divide by 2
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;DCLKDIV = 1 ==> Divide by 2
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Data.Set ZSD:0x101E0058 %LE %Long 0x80e5
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; Programming PLL1 and PLL2 multiplication factors
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; PLL1 VCO Freq= 26*48 = 1248 MHz. CLK = VCO/2 = 624 MHz
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; PLL2 VCO Freq= 26*24 = 624 MHz. PLL2CLK = VCO/1 = 624 MHz
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Data.Set ZSD:0x101E0014 %LE %Long 0x18001f01
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; Enabling PLL2
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Data.Set ZSD:0x101E0010 %LE %Long 0x10000002
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Data.Set ZSD:0x101E0000 %LE %Long 0x4001A97
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RETURN
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