166 lines
5.5 KiB
Plaintext
166 lines
5.5 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: Freescale QorIQ LS1043A RDB NAND FLASH Programming Template
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; @Description:
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; NAND FLASH(MT29F4G08) is connected to CS0
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; The board RCW_SRC[0:8] selects : 1_0000_0110: 8-bit NAND flash, 2 KB page,
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; 64 pages/block
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; The RCW_SRC field (9 bits) is spread over SW4[1-8] and SW5[1].
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; This script uses SYStem.Option.HRCWOVerRide to set a custom RCW for the flash
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; programming phase. This should allow access to the SoC even if the flash is
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; empty/corrupted and the RCW/PBL is not valid. The RCW is a template and is not
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; guaranteed to work on every board.
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;
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; Internal SRAM : 0x10001000
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; IFC base : 0x01530000
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; IFC_SRAM : 0x7e800000
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; CS# : 0
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;
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; @Author: jjeong
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; @Chip: LS1043A
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; @Keywords: Flash NAND
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; --------------------------------------------------------------------------------
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; $Id: ls1043-nand2g08-rcwovr.cmm 11733 2023-01-16 08:55:12Z bschroefel $
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LOCAL &arg1
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ENTRY &arg1
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&arg1=STRing.UPpeR("&arg1") // for example "PREPAREONLY"
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&BASE=A:0x1530000
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RESet
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SYStem.RESet
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SYStem.CPU LS1043A
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SYStem.Option HRCWOVerRide OFF
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SYStem.Option TRST OFF
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SYStem.Option EnReset ON
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CORE.ASSIGN 1. ; select only master core
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Trace.DISable
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SYStem.JtagClock CTCK 10MHz
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; <temporarily override the RCW>
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; temporarily override the RCW. The RCW is fetched while the boot phase and defines initial
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; pinmux/serdes/qspi/nor/nand/... configurations.
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; The RCW override requires to reset the SoC. Two methods are supported.
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; Method 1: EnReset OFF && HRCWOVerRide ON /PORESET - do not assert the nReset line, issue a JTAG based PORESET
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; Method 2: EnReset ON && HRCWOVerRide ON - assert the nReset line
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; Steps - Override RCW_SRC only
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; * set EnReset & HRCWOVerRide - Method 1/2
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; * switch to SYStem.Mode Prepare
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; * write the RCW_SRC value to EDBG:0x42000040
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; * switch to SYStem.Up
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; Steps - Override RCW completely
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; * set EnReset & HRCWOVerRide - Method 1/2
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; * switch to SYStem.Mode Prepare
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; * write the RCW_SRC value HARDCODED to EDBG:0x42000040
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; * write the RCW itself to EDBG:0x42000000 onwards
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; * ensure in RCW[6]/EDBG:0x42000018 the PBL_SRC is reserved e.g. 0xfb8?????
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; * switch to SYStem.Up
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; The following RCW is used to connect to the device even with a empty flash.
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; The pinmux is configured to map the NAND pins.
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SYStem.Option EnReset OFF
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SYStem.Option HRCWOVerRide ON /PORESET
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SYStem.Mode.Prepare
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; override RCW_SRC = Hardcoded
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Data.Set EDBG:0x42000040 %Long 0x9e
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; override the RCW itself - values as in uboot mainline LS1043A RDB NAND
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Data.Set EDBG:0x42000000 %Long 0x08100010
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Data.Set EDBG:0x42000004 %Long 0x0A000000
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Data.Set EDBG:0x42000008 %Long 0x00000000
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Data.Set EDBG:0x4200000c %Long 0x00000000
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Data.Set EDBG:0x42000010 %Long 0x14550002
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Data.Set EDBG:0x42000014 %Long 0x80004012
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;Data.Set EDBG:0x42000018 %Long 0xE0106000 ; PBL=IFC, IFC=0x106
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Data.Set EDBG:0x42000018 %Long 0xfb800a00 ; PBL_SRC=reserved, IFC=0xa
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Data.Set EDBG:0x4200001C %Long 0xC1002000
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Data.Set EDBG:0x42000020 %Long 0x00000000
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Data.Set EDBG:0x42000024 %Long 0x00000000
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Data.Set EDBG:0x42000028 %Long 0x00000000
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Data.Set EDBG:0x4200002C %Long 0x00038800
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Data.Set EDBG:0x42000030 %Long 0x00000000
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Data.Set EDBG:0x42000034 %Long 0x00001100
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Data.Set EDBG:0x42000038 %Long 0x00000096
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Data.Set EDBG:0x4200003C %Long 0x00000001
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; </temporarily override the RCW>
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SYStem.Up
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Register.Set M 0x5 ;EL1h
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Data.Set AZD:0x1530010 %LE %Long 0x8300807E ;Chip-select Property register n (IFC_CSPR0)
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Data.Set AZD:0x15301C0 %LE %Long 0x0a07180e ;Flash Timing register 0 for Chip Select 0
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Data.Set AZD:0x15301C4 %LE %Long 0x180e3932 ;Flash Timing register 1 for Chip Select 0
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Data.Set AZD:0x15301C8 %LE %Long 0x1e50e001 ;Flash Timing register 2 for Chip Select 0
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Data.Set AZD:0x15301CC %LE %Long 0x0 ;Flash Timing register 3 for Chip Select 0
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GOSUB READ_ID
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LOCAL &pdd
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&pdd=OS.PresentDemoDirectory()
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Break.RESet
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FLASHFILE.RESet
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; FLASHFILE.CONFIG <IFC base address> <0x0> <NFC buffer RAM address> <chip select>
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FLASHFILE.CONFIG &BASE 0x0 A:0x7E800000 0x0
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; FLASHFILE.TARGET <code_range> <data_range> <algorithm file>
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FLASHFILE.TARGET 0x10001000++0x1FFF 0x10004000++0x3FFF &pdd/flash/byte/nand2g08_lsifc.bin /KEEP /STACKSIZE 0x200
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; Read FLASH Manufacturer and Device ID
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FLASHFILE.GETID
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//End of the test prepareonly
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IF "&arg1"=="PREPAREONLY"
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ENDDO
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//Read FLASH
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FLASHFILE.DUMP 0x0
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//Erase FLASH
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; FLASHFILE.ERASE 0x0--0xFFFFF /EraseBadBlocks
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//Write FLASH
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; FLASHFILE.LOAD * 0x0 /WriteBadBlocks
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; FLASHFILE.LOAD * 0x0 /WriteBadBlocks /ComPare ;verify
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ENDDO
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READ_ID:
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(
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SCREEN.OFF
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Data.Set &BASE+0x1014 %BE %Long 0x90000000 ; FCR0 0x90
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Data.Set &BASE+0x1018 %BE %Long 0x00000000 ; FCR1
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Data.Set &BASE+0x1110 %BE %Long 0x46084000 ; FIR0
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Data.Set &BASE+0x1114 %BE %Long 0x0 ; FIR1
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Data.Set &BASE+0x1118 %BE %Long 0x0 ; FIR2
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Data.Set &BASE+0x115C %BE %Long 0x00000000 ; CS0 select
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;Data.Set &BASE+0x115C %BE %Long 0x04000000 ; CS1 select
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Data.Set &BASE+0x1108 %BE %Long 0x00000010 ; Byte count
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Data.Set &BASE+0x116C %BE %Long 0x00000000 ; state clear
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Data.Set &BASE+0x103C %BE %Long 0x00000000 ; IFC_ROW0
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Data.Set &BASE+0x1044 %BE %Long 0x00000000 ; IFC_COL0
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Data.Set &BASE+0x1164 %BE %Long 0x80000000 ; IFC operation start
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&temp=Data.Long(A:0x7e800000)
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PRINT "1st: 0x" &temp&0xFF " (manufacture id)"
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PRINT "2nd: 0x" (&temp>>8.)&0xFF " (device id)"
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PRINT "3rd: 0x" (&temp>>16.)&0xFF
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PRINT "4th: 0x" (&temp>>24.)&0xFF
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SCREEN.ON
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RETURN
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)
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