196 lines
6.2 KiB
Plaintext
196 lines
6.2 KiB
Plaintext
; @Title: SABRE Board (i.MX 6SoloX) Quad SPI FLASH Program script
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; @Description:
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; The S25FL128 (Spansion SPI flash) is on the QSPI2A_SS0 & QSPI2B_SS0
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; SABRE Board for Smart Devices Based on i.MX 6SoloX
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;
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; SRAM: 0x900000
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; QuadSPI(controller) Base: 0x021E4000
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; FLASH BASE ADDRESS: 0x70000000
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;
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; @Author: jjeong
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; @Chip: imx6*
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; @Keywords: S25FL128 Spansion Flash SPI QuadSPI
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; $Id: imx6sxqspi-spi64.cmm 11733 2023-01-16 08:55:12Z bschroefel $
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;
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LOCAL &arg1
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ENTRY &arg1
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&arg1=STRing.UPpeR("&arg1") // for example "PREPAREONLY"
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&QSPI_BASE=0x021E4000 ; QSPI2=0x021E4000 , qspi controller based address
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&QSPI_AMBA_BASE=0x70000000 ; QSPI2A_AMBA_BASE=0x70000000, QSPI2B_AMBA_BASE=0x78000000 , the memory base address for qspi memory
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SYStem.RESet
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SYStem.CPU IMX6SLX-CA9
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SYStem.JtagClock 10Mhz
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SYStem.Option ResBreak OFF
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IF VERSION.BUILD()<92177.
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(
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SYStem.Option WaitReset 15ms
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)
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ELSE
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(
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SYStem.Option WaitIDCODE 1.5s
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)
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SYStem.Up
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Data.Set C15:0x1 %Long (Data.Long(C15:0x1)&~(0x1005)) ; disable cache and mmu
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Data.Set A:0x020bc000 %Word 0x30 ;disable Watchdog
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Data.Set A:0x020C0000 %Word 0x30 ;disable Watchdog
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Data.Set A:0x02280000 %Word 0x30 ;disable Watchdog
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//clk
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Data.Set A:0x20c4074 %Long 0xFFFFFFFF ; (CCM_CCGR3) QSPI1_CLK for qspi1
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Data.Set A:0x20c4078 %Long 0x0FFFFFFFF ; (CCM_CCGR4) QSPI2_CLK for qspi2
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Data.Set A:0x20c401c %Long 0x14900200 ; CCM_CSCMR1 for qspi1
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Data.Set A:0x20c402c %Long 0x736C1 ;CCMCS2CDR for qspi2
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//pin mux for QSPI2A
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Data.Set A:0x20E0174 %Long 0x2 ;QSPI2A_DAT1,(IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B)
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Data.Set A:0x20E017C %Long 0x2 ;QSPI2A_DAT0,(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B)
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Data.Set A:0x20E014C %Long 0x2 ;QSPI2A_SCLK,(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE)
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Data.Set A:0x20E0140 %Long 0x2 ;QSPI2A_SS0_B,(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE)
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Data.Set A:0x20E04BC %Long 0x70F1 ;QSPI2A_DAT1,(IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B)
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Data.Set A:0x20E04C4 %Long 0x70F1 ;QSPI2A_DAT0,(IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B)
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Data.Set A:0x20E0494 %Long 0x70F1 ;QSPI2A_SCLK,(IOMUXC_SW_PAD_CTL_PAD_NAND_CLE)
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Data.Set A:0x20E0488 %Long 0x70F1 ;QSPI2A_SS0_B,(IOMUXC_SW_PAD_CTL_PAD_NAND_ALE)
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//pin mux for QSPI2B
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Data.Set A:0x20E0150 %l 0x2 ;QSPI2B_DAT1, (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00)
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Data.Set A:0x20E0154 %l 0x2 ;QSPI2B_DAT0, (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01)
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Data.Set A:0x20E0158 %l 0x2 ; QSPI2B_SCLK, (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02)
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Data.Set A:0x20E015C %l 0x2 ; QSPI2B_SS0_B, (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03)
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Data.Set A:0x20E0498 %l 0x70F1 ; QSPI2B_DAT1 (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00)
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Data.Set A:0x20E049C %l 0x70F1 ; QSPI2B_DAT0 (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01)
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Data.Set A:0x20E04A0 %l 0x70F1 ; QSPI2B_SCLK, (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02)
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Data.Set A:0x20E04A4 %l 0x70F1 ; QSPI2B_SS0_B, (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03)
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//qspi controller
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Data.Set A:(&QSPI_BASE) %Long 0x0F400C ;disable
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Data.Set A:(&QSPI_BASE+0x30) %Long 0x0
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Data.Set A:(&QSPI_BASE+0x180) %Long 0x74000000 ; Serial Flash A1 Top Address(QuadSPIx_SFA1AD)
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Data.Set A:(&QSPI_BASE+0x184) %Long 0x78000000 ; Serial Flash A2 Top Address(QuadSPIx_SFA2AD)
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Data.Set A:(&QSPI_BASE+0x188) %Long 0x7C000000 ; Serial Flash B1Top Address (QuadSPIx_SFB1AD)
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Data.Set A:(&QSPI_BASE+0x18C) %Long 0x80000000 ; Serial Flash B2Top Address (QuadSPIx_SFB2AD)
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Data.Set A:(&QSPI_BASE+0x10) %Long 0x0E
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Data.Set A:(&QSPI_BASE+0x14) %Long 0x0E
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Data.Set A:(&QSPI_BASE+0x18) %Long 0x0E
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Data.Set A:(&QSPI_BASE+0x1C) %Long 0x80002000
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Data.Set A:(&QSPI_BASE+0x100) %Long 0x70000000
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Data.Set A:(&QSPI_BASE+0x15C) %Long 0x13C00
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Data.Set A:(&QSPI_BASE+0x160) %Long 0x8010000
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//QSPI AHB(A:0x08000000) read configuration
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//3byte read at &QSPI_AMBA_BASE
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D.S A:(&QSPI_BASE+0x310) %Long (0x08180400|0x3) ;default
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D.S A:(&QSPI_BASE+0x314) %Long 0x24001C08
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D.S A:(&QSPI_BASE+0x318) %Long 0x0 ;STOP
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//4byte read for spansion flash memory
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;D.S A:(&QSPI_BASE+0x310) %Long (0x08200400|0x13) ;ADDR(32bits) 0 & CMD(0x13)
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;D.S A:(&QSPI_BASE+0x314) %Long 0x24001C08 ;JMP_ON_CS(inst 0)& READ(8bytes)
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;D.S A:(&QSPI_BASE+0x318) %Long 0x0 ;STOP
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Data.Set A:(&QSPI_BASE) %Long 0x0F000C ;enable
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//FLASH READ ID TEST
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AREA.CLEAR
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AREA.view
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GOSUB READ_ID_TEST
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DIALOG.YESNO "the flash id is correct on AREA window?"
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ENTRY &result
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IF !&result
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(
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PRINT "pls, check your register configuration to enable your flash controller"
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ENDDO
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)
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//S(D)RAM TEST for algorithm file
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GOSUB SDRAM_INIT
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Data.Test 0x900000++0x3FFF /Prime ;s(d)ram test
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IF FOUND()
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(
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PRINT "s(d)ram is NOT initialized around 0x" ADDRESS.OFFSET(TRACK.ADDRESS())
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ENDDO
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)
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programFlash:
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Break.RESet
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FLASHFILE.RESet
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//FLASHFILE.CONFIG <QuadSPI Base> <QSPIx MEMORY>
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FLASHFILE.CONFIG &QSPI_BASE &QSPI_AMBA_BASE
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//FLASHFILE.TARGET <Code_range> <Data_range> <Algorithm file>
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FLASHFILE.TARGET 0x900000++0x1FFF EAHB:0x902000++0x1FFF ~~/demo/arm/flash/byte/spi64_vybridqspi.bin /KEEP /DUALPORT
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FLASHFILE.GETID
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//End of the test prepareonly
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IF "&arg1"=="PREPAREONLY"
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ENDDO
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FLASHFILE.UNLOCK 0x0--0xFFFFFF
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FLASHFILE.DUMP 0x0
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//Erase Serial FLASH
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;FLASHFILE.ERASE 0x0--0xFFFFF
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//Write
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;FLASHFILE.LOAD * 0x0
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;FLASHFILE.LOAD * 0x0 /ComPare ;verify
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ENDDO
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READ_ID_TEST:
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&cmd=0x9F; read ID JEDEC Manufacture ID and JEDEC CFI
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&temp=Data.Long(A:&QSPI_BASE)
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Data.Set A:&QSPI_BASE %Long (&temp|0x0c00) //clear Tx/Rx buffer
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Data.Set A:(&QSPI_BASE+0x300) %LE %Long 0x5AF05AF0 ; LUTKEY
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Data.Set A:(&QSPI_BASE+0x304) %LE %Long 0x2 ; LCKCR
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//0. read id
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Data.Set A:(&QSPI_BASE+0x360) %LE %Long (0x1c040400)|&cmd ; LUT0, SEQID0
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Data.Set A:(&QSPI_BASE+0x364) %LE %Long 0x0
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Data.Set A:(&QSPI_BASE+0x368) %LE %Long 0x0
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Data.Set A:(&QSPI_BASE+0x36C) %LE %Long 0x0
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Data.Set A:(&QSPI_BASE+0x100) %Long &QSPI_AMBA_BASE ; SFAR , FLASH BASE ADDRESS
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// assert Read id command
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Data.Set A:(&QSPI_BASE+0x008) %Long (0x5<<24.) ; (5.<<24.)
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WAIT 100.ms
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&temp=Data.Long(A:&QSPI_BASE)
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Data.Set A:&QSPI_BASE %Long (&temp|0x0800) //clear Tx buffer
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PRINT "1st 0x" Data.Long(A:(&QSPI_BASE+0x200))&0xFF " (Manufacturer)"
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PRINT "2nd 0x" (Data.Long(A:(&QSPI_BASE+0x200))>>8.)&0xFF " (Device ID)"
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PRINT "3rd 0x" (Data.Long(A:(&QSPI_BASE+0x200))>>16.)&0xFF
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PRINT "4th 0x" (Data.Long(A:(&QSPI_BASE+0x200))>>24.)&0xFF
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RETURN
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SDRAM_INIT:
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RETURN
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